JP2007259369A - Decoding method and decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that it is difficult to conduct a seamless change-over by a simple constitution synchronously due to increasing the circuit scale related to the synchronization in the case that an apparatus to decode a plurality of MPEG data which are asynchronous each other is constituted and that it is difficult to change over in a short time due to a structure of the MPEG data. <P>SOLUTION: Decoding portions 11 and 12 decode the MPEG data A and B input asynchronously and in parallel each and generate the encoded image signals A and B. Memory control portions 13 and 15 write the decoded image signals A and B in memories 14 and 16 asynchronously and read the encoded image signals A and B from the memories 14 and 16 at the same read timing. One of the read encoded image signals is changed over and output by a change-over portion 17. The asynchronously decoded image signals conduct the seamless change-over which is achieved in a short time with no shock, and is not restricted by a processing time due to its structure even if the decoded image signals are the MPEG data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a decoding method and a decoding apparatus, and in particular, among a plurality of encoded data asynchronously obtained (hereinafter also referred to as MPEG data) obtained by compressing and encoding a video signal by the MPEG (Moving Picture Experts Group) method. The present invention relates to a decoding method and a decoding apparatus for obtaining a decoded output of one arbitrarily selected encoded data.

  When a plurality of encoded video signals (MPEG data) transmitted asynchronously from a plurality of transmission devices are received by a single receiver and arbitrarily switched and displayed, the receiver receives a plurality of received video signals. A decoding device for decoding and selectively displaying the encoded video signal is required.

  As a method for displaying one video signal arbitrarily selected from a plurality of video signals, for example, a method for quickly viewing a switched video signal by switching channels of a digital broadcast is conventionally known ( For example, see Patent Document 1). That is, in Patent Document 1, in a multimedia information device having a digital broadcast receiving function, a streaming broadcast receiving function, or an Internet connection function, a user profile generation unit stores history data of user channel transitions stored in a storage unit. A user profile indicating an operation pattern related to the user's channel (program) transition is created and stored in the user profile storage unit, and the channel transition inference unit relates to the user profile from the storage unit and the channel currently being viewed. By inferring and determining channel candidates that are likely to move to the next from the information, and setting the reception of channel candidates based on the inference results, the next time when the user switches channels Switch channels and display at high speed It can be switched.

JP-A-2005-130087

  However, the invention described in Patent Document 1 described above switches display channels at high speed based on the history data of the channel transition of the user, and a plurality of encoded video signals (MPEG data) can be obtained without using history data. It is not a configuration for seamlessly switching and displaying one video signal obtained by decoding and arbitrarily selecting.

  Further, as is well known in the MPEG system, between frames obtained by performing forward prediction between frames of an I picture obtained by intra-coding all of one frame of a video signal and a predetermined picture such as an I picture. Bidirectional predictive encoded image (B picture) obtained by performing predictive encoding between a forward predictive encoded image (P picture) and a temporally forward and backward bidirectional I picture or P picture Random access is achieved by transmitting in a GOP (Group of Picture) unit composed of a plurality of pictures in which one I picture and a plurality of P pictures and B pictures are appropriately combined among the three types of pictures (MPEG data) Is possible.

  For example, as shown in FIG. 4, when the total number N of I pictures, P pictures, and B pictures constituting the GOP is “9”, for example, nine frames of MPEG data are accumulated. Since it is structured to be able to decode consecutive pictures from the beginning, when decoding a plurality of MPEG data that are asynchronous with each other on the sending side and the receiving side that are asynchronous with each other, 9 frames of MPEG data are not accumulated. Therefore, it is not possible to switch to different MPEG data.

  Further, when a decoding apparatus configured to switch and decode a plurality of asynchronous MPEG data, the circuit scale related to the synchronization construction between the plurality of asynchronous MPEG data is increased, and in some cases, a plurality of decoders or a plurality of decoders may be used. Since it is a multiple operation at the apparatus level, such as a switch, it is difficult to perform seamless seamless switching synchronously in parallel operations such as decoding a plurality of asynchronous MPEG data.

  The present invention has been made in view of the above points, and provides a decoding method and a decoding apparatus capable of switching a plurality of MPEG data in a short time and displaying them at high speed without being restricted by the processing time due to the structure of the MPEG data. For the purpose.

  Another object of the present invention is to incorporate a plurality of highly integrated asynchronous decoders and a memory for synchronization in a space-saving manner, thereby reducing the size and weight of the apparatus and simplifying the configuration. Another object of the present invention is to provide a decoding method and a decoding apparatus capable of realizing seamless switching without a shock for an asynchronous decoded video signal.

  In order to achieve the above object, according to the decoding method of the present invention, a plurality of encoded video signals obtained by compressing and encoding a video signal by a predetermined encoding method are input in parallel and asynchronously to each other. A decoding method for outputting a decoded video signal of one encoded video signal arbitrarily selected from video signals, wherein a plurality of encoded video signals input asynchronously with each other are decoded separately, A first step of generating a decoded video signal; and supplying a plurality of decoded video signals to a plurality of memories provided in a one-to-one correspondence, and separately synchronizing video signals of each decoded video signal The second step of writing based on the third step, the third step of reading the decoded video signal stored in each memory from the plurality of memories at the same read timing, and the third step A desired second decoded video signal is switched and output within a predetermined blanking period from the first decoded video signal selected and output from among the plurality of decoded video signals that are output. And a fourth step.

  In the present invention, the encoded video signals that are input asynchronously with each other are decoded to generate decoded video signals, and then the asynchronous decoded video signals are separately written in a plurality of memories and then synchronized with each other. Since reading is performed at the same reading timing, when switching from one first decoded video signal to another second decoded video signal, switching can be performed immediately.

  Here, each of the plurality of memories is divided into two areas, and when the decoding video signal is written in one area in the second step, the decoding that has been written in the other area is performed. The digitized video signal is read in the third step. In the present invention, the storage area of the memory can be used effectively.

  In order to achieve the above object, the decoding device of the present invention is configured such that a plurality of encoded video signals obtained by compressing and encoding a video signal by a predetermined encoding method are input in parallel in a plurality of asynchronous manners. A decoding device for outputting a decoded video signal of one encoded video signal arbitrarily selected from the encoded video signal, wherein a plurality of encoded video signals input asynchronously with each other are separately decoded, A plurality of decoding means for generating a plurality of decoded video signals; a plurality of memories for reading after the plurality of decoded video signals are written separately; and a plurality of decoded video signals for each of the plurality of memories. The corresponding decoded video signal is asynchronously written independently of each other based on the video synchronization signal of the decoded video signal, and a predetermined one of the plurality of decoded video signals is used as a reference. The memory control means for reading the stored decoded video signals from the plurality of memories in synchronization with the read timing, and the first selected from the plurality of decoded video signals read from the plurality of memories for output. Switching means for switching and outputting another desired second decoded video signal within a predetermined blanking period from the decoded video signal.

  In the present invention, the encoded video signals that are input asynchronously with each other are decoded to generate decoded video signals, and then the asynchronous decoded video signals are separately written in a plurality of memories and then synchronized with each other. Since reading is performed at the same reading timing, when switching from one first decoded video signal to another second decoded video signal, switching can be performed immediately.

  Here, the memory control means uses a plurality of memories divided into two areas, respectively, and when the decoded video signal writing operation is performed in one area, the decoding already written in the other area. It is characterized by reading the digitized video signal. In the present invention, the storage area of the memory can be used effectively.

  In the present invention, the plurality of decoding means, the plurality of memories, the memory control means, and the switching means are provided in one receiver that simultaneously receives a plurality of encoded video signals asynchronously and integrated. It is characterized by comprising a circuit. In this invention, a plurality of asynchronous decoding means, a memory for synchronization, a memory control means, and a switching means can be incorporated in a single receiver in a space-saving manner, and a simple circuit configuration is provided. Can do.

  According to the present invention, after decoding encoded video signals that are input asynchronously with each other to generate decoded video signals, the asynchronous video signals that are asynchronously written to each other are separately written in a plurality of memories, and then The decoded video signal that is read out at the same synchronized read timing and switched from one first decoded video signal to another second decoded video signal is switched within the blanking period. Thus, seamless switching without shock can be executed in a short time, and even if the encoded video signal is MPEG data, the processing time by the structure is not restricted.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a decoding apparatus according to the present invention. In the figure, MPEG data A and MPEG data B asynchronous to each other input to the decoding apparatus of the present embodiment are supplied to decoding units 11 and 12 provided in a one-to-one correspondence. Here, the above-mentioned MPEG data A and MPEG data B are, for example, transmitted asynchronously from two transmission devices, respectively, and received by a single receiver and compressed and encoded by the MPEG system. It is an encoded video signal.

  The decoding unit 11 decodes (decodes) the MPEG data A by the MPEG method, generates a decoded video signal A, and supplies the decoded video signal A to the memory control unit 13. The memory control unit 13 supplies the decoded video signal A to the memory 14. On the other hand, in parallel with this, the decoding unit 12 decodes (decodes) the MPEG data B by the MPEG method, generates a decoded video signal B, and supplies it to the memory control unit 15. The memory control unit 15 supplies the decoded video signal B to the memory 16.

  Further, since the MPEG data A and the MPEG data B are asynchronous, the decoded video signal A and the decoded video signal B obtained by decoding them are asynchronous, and in order to synchronize them, the memory control is performed. Before the unit 15 passes the decoded video signal B to the memory 16, the memory control unit 13 passes time information of the timing for writing the decoded video signal A to the memory 14 to the memory control unit 15.

  Further, the data read from the memory 14 and the memory 16 is performed with the same signal, and signals (decoded video signals) read from the memory 14 and the memory 16 are respectively transmitted through the memory control unit 13 and the memory control unit 15. Then, one decoded video signal supplied to the switching unit 17 and selected by the switching unit 17 is output to the outside as an output video signal.

  Next, the operation of the present embodiment will be described. MPEG data A obtained by compressing and encoding the first video signal by the MPEG method is supplied to the decoding unit 11 and decoded to be a decoded video signal A. On the other hand, MPEG data B asynchronous with MPEG data A, obtained by compressing and encoding the second video signal by the MPEG method, is supplied to the decoding unit 12 for decoding processing and decoded video signal B Is done.

  The decoded video signal A is passed to the memory 14 via the memory control unit 13. The memory control unit 13 detects a video synchronization signal included in the decoded video signal A, and generates a timing for writing the decoded video signal A into the memory 14. On the other hand, the decoded video signal B is passed to the memory 16 via the memory control unit 15.

  The memory control unit 15 detects a video synchronization signal included in the decoded video signal B, and receives a timing for writing the decoded video signal A into the memory 14 from the memory control unit 13 as temporal information. The same pointer value as that of the memory control unit 13 is calculated, and the timing for writing the decoded video signal B into the memory 16 is generated.

  Here, as shown in FIG. 2A, the storage area of the memory 14 is as shown in FIG. 2A, and the storage area of the memory 16 is the same as the α areas 21 and 23, which are data areas for one frame, respectively. It is divided into β areas 22 and 24, which are data areas for one frame, and has the same configuration. This frame division is a bank configuration, and the usage area of the memory 14 and the usage area of the memory 16 may use different areas. For example, when the α area 21 of the memory 14 is used, the β area of the memory 16 is used. 24 may be used.

  In this embodiment, the memory control unit 13 passes the timing for writing the decoded video signal A to the memory 14 as temporal information to the memory control unit 15, and the memory control unit 15 stores the decoded video signal in the memory 16. The difference of the pointer value in one frame frame from the timing of writing the signal B is recognized. This will be described in detail with reference to FIG.

  FIG. 2B shows the original write timing (Write′B) generated from the video synchronization signal included in the decoded video signal B that is asynchronous with the decoded video signal A in the α region 23 of the memory 16. It shows that there is a difference between the write timing (WriteB) to the memory 14 generated from the video synchronization signal included in the decoded video signal A. FIG. 2A shows the write timing (WriteA) to the memory 14 generated from the video synchronization signal included in the decoded video signal A in the α region 21 of the memory 14.

  Write B in FIG. 2B is a pointer value in one frame frame generated by the memory control unit 15 based on temporal information indicating the timing of writing the decoded video signal A into the memory 14. Further, the read timing of the memory 14 and the memory 16 is based on the same read control signal as indicated by Read in FIGS. 2A and 2B, and is always the same.

  The case where the decoded video signal A and the decoded video signal B have a difference of one frame is the original write timing of the memory 16 (Write B in FIG. 2B), and the read timing is between frames. Although it is possible to switch in units of one frame, the difference between the decoded video signal A and the decoded video signal B by 0.5 frame is Write'B of the memory 16 shown in FIG. It is necessary to wait for 0.5 frame because 0.5 frame is insufficient at the timing of reading out in units of one frame and image frame shift occurs.

  On the contrary, the case where the decoded video signal B is delayed by 0.5 frame with respect to the decoded video signal A is Write “B” of the memory 16, and 1.5 frames at the timing of reading out in units of one frame. It is necessary to wait for 0.5 frame because the frame is shifted due to the fractional effect, and in this case, the decoded video signal B is delayed by one frame with respect to the decoded video signal A. It will be.

  In addition, by quantitatively grasping this waiting time, it is possible to read sequentially without delaying one frame, and for this reason, the difference between Write A and Write'B or Write "B is recognized. 14 and the memory 16 can be monitored by writing positions within one frame, so that the synchronized management of the decoded video signal A and the decoded video signal B can be performed asynchronously.

  Thereafter, the decoded video signal A and the decoded video signal B written in the memory 14 and the memory 16, respectively, are read timing signals (Read signals) having the same timing indicated by Read in FIGS. 2 (A) and 2 (B). ) And is supplied to the switching unit 17 via the memory control unit 13 and the memory control unit 15, respectively. The switching unit 17 switches the video signal in units of one frame in the vertical blanking period of the video signal in which the video switching shock is not displayed on the screen, and outputs it as an output video signal.

  Next, each of the stored decoded video signals of the memories 14 and 16 and the output video signal of the switching unit 17 will be described in detail with reference to FIG. 3A shows the transition of the stored video signal in the memory 14, FIG. 3B shows the transition of the output video signal of the switching unit 17, and FIG. 3C or FIG. It shows the transition of the signal. Here, FIG. 3C shows the transition of the stored decoded video signal in the memory 16 in the case where the decoded video signal B has a difference of 0.5 frame advance with respect to the decoded video signal A. FIG. Shows the transition of the decoded decoded video signal in the memory 16 when the decoded video signal B is a difference delayed by 0.5 frame from the decoded video signal A.

  In FIG. 3A, “Aα” and “Aβ” indicate one frame of the decoded video signal A stored in the α area 21 and the β area 22 which are storage areas of the memory 14, respectively. Subsequent positive or negative numbers are shown with respect to the frame in which Write A is located as a reference, with the past frame being negative in time and the future frame being positive. Similarly, in FIGS. 3C and 3D, “Bα” and “Bβ” indicate one frame of the decoded video signal B stored in the α region 23 and the β region 24 which are storage regions of the memory 16, respectively. The positive or negative numbers following Bα or Bβ are negative in the past frame and positive in the future frame with respect to the frame where Write'B is located.

  In FIG. 3A, after one frame of the decoded video signal A is stored in the β region 22 of the memory 14 as indicated by “Aβ-1”, the decoded video signal A is subsequently stored in the α region 21. The next frame is written as indicated by “Aα”. When the pointer value at the time of starting writing of one frame of Aα is indicated by WriteA, at this time, the decoded video signal B with respect to the decoded video signal A is written. Is a difference of advancing by 0.5 frames, as shown in FIG. 5C, during a period in which one frame of the decoded video signal B is recorded in the α area 23 of the memory 16 as indicated by “Bα”. Write'B indicates a half position, that is, a pointer value of 0.5 frame.

  On the other hand, as shown in FIG. 2A, at the start of writing one frame of Aα in the memory 14, there is a read pointer value at the first position of the β area 22 of the memory 14, as indicated by “Read”. , Reading of the decoded video signal A of the previous frame indicated by “Aβ-1” stored in the β region 22 is started.

  Thereafter, as shown in FIG. 3A, after one frame having the decoded video signal A is stored in the α area 21 after the pointer indicated by Write A in the memory 14, the decoded video is subsequently stored in the β area 22. As shown by “Aβ” in the next frame of the signal A, writing is started by overwriting, but within the vertical blanking period of the decoded video signal A immediately before the recording starts, the switching unit 17 decodes the decoded video signal. It is assumed that A is switched to the decoded video signal B. At this time of switching, if the decoded video signal B is a difference of 0.5 frames ahead of the decoded video signal A in the memory 16, as shown by “Bβ” in FIG. In this state, 0.5 frame of the decoded video signal B has already been written in 24 and is still being written.

  However, in the present embodiment, since the memory 14 and the memory 16 are read synchronously from the same read point, each read point of the memory 14 and the memory 16 is not changed at the above switching time. The α regions 21 and 23 are at the beginning, and therefore, from the memory 16, the period from 1.5 frames before the switching point to 0.5 frames before indicated by “Bα” in FIG. The decoded video signal B for one frame indicated by “Bα” in FIG. 3C in the state written in the α region 23 of the memory 16 is read and output from the switching unit 17. Thereby, the output video signal of the switching unit 17 changes as schematically shown in FIG.

  Similarly to the above, when the decoded video signal B is delayed by 0.5 frame with respect to the decoded video signal A, as shown by “Bα” in FIG. 16 frames of the decoded video signal B have already been written in the 16 α region 23 and are still being written. However, in the present embodiment, when Write “B” indicates a pointer value delayed by 0.5 frame from Write A on the memory area, the read pointer is at the beginning of the β area 24, and therefore the above switching time point. The decoded video for one frame indicated by “Bβ-1” in FIG. 3D, which is written in the β area 24 of the memory 16 during the period from 1.5 frames before to 0.5 frames before. The signal B is read and output from the switching unit 17.

  As described above, in this embodiment, by monitoring the writing position in one frame of the memory 14 and the memory 16, the asynchronous management of the decoded video signal A and the decoded video signal B can be performed asynchronously. In addition, it is possible to switch between the decoded video signals of two MPEG data without waiting for the number N of pictures in the GOP of the MPEG data as in the prior art. In addition, since the two decoded video signals are switched during the vertical blanking period, seamless video switching without shock can be performed.

  Although the asynchronous / synchronous relationship between the write timing and the read timing of the memory control unit 13 and the memory control unit 15 is not particularly described, the same read timing signal is generated based on the same reference clock for the read timing. As for the write timing, as described above, the write timing signal is generated by recognizing the difference between Write B and Write'B or Write "B (pointer value difference in one frame frame). However, since these timing signal generating means themselves can be realized by a known technique as a frame synchronizer (FS) operation, detailed description thereof is omitted.

  The present invention is not limited to the above-described embodiment. For example, FIG. 2 illustrates frame division, but field division or line division is controlled by the memory control unit 14 or the memory control unit 16. Is feasible. In the above-described embodiment, the switching unit 17 is described as switching the decoded video signal within the vertical blanking period. However, the switching unit 17 may be switched within the horizontal blanking period.

  In addition, since a synchronized circuit can be simpler, the present invention is a general method and includes a wide variety of method applications suitable for individual reasons. In FIG. 1, two asynchronous MPEG data are described as being handled, but it is also possible to handle three or more asynchronous MPEG data by a similar method.

  In addition, the decoding units 11 and 12, the memory control circuits 13 and 15 and the switching unit 17 of the above-described embodiment are configured by a highly integrated integrated circuit and are simply combined, so that display quality can be reduced in size and speed. Therefore, it is possible to realize a decoding device that performs a switching operation without any problem.

It is a block diagram of one embodiment of a decoding device of the present invention. FIG. 2 is an explanatory diagram of a memory configuration and write / read control in FIG. 1. 3 is a timing chart for explaining operations in FIGS. 1 and 2. It is a figure which shows the structure of an example of GOP.

Explanation of symbols

11, 12 Decoding unit 13, 15 Memory control unit 14, 16 Memory 17 Switching unit

Claims (7)

A plurality of encoded video signals obtained by compressing and encoding a video signal by a predetermined encoding method are input in parallel and asynchronously with each other, and one encoded video signal arbitrarily selected from the plurality of encoded video signals A decoding method for outputting a decoded video signal,
A first step of separately decoding the plurality of encoded video signals input asynchronously with each other to generate a plurality of decoded video signals;
A second step of supplying the plurality of decoded video signals to a plurality of memories provided in a one-to-one correspondence and writing each separately based on a video synchronization signal of each decoded video signal;
A third step of reading out the decoded video signal stored in each memory at the same read timing from the plurality of memories;
Of the plurality of decoded video signals read out in the third step, a desired second decoded video signal is selected from the first decoded video signal selected and output. And a fourth step of switching and outputting within the blanking period.   Each of the plurality of memories is divided into two areas. When the decoded video signal is written in one area in the second step, the decoding that has been written in the other area is performed. 2. The decoding method according to claim 1, wherein a video signal is read in the third step.   3. The decoding method according to claim 1, wherein the encoded video signal is MPEG data obtained by compressing and encoding the video signal by MPEG. A plurality of encoded video signals obtained by compressing and encoding a video signal by a predetermined encoding method are input in parallel and asynchronously with each other, and one encoded video signal arbitrarily selected from the plurality of encoded video signals A decoding device that outputs a decoded video signal,
A plurality of decoding means for generating a plurality of decoded video signals by separately decoding the plurality of encoded video signals input asynchronously with each other;
A plurality of memories to be read after separately writing the plurality of decoded video signals;
Into each of the plurality of memories, a corresponding decoded video signal among the plurality of decoded video signals is written independently and asynchronously based on a video synchronization signal of the decoded video signal, Memory control means for synchronizing the readout timing with reference to one predetermined decoded video signal among the decoded video signals and reading out the stored decoded video signals from the plurality of memories;
Of the plurality of decoded video signals read out from the plurality of memories, a desired second decoded video signal is selected from a first decoded video signal selected and output. And a switching means for switching and outputting within the ranking period.   The memory control unit divides the plurality of memories into two areas, and uses the decoded video signal written to the other area when the decoded video signal is written to the other area. 5. A decoding apparatus according to claim 4, wherein a video signal is read out.   The plurality of decoding means, the plurality of memories, the memory control means, and the switching means are provided in a single receiver that simultaneously receives the plurality of encoded video signals asynchronously and are configured by an integrated circuit. 6. The decoding apparatus according to claim 4, wherein the decoding apparatus is provided.   7. The decoding apparatus according to claim 4, wherein the encoded video signal is MPEG data obtained by compressing and encoding the video signal by MPEG.

Images