JP2006310906A - Video signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of occurrence of frame deviation in displayed video, resulting in the video with discomfort if a plurality of video signals, synchronized with each other, fall in out of synchronization even a single time while a plurality of video signals are displayed on a single display device. <P>SOLUTION: A memory means writing circuit 11 writes, in parallel, animation signals of four channels inputted parallel into banks of four memory means 13-1 to 13-4 for each channel. A bank that performs writing of memory means 13-1 to 13-4 is changed to the next one from the current one each time a synchronous signal detecting signal is supplied that is outputted when the vertical synchronous signal is detected by a synchronous signal detecting circuit 12. If disturbance occurs in the synchronous signal due to noises and a false vertical synchronous signal is detected by the synchronous signal detected circuit 12, the video signal on and after the disturbance occurs is written in the next bank instead of a bank being written in the memory means 13-1 to 13-4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus, and more particularly to a video signal processing apparatus for performing multi-screen display in which a plurality of video signals are displayed on the same screen.

  In recent video display devices, resolution has been rapidly improved. Up to now, it was only possible to display one channel of video signal (720P) with 720 horizontal scanning lines and high definition television (HDTV) video in the progressive system. Among such micro devices, those having a resolution of 4000 horizontal pixels / 2000 vertical pixels have been put into practical use.

  By the way, when performing such ultra-high-definition video display, conventionally, a multi-screen display device is known in which a plurality of video display devices are arranged adjacent to each other vertically and horizontally to form one display screen (for example, patents). Reference 1). In the multi-screen display device of Patent Document 1, each of a plurality of video display devices is a projection device that projects a video on a screen, a video signal processing circuit that processes a video signal, and an input switching circuit that selects a video source. And a timer circuit having a self-reset function that measures a predetermined time and generates an interrupt signal after a predetermined time, and controls the operating state of the projection apparatus in synchronization with the interrupt signal from the timer circuit. And a system control circuit for controlling the image output timing of the projection apparatus by outputting a control signal and the like.

  In this multi-screen display device, a plurality of projection devices (projectors) project images on a plurality of screens on a one-to-one basis, and a single image (for example, an HDTV image in the horizontal and vertical directions) is synthesized on the entire screen. 2 times each), individual images are displayed separately on multiple screens, and variations in individual output timings of video display devices that occur in unstable operation such as when switching video sources To prevent.

Japanese Patent Laid-Open No. 11-234595

  However, the above-mentioned multi-screen display device is expensive because it requires a plurality of projection devices (projectors), and has a problem of high power consumption. On the other hand, when an image is displayed by a micro device using a liquid crystal having a resolution of 4000 horizontal pixels / 2000 vertical pixels, there is one image display device, which is less expensive than the multi-screen display device described in Patent Document 1. However, in the case of displaying an image with the above-mentioned micro device, signal processing is performed such that the input video signals such as HDTV video signals are combined on the screen. A display video signal is generated.

  However, in this conventional image display device, even if a plurality of video signals are input in synchronization with each other, if each video signal is out of synchronization from the synchronized state due to noise or the like, From then on, the displayed video continues to be out of frame, resulting in a video that is very difficult to see. Further, there is a problem that the operation is troublesome because the normal image display is not restored unless the reset operation is manually performed.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a video signal processing apparatus that can automatically return to normal video display even when synchronization disturbance occurs in a plurality of input video signals. .

  In order to achieve the above object, the present invention provides a video signal processing apparatus for performing processing for outputting a plurality of synchronized video signals input in parallel in a predetermined order. Among them, a synchronization signal detection circuit that detects a synchronization signal in a video signal of one channel, a storage unit that stores a video signal of a plurality of channels in a unit of a fixed storage capacity, and a plurality of storages of the video signal of a plurality of channels The block is cyclically switched and written to one selected memory block, and each time the synchronization signal detection signal is supplied from the synchronization signal detection circuit, the memory block in which the storage means is being written is stored in the current memory block. A storage means writing circuit for changing from one block to the next storage block, and a plurality of channels of video signals stored in the storage means In panel order, and is obtained by a structure having a sequentially reading storage unit read circuit from writing before the storage block running write memory means is executed storage block.

  In this invention, a plurality of synchronized video signals input in parallel are written in one memory block selected by cyclically switching among a plurality of storage blocks of the storage means, and the video signal of one channel is also recorded. Each time a synchronization signal is detected, the storage block in which the storage means is being written is changed from the current storage block to the next storage block, and before the storage block in which the storage means is being written. By sequentially reading out multiple channels of video signals in series from the storage block where writing has been performed, even if there are variations in the synchronization signals of the multiple channels of video signals, there will be no variations in the synchronization signals of the multiple channels of video signals Since the write operation and the read operation are normally resumed from the beginning of the storage block having the storage means, the storage means read circuit When the output video signal is displayed on the screen, if there is a momentary variation in the synchronization signal of the video signals of multiple channels, the screen will be disturbed at that moment, but after that, it can be displayed normally again .

  According to the present invention, when there is no variation in the synchronization signals of the video signals of the plurality of channels, the write operation and the read operation are resumed normally from the beginning of the storage block having the storage means, so that the output is output from the storage means read circuit. When the video signal is displayed on the screen, if there is a momentary variation in the synchronization signal of the video signals of multiple channels, the screen may be disturbed at that moment, but it can automatically return to the normal video display, so manual This eliminates the need for a resetting operation and improves operability.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video signal processing apparatus according to the present invention. As shown in the figure, the video signal processing apparatus according to the present embodiment includes a storage means writing circuit 11 that receives a plurality of channels, for example, 4 channels of video signals to be displayed in parallel, A synchronization detection circuit 12 that detects a synchronization signal from an input video signal of one channel in an input video signal of four channels, four storage units 13-1 to 13-4 that store the video signal of each channel, and a storage unit 13 And storage means readout circuit 14 for reading out and outputting the stored video signals from -1 to 13-4.

  Here, it is assumed that the 4-channel video signals input in parallel to the storage means writing circuit 11 are synchronized with each other. Each of the storage means 13-1 to 13-4 is divided into four storage blocks (hereinafter referred to as banks) as shown in FIGS. 2A to 2D, and stores video signals in each bank. Possible configuration.

  Next, the operation of the present embodiment of FIG. 1 will be described with reference to the timing charts of FIGS. In this embodiment, when a moving image is displayed on a liquid crystal device having a resolution of 4096 pixels in the horizontal direction and 2160 pixels in the vertical direction, the screen is divided into two parts each in the horizontal direction and the vertical direction. Assume that 4-channel moving image signals corresponding to the screen are input.

  The first to fourth moving image signals of the four channels are supplied in parallel to the storage means writing circuit 11, while the moving image signal of one of the channels (for example, the first channel) is the synchronization detection circuit 12. To be supplied. Here, the moving image signal of each channel is, for example, three primary color signals R, G, and B, and each primary color signal is a digital video signal having a quantization bit number of 10 bits. It will be described as a signal.

  Since the above four-channel moving image signals are generated so as to be synchronized with each other, the vertical synchronization signal of the first channel detected by the synchronization detection circuit 12 and the vertical synchronization signals of the other three channels are in the same phase. It is. The storage means writing circuit 11 writes the 4-channel moving image signals inputted in parallel to the banks of the four storage means 13-1 to 13-4 for each channel in parallel. Each time the synchronization signal detection signal output when the vertical synchronization signal is detected is supplied, the bank in which the storage means 13-1 to 13-4 is being written is changed from the current bank to the next bank. To do.

  Accordingly, the storage means 13-1 to 13-4 store, for each frame, bank-1 → bank-2 → bank-3 → bank-4 → bank-1 → shown in FIGS. As such, the bank which is the memory location is sequentially switched in a cyclic manner.

  Thereby, the input moving image signals of the first channel, the second channel, the third channel, and the fourth channel are stored as schematically shown in FIGS. 3 (A), (B), (C), and (D). When input to the means write circuit 11 in parallel, each bank of the storage means 13-1, 13-2, 13-3, 13-4 has the same (E), (F), (G), As schematically shown in (H), each frame is stored and its storage bank is cyclically switched every frame. In FIG. 3, CH indicates a channel and F indicates a frame. Therefore, for example, “CH2-F5” means the fifth frame of the second channel (the same applies to FIG. 4).

  The storage means reading circuit 14 reads the stored moving image signal of the bank immediately before the bank of the storage means 13-1 to 13-4 to which the storage means writing circuit 11 is writing at the same rate as at the time of writing. Read within one frame writing period. In this reading, for example, the first channel CH1 and the second channel CH2 are alternately read in line order and all 1080 lines are read, and then the third channel CH3 and the fourth channel are alternately read in line order. Reading is performed so that all 1080 lines are read. As a result, the storage means readout circuit 14 can always output the 4-channel moving image signals one frame before the currently input moving image signal in series.

  Since the storage means reading circuit 14 and the storage means writing circuit 11 operate completely independently of each other, the storage means reading circuit 14 writes to which bank the storage means writing circuit 11 writes during the vertical synchronization period. The bank to be read next is determined. The 4-channel moving image signals read in series from the storage means reading circuit 14 are respectively displayed in four divided screen areas of a liquid crystal device having a resolution of 4096 pixels in the horizontal direction and 2160 pixels in the vertical direction. Displayed as one image.

  By the way, the timing chart of FIG. 3 is a timing chart when writing is normally performed in the storage units 13-1 to 13-4. Here, if the synchronization signal is disturbed due to noise or the like, the detection signal obtained by detecting the false vertical synchronization signal from the synchronization detection circuit 12 during the storage operation of the third frame F3 is the storage means writing circuit 11. , The storage means writing circuit 11 changes the bank in which the storage means 13-1 to 13-4 are being written from the current bank to the next bank.

  Accordingly, in this case, the storage units 13-1 to 13-4 store the third frame F3 of the corresponding channel up to the middle of the bank 3, as schematically shown in FIGS. Subsequently, the remainder of the third frame F3 of the corresponding channel is stored from the middle of the bank 4. Assuming that the vertical synchronization signal is normally detected after the fourth frame F4, the storage contents of each bank of the storage means 13-1 to 13-4 are schematically shown in FIGS. It will continue to change.

  Further, the storage moving image signal is read out from the storage means readout circuit 14 as schematically shown in FIG. Here, at the time of reading out the third frame, as shown schematically in FIGS. 4A to 4D, the third frame F3 is halfway in each bank 3 of the storage means 13-1 to 13-4. Since it is stored, a normal moving image signal of the third frame F3 is read from the beginning of the third frame F3 to the middle line, but after that, noise or other stored signals are output until the end of the third frame. Read out.

  At the time of reading the next fourth frame, since the remaining image signals of the third frame F3 are stored in the banks 4 of the storage means 13-1 to 13-4 from the middle, the reading period of the next frame Then, noise or other stored signals are read from the beginning to the middle, and the remaining moving image signals of the third frame F3 are read from the middle of the frame reading period. In the subsequent frame readout period, the moving image signals in the fourth and subsequent frames are normally read out.

  Therefore, in the present embodiment, even if a disturbance occurs in the vertical synchronization signal during the storage operation of the third frame F3 due to noise or the like, the disturbance of the image of the third frame occurs over a period of two frames. That is a moment, after which it can automatically return to normal image display. Therefore, the state of image degradation can be made extremely shorter than before, and a manual reset operation for returning to a normal image display is not required, and operability can be improved.

  The present invention is not limited to the above embodiment, and the number of channels of video signals input in parallel is appropriately selected according to the specifications of the input video signal and the resolution of the display device. Of course, it is not limited to four channels. The present invention can also be applied to a multi-screen compatible device that inputs and displays a plurality of video signals.

It is a block diagram of one embodiment of the present invention. It is explanatory drawing of the bank (memory block) of the memory | storage means in FIG. 2 is a timing chart for explaining operations during normal writing in FIG. 1. 2 is a timing chart for explaining an operation when a loss of synchronization occurs in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Memory means writing circuit 12 Synchronization detection circuit 13-1 to 13-4 Memory means 14 Memory means reading circuit

Claims (1)

A video signal processing apparatus that performs processing of outputting video signals of a plurality of channels that are synchronized with each other in parallel and that are output in a predetermined order,
A sync signal detection circuit for detecting a sync signal in the video signal of one channel among the video signals of the plurality of channels;
Storage means for storing the video signals of the plurality of channels in a constant storage capacity unit;
Each time the video signal of the plurality of channels is cyclically switched among the plurality of storage blocks of the storage means and written to one storage block, and each time a synchronization signal detection signal is supplied from the synchronization signal detection circuit, A storage means writing circuit for changing a storage block in which the storage means is being written from a current storage block to a next storage block;
The video signals of the plurality of channels stored in the storage means are sequentially written in a predetermined channel order and from a storage block in which writing has been performed prior to the storage block in which the writing of the storage means has been executed. A video signal processing apparatus comprising: a storage means reading circuit for reading.

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