JP2007300568A - Video signal processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in order to output an analog signal inputted from the outside with an internal synchronizing signal reference generated by frequency-dividing a reference clock, it is necessary to perform frame synchronization for changing riding of a synchronizing signal but in a case where a frame rate of an input signal is lower than that of an internal synchronizing signal since the input signal is an interlace signal, when a frame video image is double outputted, a fast moving and temporally reversing video image is outputted and when a field video image is double outputted, a still image of which the vertical resolution is reduced, is outputted. <P>SOLUTION: A video signal processing apparatus comprises: a memory means for recording a decoded video signal; a first memory control means for reading a video signal from the memory means, a filter means for converting a video signal read from the first memory control means to the signal of an output image size; a video converting means for converting an analog video signal into the signal of a format readable for the first memory control means; and a second memory control means for writing an output of the video converting means into the memory means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus, and more particularly to a frame synchronization operation for changing a video signal input from the outside to a synchronizing signal to be output.

  In recent years, TVs and recorders that receive digital broadcasts output a decoded video signal based on a synchronization signal generated by dividing a clock synchronized with PCR when outputting a decoded digital video. This synchronization signal is output with guaranteed continuity, except when switching the resolution of the video to be output, in order to prevent image disturbance during screen display. Also, in many devices, even when the resolution of the input video changes, the image is converted by filter interpolation so that the image is not disturbed during screen display so that the output always has the same resolution and frame rate. I have to. In these devices, when displaying and outputting an asynchronous video signal input from the external input terminal, as a method to guarantee the continuity of the output synchronization signal, the input video signal is written to the memory, and the output synchronization signal reference In general, a frame sync that reads out in units of frame images is used.

  FIG. 5 is a block diagram of a conventional video signal processing apparatus, where 1 is an input terminal 1, 2 is a decoder, 3 is memory means 1, 4 is first memory control means, 5 is filter means, and 6 is output. Terminal 7, input terminal 2, 8 AD conversion, 9 memory means 2, 10 color demodulation means 11, second memory control means 20, YC separation, YC separation based on line correlation 2 Dimensional YC separation 21, three-dimensional YC separation 22 that performs YC separation based on frame correlation, motion detection 23 that generates motion information from frame differences, two-dimensional YC separation output and three-dimensional YC separation based on motion information The selector 24 is configured to switch the output. In the figure, a solid line is a path through which a video signal flows, and a broken line indicates a path of control information.

  At the time of digital broadcast reception, an MPEG compressed stream is input from the input terminal 1 of 1, and the video signal decoded by the decoder of 2 is placed in the area (a) of the memory means 1 of 3. The first memory control unit 4 reads out the video signal based on the information from the decoder based on the output synchronization signal reference generated by dividing the clock with the clock synchronized with the PCR of the stream to be decoded. At the same time, the image size information from the decoder and the output image resolution are controlled from the output terminal 6 by controlling the horizontal and vertical enlargement ratios of the 5 filter means.

  At the time of analog broadcast reception, the analog composite video signal inputted from the input terminal 2 of 7 is converted into digital data by AD conversion of 8, and then separated into a luminance signal and a modulated color signal by 20 YC separation. The modulated color signal is converted into a color difference signal by 10 color demodulating means, and then written together with the luminance signal into the area (b) of the memory means 1 by 11 second memory control means. In 20 YC separation, three-dimensional YC separation is performed using frame delay data generated by writing to 9 memory means 2.

  When the digital broadcast is switched to the analog broadcast, the video signal read by the four first memory control means from the memory means 1 is switched to the signal written in the area (b) of the memory means 1. At the time of analog input, since the input video signal and the video signal to be output are asynchronous, information on the video write position of the memory control unit 11 is provided so that the video is not overtaken or overtaken on the screen. Based on this, frame synchronization is performed by controlling the readout video in units of frames.

An example of a frame synchronization operation when the video signal input from the external input terminal is an interlace signal and the output frame period is shorter than the frame period of the input signal will be described with reference to FIG. 6A shows an input video signal, and FIG. 6B shows an output video after frame synchronization. In the figure, the frame image is represented by An (n = 1, 2,...), The first field image of An is represented by An-1, and the second field image is represented by An-2. The synchronization signal is switched by writing the input signal to the memory in units of frames and reading it on the basis of the output synchronization signal. Since the frame period to be output is shorter than the frame period of the input signal, at the timing indicated by X in the figure, the timing on the video writing side and the reading side are close, and the frame image A1 one frame before is not generated so that screen overtaking does not occur. Is output again. For this reason, the A1-2 field image is output after the A1-1 field image, and an image whose time has returned is displayed in a fast-moving image. For this reason, instead of outputting the A1 frame image at the timing X in FIG. 6, a method of generating and outputting an interpolated image from the A1 and A2 images in advance has been proposed (see, for example, Patent Document 1). ).
JP 2001-309202 A

  The problem to be solved is that a time return indicated by X in FIG. 6 occurs in a normal frame sync structure. In addition, in order to prevent this problem, it is necessary to add a considerably large circuit such as an interpolation image creating unit.

  A video signal processing apparatus according to the present invention includes a decoder for decoding an encoded and compressed stream, memory means for recording a video signal decoded by the decoder, and first memory control means for reading the video signal from the memory means. A filter means for converting the video signal read by the first memory control means into an output image size, a video conversion means for converting the analog video signal into a format readable by the first memory control means, Second memory control means for writing the output of the video conversion means to the memory means, and changing the address read by the first memory control means to the position of the video signal written by the second memory control means The analog video signal can be output from the filter means.

  In the video signal processing apparatus according to the present invention, when the first memory control means starts reading the frame video, the next frame video of the previously read frame video is read or the same video as the previously read frame video Is controlled based on the video writing information of the second memory control means whether to read the next frame video from the previously read frame video and to read the next frame video. .

  Further, in the video signal processing apparatus according to the present invention, when the video signal to be processed is an interlace signal and the first memory control means reads again the same video signal as the previously read frame video, the readout that outputs the first field At the timing, the video signal of the second field on the memory is read, and at the read timing at which the second field is output, the video signal of the second field on the memory is read again.

  Further, in the video signal processing device according to the present invention, the video conversion means has a function of delaying the video signal by frame, generating a difference between frames of the video, and processing, and the video signal to be processed is an interlace signal, When the first memory control means reads again the same video signal as the previously read frame video, the video signal of the first field on the memory is read or the video of the second field is read at the read timing for outputting the first field. Whether to read a signal is switched based on information generated by the inter-frame difference of the video generated by the video conversion means.

  In the video signal processing apparatus according to the present invention, the first memory control means controls the filter means when reading the video signal of the second field on the memory at the read timing for outputting the first field. Thus, the image center of gravity of the field image to be output is converted into the image center of gravity of the first field and output.

  In the video signal processing apparatus according to the present invention, the video conversion means performs noise reduction using a difference between frames of the video.

  In the video signal processing apparatus according to the present invention, the video conversion means separates the luminance signal and the modulated color signal from the composite video signal using the inter-frame difference of the video.

  In the video signal processing apparatus according to the present invention, the video conversion means includes an AD conversion apparatus, a YC separation apparatus, and a color demodulation means, and the YC separation apparatus includes a two-dimensional YC separation means, a three-dimensional YC separation means, A motion detection means is provided.

  In the video signal processing apparatus according to the present invention, the video conversion means includes an AD conversion apparatus, a two-dimensional YC separation apparatus, a three-dimensional NR apparatus, and a color demodulation means, and the three-dimensional NR apparatus serves as a motion detection means. It is characterized by having.

  In the video signal processing apparatus according to the present invention, the video conversion means includes an AD conversion apparatus, a two-dimensional YC separation means, a three-dimensional YC separation means, and a YC separation apparatus and a color demodulation means provided with a motion detection means. Further, a three-dimensional NR device is disposed after the color demodulating means via a selector means.

  The video signal processing apparatus of the present invention controls the readout position from the memory and the image centroid conversion of the output resolution conversion filter means by the motion information used in the three-dimensional processing in the input analog signal processing, By adding a small number of circuits, it is possible to obtain a time-reversed video output with a fast-moving interlace signal and a good frame-synchronized image with no resolution degradation in a still image.

  In equipment that supports reception of both digital and analog broadcasts, we have realized a good frame-synchronized image without time-reversed video output with a fast-moving interlaced signal and resolution degradation in still images.

(Embodiment 1)
FIG. 1 is a block diagram of a first embodiment of the present invention, where 1 is an input terminal 1, 2 is a decoder, 3 is memory means 1, 4 is first memory control means, 5 is filter means, 6 is an output terminal, 7 is an input terminal 2, 8 is AD conversion, 9 is memory means 2, 10 is color demodulation means, 11 is second memory control means, 20 is YC separation, and YC separation based on line correlation Two-dimensional YC separation 21 for performing motion detection, three-dimensional YC separation 22 for performing YC separation based on frame correlation, motion detection 23 for generating motion information from frame differences, two-dimensional YC separation output based on motion information, and 3 The selector 24 is configured to switch the dimension YC separation output. In the figure, a solid line is a path through which a video signal flows, and a broken line indicates a path of control information.

  At the time of digital broadcast reception, an MPEG compressed stream is input from the input terminal 1 of 1, and the video signal decoded by the decoder of 2 is placed in the area (a) of the memory means 1 of 3. The first memory control unit 4 reads out the video signal based on the information from the decoder based on the output synchronization signal reference generated by dividing the clock with the clock synchronized with the PCR of the stream to be decoded. At the same time, the image size information from the decoder and the output image resolution are output from 6 output terminals by controlling the horizontal and vertical enlargement ratios of the 5 filter means.

  At the time of analog broadcast reception, the analog composite video signal inputted from the input terminal 2 of 7 is converted into digital data by AD conversion of 8, and then separated into a luminance signal and a modulated color signal by 20 YC separation. The modulated color signal is converted into a color difference signal by 10 color demodulating means, and then written together with the luminance signal into the area (b) of the memory means 1 by 11 second memory control means. In 20 YC separation, three-dimensional YC separation is performed using frame delay data generated by writing to 9 memory means 2.

  When the digital broadcasting is switched to the analog broadcasting, the information written by the 11 second memory control means to the memory means 1 by the 11 second memory control means is read by the 4 first memory control means from the 3 memory means 1 Switching is performed by reading based on the above. The synchronization signal used for reading by the first memory control unit 4 is guaranteed to be continuous before and after switching. Further, when the video signal input from the external input terminal 2 of 7 is an interlace signal, and a frame image is repeatedly output by frame synchronization, it is based on motion information obtained from motion detection of 23 in 20 YC separations. Thus, control is performed so as to obtain an optimum frame-synchronized image by controlling the interpolation phase of the field image read by the first memory control unit 4 and the filter unit 5.

  Hereinafter, the frame synchronization operation will be described with reference to FIG. 2 (a) and 2 (c) show video signals written in the third memory means 1 by the eleventh second memory control means, and FIGS. 2 (b) and 2 (d) show the four first signals. The video signal read by a memory control means is shown. 2A and 2B show the case of a video signal with intense motion, and FIGS. 2C and 2D show the case of a video signal close to a still image with little motion. In the figure, the frame image is represented by An (n = 1, 2,...), The first field image of An is represented by An-1, and the second field image is represented by An-2. At the timing of X when the video writing side and reading side timing are close and the frame image needs to be repeated, it is detected that the motion information obtained from the motion detection of 23 in FIG. When the frame image of A1 is output repeatedly, the second field image of A1 based on the position of the second field image of A1 transmitted from the second memory control unit of FIG. 11 at the output signal timing of the first field. Is read. At this time, since the center of gravity of the image is shifted by one line, the filter unit 5 in FIG. 1 is controlled to change the setting for enlargement / reduction to the output resolution, and the correction of the center of gravity of the image is also performed. In the figure, an image obtained by converting the image centroid of the video signal A1-2 into the centroid of the first field is represented by (A1-2) '. As a result, it is possible to prevent the output of the time-returned image even at the timing of X.

  In a still image, when the image center of gravity is converted, the reduction in vertical resolution becomes conspicuous. For this reason, when the motion information obtained from the motion detection of 23 in FIG. 1 is smaller than a predetermined value, as shown in (d), at the timing of X, at the first field output timing, the first field image A1-1. The filter means 5 in FIG. 1 is controlled so as not to perform image center of gravity correction, and is controlled in units of pixels so that the vertical resolution does not deteriorate.

  The embodiment shown in FIG. 3 is good for a device that supports digital signal reception and external analog signal input such as a VTR, and that there is no time-returned video output with a fast-moving interlace signal and no resolution degradation in still images. A frame-synchronized image was realized.

(Embodiment 2)
FIG. 3 is a block diagram of Embodiment 2 of the device of the present invention, wherein 1 to 10 are the same as FIG. Reference numeral 11 denotes second memory control means for writing luminance and color difference signals and reading luminance and color difference signals one frame before. 20 is YC separation, 30 is a three-dimensional NR, and a frame difference 33 for generating a difference signal between the input signal and a frame delayed signal read by the second memory control means 11 and motion information based on the frame difference signal , A noise extraction 32 that generates a noise signal based on the frame difference signal and the motion information, and a noise removal 31 that removes the noise signal from the input signal. The meanings of the thick line, solid line, and broken line in the route are all the same as those in FIG. Since the VTR signal input from the outside is a non-standard signal, the YC separation means 21 uses a configuration of only two-dimensional YC separation that performs separation using line correlation. Further, since the S / N of the VTR signal is poor, 30 three-dimensional NRs that perform noise reduction using frame correlation are configured. The difference from the first embodiment is that the generation source of motion information for controlling frame synchronization is the motion detection 34 within 30 three-dimensional NR.

(Embodiment 3)
FIG. 4 is a block diagram of Embodiment 3 of the device of the present invention, wherein 1 to 20 are the same as FIG. 1, and by providing the 3DNR 30 and the selector means 40 in FIG. In the case of a standard signal that does not apply dimension NR, noise information can be reduced using frame correlation for non-standard signals that are not subjected to three-dimensional YC separation using motion information obtained from three-dimensional YC separation. In this case, the frame synchronization can be controlled using the motion information obtained from the three-dimensional NR. All other configurations are the same as in FIG.

  The video signal processing apparatus according to the present invention integrates motion information generated by the inter-frame difference of the video in the video conversion means in the field or frame to perform motion determination, and performs frame repeat at the time of frame synchronization. The switching between (b) and (d) in FIG. 2 can also be applied to devices that perform switching in field or frame units.

Block diagram of the first embodiment of the present invention Explanatory drawing of the frame synchronization operation | movement of the 1st Embodiment of this invention Block diagram of the second embodiment of the present invention Block diagram of the third embodiment of the present invention Block diagram of conventional embodiment Illustration of conventional frame sync operation

Explanation of symbols

1 Input terminal 1
2 Decoder 3 Memory 1
4 First memory control means 5 Filter means 6 Output terminal 7 Input terminal 2
8 AD conversion means 9 Memory means 2
DESCRIPTION OF SYMBOLS 10 Color demodulation means 11 2nd memory control means 20 YC separation means 21 2D YC separation block 22 3D YC separation block 23 Motion detection block 24 Selector block 30 3D NR
31 noise removal block 32 noise extraction block 33 frame difference block 34 motion detection block 40 selector means

Claims (10)

A decoder for decoding the encoded and compressed stream; memory means for recording the video signal decoded by the decoder; first memory control means for reading the video signal from the memory means; and the first memory control Filter means for converting the video signal read from the means into an output image size, video conversion means for converting the analog video signal into a format readable by the first memory control means, and output of the video conversion means. Second memory control means for writing to the memory means, and by changing the address read by the first memory control means to the address written by the second memory control means, A video signal processing apparatus characterized in that a video signal can be output. When the first memory control means starts reading the frame image, the next frame image after the previously read frame image is read, the same image as the previously read frame image is read again, or the next frame image read next time 2. The video signal processing apparatus according to claim 1, wherein whether to skip the next frame video and read the next frame video is controlled based on the video write address of the second memory control means. When the video signal to be processed is an interlace signal and the first memory control means reads again the same video signal as the previously read frame video, the video signal of the second field on the memory is read at the read timing for outputting the first field. 3. The video signal processing apparatus according to claim 2, wherein the video signal of the second field on the memory is read again at the read timing for reading out the second field and outputting the second field. The video converting means has a function of delaying the video signal by frame and generating a difference between the frames of the video to perform processing. The video signal to be processed is an interlace signal, and the frame video previously read by the first memory control means When the same video signal is read again, the video conversion means generates whether to read the video signal of the first field on the memory or the video signal of the second field at the read timing for outputting the first field. 3. The video signal processing apparatus according to claim 2, wherein switching is performed based on information generated by a difference between frames of video. When the first memory control means reads the video signal of the second field on the memory at the read timing for outputting the first field, the image gravity center of the field video to be outputted is controlled by controlling the filter means. 5. The video signal processing device according to claim 3, wherein the video signal processing device converts the video gravity center of the first field and outputs the converted image. 5. The video signal processing apparatus according to claim 4, wherein the video conversion means performs noise reduction using a difference between frames of the video. 5. The video signal processing apparatus according to claim 4, wherein the video conversion means separates the luminance signal and the modulated color signal from the composite video signal using the inter-frame difference of the video. The video conversion means comprises an AD conversion means, a YC separation means, and a color demodulation means. The YC separation means is a two-dimensional YC separation means, a three-dimensional YC separation means, a first motion detection means, and a first selector. 2. The video signal processing according to claim 1, wherein the first selector means selectively selects the two-dimensional YC separation means and the three-dimensional YC separation means. apparatus. The video conversion means comprises an AD conversion means, a two-dimensional YC separation means, a three-dimensional NR means, and a color demodulation means, and the three-dimensional NR device comprises a second motion detection means. The video signal processing apparatus according to 1. The video conversion means is composed of an AD conversion device, a two-dimensional YC separation means, a YC separation means and a color demodulation means provided with a three-dimensional YC separation means and a first motion detection means. When a two-dimensional YC separation unit is used in the video conversion unit, a signal for controlling the first memory control unit and the filter unit is provided. 2. The video signal processing apparatus according to claim 1, wherein the second selector means is configured to select a signal output from the second motion detecting means.

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