JP2003059290A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003059290A5 JP2003059290A5 JP2002145210A JP2002145210A JP2003059290A5 JP 2003059290 A5 JP2003059290 A5 JP 2003059290A5 JP 2002145210 A JP2002145210 A JP 2002145210A JP 2002145210 A JP2002145210 A JP 2002145210A JP 2003059290 A5 JP2003059290 A5 JP 2003059290A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- read
- error detection
- correction
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002145210A JP4050091B2 (ja) | 2001-06-04 | 2002-05-20 | 半導体メモリ装置 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001168706 | 2001-06-04 | ||
JP2001-168706 | 2001-06-04 | ||
JP2002145210A JP4050091B2 (ja) | 2001-06-04 | 2002-05-20 | 半導体メモリ装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2003059290A JP2003059290A (ja) | 2003-02-28 |
JP2003059290A5 true JP2003059290A5 (ko) | 2005-08-04 |
JP4050091B2 JP4050091B2 (ja) | 2008-02-20 |
Family
ID=26616317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002145210A Expired - Fee Related JP4050091B2 (ja) | 2001-06-04 | 2002-05-20 | 半導体メモリ装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4050091B2 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005025827A (ja) | 2003-06-30 | 2005-01-27 | Toshiba Corp | 半導体集積回路装置およびそのエラー検知訂正方法 |
EP1657723B1 (en) | 2003-08-18 | 2013-03-06 | Fujitsu Semiconductor Limited | Semiconductor memory and operation method of semiconductor memory |
JP2006099911A (ja) | 2004-09-30 | 2006-04-13 | Toshiba Corp | 半導体集積回路装置 |
JP2006190425A (ja) * | 2005-01-07 | 2006-07-20 | Nec Electronics Corp | 半導体記憶装置 |
JP4703220B2 (ja) * | 2005-03-04 | 2011-06-15 | 株式会社東芝 | 半導体記憶装置 |
JP4643334B2 (ja) * | 2005-03-31 | 2011-03-02 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
JP4547313B2 (ja) * | 2005-08-01 | 2010-09-22 | 株式会社日立製作所 | 半導体記憶装置 |
JP2007066423A (ja) * | 2005-08-31 | 2007-03-15 | Toshiba Corp | 半導体集積回路装置 |
JP4820795B2 (ja) | 2007-10-04 | 2011-11-24 | パナソニック株式会社 | 半導体記憶装置 |
JP2010020839A (ja) * | 2008-07-10 | 2010-01-28 | Panasonic Corp | 半導体記憶装置 |
JP2013033560A (ja) | 2009-12-03 | 2013-02-14 | Panasonic Corp | 半導体記憶装置 |
JP7016332B2 (ja) * | 2019-07-05 | 2022-02-04 | 華邦電子股▲ふん▼有限公司 | 半導体メモリ装置 |
-
2002
- 2002-05-20 JP JP2002145210A patent/JP4050091B2/ja not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7458004B2 (en) | Semiconductor storage device | |
JP3892832B2 (ja) | 半導体記憶装置 | |
KR102002925B1 (ko) | 메모리 모듈, 그것을 포함하는 메모리 시스템, 그것의 구동 방법 | |
KR101750662B1 (ko) | 데이터 에러 교정용 회로, 장치, 및 방법 | |
KR100842680B1 (ko) | 플래시 메모리 장치의 오류 정정 컨트롤러 및 그것을포함하는 메모리 시스템 | |
EP1815338B1 (en) | Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory | |
US7299400B2 (en) | Error correction circuit | |
US8286054B2 (en) | Semiconductor memory, operating method of semiconductor memory, and system | |
US10803971B2 (en) | Device for supporting error correction code and test method thereof | |
US8307260B2 (en) | Memory apparatus and method using erasure error correction to reduce power consumption | |
KR102014624B1 (ko) | 오류 정정 코딩이 있는 메모리 연산을 파이프라이닝하기 위한 방법 및 장치 | |
JP2005025827A (ja) | 半導体集積回路装置およびそのエラー検知訂正方法 | |
JP2001351398A (ja) | 記憶装置 | |
US8122320B2 (en) | Integrated circuit including an ECC error counter | |
JP2003059290A5 (ko) | ||
US7949933B2 (en) | Semiconductor integrated circuit device | |
US6799291B1 (en) | Method and system for detecting a hard failure in a memory array | |
JP2008021390A (ja) | 半導体記憶装置 | |
JP2007066423A (ja) | 半導体集積回路装置 | |
JP4050091B2 (ja) | 半導体メモリ装置 | |
US8225171B2 (en) | Semiconductor memory device having an error correction function and associated method | |
US7075851B2 (en) | Semiconductor memory device inputting/outputting data and parity data in burst operation | |
US11417413B2 (en) | Semiconductor memory apparatus and method for reading the same | |
JP4742553B2 (ja) | 記憶装置 | |
US8078947B2 (en) | Data processing circuit and method |