JP2003051560A - Package of semiconductor device - Google Patents

Package of semiconductor device

Info

Publication number
JP2003051560A
JP2003051560A JP2001235731A JP2001235731A JP2003051560A JP 2003051560 A JP2003051560 A JP 2003051560A JP 2001235731 A JP2001235731 A JP 2001235731A JP 2001235731 A JP2001235731 A JP 2001235731A JP 2003051560 A JP2003051560 A JP 2003051560A
Authority
JP
Japan
Prior art keywords
metal base
adhesive
groove
case
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001235731A
Other languages
Japanese (ja)
Other versions
JP4710194B2 (en
Inventor
Shin Soyano
伸 征矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001235731A priority Critical patent/JP4710194B2/en
Publication of JP2003051560A publication Critical patent/JP2003051560A/en
Application granted granted Critical
Publication of JP4710194B2 publication Critical patent/JP4710194B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent imperfect wire bonding to inner leads of main circuit terminals which are subjected to insert molding on an enveloping case, by improving the shape of an adhesive agent spreading trench on a bottom surface of the case bonded to a metal base. SOLUTION: In a package structure, the metal base 1 mounting a power circuit is bonded to the bottom surface of the enveloping case 2 which is collectively formed integrally with terminals, and wire bonding is performed by an ultrasonic compression bonding method on parts between the inner leads 4a of the main circuit terminals 4 which are subjected to insert molding on the case 2, and the power circuit. In the structure, corresponding to parts in which at least the inner leads of the main circuit terminals overlap vertically with inner leads of other terminals, a trench width enlarging part 2b wherein trench width is enlarged partially toward the lower surface regions of the inner leads is formed in a recessed trench 2a which is formed on the bottom surface of the case 2 and used for spreading adhesive agent. The lower surface region of the inner leads 4a is bonded perfectly to the metal base 1, so that ultrasonic bonding of wires is stabilized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、インバータ装置な
どに適用するインテリジェントパワーモジュール(IP
M:Intelligent Power Module) を対象とした半導体装
置のパッケージ構造に関する。
TECHNICAL FIELD The present invention relates to an intelligent power module (IP) applied to an inverter device or the like.
M: relates to the package structure of a semiconductor device targeted for Intelligent Power Module).

【0002】[0002]

【従来の技術】まず、頭記したインバータ装置に適用す
るIPMを例に、そのモジュールの組立構造を図2(a),
(b) ないし図4に、またその等価回路を図5に示す。図
において、1は放熱用の金属ベース(銅ベース)、2は
樹脂成形品になる端子一体形の外囲ケース、3は外囲ケ
ース2の上面に被着した上蓋、4は外囲ケース2と一体
にインサート成形したパワー回路に対する入,出力用の
主回路端子(銅フレーム端子)、5は制御回路に対する
外部端子ブロック、6は金属ベース1にセラミック基板
等の絶縁回路基板を介してはんだマウントしたパワー回
路(インバータ回路)、7は二階建て方式でパワー回路
6の上方に配置した制御回路、8はパワー回路6と制御
回路7の間を接続するよう外囲ケース2の内周側に一体
成形した中継端子ブロック、9は内部配線用のボンディ
ングワイヤであり、ボンディングワイヤ9はパワー回路
6の各半導体素子とその回路基板の導体パターンとの
間、および回路基板と主回路端子4,中継端子8の間に
配線されている。
2. Description of the Related Art First, as an example of an IPM applied to the above-mentioned inverter device, the module assembly structure is shown in FIG.
(b) to FIG. 4 and its equivalent circuit are shown in FIG. In the figure, 1 is a metal base (copper base) for heat dissipation, 2 is a terminal integrated type enclosure case which is a resin molded product, 3 is a top cover attached to the upper surface of the enclosure case 2, and 4 is an enclosure case 2 Input / output main circuit terminals (copper frame terminals) for the power circuit integrally insert-molded with, 5 is an external terminal block for the control circuit, 6 is a solder mount on a metal base 1 via an insulating circuit board such as a ceramic board. Power circuit (inverter circuit), 7 is a control circuit arranged above the power circuit 6 in a two-story system, and 8 is integrated with the inner peripheral side of the outer casing 2 so as to connect between the power circuit 6 and the control circuit 7. The molded relay terminal block 9 is a bonding wire for internal wiring, and the bonding wire 9 is provided between each semiconductor element of the power circuit 6 and the conductor pattern of the circuit board, and a circuit board. A main circuit terminal 4 are wired between the relay terminals 8.

【0003】ここで、図示例のパワー回路6は、図5に
示すインバータ回路の上アーム回路,下アーム回路およ
びブレーキ回路に対応する7個組のパワー半導体素子
(IGBT)6a,およびフリーホイーリングダイオー
ド6bが、2枚に分けて左右に並置した回路基板(セラ
ミック基板)6c-1,6c-2に振り分けて実装されてお
り、各回路基板6c-1,6c-2の導体パターンと対応す
るように主回路端子4が後記のように左右一列に配列し
て外囲ケース2にインサート成形されている。一方、制
御回路7はプリント基板に前記パワー半導体素子6bの
駆動用ICを含む各種回路部品を実装した構成になり、
図2(b) で示すように制御回路の外部端子ブロック5か
らケース内側方に突き出たリードと中継端子ブロック8
から上方に起立するリードとの間に跨がって架設されて
いる。
Here, the power circuit 6 of the illustrated example is a set of seven power semiconductor devices (IGBTs) 6a corresponding to the upper arm circuit, the lower arm circuit and the brake circuit of the inverter circuit shown in FIG. 5, and free wheeling. The diodes 6b are separately mounted on the circuit boards (ceramic boards) 6c-1 and 6c-2 which are divided into two pieces and arranged side by side. The diodes 6b correspond to the conductor patterns of the circuit boards 6c-1 and 6c-2. As described below, the main circuit terminals 4 are arranged in a line on the left and right sides and insert-molded in the enclosure case 2. On the other hand, the control circuit 7 has a structure in which various circuit components including a driving IC for the power semiconductor element 6b are mounted on a printed circuit board,
As shown in Fig. 2 (b), the lead protruding inside the case from the external terminal block 5 of the control circuit and the relay terminal block 8
Is installed so as to straddle the lead that stands up from.

【0004】また、図2(a) でケース上蓋3にマーキン
グした端子記号について、P,Nは直流の入力端子、
U,V,Wは三相の交流出力端子、Bはブレーキ部の端
子、No1〜19は制御端子の端子番号を表している。そ
して、端子記号P,N,U,V,Wに対応する各主回路
端子(銅フレーム端子)4は図4(a) 〜(c) で表すよう
なレイアウトに配列しており、特にU,V,W相の交流
出力端子については、そのインナーリードが前記した左
右2枚の回路基板6c-1,6c-2に形成したU,V,W
相に対応する導体パターンに跨がるよう二股状に延在
し、かつ図2(b) で示すようにL字状に屈曲したインナ
ーリード4aを外囲ケース2の内周側に引出し、後記の
ようにインナーリード4aの先端部とパワー回路6との
間でワイヤボンディングを施して接続するようにしてい
る。また、この端子配列においては、図示のようにV,
W相端子のインナーリードとNおよびU相端子のインナ
ーリードとが上下に重なって並ぶように配置されてい
る。
Further, regarding terminal symbols marked on the case lid 3 in FIG. 2 (a), P and N are DC input terminals,
U, V, and W are three-phase AC output terminals, B is a terminal of the brake unit, and Nos. 1 to 19 are terminal numbers of control terminals. The main circuit terminals (copper frame terminals) 4 corresponding to the terminal symbols P, N, U, V, W are arranged in a layout as shown in FIGS. Regarding AC output terminals of V and W phases, U, V and W whose inner leads are formed on the two left and right circuit boards 6c-1 and 6c-2 described above.
An inner lead 4a extending in a bifurcated manner so as to straddle the conductor pattern corresponding to the phase and bent in an L shape as shown in FIG. As described above, wire bonding is performed between the tip portion of the inner lead 4a and the power circuit 6 for connection. Also, in this terminal arrangement, as shown in the drawing, V,
The inner leads of the W-phase terminal and the inner leads of the N- and U-phase terminals are arranged so as to be vertically overlapped with each other.

【0005】前記構成のIPMは次記の手順で組み立て
られる。まず、パワー回路6の回路基板6cを金属ベー
ス板1にはんだマウントし、続いて金属ベース板1の上
に端子一体形の外囲ケース2を接着剤で接合し、この状
態でパワー回路基板6cの導体パターンと外囲ケース2
から内方に突き出した主回路端子4のインナーリード4
aとの間,および中継端子ブロック8のリードとの間を
超音波圧着法によりワイヤボンディングを施して内部配
線する。次に外囲ケース2の上面中央寄りに制御回路の
外部端子ブロック5を組付けたうえで、該端子ブロック
5からケース内方に突き出した端子リードの先端部と中
継端子ブロック8から上向きに突き出したリードの間に
跨がって制御回路7のプリント基板を二階建て式に架け
渡してはんだ付けする。次に、この組立状態でパッケー
ジ内にゲル状充填材(例えばシリコーンゲル)を注入し
て主回路6,制御回路7を封止し、最後に外囲ケース2
に上蓋3を被せて接着剤で固着する。
The IPM having the above structure is assembled by the following procedure. First, the circuit board 6c of the power circuit 6 is solder-mounted on the metal base plate 1, and then the terminal-integrated enclosure case 2 is bonded onto the metal base plate 1 with an adhesive. In this state, the power circuit board 6c Conductor pattern and enclosure case 2
Inner lead 4 of main circuit terminal 4 protruding inward from
The internal wiring is performed by performing wire bonding between the terminal a and the lead of the relay terminal block 8 by the ultrasonic pressure bonding method. Next, after assembling the external terminal block 5 of the control circuit near the center of the upper surface of the outer case 2, the tip end of the terminal lead protruding inward from the terminal block 5 and the relay terminal block 8 are projected upward. The printed circuit board of the control circuit 7 is laid across the two leads in a two-story manner and soldered. Next, in this assembled state, a gel filler (for example, silicone gel) is injected into the package to seal the main circuit 6 and the control circuit 7, and finally, the outer case 2
The upper lid 3 is put on and fixed with an adhesive.

【0006】ここで、金属ベース1と外囲ケース2を接
着剤で接合するには、あらかじめ金属ベース1の外周縁
と対向する外囲ケース2の底面周域に沿って接着剤を塗
布する等幅の浅い凹溝2a(図2(b) 参照)を形成して
おき、この凹溝2aのルートに沿って移動する接着剤デ
ィスペンサ(図示せず)から供給した流動性の接着剤を
均一に塗布し、続いて金属ベース1の上に外囲ケース2
を重ね合わせ、加圧力を加えた状態で接着剤を硬化させ
て接合するようにしている。
Here, in order to join the metal base 1 and the outer case 2 with an adhesive, the adhesive is applied in advance along the peripheral area of the bottom surface of the outer case 2 facing the outer peripheral edge of the metal base 1. The shallow groove 2a (see FIG. 2 (b)) is formed, and the fluid adhesive supplied from an adhesive dispenser (not shown) that moves along the route of the groove 2a is evenly distributed. Apply and then enclose the case 2 on the metal base 1.
Are piled up, and the adhesive is hardened to bond them while applying a pressure.

【0007】また、主回路端子4のインナーリード4a
とパワー回路6の回路基板6cとの間を接続する超音波
ボンディング工程では、周知のように金属ベース1を下
にしてモジュール組立体を超音波ボンダのワークホルダ
に載せ、主回路端子4のインナーリード4aの上に重ね
たボンディングワイヤ(Alワイヤ)をボンダのホーンに
取付けたウエッジで押圧しながら超音波振動を加える。
これにより、超音波振動の摩擦によって接合面の不純物
(酸化物)を除去し、同時に生じる接合面の発熱により
ワイヤが塑性変形を生じて電極部とワイヤとが固相接合
される。
The inner lead 4a of the main circuit terminal 4
In the ultrasonic bonding process for connecting between the power circuit 6 and the circuit board 6c of the power circuit 6, as is well known, the module assembly is placed on the work holder of the ultrasonic bonder with the metal base 1 facing down, and the inner of the main circuit terminal 4 is inserted. Ultrasonic vibration is applied while pressing the bonding wire (Al wire) stacked on the lead 4a with the wedge attached to the horn of the bonder.
As a result, impurities (oxides) on the joint surface are removed by the friction of ultrasonic vibration, and the wire is plastically deformed by the heat generated on the joint surface at the same time, so that the electrode portion and the wire are solid-phase joined.

【0008】[0008]

【発明が解決しようとする課題】ところで、前記構成に
なるIPMは、その組立工程で次記のような解決すべき
問題点のあることが判明した。すなわち、 (1) 金属ベース1に外囲ケース2を接着剤により接合し
た状態で、外囲ケース2と一体にインサート成形した主
回路端子4のインナーリード4aの先端部にボンディン
グワイヤ8を超音波圧着法によりボンディングする際
に、外囲ケース2の内周側に引出した前記インナーリー
ド4aの下面域(図2(b) 参照)を覆っているケース部
分が金属ベース1に完全に接着されていないと、ボンダ
からボンディングワイヤ9に加えた超音波振動の加振力
が逃げてしまってボンディング部分に有効作用せず、こ
のためにボンディング不良を引き起こす。
By the way, it has been found that the IPM having the above-mentioned structure has the following problems to be solved in the assembling process. That is, (1) ultrasonically attach a bonding wire 8 to the tip of the inner lead 4a of the main circuit terminal 4 which is insert-molded integrally with the outer case 2 while the outer case 2 is bonded to the metal base 1 with an adhesive. At the time of bonding by the crimping method, the case portion covering the lower surface area (see FIG. 2 (b)) of the inner lead 4a drawn to the inner peripheral side of the outer case 2 is completely adhered to the metal base 1. If it is not, the exciting force of ultrasonic vibration applied from the bonder to the bonding wire 9 escapes and does not act effectively on the bonding portion, which causes defective bonding.

【0009】かかる点、従来構造では外囲ケース2の底
面周域に沿って形成した接着剤塗布面となる凹溝2aは
金属ベース1の外周縁に沿うように形成するとともに、
凹溝2aの溝幅は必要な接着強度を確保するのに要する
最小限の幅に設定して接着剤の塗布量(消費量)をでき
るだけ抑えてコスト低減を図るようにしているのに対
し、図4で述べたように主回路端子4のL字状インナー
リード4aが上下に重なって外囲ケース2の内周側に突
き出した部分では、上側のインナーリードが下側のイン
ナーリードよりも内側に位置しているために、上側のイ
ンナーリードが前記した接着剤塗布面となる凹溝2aよ
りも内周側に突き出すようになる。このために、インナ
ーリードの先端側下面領域が金属ベース1に完全接着さ
れず、その結果としてワイヤボンディング工程で前記イ
ンナーリード4aにボンディングワイヤ9を超音波ボン
ディングする際に、前記のようなボンディング不良が発
生し易くなる。
With respect to this point, in the conventional structure, the concave groove 2a which is an adhesive coating surface formed along the peripheral area of the bottom surface of the outer casing 2 is formed along the outer peripheral edge of the metal base 1, and
While the groove width of the recessed groove 2a is set to the minimum width required to secure the required adhesive strength, the application amount (consumption amount) of the adhesive is suppressed as much as possible to achieve cost reduction. As described with reference to FIG. 4, in the portion where the L-shaped inner leads 4a of the main circuit terminal 4 are vertically overlapped and protrude toward the inner peripheral side of the outer casing 2, the upper inner lead is located inside the lower inner lead. Since it is located at, the inner lead on the upper side is projected to the inner peripheral side from the concave groove 2a serving as the adhesive application surface. For this reason, the lower surface area of the inner lead on the tip side is not completely adhered to the metal base 1, and as a result, when the bonding wire 9 is ultrasonically bonded to the inner lead 4a in the wire bonding process, the above-mentioned bonding failure occurs. Is likely to occur.

【0010】なお、このようなボンディング不良の発生
を防ぐために、前記した凹溝2aの溝幅をあらかじめそ
の全域で広く設定しておくことが考えられるが、凹溝2
aの溝幅を必要以上に広げることは、接着剤の塗布量
(消費量)が増えて製品コストが高まるので実用的でな
い。 (2) また、外囲ケース2の底面周域に形成した凹溝2a
に接着剤を塗布する工程では、先記のように接着剤ディ
スペンサを用い、凹溝2aのルート上に定めたスタート
地点にディスペンサのノズルを位置合わせして接着剤の
供給を開始し、ここから凹溝2aのルートに沿ってディ
スペンサノズルを移動させながら接着剤を塗布し、凹溝
ルートのエンド点まで移動したところでディスペンサの
接着剤供給を停止するように行っているが、そのスター
ト地点では接着剤の供給開始とディスペンサの移動開始
とのタイミングのずれ、またエンド地点ではディスペン
サノズルからの接着剤の後垂れなどが原因で、接着剤の
塗布量が他の範囲に比べて多少過剰になることが避けら
れない。
In order to prevent the occurrence of such a defective bonding, it is conceivable that the groove width of the above-mentioned groove 2a is set to be wide in its entire area in advance.
It is not practical to widen the groove width of a more than necessary because the amount of adhesive applied (consumption amount) increases and the product cost increases. (2) Also, the concave groove 2a formed in the peripheral area of the bottom surface of the outer casing 2
In the step of applying the adhesive to the adhesive, the adhesive dispenser is used as described above, the nozzle of the dispenser is aligned with the start point defined on the route of the concave groove 2a, and the supply of the adhesive is started. The adhesive is applied while moving the dispenser nozzle along the route of the groove 2a, and the adhesive supply of the dispenser is stopped when the dispenser nozzle moves to the end point of the groove route. The amount of adhesive applied may be slightly excessive compared to other ranges due to the timing difference between the start of supply of the agent and the start of movement of the dispenser, and the end point of the adhesive dripping from the dispenser nozzle. Is inevitable.

【0011】このために、続く組立工程で外囲ケース2
を金属ベース1の上に重ね合わせて加圧力を加えると、
前記のスタート/エンド地点では凹溝2aから溢れ出た
余剰の接着剤が外囲ケース2の内周側にはみ出してパワ
ー回路6の回路基板に付着して導体パターンのボンディ
ング面を汚損する不具合を引き起こすことがある。本発
明は上記の点に鑑みなされたものであり、その目的は前
記した組立工程での問題点を解消して製品の品質向上が
図れるように改良した半導体装置のパッケージを提供す
ることにある。
Therefore, in the subsequent assembling process, the outer case 2
When is superimposed on the metal base 1 and pressure is applied,
At the start / end point, there is a problem that the excess adhesive overflowing from the concave groove 2a sticks out to the inner peripheral side of the outer case 2 and adheres to the circuit board of the power circuit 6 to stain the bonding surface of the conductor pattern. May cause. The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device package improved so as to solve the above-mentioned problems in the assembly process and improve the quality of products.

【0012】[0012]

【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、パワー回路を搭載した金属ベース
に端子一体形の外囲ケース, および上蓋を組合せてその
相互間を接着した構造になる半導体装置のパッケージ
で、その外囲ケースにはパワー回路に対する入,出力用
の主回路端子を左右に配列してインサート成形するとと
もに、金属ベースの外周縁に対向して外囲ケースの底面
周域に接着剤塗布面となる凹溝を形成し、該凹溝に接着
剤を塗布して金属ベースと接合した状態で、L字状に屈
曲して外囲ケースの内周側に引出した主回路端子のイン
ナーリードとパワー回路との間に超音波圧着法によるワ
イヤボンディングを施して配線したものにおいて、外囲
ケースにインサート成形した前記の主回路端子のうち、
少なくともインナーリードが別な端子のインナーリード
と上下に重なる端子に対応して、ケース底面に形成した
前記凹溝の溝幅をインナーリードの下面領域に向けて部
分的に拡大するようにする(請求項1)。
In order to achieve the above object, according to the present invention, a metal base on which a power circuit is mounted is combined with a terminal-integrated enclosure case and an upper lid, and they are bonded together. A semiconductor device package with a structure.In the outer case, the main circuit terminals for input and output for the power circuit are arranged on the left and right sides and insert-molded, and the outer case of the outer case faces the outer peripheral edge of the metal base. A groove is formed in the peripheral area of the bottom surface to serve as an adhesive application surface, the adhesive is applied to the groove and is joined to a metal base, and then bent into an L-shape and drawn out to the inner peripheral side of the enclosure case. Among the main circuit terminals insert-molded in the outer case, the main circuit terminals are wire-bonded by an ultrasonic pressure bonding method between the inner leads of the main circuit terminals and the power circuit.
At least the inner lead corresponds to a terminal that vertically overlaps with the inner lead of another terminal, and the groove width of the concave groove formed on the bottom surface of the case is partially enlarged toward the lower surface area of the inner lead (claim Item 1).

【0013】そして、外囲ケースの底面に形成した凹溝
に接着剤を塗布する際に、前記の溝幅拡大部分にも接着
剤を塗布しておくことにより、接着剤の塗布量を必要以
上に増加させることなしに、しかも金属ベースに外囲ケ
ースを重ね合わせて接合した状態では、前記した主回路
端子のインナーリードの下面域が金属ベースに対して完
全に接着されるようになる。これにより、続く超音波圧
着法によるワイヤボンディング工程では、主回路端子の
インナーリードとボンディングワイヤとが確実に接合し
てボンディング不良の発生を防ぐことができる。
When the adhesive is applied to the concave groove formed on the bottom surface of the outer case, the adhesive is applied to the groove width enlarged portion, so that the amount of the adhesive applied is greater than necessary. In the state where the enclosure case is superposed on and joined to the metal base without increasing the thickness, the lower surface area of the inner lead of the main circuit terminal is completely bonded to the metal base. Accordingly, in the subsequent wire bonding process by ultrasonic pressure bonding, the inner lead of the main circuit terminal and the bonding wire can be reliably bonded to each other to prevent defective bonding.

【0014】また、本発明によれば、パワー回路を搭載
した金属ベースに端子一体形の外囲ケース, および上蓋
を組合せてその相互間を接着した構造になる半導体装置
のパッケージであり、金属ベースの周縁に対向して外囲
ケースの底面周域には接着剤塗布面となる凹溝を形成
し、該凹溝に沿い接着剤ディスペンサより供給した接着
剤を塗布したうえで、金属ベースに外囲ケースを重ね合
わせて加圧接着するようにしたものにおいて、前記凹溝
のルート上に定めた接着剤の塗布スタート/エンド地点
に対応する箇所で、凹溝の溝幅を溝の外周側に向けて部
分的に拡大するように設定する(請求項2)。
Further, according to the present invention, there is provided a semiconductor device package having a structure in which a metal base on which a power circuit is mounted is combined with a terminal-integrated enclosure case and an upper lid, and the two are bonded together. A groove is formed in the peripheral area of the bottom surface of the outer case facing the periphery of the adhesive case, and the adhesive supplied from the adhesive dispenser is applied along the groove to apply the adhesive to the metal base. In the case where the surrounding cases are overlapped and pressure-bonded, the groove width of the concave groove is set to the outer peripheral side of the groove at a position corresponding to the adhesive application start / end point defined on the route of the concave groove. It is set so as to partially enlarge the image (claim 2).

【0015】上記により、凹溝のルートに沿って接着剤
ディスペンサから供給した接着剤を塗布した後、外囲ケ
ースを金属ベース上に重ねて加圧力を加えた際に、その
接着剤の塗布スタート,エンド地点では定量より多少多
めに塗布された接着剤が前記の溝幅拡大部に逃げるよう
になり、その結果として余剰な接着剤が外囲ケースの内
側にはみ出してパワー回路基板に付着するのを回避でき
る。これにより、接着剤塗布量のコントロール管理が容
易となる。
According to the above, when the adhesive supplied from the adhesive dispenser is applied along the route of the concave groove, and when the pressure is applied by stacking the enclosure case on the metal base, the application of the adhesive is started. , At the end point, the adhesive applied a little more than the fixed amount escapes to the groove width expansion part, and as a result, the excess adhesive sticks out to the inside of the enclosure case and adheres to the power circuit board. Can be avoided. This facilitates control of the amount of adhesive applied.

【0016】[0016]

【発明の実施の形態】以下、本発明の実施の形態を図1
(a) 〜(c) に示す実施例に基づいて説明する。なお、実
施例の図中で図2〜図4に対応する部材には同じ符号を
付してその説明は省略する。図示例のIPMのパッケー
ジは基本的に先記した図2〜図4の構造と同様であり、
外囲ケース2にはパワー回路に対する入,出力用の主回
路端子4(各端子に付した端子記号P,N,U,V,W
およびBは図3に付した端子記号に対応する)が左右一
列に並んでインサート形成されており、各端子ごとにL
字状に屈曲したインナーリード4aの先端部が外囲ケー
ス2の内周側に突き出しているのに対して、この実施例
では図1(c) で示すように外囲ケース2の底面周囲に沿
って形成した接着剤塗布面となる凹溝2a(図中に斜線
で表した部分)が次のようなパターンに形成されてい
る。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
Description will be made based on the examples shown in (a) to (c). In the drawings of the embodiments, members corresponding to those in FIGS. 2 to 4 are designated by the same reference numerals, and the description thereof will be omitted. The IPM package of the illustrated example is basically the same as the structure shown in FIGS.
The outer case 2 has main circuit terminals 4 for input and output to the power circuit (terminal symbols P, N, U, V, W attached to each terminal).
And B correspond to the terminal symbols shown in FIG. 3) and are insert-formed side by side in a line.
In contrast to the tip of the inner lead 4a bent in a letter shape protruding toward the inner peripheral side of the outer case 2, in this embodiment, as shown in FIG. The concave groove 2a (the portion shown by hatching in the figure) which is an adhesive application surface formed along the side is formed in the following pattern.

【0017】すなわち、前記凹溝2aは、基本的には外
囲ケース2に接合する金属ベース1の周縁に対応するル
ートに沿って等幅に形成されているが、特に左右に並ん
で主回路端子4が配列している範囲では、少なくとも主
回路端子4のインナーリード4aが別な端子のインナー
リード4aと上下に重なる部分に対応して図中にa〜d
で表した各部位では、凹溝2aの溝幅がインナーリード
先端部の下面領域に向けて部分的に拡大するように溝幅
拡大部2bを形成し、該溝幅拡大部2bを含めてこの範
囲では凹溝2aが波形を呈するようなパターンに形成し
ている。
That is, the concave grooves 2a are basically formed to have the same width along the route corresponding to the peripheral edge of the metal base 1 joined to the outer case 2, but especially the right and left side main circuits are arranged side by side. In the range in which the terminals 4 are arranged, at least the inner leads 4a of the main circuit terminals 4 correspond to the portions vertically overlapping the inner leads 4a of the other terminals, and are indicated by a to d in the figure.
In each of the portions shown by, the groove width enlarged portion 2b is formed so that the groove width of the concave groove 2a is partially enlarged toward the lower surface region of the inner lead tip portion, and the groove width enlarged portion 2b is included. In the range, the concave groove 2a is formed in a pattern having a wavy shape.

【0018】さらに、接着剤ディスペンサを用いて前記
凹溝2aに接着剤を塗布する工程で、その接着剤塗布ル
ート上のスタート/エンド地点に対応する箇所(通常は
外郭が長方形になる外囲ケース2の短辺側に定めてい
る)に対しては、凹溝2aの溝幅を溝の外周側に向けて
部分的に拡大した溝幅拡大部2cを形成し、この溝幅拡
大部2cで余分な接着剤を逃がすダム機能を持たせるよ
うにしている。
Further, in the step of applying the adhesive to the groove 2a using an adhesive dispenser, a portion corresponding to the start / end point on the adhesive application route (usually an enclosure case having a rectangular outer shell) 2) is defined on the short side of 2), the groove width enlarged portion 2c is formed by partially enlarging the groove width of the concave groove 2a toward the outer peripheral side of the groove. It has a dam function that allows excess adhesive to escape.

【0019】上記の構成により、外囲ケース2の底面に
形成した凹溝2aに接着剤を塗布する際に、前記の溝幅
拡大部2bにも接着剤を塗布しておくことにより、金属
ベース1に外囲ケース2を重ね合わせて接合した状態で
は、前記した主回路端子4のインナーリード4aの下面
領域が金属ベース1に対して完全に接着されるようにな
る。これにより、続く超音波ボンディング工程では、主
回路端子4のインナーリード4aとボンディングワイヤ
9(図2,図3参照)とをボンディング不良の発生なし
に確実にボンディングできる。
With the above structure, when the adhesive is applied to the concave groove 2a formed on the bottom surface of the outer casing 2, the adhesive is also applied to the groove width enlarged portion 2b, so that the metal base is formed. In the state where the outer case 2 is superposed on and bonded to the outer case 1, the lower surface region of the inner lead 4a of the main circuit terminal 4 is completely bonded to the metal base 1. As a result, in the subsequent ultrasonic bonding step, the inner leads 4a of the main circuit terminals 4 and the bonding wires 9 (see FIGS. 2 and 3) can be reliably bonded without causing defective bonding.

【0020】また、凹溝2aのルートに沿って接着剤デ
ィスペンサから供給した接着剤を塗布した後、外囲ケー
スを金属ベース上に重ねて加圧力を加えた際には、その
接着剤の塗布スタート,エンド地点に定量より多少多め
に塗布された接着剤が溝幅拡大部2cに逃げるようにな
る。その結果、接着剤の余剰分が外囲ケース2の内側に
はみ出してパワー回路6(図2,図3参照)の回路基板
に付着し、続くワイヤボンディング工程での障害となる
のを未然に防げる。これにより、接着剤ディスペンサを
使って凹溝2aに接着剤を塗布する工程での接着剤塗布
量のコントロール管理が容易となる。
Further, after applying the adhesive supplied from the adhesive dispenser along the route of the concave groove 2a, when the pressure is applied by stacking the outer case on the metal base, the adhesive is applied. The adhesive applied a little more than the fixed amount at the start and end points comes to escape to the groove width enlarged portion 2c. As a result, it is possible to prevent the excess amount of the adhesive from sticking out to the inside of the enclosure case 2 and adhering to the circuit board of the power circuit 6 (see FIGS. 2 and 3), which becomes an obstacle in the subsequent wire bonding process. . This facilitates control management of the adhesive application amount in the step of applying the adhesive to the concave groove 2a using the adhesive dispenser.

【0021】なお、図示実施例では、溝幅拡大部2bを
特定した主回路端子4のインナーリード4aと対応する
部位に限定して形成しているが、主回路端子4の全ての
インナーリードに対応した部位に形成して実施すること
もできる。
In the illustrated embodiment, the groove width enlarged portion 2b is limited to the specified portion corresponding to the inner lead 4a of the main circuit terminal 4, but all inner leads of the main circuit terminal 4 are formed. It can also be formed by forming it at a corresponding portion.

【0022】[0022]

【発明の効果】以上述べたように、本発明の構成によれ
ば、次記の効果を奏する。 (1) パワー回路を搭載した金属ベースに端子一体形の外
囲ケース, および上蓋を組合せてその相互間を接着した
構造になる半導体装置のパッケージで、その外囲ケース
にはパワー回路に対する入, 出力用の主回路端子を左右
に配列してインサート成形するとともに、金属ベースの
外周縁に対向して外囲ケースの底面周域に接着剤塗布面
となる凹溝を形成し、該凹溝に接着剤を塗布して金属ベ
ースと接合した状態で、L字状に屈曲して外囲ケースの
内周側に引出した主回路端子のインナーリードとパワー
回路との間に超音波圧着法によるワイヤボンディングを
施して内部配線したものにおいて、前記主回路端子のう
ち、少なくともインナーリードが別な端子のインナーリ
ードと上下に重なる端子に対応して、ケース底面に形成
した前記凹溝の溝幅をインナーリードの下面領域に向け
て部分的に拡大したことにより、接着剤の塗布量を必要
以上に増量することなしに、金属ベースに外囲ケースを
重ね合わせて接着した状態では、前記した主回路端子の
インナーリードの下面域が金属ベースに対して完全に接
着されるようになるので、これにより続く超音波圧着法
によるワイヤボンディング工程では、主回路端子のイン
ナーリードとボンディングワイヤとが確実に接合してボ
ンディング不良の発生を効果的に防ぐことができる。
As described above, the structure of the present invention has the following effects. (1) A semiconductor device package that has a structure in which a metal base on which a power circuit is mounted and a terminal-integrated enclosure case, and an upper lid are combined and the two are bonded together. The main circuit terminals for output are arranged on the left and right sides and insert-molded, and at the same time, a groove is formed in the peripheral area of the bottom surface of the enclosure case as an adhesive application surface facing the outer peripheral edge of the metal base. A wire formed by ultrasonic bonding between the inner lead of the main circuit terminal and the power circuit, which is bent in an L shape and is drawn out to the inner peripheral side of the outer case in a state where the adhesive is applied and bonded to the metal base. Among the main circuit terminals, which have been internally wired by bonding, at least the inner lead corresponds to the terminal vertically overlapping the inner lead of another terminal, and the groove width of the concave groove formed on the bottom surface of the case. By partially enlarging it toward the lower surface area of the inner lead, the main circuit described above can be used in a state where the enclosure case is overlaid and adhered to the metal base without increasing the adhesive application amount more than necessary. Since the lower surface area of the inner lead of the terminal is completely adhered to the metal base, the inner lead of the main circuit terminal and the bonding wire are securely joined in the wire bonding process by the ultrasonic bonding method which follows. Therefore, the occurrence of defective bonding can be effectively prevented.

【0023】(2) また、前記凹溝のルート上に定めた接
着剤の塗布スタート/エンド地点に対応する箇所で、凹
溝の溝幅を溝の外周側に向けて部分的に拡大した請求項
2の構成によれば、凹溝のルートに沿って接着剤ディス
ペンサから供給した接着剤を塗布した後、外囲ケースを
金属ベース上に重ねて加圧力を加えた際に、前記のスタ
ート,エンド地点で定量より多少多めに塗布された接着
剤が前記の溝幅拡大部に逃げるようになり、その結果と
して余剰な接着剤が外囲ケースの内側にはみ出してパワ
ー回路基板に付着するのを回避できるとともに、接着剤
塗布量のコントロール管理も容易となる。
(2) Further, the groove width of the concave groove is partially enlarged toward the outer peripheral side of the groove at a position corresponding to the adhesive application start / end point defined on the route of the concave groove. According to the configuration of Item 2, when the adhesive supplied from the adhesive dispenser is applied along the route of the concave groove, and the pressing force is applied by overlapping the outer case on the metal base, the start, At the end point, the adhesive applied a little more than the fixed amount will escape to the groove width expansion part, and as a result, excess adhesive will stick out to the inside of the enclosure case and adhere to the power circuit board. This can be avoided and the control of the amount of adhesive applied can be controlled easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例によるIPMのパッケージの構
成図で、(a),(b) および(c) は、それぞれ外囲ケースの
平面図、主回路端子の配列を表した側面図、および外囲
ケースの底面図
FIG. 1 is a configuration diagram of an IPM package according to an embodiment of the present invention, in which (a), (b) and (c) are respectively a plan view of an outer case and a side view showing an arrangement of main circuit terminals, And bottom view of enclosure

【図2】本発明の実施対象となるIPMの全体図で、
(a) は外観平面図、(b) は(a) の側視断面図
FIG. 2 is an overall view of an IPM to which the present invention is applied,
(a) is an external plan view, (b) is a cross-sectional side view of (a)

【図3】図2のIPMで、パワー回路を搭載した金属ベ
ースに外囲ケースを接合してワイヤボンディングを施し
た組立状態を表す平面図
FIG. 3 is a plan view showing an assembled state in which an IPM of FIG. 2 has a metal base on which a power circuit is mounted and an outer case is joined to perform wire bonding.

【図4】図3における主回路端子の配列を表す図で、
(a) 〜(c) はそれぞれU,V,W相の交流出力端子に分
けて表した端子配列図
FIG. 4 is a diagram showing an arrangement of main circuit terminals in FIG.
(a) to (c) are terminal arrangement diagrams showing the U, V, and W phase AC output terminals separately.

【図5】図3の等価回路図5 is an equivalent circuit diagram of FIG.

【符号の説明】[Explanation of symbols]

1 金属ベース 2 外囲ケース 2a 接着剤を塗布する底面側の凹溝 2b 主回路端子のインナーリードに対応する溝幅拡大
部 2c 接着剤塗布のスタート/エンド地点に対応する溝
幅拡大部 4 主回路端子 4a インナーリード 6 パワー回路 6a パワー半導体素子 6c-1,6c-2 回路基板 9 ボンディングワイヤ
1 Metal base 2 Envelope case 2a Groove width 2b corresponding to inner lead of main circuit terminal 2c Groove width expansion part corresponding to inner lead of main circuit terminal 2c Groove width expansion part 4 corresponding to start / end points of adhesive application 4 Main Circuit terminal 4a Inner lead 6 Power circuit 6a Power semiconductor element 6c-1, 6c-2 Circuit board 9 Bonding wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】パワー回路を搭載した金属ベースに端子一
体形の外囲ケース,および上蓋を組合せてその相互間を
接着した構造になる半導体装置のパッケージであり、外
囲ケースにはパワー回路に対する入, 出力用の主回路端
子を左右に配列してインサート成形するとともに、金属
ベースの外周縁に対向して外囲ケースの底面周域に接着
剤塗布面となる凹溝を形成し、該凹溝に接着剤を塗布し
て金属ベースと接合した状態で、L字状に屈曲して外囲
ケースの内周側に引出した主回路端子のインナーリード
とパワー回路との間に超音波圧着法によるワイヤボンデ
ィングを施して内部配線したものにおいて、 前記主回路端子のうち、少なくともインナーリードが別
な端子のインナーリードと上下に重なる端子に対応し
て、ケース底面に形成した前記凹溝の溝幅をインナーリ
ードの下面領域に向けて部分的に拡大したことを特徴と
する半導体装置のパッケージ。
1. A package of a semiconductor device having a structure in which a metal base on which a power circuit is mounted, a terminal-integrated enclosure case, and an upper lid are combined and bonded to each other. The main circuit terminals for input and output are arranged on the left and right sides and insert-molded, and at the same time, a concave groove is formed on the peripheral area of the bottom surface of the enclosure case as an adhesive application surface facing the outer peripheral edge of the metal base. Ultrasonic pressure bonding method between the inner lead of the main circuit terminal and the power circuit, which is bent in an L shape and is pulled out to the inner circumference side of the outer case in a state where the groove is coated with an adhesive and joined to the metal base. Of the main circuit terminals, at least the inner leads corresponding to the terminals vertically overlapping the inner leads of the other terminals of the main circuit terminals. A package of a semiconductor device, wherein a groove width of a groove is partially enlarged toward a lower surface region of an inner lead.
【請求項2】パワー回路を搭載した金属ベースに端子一
体形の外囲ケース,および上蓋を組合せてその相互間を
接着した構造になる半導体装置のパッケージであり、金
属ベースの周縁に対向して外囲ケースの底面周域には接
着剤塗布面となる凹溝を形成し、該凹溝のルートに沿っ
て接着剤ディスペンサより供給した接着剤を塗布したう
えで、金属ベースに外囲ケースを重ね合わせて加圧接着
するようにしたものにおいて、 前記凹溝のルート上に定めた接着剤の塗布スタート/エ
ンド地点に対応する箇所で、凹溝の溝幅を溝の外周側に
向けて部分的に拡大したことを特徴とする半導体装置の
パッケージ。
2. A package of a semiconductor device having a structure in which a metal base on which a power circuit is mounted, a terminal integrated type enclosure case, and an upper lid are combined and bonded to each other, the package being opposed to the peripheral edge of the metal base. A groove is formed on the bottom surface of the outer case as an adhesive application surface, the adhesive supplied from the adhesive dispenser is applied along the route of the groove, and then the outer case is attached to the metal base. In a case where they are overlapped and pressure-bonded, the groove width of the concave groove is directed toward the outer peripheral side of the groove at a position corresponding to the adhesive application start / end point defined on the root of the concave groove. The semiconductor device package is characterized in that it has been expanded.
JP2001235731A 2001-08-03 2001-08-03 Semiconductor device package Expired - Lifetime JP4710194B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001235731A JP4710194B2 (en) 2001-08-03 2001-08-03 Semiconductor device package

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JP2003051560A true JP2003051560A (en) 2003-02-21
JP4710194B2 JP4710194B2 (en) 2011-06-29

Family

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8546933B2 (en) 2010-07-01 2013-10-01 Fuji Electric Co., Ltd. Semiconductor apparatus including resin case
JP2020064992A (en) * 2018-10-18 2020-04-23 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
CN113380738A (en) * 2021-05-07 2021-09-10 西安交通大学 Direct integrated phase transition radiating carborundum power module packaging structure
CN114245929A (en) * 2019-08-29 2022-03-25 迪睿合株式会社 Protection element and battery pack
US11348852B2 (en) 2018-12-10 2022-05-31 Fuji Electric Co., Ltd. Semiconductor device
US11502434B2 (en) 2017-06-07 2022-11-15 Hitachi Energy Switzerland Ag Power semiconductor module
JP7482259B2 (en) 2020-06-12 2024-05-13 無錫利普思半導体有限公司 Power Semiconductor Modules

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Publication number Priority date Publication date Assignee Title
JPH0470752U (en) * 1990-10-30 1992-06-23
JP2000323593A (en) * 1999-05-06 2000-11-24 Yazaki Corp Semiconductor device
JP2000323646A (en) * 1999-05-14 2000-11-24 Mitsubishi Electric Corp Insulating material case and semiconductor device
JP2000353777A (en) * 1999-06-09 2000-12-19 Yazaki Corp Power semiconductor module and manufacture thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0470752U (en) * 1990-10-30 1992-06-23
JP2000323593A (en) * 1999-05-06 2000-11-24 Yazaki Corp Semiconductor device
JP2000323646A (en) * 1999-05-14 2000-11-24 Mitsubishi Electric Corp Insulating material case and semiconductor device
JP2000353777A (en) * 1999-06-09 2000-12-19 Yazaki Corp Power semiconductor module and manufacture thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8546933B2 (en) 2010-07-01 2013-10-01 Fuji Electric Co., Ltd. Semiconductor apparatus including resin case
US11502434B2 (en) 2017-06-07 2022-11-15 Hitachi Energy Switzerland Ag Power semiconductor module
JP2020064992A (en) * 2018-10-18 2020-04-23 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
JP7238330B2 (en) 2018-10-18 2023-03-14 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
US11348852B2 (en) 2018-12-10 2022-05-31 Fuji Electric Co., Ltd. Semiconductor device
CN114245929A (en) * 2019-08-29 2022-03-25 迪睿合株式会社 Protection element and battery pack
JP7482259B2 (en) 2020-06-12 2024-05-13 無錫利普思半導体有限公司 Power Semiconductor Modules
CN113380738A (en) * 2021-05-07 2021-09-10 西安交通大学 Direct integrated phase transition radiating carborundum power module packaging structure
CN113380738B (en) * 2021-05-07 2024-05-07 西安交通大学 Direct integrated phase-change radiating silicon carbide power module packaging structure

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