JP2003049280A - Electroless plating solution and semiconductor device - Google Patents
Electroless plating solution and semiconductor deviceInfo
- Publication number
- JP2003049280A JP2003049280A JP2001179341A JP2001179341A JP2003049280A JP 2003049280 A JP2003049280 A JP 2003049280A JP 2001179341 A JP2001179341 A JP 2001179341A JP 2001179341 A JP2001179341 A JP 2001179341A JP 2003049280 A JP2003049280 A JP 2003049280A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electroless plating
- wiring
- plating solution
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 186
- 238000007772 electroless plating Methods 0.000 title claims abstract description 61
- 230000001681 protective effect Effects 0.000 claims abstract description 31
- 229910052783 alkali metal Inorganic materials 0.000 claims abstract description 25
- 150000001340 alkali metals Chemical class 0.000 claims abstract description 25
- 239000003638 chemical reducing agent Substances 0.000 claims abstract description 24
- 229910001429 cobalt ion Inorganic materials 0.000 claims abstract description 12
- XLJKHNWPARRRJB-UHFFFAOYSA-N cobalt(2+) Chemical compound [Co+2] XLJKHNWPARRRJB-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000008139 complexing agent Substances 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims description 65
- 229910052802 copper Inorganic materials 0.000 claims description 62
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 61
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 30
- 229910000085 borane Inorganic materials 0.000 claims description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 14
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 239000004332 silver Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 239000003870 refractory metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- -1 cobalt ions Chemical class 0.000 claims description 9
- 239000003002 pH adjusting agent Substances 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 7
- 239000003381 stabilizer Substances 0.000 claims description 7
- 239000004094 surface-active agent Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910001385 heavy metal Inorganic materials 0.000 claims description 5
- 150000002736 metal compounds Chemical class 0.000 claims description 5
- 150000003464 sulfur compounds Chemical class 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910000531 Co alloy Inorganic materials 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 125000003282 alkyl amino group Chemical group 0.000 claims 2
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000011109 contamination Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 143
- 238000007747 plating Methods 0.000 description 107
- 238000004140 cleaning Methods 0.000 description 47
- 229910045601 alloy Inorganic materials 0.000 description 42
- 239000000956 alloy Substances 0.000 description 42
- 239000010410 layer Substances 0.000 description 38
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 27
- 229910001096 P alloy Inorganic materials 0.000 description 26
- 238000005498 polishing Methods 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 18
- 229910017262 Mo—B Inorganic materials 0.000 description 16
- 229910052763 palladium Inorganic materials 0.000 description 14
- 150000003973 alkyl amines Chemical class 0.000 description 13
- 229910000521 B alloy Inorganic materials 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 239000007788 liquid Substances 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 10
- 239000003054 catalyst Substances 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 238000011084 recovery Methods 0.000 description 7
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 6
- 238000001035 drying Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052708 sodium Inorganic materials 0.000 description 6
- 239000011734 sodium Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 150000003839 salts Chemical class 0.000 description 5
- 239000006061 abrasive grain Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- RJTANRZEWTUVMA-UHFFFAOYSA-N boron;n-methylmethanamine Chemical compound [B].CNC RJTANRZEWTUVMA-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- KWSLGOVYXMQPPX-UHFFFAOYSA-N 5-[3-(trifluoromethyl)phenyl]-2h-tetrazole Chemical compound FC(F)(F)C1=CC=CC(C2=NNN=N2)=C1 KWSLGOVYXMQPPX-UHFFFAOYSA-N 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- DHMQDGOQFOQNFH-UHFFFAOYSA-N Glycine Chemical compound NCC(O)=O DHMQDGOQFOQNFH-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 150000007513 acids Chemical class 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- VDTVZBCTOQDZSH-UHFFFAOYSA-N borane N-ethylethanamine Chemical compound B.CCNCC VDTVZBCTOQDZSH-UHFFFAOYSA-N 0.000 description 2
- 239000002738 chelating agent Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000006174 pH buffer Substances 0.000 description 2
- 239000006179 pH buffering agent Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 125000001453 quaternary ammonium group Chemical group 0.000 description 2
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- KXDHJXZQYSOELW-UHFFFAOYSA-N Carbamic acid Chemical class NC(O)=O KXDHJXZQYSOELW-UHFFFAOYSA-N 0.000 description 1
- 229910020674 Co—B Inorganic materials 0.000 description 1
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 description 1
- 239000004471 Glycine Substances 0.000 description 1
- 101000650817 Homo sapiens Semaphorin-4D Proteins 0.000 description 1
- 101000854908 Homo sapiens WD repeat-containing protein 11 Proteins 0.000 description 1
- 101100028920 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) cfp gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 102100027744 Semaphorin-4D Human genes 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- 102100020705 WD repeat-containing protein 11 Human genes 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- BFNBIHQBYMNNAN-UHFFFAOYSA-N ammonium sulfate Chemical compound N.N.OS(O)(=O)=O BFNBIHQBYMNNAN-UHFFFAOYSA-N 0.000 description 1
- 229910052921 ammonium sulfate Inorganic materials 0.000 description 1
- 235000011130 ammonium sulphate Nutrition 0.000 description 1
- 125000000129 anionic group Chemical group 0.000 description 1
- 239000003945 anionic surfactant Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- WVMHLYQJPRXKLC-UHFFFAOYSA-N borane;n,n-dimethylmethanamine Chemical compound B.CN(C)C WVMHLYQJPRXKLC-UHFFFAOYSA-N 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 235000010338 boric acid Nutrition 0.000 description 1
- RLDQYSHDFVSAPL-UHFFFAOYSA-L calcium;dithiocyanate Chemical class [Ca+2].[S-]C#N.[S-]C#N RLDQYSHDFVSAPL-UHFFFAOYSA-L 0.000 description 1
- 150000001735 carboxylic acids Chemical class 0.000 description 1
- 125000002091 cationic group Chemical group 0.000 description 1
- 239000003093 cationic surfactant Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001868 cobalt Chemical class 0.000 description 1
- 229940011182 cobalt acetate Drugs 0.000 description 1
- GVPFVAHMJGGAJG-UHFFFAOYSA-L cobalt dichloride Chemical compound [Cl-].[Cl-].[Co+2] GVPFVAHMJGGAJG-UHFFFAOYSA-L 0.000 description 1
- 229940044175 cobalt sulfate Drugs 0.000 description 1
- 229910000361 cobalt sulfate Inorganic materials 0.000 description 1
- KTVIXTQDYHMGHF-UHFFFAOYSA-L cobalt(2+) sulfate Chemical compound [Co+2].[O-]S([O-])(=O)=O KTVIXTQDYHMGHF-UHFFFAOYSA-L 0.000 description 1
- QAHREYKOYSIQPH-UHFFFAOYSA-L cobalt(II) acetate Chemical compound [Co+2].CC([O-])=O.CC([O-])=O QAHREYKOYSIQPH-UHFFFAOYSA-L 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002611 lead compounds Chemical class 0.000 description 1
- VLAPMBHFAWRUQP-UHFFFAOYSA-L molybdic acid Chemical compound O[Mo](O)(=O)=O VLAPMBHFAWRUQP-UHFFFAOYSA-L 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002736 nonionic surfactant Substances 0.000 description 1
- 150000002940 palladium Chemical class 0.000 description 1
- AVFBYUADVDVJQL-UHFFFAOYSA-N phosphoric acid;trioxotungsten;hydrate Chemical compound O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.O=[W](=O)=O.OP(O)(O)=O AVFBYUADVDVJQL-UHFFFAOYSA-N 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- CMPGARWFYBADJI-UHFFFAOYSA-L tungstic acid Chemical compound O[W](O)(=O)=O CMPGARWFYBADJI-UHFFFAOYSA-L 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1635—Composition of the substrate
- C23C18/1637—Composition of the substrate metallic substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
- C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/52—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating using reducing agents for coating with metallic material not provided for in a single one of groups C23C18/32 - C23C18/50
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、無電解めっき液及
び半導体装置に関し、特に半導体基板等の基板の表面に
設けた配線用の微細な凹部に、銅や銀等の導電体を埋め
込んで構成した埋め込み配線構造を有する半導体装置の
露出配線の表面を選択的に保護する保護膜を形成するの
に使用される無電解めっき液、及び露出配線の表面を保
護膜で選択的に保護した半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electroless plating solution and a semiconductor device, and in particular, a fine recess for wiring provided on the surface of a substrate such as a semiconductor substrate is filled with a conductor such as copper or silver. Electroless plating solution used to form a protective film that selectively protects the surface of the exposed wiring of the semiconductor device having the embedded wiring structure, and a semiconductor device in which the surface of the exposed wiring is selectively protected by the protective film. It is about.
【０００２】[0002]
【従来の技術】半導体装置の配線形成プロセスとして、
配線溝及びコンタクトホールに金属（導電体）を埋込む
ようにしたプロセス（いわゆる、ダマシンプロセス）が
使用されつつある。これは、層間絶縁膜に予め形成した
配線溝やコンタクトホールに、アルミニウム、近年では
銅や銀等の金属を埋め込んだ後、余分な金属を化学的機
械的研磨（ＣＭＰ）によって除去し平坦化するプロセス
技術である。2. Description of the Related Art As a wiring forming process of a semiconductor device,
A process (a so-called damascene process) in which a metal (conductor) is embedded in a wiring groove and a contact hole is being used. This is because after filling a wiring groove or contact hole previously formed in an interlayer insulating film with a metal such as aluminum, copper or silver in recent years, excess metal is removed by chemical mechanical polishing (CMP) to planarize the metal. It is a process technology.
【０００３】この種の配線にあっては、平坦化後、その
配線の表面が外部に露出しており、この上に埋め込み配
線を形成する際、例えば次工程の層間絶縁膜形成プロセ
スにおけるＳｉＯ２形成時の表面酸化やビアホールを形
成するためのＳｉＯ２エッチング等に際して、ビアホー
ル底に露出した配線のエッチャントやレジスト剥離等に
よる表面汚染が懸念されている。このため、従来、表面
が露出している配線形成部のみならず、半導体基板の全
表面にＳｉＮ等の配線保護膜を形成して、配線のエッチ
ャント等による汚染を防止することが一般に行われてい
た。In this type of wiring, the surface of the wiring is exposed to the outside after being flattened, and when a buried wiring is formed thereon, for example, SiO 2 in the next step of forming an interlayer insulating film. During surface oxidation at the time of formation, SiO 2 etching for forming a via hole, etc., there is concern about surface contamination due to etchant of wiring exposed at the bottom of the via hole, resist peeling, and the like. Therefore, conventionally, not only the wiring formation portion whose surface is exposed, but also the wiring protection film such as SiN is formed on the entire surface of the semiconductor substrate to prevent the wiring from being contaminated by an etchant or the like. It was
【０００４】しかしながら、半導体基板の全表面にＳｉ
Ｎ等の保護膜を形成すると、埋め込み配線構造を有する
半導体装置においては、層間絶縁膜の誘電率が上昇して
配線遅延を誘発し、配線材料として銅や銀のような低抵
抗材料を使用したとしても、半導体装置として能力向上
を阻害してしまう。このため、銅や銀等の配線材料との
接合が強く、しかも比抵抗（ρ）が低い、例えば無電解
めっきによって得られる合金膜で露出配線の表面を選択
的に覆って配線を保護することが提案されている。However, the entire surface of the semiconductor substrate has Si
When a protective film of N or the like is formed, in a semiconductor device having a buried wiring structure, the dielectric constant of the interlayer insulating film rises to induce wiring delay, and a low resistance material such as copper or silver is used as the wiring material. Even so, the ability of the semiconductor device is hindered from being improved. For this reason, the connection with the wiring material such as copper or silver is strong, and the specific resistance (ρ) is low. For example, the surface of the exposed wiring is selectively covered with an alloy film obtained by electroless plating to protect the wiring. Is proposed.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、無電解
めっきによって得られる合金膜で露出配線の表面を選択
的に覆って配線を保護するにあたっては、還元剤として
次亜りん酸ナトリウム塩が一般に使用されており、この
ため、以下のような問題があると考えられる。However, in order to protect the wiring by selectively covering the surface of the exposed wiring with an alloy film obtained by electroless plating, sodium hypophosphite is generally used as a reducing agent. Therefore, the following problems are considered to occur.
【０００６】 還元剤にナトリウムが含有されている
ため、半導体装置のアルカリ金属汚染が懸念される。
還元剤として次亜りん酸ナトリウム塩を使用する
と、銅等に対して酸化電流を流せないので、銅等にパラ
ジウム触媒を付与する必要が有り、このため、工程が増
してスループットが下がる。
銅等にパラジウム触媒を付与すると、原理的に下地
の銅等からなる配線がパラジウムで置換され、配線中に
ボイドが生成されて配線の信頼性が損なわれてしまう。
銅等にパラジウム触媒を付与すると、パラジウムは
銅等への拡散元素であるので、配線の抵抗が増加してし
まう。
配線形成領域に限らず、絶縁膜上にもめっき膜が析
出し易く、選択めっきが困難である。[0006] Since the reducing agent contains sodium, there is concern that the semiconductor device may be contaminated with alkali metals. When sodium hypophosphite is used as a reducing agent, an oxidizing current cannot be applied to copper or the like, so it is necessary to add a palladium catalyst to copper or the like, which increases the number of steps and lowers the throughput. When a palladium catalyst is added to copper or the like, in principle, the underlying wiring made of copper or the like is replaced with palladium, and voids are generated in the wiring, thus impairing the reliability of the wiring. When a palladium catalyst is applied to copper or the like, palladium is a diffusing element to copper or the like, so that the resistance of the wiring increases. Not only in the wiring formation region, a plating film easily deposits on the insulating film, and selective plating is difficult.
【０００７】本発明は上記事情に鑑みてなされたもの
で、アルカリ金属による汚染や配線内部のボイドの生成
等を防止しつつ、配線の表面のみを選択的に覆って露出
配線を保護するめっき膜（保護膜）を形成するのに使用
される無電解めっき液、及び露出配線を保護膜で選択的
に保護した半導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and a plating film which selectively covers only the surface of the wiring and protects the exposed wiring while preventing contamination by an alkali metal and generation of voids inside the wiring. An object of the present invention is to provide an electroless plating solution used for forming a (protective film) and a semiconductor device in which exposed wiring is selectively protected by a protective film.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明の無電解めっき液は、埋め込み配線構造を有
する半導体装置の露出配線の表面に無電解めっき膜を選
択的に形成する無電解めっき液であって、コバルトイオ
ン、錯化剤、及びアルカリ金属を含まない還元剤を含有
することを特徴とする。In order to achieve the above object, the electroless plating solution of the present invention is an electroless plating film for selectively forming an electroless plating film on the surface of an exposed wiring of a semiconductor device having a buried wiring structure. The plating solution is characterized by containing cobalt ions, a complexing agent, and a reducing agent containing no alkali metal.
【０００９】このように、還元剤として、アルカリ金属
を含まないものを使用することで、半導体装置のアルカ
リ金属による汚染を防止することができる。As described above, by using a reducing agent that does not contain an alkali metal, it is possible to prevent the semiconductor device from being contaminated by the alkali metal.
【００１０】このアルカリ金属を含まない還元剤とし
て、アルキルアミンボランを用いることができる。この
ように、銅、銅合金、銀または銀合金に対して酸化電流
を流せて直接無電解めっきが可能で、ナトリウムを含有
していないアルキルアミンボランを用いることで、半導
体装置のアルカリ金属による汚染を防止し、しかもパラ
ジウム触媒を付与することなく、無電解めっき処理を行
うことができる。As the reducing agent containing no alkali metal, alkylamine borane can be used. As described above, direct electroless plating can be performed by applying an oxidation current to copper, copper alloy, silver or silver alloy, and by using sodium-free alkylamine borane, contamination of semiconductor device with alkali metal is caused. And the electroless plating treatment can be performed without adding a palladium catalyst.
【００１１】ここで、アルキルアミンボランとしては、
例えばジメチルアミンボラン、ジエチルアミンボランや
トリメチルアミンボラン等が挙げられる。無電解めっき
液に、安定剤としての重金属化合物または硫黄化合物の
１種または２種以上、または界面活性剤の少なくとも一
方を更に含有するようにしてもよい。Here, as the alkylamine borane,
Examples thereof include dimethylamine borane, diethylamine borane and trimethylamine borane. The electroless plating solution may further contain one or more heavy metal compounds or sulfur compounds as a stabilizer, or at least one of surfactants.
【００１２】アルカリ金属を含まないｐＨ調整剤を用い
て、無電解めっき液のｐＨを５〜１４に調整することが
好ましい。このように、例えばアンモニア水や水酸化第
四級アンモニウム等のアルカリ金属を含まないｐＨ調整
剤を用いてｐＨを調整することで、めっき液にナトリウ
ムが含まれることを防止することができる。めっき液の
ｐＨは、６〜１０であることが更に好ましい。It is preferable to adjust the pH of the electroless plating solution to 5 to 14 using a pH adjusting agent containing no alkali metal. Thus, by adjusting the pH using a pH adjusting agent that does not contain an alkali metal such as aqueous ammonia or quaternary ammonium hydroxide, it is possible to prevent the plating solution from containing sodium. The pH of the plating solution is more preferably 6-10.
【００１３】本発明の他のめっき液は、埋め込み配線構
造を有する半導体装置の露出配線の表面に無電解めっき
膜を選択的に形成する無電解めっき液であって、コバル
トイオン、錯化剤、高融点金属を含む化合物、及びアル
カリ金属を含まない還元剤を含有することを特徴とす
る。Another plating solution of the present invention is an electroless plating solution for selectively forming an electroless plating film on the surface of an exposed wiring of a semiconductor device having a buried wiring structure, which contains cobalt ions, a complexing agent, It is characterized by containing a compound containing a refractory metal and a reducing agent containing no alkali metal.
【００１４】この高融点金属としては、例えばタングス
テン及び／またはモリブデンが使用される。これによ
り、還元剤としてアルキルアミンボランを用いること
で、Ｃｏ−Ｗ−Ｂ合金膜、Ｃｏ−Ｍｏ−Ｂ合金膜または
Ｃｏ−Ｍｏ−Ｗ−Ｂ合金膜からなる保護膜で、露出配線
の表面を保護することができる。As the refractory metal, for example, tungsten and / or molybdenum is used. As a result, by using alkylamine borane as the reducing agent, the surface of the exposed wiring is protected by the protective film formed of the Co-WB alloy film, the Co-Mo-B alloy film or the Co-Mo-WB alloy film. Can be protected.
【００１５】本発明の半導体装置は、銅、銅合金、銀ま
たは銀合金を配線材料とした埋め込み配線構造を有し、
コバルトイオン、錯化剤、及びアルカリ金属を含まない
還元剤を含有する無電解めっき液を用いた無電解めっき
を施して、露出配線の表面を保護膜で選択的に覆ったこ
とを特徴とする。The semiconductor device of the present invention has a buried wiring structure using copper, copper alloy, silver or silver alloy as a wiring material.
Characterized by electroless plating using an electroless plating solution containing a cobalt ion, a complexing agent, and a reducing agent containing no alkali metal, and selectively covering the surface of the exposed wiring with a protective film. .
【００１６】これにより、銀や銅との結合力が強く、か
つ比抵抗（ρ）の低い合金膜からなる保護膜で配線の表
面を選択的に覆って配線を保護することで、埋め込み配
線構造を有する半導体装置における層間絶縁膜の誘電率
の上昇を抑え、更に配線材料として銀や銅のような低抵
抗材料を使用することで、半導体装置の高速化、高密度
化を図ることができる。As a result, the surface of the wiring is selectively covered with the protective film made of an alloy film having a strong binding force with silver or copper and having a low specific resistance (ρ) to protect the wiring. By suppressing an increase in the dielectric constant of the interlayer insulating film in the semiconductor device having the above, and by using a low resistance material such as silver or copper as the wiring material, it is possible to increase the speed and density of the semiconductor device.
【００１７】本発明の他の半導体装置は、埋め込み配線
構造を有する半導体装置の露出配線の表面が、コバルト
を含有する金属膜からなる保護膜で選択的に覆われてい
ることを特徴とする。この金属膜の膜厚は、例えば０．
１から５００ｎｍの範囲内にあることが好ましい。Another semiconductor device of the present invention is characterized in that a surface of an exposed wiring of a semiconductor device having a buried wiring structure is selectively covered with a protective film made of a metal film containing cobalt. The film thickness of this metal film is, for example, 0.
It is preferably in the range of 1 to 500 nm.
【００１８】本発明の更に他の半導体装置は、埋め込み
配線構造を有する半導体装置の露出配線の表面が、コバ
ルトと高融点金属を含む金属の合金からなる保護膜で選
択的に覆われていることを特徴とする。この高融点金属
としては、例えばタングステン及び／又はモリブデンが
使用される。In still another semiconductor device of the present invention, the surface of the exposed wiring of the semiconductor device having a buried wiring structure is selectively covered with a protective film made of an alloy of a metal containing cobalt and a refractory metal. Is characterized by. As the refractory metal, for example, tungsten and / or molybdenum is used.
【００１９】この合金としては、例えばＣｏ−Ｂ合金、
Ｃｏ−Ｐ合金、Ｃｏ−Ｗ−Ｂ合金、Ｃｏ−Ｗ−Ｐ合金、
Ｃｏ−Ｍｏ−Ｂ合金、Ｃｏ−Ｍｏ−Ｐ合金、Ｃｏ−Ｗ−
Ｍｏ−Ｂ合金、Ｃｏ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−
Ｂ合金、Ｃｏ−Ｔｉ−Ｐ合金、Ｃｏ−Ｔａ−Ｂ合金、Ｃ
ｏ−Ｔａ−Ｐ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｔａ−Ｐ合金、Ｃｏ−Ｔｉ−Ｗ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｗ−Ｐ合金、Ｃｏ−Ｔｉ−Ｍｏ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｂ合金、Ｃｏ
−Ｔｉ−Ｔａ−Ｐ合金、Ｃｏ−Ｔａ−Ｗ−Ｂ合金、Ｃｏ
−Ｔａ−Ｗ−Ｐ合金、Ｃｏ−Ｔａ−Ｍｏ−Ｂ合金、Ｃｏ
−Ｔａ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−Ｗ−Ｍｏ−Ｂ合
金、Ｃｏ−Ｔｉ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔａ−Ｗ−
Ｍｏ−Ｂ合金、Ｃｏ−Ｔａ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−
Ｔｉ−Ｔａ−Ｗ−Ｍｏ−Ｂ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｗ
−Ｍｏ−Ｐ合金等が挙げられる。As this alloy, for example, Co--B alloy,
Co-P alloy, Co-WB alloy, Co-W-P alloy,
Co-Mo-B alloy, Co-Mo-P alloy, Co-W-
Mo-B alloy, Co-W-Mo-P alloy, Co-Ti-
B alloy, Co-Ti-P alloy, Co-Ta-B alloy, C
o-Ta-P alloy, Co-Ti-Ta-B alloy, Co-
Ti-Ta-P alloy, Co-Ti-WB alloy, Co-
Ti-WP alloy, Co-Ti-Mo-B alloy, Co-
Ti-Mo-P alloy, Co-Ti-Ta-B alloy, Co
-Ti-Ta-P alloy, Co-Ta-WB alloy, Co
-Ta-WP alloy, Co-Ta-Mo-B alloy, Co
-Ta-Mo-P alloy, Co-Ti-W-Mo-B alloy, Co-Ti-W-Mo-P alloy, Co-Ta-W-
Mo-B alloy, Co-Ta-W-Mo-P alloy, Co-
Ti-Ta-W-Mo-B alloy, Co-Ti-Ta-W
-Mo-P alloy etc. are mentioned.
【００２０】[0020]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図１（ａ）乃至図１（ｃ）
は、本発明の半導体装置における銅配線形成例を工程順
に示すもので、図１（ａ）に示すように、半導体素子を
形成した半導体基材１上の導電層１ａの上にＳｉＯ２か
らなる絶縁膜２を堆積し、この絶縁膜２の内部に、例え
ばリソグラフィ・エッチング技術によりコンタクトホー
ル３と配線用の溝４を形成し、その上にＴａＮ等からな
るバリア層５、更にその上に電解めっきの給電層として
の銅シード層６をスパッタリング等により形成する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (c)
FIG. 1 shows an example of copper wiring formation in the semiconductor device of the present invention in the order of steps. As shown in FIG. 1A, SiO 2 is formed on a conductive layer 1a on a semiconductor substrate 1 on which a semiconductor element is formed. An insulating film 2 is deposited, a contact hole 3 and a wiring groove 4 are formed inside the insulating film 2 by, for example, a lithographic etching technique, a barrier layer 5 made of TaN or the like is formed thereon, and an electrolytic film is formed on the barrier layer 5. A copper seed layer 6 as a power feeding layer for plating is formed by sputtering or the like.
【００２１】そして、図１（ａ）に示すように、半導体
基板Ｗの表面に銅めっきを施すことで、半導体基板Ｗの
コンタクトホール３及び溝４内に銅を充填させるととも
に、絶縁膜２上に銅層７を堆積させる。その後、化学的
機械的研磨（ＣＭＰ）により、絶縁膜２上の銅層７を除
去して、コンタクトホール３及び配線用の溝４に充填さ
せた銅層７の表面と絶縁膜２の表面とをほぼ同一平面に
する。これにより、図１（ｃ）に示すように、絶縁膜２
の内部に銅シード層６と銅層７からなる配線８を形成す
る。Then, as shown in FIG. 1A, the contact hole 3 and the groove 4 of the semiconductor substrate W are filled with copper by plating the surface of the semiconductor substrate W with copper, and at the same time, on the insulating film 2. A copper layer 7 is deposited on. Then, the copper layer 7 on the insulating film 2 is removed by chemical mechanical polishing (CMP), and the surface of the copper layer 7 filled in the contact hole 3 and the wiring groove 4 and the surface of the insulating film 2 are removed. Are almost in the same plane. As a result, as shown in FIG. 1C, the insulating film 2
A wiring 8 composed of a copper seed layer 6 and a copper layer 7 is formed inside.
【００２２】次に、半導体基板Ｗの表面に無電解めっき
を施して、配線８の外部への露出表面に、合金膜からな
る保護膜９を選択的に形成して配線８を保護する。この
保護膜９の膜厚は、０．１〜５００ｎｍ、好ましくは、
１〜２００ｎｍ、更に好ましくは、１０〜１００ｎｍ程
度である。Next, the surface of the semiconductor substrate W is electroless plated to selectively form a protective film 9 made of an alloy film on the exposed surface of the wiring 8 to protect the wiring 8. The protective film 9 has a thickness of 0.1 to 500 nm, preferably
The thickness is 1 to 200 nm, and more preferably 10 to 100 nm.
【００２３】この保護膜９は、例えば、コバルトイオ
ン、錯化剤、ｐＨ緩衝剤、ｐＨ調整剤及び還元剤として
のアルキルアミンボランを含有するめっき液、更には、
この他にタングステンやモリブデン等の高融点金属を含
有しためっき液を使用し、このめっき液に半導体基板Ｗ
の表面を浸漬させることで形成される。The protective film 9 is, for example, a plating solution containing cobalt ions, a complexing agent, a pH buffering agent, a pH adjusting agent and an alkylamine borane as a reducing agent, and further,
In addition, a plating solution containing a refractory metal such as tungsten or molybdenum is used.
It is formed by immersing the surface of.
【００２４】このめっき液には、必要に応じて、安定剤
としての重金属化合物または硫黄化合物の１種または２
種以上、または界面活性剤の少なくとも一方が添加さ
れ、またアンモニア水または水酸化第四級アンモニウム
等のｐＨ調整剤を用いて、ｐＨが好ましくは５〜１４、
より好ましくは６〜１０に調整されている。めっき液の
温度は、例えば３０〜９０℃、好ましくは４０〜８０℃
である。If necessary, the plating solution may contain one or two of a heavy metal compound or a sulfur compound as a stabilizer.
Or more, or at least one of surfactants is added, and the pH is preferably 5 to 14, using a pH adjuster such as aqueous ammonia or quaternary ammonium hydroxide.
It is more preferably adjusted to 6 to 10. The temperature of the plating solution is, for example, 30 to 90 ° C, preferably 40 to 80 ° C.
Is.
【００２５】このように、保護膜９を形成して配線８を
保護することで、この上に多層に埋め込み配線を形成す
る際、例えば次工程の層間絶縁膜形成プロセスにおける
ＳｉＯ２形成時の表面酸化やＳｉＯ２エッチング等に際
して、エッチャントやレジスト剥離等によって、配線が
汚染されるのを防止することができる。By thus forming the protective film 9 to protect the wiring 8 and thus forming a multi-layered buried wiring thereon, for example, the surface at the time of forming SiO 2 in the interlayer insulating film forming process of the next step. It is possible to prevent the wiring from being contaminated by an etchant, resist peeling, or the like during oxidation or SiO 2 etching.
【００２６】ここで、めっき液として、コバルトイオ
ン、錯化剤、ｐＨ緩衝剤、ｐＨ調整剤及び還元剤として
のアルキルアミンボランを含有するめっき液を使用する
と、Ｃｏ−Ｂ合金膜からなる保護膜９が形成され、この
他にタングステンやモリブデン等の高融点金属を含有し
ためっき液を使用すると、Ｃｏ−Ｗ−Ｂ合金膜、Ｃｏ−
Ｍｏ−Ｂ合金膜またはＣｏ−Ｍｏ−Ｗ−Ｂ合金膜からな
る保護膜９が形成される。このように、配線材料として
の銅との結合力が強く、かつ比抵抗（ρ）の低い合金膜
からなる保護膜９で配線８の表面を選択的に覆って配線
８を保護することで、埋め込み配線構造を有する半導体
における層間絶縁膜の誘電率の上昇を抑え、更に配線材
料として低抵抗材料である銅を使用することで、半導体
の高速化、高密度化を図ることができる。なお、この例
は、配線材料として、銅を使用した例を示しているが、
この銅の他に、銅合金、銀及び銀合金等を使用しても良
い。When a plating solution containing cobalt ions, a complexing agent, a pH buffering agent, a pH adjusting agent and an alkylamine borane as a reducing agent is used as the plating solution, a protective film made of a Co--B alloy film is used. 9 is formed, and when a plating solution containing a refractory metal such as tungsten or molybdenum is used, a Co-WB alloy film, a Co-
The protective film 9 made of a Mo-B alloy film or a Co-Mo-WB alloy film is formed. In this way, by selectively covering the surface of the wiring 8 with the protective film 9 made of an alloy film having a strong bonding force with copper as a wiring material and having a low specific resistance (ρ), the wiring 8 is protected. By suppressing an increase in the dielectric constant of the interlayer insulating film in a semiconductor having a buried wiring structure and by using copper, which is a low resistance material, as a wiring material, it is possible to increase the speed and density of the semiconductor. Although this example shows an example in which copper is used as the wiring material,
In addition to this copper, copper alloy, silver, silver alloy, etc. may be used.
【００２７】めっき液のコバルトイオンの供給源として
は、例えば硫酸コバルト、塩化コバルト、酢酸コバルト
等のコバルト塩を挙げることができる。コバルトイオン
の添加量は、例えば０．００１〜１ｍｏｌ／Ｌ、好まし
くは０．０１〜０．３ｍｏｌ／Ｌ程度である。Examples of the cobalt ion supply source of the plating solution include cobalt salts such as cobalt sulfate, cobalt chloride, and cobalt acetate. The amount of cobalt ions added is, for example, about 0.001 to 1 mol / L, preferably about 0.01 to 0.3 mol / L.
【００２８】錯化剤としては、例えば酢酸等のカルボン
酸及びそれらの塩、酒石酸、クエン酸等のオキシカルボ
ン酸及びそれらの塩、グリシン等のアミノカルボン酸及
びそれらの塩を挙げることができる。また、それらは単
独で使用してもよく、２種以上併用してもよい。錯化剤
の総添加量は、例えば０．００１〜１．５ｍｏｌ／Ｌ、
好ましくは０．０１〜１．０ｍｏｌ／Ｌ程度である。Examples of the complexing agent include carboxylic acids such as acetic acid and salts thereof, oxycarboxylic acids such as tartaric acid and citric acid and salts thereof, aminocarboxylic acids such as glycine and salts thereof. Further, they may be used alone or in combination of two or more kinds. The total amount of complexing agent added is, for example, 0.001 to 1.5 mol / L,
It is preferably about 0.01 to 1.0 mol / L.
【００２９】ｐＨ緩衝剤としては、ナトリウム等のアル
カリ金属を含まないものであればよく、例えば硫酸アン
モニウム、塩化アンモニウム、ホウ酸等を挙げることが
できる。ｐＨ緩衝剤の添加量は、例えば０．０１〜１．
５ｍｏｌ／Ｌ、好ましくは０．１〜１ｍｏｌ／Ｌ程度あ
る。Any pH buffer may be used as long as it does not contain an alkali metal such as sodium, and examples thereof include ammonium sulfate, ammonium chloride and boric acid. The addition amount of the pH buffer is, for example, 0.01 to 1.
It is about 5 mol / L, preferably about 0.1 to 1 mol / L.
【００３０】ｐＨ調整剤としては、ナトリウム等のアル
カリ金属を含まないものであればよく、例えばアンモニ
ア水、水酸化テトラメチルアンモニウム（ＴＭＡＨ）等
を挙げることができ、ｐＨを５〜１４、好ましくはｐＨ
６〜１０に調整する。還元剤も、ナトリウム等のアルカ
リ金属を含まないものである必要があり、アルキルアミ
ンボランが好適である。アルキルアミンボランとして
は、例えばジメチルアミンボラン（ＤＭＡＢ）、ジエチ
ルアミンボラン等を挙げることができる。還元剤の添加
量は、例えば０．０１〜１ｍｏｌ／Ｌ、好ましくは０．
０１〜０．５ｍｏｌ／Ｌ程度である。The pH adjustor may be any one containing no alkali metal such as sodium, and examples thereof include aqueous ammonia and tetramethylammonium hydroxide (TMAH). The pH is 5 to 14, preferably. pH
Adjust to 6-10. The reducing agent also needs to contain no alkali metal such as sodium, and alkylamine borane is preferable. Examples of the alkylamine borane include dimethylamine borane (DMAB) and diethylamine borane. The amount of the reducing agent added is, for example, 0.01 to 1 mol / L, preferably 0.1.
It is about 01 to 0.5 mol / L.
【００３１】高融点金属を含む化合物としては、例えば
タングステン酸、モリブデン酸等及びそれらの塩、また
は、タングストリン酸（例えば、Ｈ３(ＰＷ１２Ｐ４０)
・ｎＨ２Ｏ）等のヘテロポリ酸及びそれらの塩等を挙げ
ることができる。また、無電解めっきの手段によらなけ
れば、ＴｉやＴａ等を用いてもよい。高融点金属を含む
化合物の添加量は、例えば０．００１〜１ｍｏｌ／Ｌ、
好ましくは０．０１〜０．１ｍｏｌ／Ｌ程度である。コ
バルトと高融点金属との合金としては、Ｃｏ−Ｂ合金、
Ｃｏ−Ｐ合金、Ｃｏ−Ｗ−Ｂ合金、Ｃｏ−Ｗ−Ｐ合金、
Ｃｏ−Ｍｏ−Ｂ合金、Ｃｏ−Ｍｏ−Ｐ合金、Ｃｏ−Ｗ−
Ｍｏ−Ｂ合金、Ｃｏ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−
Ｂ合金、Ｃｏ−Ｔｉ−Ｐ合金、Ｃｏ−Ｔａ−Ｂ合金、Ｃ
ｏ−Ｔａ−Ｐ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｔａ−Ｐ合金、Ｃｏ−Ｔｉ−Ｗ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｗ−Ｐ合金、Ｃｏ−Ｔｉ−Ｍｏ−Ｂ合金、Ｃｏ−
Ｔｉ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｂ合金、Ｃｏ
−Ｔｉ−Ｔａ−Ｐ合金、Ｃｏ−Ｔａ−Ｗ−Ｂ合金、Ｃｏ
−Ｔａ−Ｗ−Ｐ合金、Ｃｏ−Ｔａ−Ｍｏ−Ｂ合金、Ｃｏ
−Ｔａ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔｉ−Ｗ−Ｍｏ−Ｂ合
金、Ｃｏ−Ｔｉ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−Ｔａ−Ｗ−
Ｍｏ−Ｂ合金、Ｃｏ−Ｔａ−Ｗ−Ｍｏ−Ｐ合金、Ｃｏ−
Ｔｉ−Ｔａ−Ｗ−Ｍｏ−Ｂ合金、Ｃｏ−Ｔｉ−Ｔａ−Ｗ
−Ｍｏ−Ｐ合金等が挙がられる。このうち、タングステ
ン及び／又はモリブデンを含む合金は、本発明の無電解
めっきに使用するのに特に好適であり、ボロン及びリン
を含む合金は、アルカリ金属を含まなければ使用可能で
ある。ＴｉとＴａを含む合金は、無電解めっき以外の手
段で使用可能である。Examples of the compound containing a refractory metal include tungstic acid, molybdic acid, etc. and salts thereof, or tungstophosphoric acid (eg, H 3 (PW 12 P 40 ).
-Heteropoly acids such as nH 2 O) and salts thereof can be mentioned. Further, Ti, Ta, or the like may be used as long as it does not use electroless plating. The addition amount of the compound containing the high melting point metal is, for example, 0.001 to 1 mol / L,
It is preferably about 0.01 to 0.1 mol / L. As an alloy of cobalt and a high melting point metal, a Co-B alloy,
Co-P alloy, Co-WB alloy, Co-W-P alloy,
Co-Mo-B alloy, Co-Mo-P alloy, Co-W-
Mo-B alloy, Co-W-Mo-P alloy, Co-Ti-
B alloy, Co-Ti-P alloy, Co-Ta-B alloy, C
o-Ta-P alloy, Co-Ti-Ta-B alloy, Co-
Ti-Ta-P alloy, Co-Ti-WB alloy, Co-
Ti-WP alloy, Co-Ti-Mo-B alloy, Co-
Ti-Mo-P alloy, Co-Ti-Ta-B alloy, Co
-Ti-Ta-P alloy, Co-Ta-WB alloy, Co
-Ta-WP alloy, Co-Ta-Mo-B alloy, Co
-Ta-Mo-P alloy, Co-Ti-W-Mo-B alloy, Co-Ti-W-Mo-P alloy, Co-Ta-W-
Mo-B alloy, Co-Ta-W-Mo-P alloy, Co-
Ti-Ta-W-Mo-B alloy, Co-Ti-Ta-W
-Mo-P alloy etc. are mentioned. Of these, alloys containing tungsten and / or molybdenum are particularly suitable for use in the electroless plating of the present invention, and alloys containing boron and phosphorus can be used as long as they do not contain an alkali metal. The alloy containing Ti and Ta can be used by means other than electroless plating.
【００３２】このめっき液には、上記成分以外に公知の
添加剤を添加することができる。この添加剤としては、
例えば、浴安定剤として鉛化合物等の重金属化合物やチ
オシアン化合物等の硫黄化合物等の１種または２種以
上、またアニオン系、カチオン系、ノニオン系の界面活
性剤を挙げることができる。In addition to the above components, known additives can be added to this plating solution. As this additive,
Examples of the bath stabilizer include one or more kinds of heavy metal compounds such as lead compounds and sulfur compounds such as thiocyan compounds, and anionic, cationic and nonionic surfactants.
【００３３】前述のように、還元剤として、銅、銅合
金、銀または銀合金に対して酸化電流を流せて直接無電
解めっきが可能で、ナトリウムを含有していないアルキ
ルアミンボランを用いることが好ましく、これにより、
半導体装置のアルカリ金属による汚染を防止し、しかも
パラジウム触媒の付与を不要となすことができる。つま
り、還元剤としてアルキルアミンボランを使用した無電
解めっき液を使用して無電解めっきを行うことにより、
パラジウム触媒を付与することなく、半導体基板Ｗの表
面をめっき液に浸漬させて無電解めっきを行うことがで
き、これにより、工程を短縮してスループットを向上さ
せ、しかもパラジウムの置換によって銅配線の内部にボ
イドが生成されることを防止して、更にパラジウム拡散
による配線抵抗の上昇をなくすことができる。As described above, as the reducing agent, it is possible to use an alkylamine borane containing no sodium, which is capable of direct electroless plating by applying an oxidizing current to copper, copper alloy, silver or silver alloy. Preferably, this allows
It is possible to prevent the semiconductor device from being contaminated with alkali metal and to dispense with the addition of the palladium catalyst. That is, by performing electroless plating using an electroless plating solution using alkylamine borane as a reducing agent,
The electroless plating can be performed by immersing the surface of the semiconductor substrate W in a plating solution without applying a palladium catalyst, thereby shortening the process and improving the throughput, and by replacing palladium, copper wiring can be formed. It is possible to prevent the formation of voids inside and further prevent the increase in wiring resistance due to palladium diffusion.
【００３４】更に、アルキルアミンボランを還元剤とす
るめっき液を使用して無電解めっきを行うと、銅や銀に
選択的にめっきされることが知られており、配線形成領
域のみの選択的めっきが可能となる。Further, it is known that when electroless plating is performed using a plating solution containing alkylamine borane as a reducing agent, copper or silver is selectively plated, and only the wiring formation region is selectively plated. Plating is possible.
【００３５】図２は、無電解めっき装置の概略構成図で
ある。図２に示すように、この無電解めっき装置は、半
導体基板Ｗをその上面に保持する保持手段１１と、保持
手段１１に保持された半導体基板Ｗの被めっき面（上
面）の周縁部に当接して該周縁部をシールする堰部材
（めっき液保持機構）３１と、堰部材３１でその周縁部
をシールされた半導体基板Ｗの被めっき面にめっき液
（無電解めっき液）を供給するシャワーヘッド（無電解
めっき液（分散）供給手段）４１を備えている。無電解
めっき装置は、さらに保持手段１１の上部外周近傍に設
置されて半導体基板Ｗの被めっき面に洗浄液を供給する
洗浄液供給手段５１と、排出された洗浄液等（めっき廃
液）を回収する回収容器６１と、半導体基板Ｗ上に保持
しためっき液を吸引して回収するめっき液回収ノズル６
５と、前記保持手段１１を回転駆動するモータ（回転駆
動手段）Ｍとを備えている。FIG. 2 is a schematic configuration diagram of the electroless plating apparatus. As shown in FIG. 2, this electroless plating apparatus contacts a holding means 11 for holding the semiconductor substrate W on its upper surface and a peripheral portion of a plated surface (upper surface) of the semiconductor substrate W held by the holding means 11. A dam member (plating solution holding mechanism) 31 that contacts and seals the peripheral edge portion, and a shower that supplies a plating solution (electroless plating solution) to the surface to be plated of the semiconductor substrate W whose peripheral edge portion is sealed by the dam member 31. A head (electroless plating solution (dispersion) supply means) 41 is provided. The electroless plating apparatus is further installed near the outer periphery of the upper part of the holding means 11, and is provided with a cleaning liquid supply means 51 for supplying a cleaning liquid to the surface to be plated of the semiconductor substrate W, and a recovery container for collecting the discharged cleaning liquid or the like (plating waste liquid). 61 and a plating solution recovery nozzle 6 for sucking and recovering the plating solution held on the semiconductor substrate W
5 and a motor (rotational drive means) M for rotationally driving the holding means 11.
【００３６】保持手段１１は、その上面に半導体基板Ｗ
を載置して保持する基板載置部１３を有している。この
基板載置部１３は、半導体基板Ｗを載置して固定するよ
うに構成されており、具体的には半導体基板Ｗをその裏
面側に真空吸着する図示しない真空吸着機構を備えてい
る。一方、基板載置部１３の裏面側には、面状であって
半導体基板Ｗの被めっき面を下面側から暖めて保温する
裏面ヒータ（加熱手段）１５が設置されている。この裏
面ヒータ１５は、例えばラバーヒータによって構成され
ている。この保持手段１１は、モータＭによって回転駆
動されると共に、図示しない昇降手段によって上下動で
きるように構成されている。The holding means 11 has a semiconductor substrate W on its upper surface.
It has a substrate mounting portion 13 for mounting and holding. The substrate mounting portion 13 is configured to mount and fix the semiconductor substrate W, and specifically includes a vacuum suction mechanism (not shown) that vacuum-sucks the semiconductor substrate W on its back surface side. On the other hand, on the back surface side of the substrate mounting portion 13, there is provided a back surface heater (heating means) 15 which is planar and warms and heats the plated surface of the semiconductor substrate W from the lower surface side. The back surface heater 15 is composed of, for example, a rubber heater. The holding means 11 is configured to be rotationally driven by a motor M and can be moved up and down by an elevating means (not shown).
【００３７】堰部材３１は、筒状であってその下部に半
導体基板Ｗの外周縁をシールするシール部３３を有し、
図示の位置から上下動しないように設置されている。シ
ャワーヘッド４１は、先端に多数のノズルを設けること
で、供給されためっき液をシャワー状に分散して半導体
基板Ｗの被めっき面に略均一に供給する構造のものであ
る。また洗浄液供給手段５１は、ノズル５３から洗浄液
を噴出する構造である。The dam member 31 is cylindrical and has a seal portion 33 for sealing the outer peripheral edge of the semiconductor substrate W at the lower portion thereof.
It is installed so as not to move up and down from the position shown. The shower head 41 has a structure in which a large number of nozzles are provided at the tip of the shower head 41 to disperse the supplied plating solution in a shower shape and supply the plated surface of the semiconductor substrate W substantially uniformly. The cleaning liquid supply means 51 has a structure in which the cleaning liquid is ejected from the nozzle 53.
【００３８】めっき液回収ノズル６５は、上下動且つ旋
回できるように構成されていて、その先端が半導体基板
Ｗの上面周縁部の堰部材３１の内側に下降して半導体基
板Ｗ上のめっき液を吸引するように構成されている。The plating solution recovery nozzle 65 is constructed so that it can move up and down and swirl, and its tip descends inside the dam member 31 at the peripheral portion of the upper surface of the semiconductor substrate W to remove the plating solution on the semiconductor substrate W. It is configured to aspirate.
【００３９】次に、この無電解めっき装置の動作を説明
する。まず図示の状態よりも保持手段１１を下降させて
堰部材３１との間に所定寸法の隙間を設け、基板載置部
１３に半導体基板Ｗを載置・固定する。半導体基板Ｗと
しては、例えばφ８インチウエハを用いる。Next, the operation of this electroless plating apparatus will be described. First, the holding means 11 is lowered from the state shown in the drawing to provide a gap of a predetermined size between the holding means 11 and the dam member 31, and the semiconductor substrate W is mounted and fixed on the substrate mounting portion 13. As the semiconductor substrate W, for example, a φ8 inch wafer is used.
【００４０】次に、図２に示すように、保持手段１１を
上昇させ、その上面を堰部材３１の下面に当接させ、同
時に半導体基板Ｗの外周を堰部材３１のシール部３３に
よってシールする。この時、半導体基板Ｗの表面は開放
された状態となっている。次に裏面ヒータ１５によって
半導体基板Ｗ自体を直接加熱して、シャワーヘッド４１
からめっき液を噴出して半導体基板Ｗの表面の略全体に
めっき液を降り注ぐ。半導体基板Ｗの表面は、堰部材３
１によって囲まれているので、注入しためっき液は全て
半導体基板Ｗの表面に保持される。供給するめっき液の
量は、半導体基板Ｗの表面に１ｍｍ厚（約３０ｍｌ）と
なる程度の少量で良い。なお被めっき面上に保持するめ
っき液の深さは１０ｍｍ以下であれば良く、この例のよ
うに１ｍｍでも良い。供給するめっき液が少量で済めば
これを加熱する加熱装置も小型のもので良くなる。Next, as shown in FIG. 2, the holding means 11 is raised, its upper surface is brought into contact with the lower surface of the dam member 31, and at the same time, the outer periphery of the semiconductor substrate W is sealed by the seal portion 33 of the dam member 31. . At this time, the surface of the semiconductor substrate W is in an open state. Next, the back surface heater 15 directly heats the semiconductor substrate W itself, and the shower head 41
The plating solution is jetted from the above to pour the plating solution onto almost the entire surface of the semiconductor substrate W. The surface of the semiconductor substrate W has the dam member 3
Since it is surrounded by 1, all of the injected plating solution is retained on the surface of the semiconductor substrate W. The amount of the plating solution supplied may be as small as 1 mm (about 30 ml) on the surface of the semiconductor substrate W. The depth of the plating solution held on the surface to be plated may be 10 mm or less, and may be 1 mm as in this example. If only a small amount of plating solution needs to be supplied, a small heating device for heating the plating solution will suffice.
【００４１】このように、半導体基板Ｗ自体を加熱する
ように構成すれば、加熱するのに大きな消費電力が必要
なめっき液の温度をそれほど高く昇温しなくても良いの
で、消費電力の低減化やめっき液の材質変化の防止が図
れ、好適である。なお半導体基板Ｗ自体の加熱のための
消費電力は小さくて良く、また半導体基板Ｗ上に溜める
めっき液の量は少ないので、裏面ヒータ１５による半導
体基板Ｗの保温は容易に行え、裏面ヒータ１５の容量は
小さくて良く、装置のコンパクト化を図ることができ
る。また半導体基板Ｗ自体を直接冷却する手段をも用い
れば、めっき中に加熱・冷却を切替えてめっき条件を変
化させることも可能である。半導体基板上に保持されて
いるめっき液は少量なので、感度良く温度制御が行え
る。In this way, if the semiconductor substrate W itself is heated, the temperature of the plating solution, which requires a large amount of power consumption for heating, does not have to be raised so high, so the power consumption is reduced. This is preferable because it can prevent the formation of metal and the change of the material of the plating solution. Since the power consumption for heating the semiconductor substrate W itself may be small and the amount of the plating solution accumulated on the semiconductor substrate W is small, the backside heater 15 can easily keep the temperature of the semiconductor substrate W, and the backside heater 15 can be kept warm. The capacity may be small, and the device can be made compact. Further, if the means for directly cooling the semiconductor substrate W itself is also used, it is possible to change the plating conditions by switching between heating and cooling during plating. Since a small amount of plating solution is held on the semiconductor substrate, temperature control can be performed with good sensitivity.
【００４２】そして、モータＭによって半導体基板Ｗを
瞬時回転させて被めっき面の均一な液濡れを行い、その
後半導体基板Ｗを静止した状態で被めっき面のめっきを
行う。具体的には、半導体基板Ｗを１ｓｅｃだけ１００
ｒｐｍ以下で回転させて半導体基板Ｗの被めっき面上を
めっき液で均一に濡らし、その後静止させて１ｍｉｎ間
無電解めっきを行わせる。なお瞬時回転時間は長くても
１０ｓｅｃ以下とする。上記めっき処理が完了した後、
めっき液回収ノズル６５の先端を半導体基板Ｗの表面周
縁部の堰部材３１の内側近傍に下降させ、めっき液を吸
い込む。このとき、半導体基板Ｗを、例えば１００ｒｐ
ｍ以下の回転速度で回転させれば、半導体基板Ｗ上に残
っためっき液を遠心力で半導体基板Ｗの周縁部の堰部材
３１の部分に集めて、効率良く、且つ高い回収率でめっ
き液の回収ができる。そして保持手段１１を下降させて
半導体基板Ｗを堰部材３１から離し、半導体基板Ｗを回
転させつつ洗浄液供給手段５１のノズル５３から洗浄液
（超純水）を半導体基板Ｗの被めっき面に噴射し、被め
っき面を冷却すると同時にめっき液を希釈化し洗浄する
ことで無電解めっき反応を停止させる。このとき、ノズ
ル５３から噴射される洗浄液を堰部材３１にも当てるこ
とで堰部材３１の洗浄を同時に行っても良い。このとき
のめっき廃液は、回収容器６１に回収され、廃棄され
る。なお、一度使用しためっき液は再利用せず、使い捨
てとする。前述のように、この装置において使用される
めっき液の量は、従来に比べて非常に少なくできるの
で、再利用しなくても廃棄するめっき液の量は少ない。
なお場合によってはめっき液回収ノズル６５を設置しな
いで、使用後のめっき液も洗浄液と共にめっき廃液とし
て回収容器６１に回収しても良い。そしてモータＭによ
って半導体基板Ｗを高速回転してスピン乾燥した後、保
持手段１１から取り出す。Then, the semiconductor substrate W is momentarily rotated by the motor M to uniformly wet the surface to be plated, and then the surface to be plated is plated while the semiconductor substrate W is stationary. Specifically, the semiconductor substrate W is set to 100 for 1 sec.
The surface to be plated of the semiconductor substrate W is uniformly wetted with the plating solution by rotating at rpm or less, and then allowed to stand still to perform electroless plating for 1 min. The instantaneous rotation time is at most 10 seconds. After the above plating process is completed,
The tip of the plating solution recovery nozzle 65 is lowered to the vicinity of the inside of the dam member 31 at the peripheral portion of the surface of the semiconductor substrate W, and the plating solution is sucked. At this time, the semiconductor substrate W is, for example, 100 rp.
If the plating solution is rotated at a rotation speed of m or less, the plating solution remaining on the semiconductor substrate W is collected by centrifugal force in the portion of the dam member 31 at the peripheral edge of the semiconductor substrate W, and the plating solution is efficiently and with a high recovery rate. Can be collected. Then, the holding means 11 is lowered to separate the semiconductor substrate W from the dam member 31, and while the semiconductor substrate W is rotated, the cleaning liquid (ultra pure water) is sprayed from the nozzle 53 of the cleaning liquid supply means 51 onto the surface to be plated of the semiconductor substrate W. At the same time as cooling the surface to be plated, the electroless plating reaction is stopped by diluting and washing the plating solution. At this time, the cleaning liquid sprayed from the nozzle 53 may be applied to the dam member 31 to simultaneously clean the dam member 31. The plating waste liquid at this time is collected in the collection container 61 and discarded. It should be noted that the plating solution used once should not be reused and should be disposable. As described above, the amount of the plating solution used in this apparatus can be made much smaller than in the conventional case, and therefore the amount of the plating solution to be discarded is small even if it is not reused.
In some cases, the plating solution recovery nozzle 65 may not be installed, and the used plating solution may be recovered together with the cleaning solution in the recovery container 61 as a plating waste solution. Then, the semiconductor substrate W is rotated at high speed by the motor M to spin-dry, and then taken out from the holding means 11.
【００４３】図３は、他の無電解めっき装置の概略構成
図である。図３において、図２に示す無電解めっき装置
と相違する点は、保持手段１１内に裏面ヒータ１５を設
ける代わりに、保持手段１１の上方にランプヒータ（加
熱手段）１７を設置し、このランプヒータ１７とシャワ
ーヘッド４１−２とを一体化した点である。即ち、例え
ば複数の半径の異なるリング状のランプヒータ１７を同
心円状に設置し、ランプヒータ１７の間の隙間からシャ
ワーヘッド４１−２の多数のノズル４３−２をリング状
に開口させている。なおランプヒータ１７としては、渦
巻状の一本のランプヒータで構成しても良いし、さらに
それ以外の各種構造・配置のランプヒータで構成しても
良い。FIG. 3 is a schematic configuration diagram of another electroless plating apparatus. 3 is different from the electroless plating apparatus shown in FIG. 2 in that instead of providing the back surface heater 15 in the holding means 11, a lamp heater (heating means) 17 is installed above the holding means 11 and this lamp is used. This is the point that the heater 17 and the shower head 41-2 are integrated. That is, for example, a plurality of ring-shaped lamp heaters 17 having different radii are installed concentrically, and a large number of nozzles 43-2 of the shower head 41-2 are opened in a ring shape from the gaps between the lamp heaters 17. It should be noted that the lamp heater 17 may be composed of a single spiral lamp heater, or may be composed of other lamp heaters having various structures and arrangements.
【００４４】このように構成しても、めっき液は各ノズ
ル４３−２から半導体基板Ｗの被めっき面上にシャワー
状に略均等に供給でき、またランプヒータ１７によって
半導体基板Ｗの加熱・保温も直接均一に行える。ランプ
ヒータ１７の場合、半導体基板Ｗとめっき液の他に、そ
の周囲の空気をも加熱するので半導体基板Ｗの保温効果
もある。Even with this structure, the plating solution can be supplied from the nozzles 43-2 to the surface of the semiconductor substrate W to be plated in a substantially uniform manner, and the lamp heater 17 can heat and heat the semiconductor substrate W. Can be done directly and evenly. In the case of the lamp heater 17, not only the semiconductor substrate W and the plating solution but also the surrounding air is heated, so that the semiconductor substrate W also has a heat retaining effect.
【００４５】なおランプヒータ１７によって半導体基板
Ｗを直接加熱するには、比較的大きい消費電力のランプ
ヒータ１７が必要になるので、その代わりに比較的小さ
い消費電力のランプヒータ１７と前記図２に示す裏面ヒ
ータ１５とを併用して、半導体基板Ｗは主として裏面ヒ
ータ１５によって加熱し、めっき液と周囲の空気の保温
は主としてランプヒータ１７によって行うようにしても
良い。また半導体基板Ｗを直接、または間接的に冷却す
る手段をも設けて、温度制御を行っても良い。In order to directly heat the semiconductor substrate W by the lamp heater 17, the lamp heater 17 of relatively large power consumption is required. Instead, the lamp heater 17 of relatively small power consumption and the lamp heater 17 shown in FIG. The semiconductor substrate W may be heated mainly by the rear surface heater 15 in combination with the rear surface heater 15 shown, and the lamp heater 17 may mainly maintain the temperature of the plating solution and the surrounding air. Further, a means for directly or indirectly cooling the semiconductor substrate W may be provided to control the temperature.
【００４６】図４は、本発明に係る半導体装置を製造す
る半導体製造装置の一例を示す平面配置図である。この
半導体製造装置は、カセット２０１−１を収容したロー
ドアンロード部２０１、第１めっき装置２０２、第１ロ
ボット２０３、反転機２０５，２０６、第２洗浄装置２
０７、第２ロボット２０８、第１洗浄装置２０９、第２
めっき装置２２７、第１ポリッシング装置２１０及び第
２ポリッシング装置２１１を有している。そして、第１
ロボット２０３の近傍には、めっき前後の膜厚を測定す
るめっき前後膜厚測定機２１２、研磨後で乾燥状態の半
導体基板Ｗの膜厚を測定する乾燥状態膜厚測定機２１３
が配置されている。FIG. 4 is a plan layout view showing an example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device according to the present invention. This semiconductor manufacturing apparatus includes a load / unload unit 201 accommodating a cassette 201-1, a first plating apparatus 202, a first robot 203, reversing machines 205 and 206, and a second cleaning apparatus 2.
07, second robot 208, first cleaning device 209, second
It has a plating device 227, a first polishing device 210 and a second polishing device 211. And the first
In the vicinity of the robot 203, a pre- and post-plating film thickness measuring device 212 for measuring the film thickness before and after plating, and a dry film thickness measuring device 213 for measuring the film thickness of the semiconductor substrate W in a dry state after polishing.
Are arranged.
【００４７】第１ポリッシング装置２１０は、研磨テー
ブル２１０−１、トップリング２１０−２、トップリン
グヘッド２１０−３、膜厚測定機２１０−４及びプッシ
ャー２１０−５を具備している。第２ポリッシング装置
２１１は、研磨テーブル２１１−１、トップリング２１
１−２、トップリングヘッド２１１−３、膜厚測定機２
１１−４及びプッシャー２１１−５を具備している。The first polishing apparatus 210 comprises a polishing table 210-1, a top ring 210-2, a top ring head 210-3, a film thickness measuring machine 210-4 and a pusher 210-5. The second polishing device 211 includes a polishing table 211-1 and a top ring 21.
1-2, top ring head 211-3, film thickness measuring device 2
11-4 and a pusher 211-5.
【００４８】次に、この半導体製造装置での各工程につ
いて説明する。先ず、銅シード層６（図１（ａ）参照）
を形成した半導体基板Ｗを収容したカセット２０１−１
をロードアンロード部２０１のロードポートに載置す
る。第１ロボット２０３で半導体基板Ｗをカセット２０
１−１から取り出し、第１めっき装置２０２で銅層７
（図１（ｂ）参照）の成膜を行う。銅層７の成膜は、ま
ず半導体基板Ｗの表面の親水処理を行い、その後に銅め
っきを行う。その後、リンス若しくは洗浄を行う。時間
に余裕があれば、乾燥してもよい。第１ロボット２０３
で半導体基板Ｗを取り出す時にめっき前後膜厚測定機２
１２で銅膜７の膜厚を測定する。その測定結果は、半導
体基板Ｗの記録データとして記録され、なお且つ第１め
っき装置２０２の異常判定にも使用される。膜厚測定
後、第１ロボット２０３が半導体基板Ｗを反転機２０５
に渡し、半導体基板Ｗを反転させる。Next, each step in this semiconductor manufacturing apparatus will be described. First, the copper seed layer 6 (see FIG. 1A)
201-1 containing a semiconductor substrate W on which a wafer is formed
Is placed on the load port of the load / unload unit 201. The semiconductor substrate W is cassette 20 by the first robot 203.
The copper layer 7 is taken out from the 1-1 by the first plating device 202.
The film formation (see FIG. 1B) is performed. To form the copper layer 7, first, the surface of the semiconductor substrate W is subjected to hydrophilic treatment, and then copper plating is performed. After that, rinsing or cleaning is performed. If you have time, you can dry it. First robot 203
When the semiconductor substrate W is taken out with the
At 12, the film thickness of the copper film 7 is measured. The measurement result is recorded as the record data of the semiconductor substrate W and is also used for the abnormality determination of the first plating apparatus 202. After measuring the film thickness, the first robot 203 inverts the semiconductor substrate W by the reversing machine 205.
And the semiconductor substrate W is inverted.
【００４９】次に、第２ロボット２０８で反転機２０５
から半導体基板Ｗを取り上げプッシャー２１０−５又は
２１１−５に載せる。続いて、トップリング２１０−２
又は２１１−２で半導体基板Ｗを吸着し、研磨テーブル
２１０−１又２１１−１上に移送し、研磨テーブル２１
０−１又は２１１−１上の研磨面に押圧して研磨を行
う。Next, the reversing machine 205 is operated by the second robot 208.
The semiconductor substrate W is picked up and placed on the pusher 210-5 or 211-5. Then, the top ring 210-2
Alternatively, the semiconductor substrate W is adsorbed by 211-2 and transferred onto the polishing table 210-1 or 211-1.
Polishing is performed by pressing the polishing surface on 0-1 or 211-1.
【００５０】研磨終了後、トップリング２１０−２又は
２１１−２は、半導体基板Ｗをプッシャー２１０−５又
は２１１−５に戻し、第２ロボット２０８で半導体基板
Ｗを取り上げ、第１洗浄ユニット２０９に搬入する。こ
の時プッシャー２１０−５又は２１１−５上で薬液を半
導体基板Ｗの表面、裏面に噴出し、パーティクルを除去
したり、つきにくくすることもある。After completion of polishing, the top ring 210-2 or 211-2 returns the semiconductor substrate W to the pusher 210-5 or 211-5, picks up the semiconductor substrate W by the second robot 208, and transfers it to the first cleaning unit 209. Bring in. At this time, the chemical solution may be jetted onto the front and back surfaces of the semiconductor substrate W on the pusher 210-5 or 211-5 to remove particles or make them difficult to stick.
【００５１】第１洗浄ユニット２０９では、半導体基板
Ｗの表面、裏面をスクラブ洗浄する。半導体基板Ｗの表
面は、主にパーティクルの除去のため洗浄水として純水
に界面活性剤、キレート剤、又はｐＨ調整剤を加えたも
のが用いられ、ＰＶＡロールスポンジでスクラブ洗浄さ
れる。半導体基板Ｗの裏面には、ＤＨＦ等の強い薬液を
噴射し、拡散している銅をエッチングしたり、又は銅拡
散の問題がなければ、表面と同じ薬液を用いてＰＶＡロ
ールスポンジでスクラブ洗浄する。The first cleaning unit 209 scrubs the front and back surfaces of the semiconductor substrate W. The surface of the semiconductor substrate W is mainly made of pure water with a surfactant, a chelating agent, or a pH adjuster added as cleaning water for removing particles, and is scrubbed with a PVA roll sponge. A strong chemical such as DHF is sprayed on the back surface of the semiconductor substrate W to etch the diffused copper, or if there is no problem of copper diffusion, scrub cleaning with a PVA roll sponge using the same chemical as the front surface. .
【００５２】洗浄後、第２ロボット２０８で半導体基板
Ｗを取り上げ、反転機２０６に渡し、該反転機２０６で
半導体基板Ｗを反転させる。第２ロボット２０８で再度
半導体基板Ｗを取り上げ、例えば図２または図３に示す
構成の無電解めっき装置からなる第２めっき装置２２７
に搬入する。第２めっき装置２２７では、例えば前述の
ような組成の無電解めっき液を使用し、半導体基板Ｗの
表面をめっき液に浸漬させ、配線８の外部への露出表面
に合金膜からなる保護膜９を選択的に形成して配線８を
保護する（図１（ｃ）参照）。しかる後、第２ロボット
２０８で半導体基板Ｗを取り上げ、反転機２０６に渡
し、該反転機２０６で半導体基板Ｗを反転させ、第２洗
浄洗浄装置２０７に渡す。第２洗浄装置２０７では、半
導体基板Ｗの表面に超音波振動を加えたメガソニック水
を噴射して洗浄する。その時、純水、界面活性剤、キレ
ート剤、又はｐＨ調整剤を加えた洗浄液を用いてペンシ
ル型スポンジで表面を洗浄してもよい。そして、半導体
基板Ｗをスピンドライにより乾燥させる。After the cleaning, the second robot 208 picks up the semiconductor substrate W and transfers it to the reversing machine 206, which reverses the semiconductor substrate W. The second robot 208 picks up the semiconductor substrate W again and, for example, the second plating apparatus 227 including an electroless plating apparatus having the configuration shown in FIG. 2 or 3.
Bring to. In the second plating apparatus 227, for example, an electroless plating solution having the above-described composition is used, the surface of the semiconductor substrate W is immersed in the plating solution, and the protective film 9 made of an alloy film is formed on the exposed surface of the wiring 8 to the outside. Are selectively formed to protect the wiring 8 (see FIG. 1C). Thereafter, the second robot 208 picks up the semiconductor substrate W, transfers it to the reversing machine 206, inverts the semiconductor substrate W with the reversing machine 206, and transfers it to the second cleaning / cleaning apparatus 207. In the second cleaning device 207, the surface of the semiconductor substrate W is cleaned by spraying megasonic water with ultrasonic vibration. At that time, the surface may be washed with a pencil type sponge using a washing liquid containing pure water, a surfactant, a chelating agent, or a pH adjuster. Then, the semiconductor substrate W is dried by spin drying.
【００５３】その後、第２ロボット２０８で半導体基板
Ｗを取り上げ、そのまま反転機２０６に渡す。第１ロボ
ット２０３は反転機２０６上の半導体基板Ｗを取り上
げ、上記研磨テーブル２１０−１、２１１−１の近傍に
配置した膜厚測定機２１０−４、２１１−４で膜厚を測
定している場合は、そのままロードアンロード部２０１
のアンロードポートに載置したカセット２０１−１に収
納する。多層膜の膜厚を測定する場合は、乾燥状態での
測定を行う必要があるので、一度、乾燥状態膜厚測定機
２１３で膜厚を測定する。After that, the second robot 208 picks up the semiconductor substrate W and transfers it to the reversing machine 206 as it is. The first robot 203 picks up the semiconductor substrate W on the reversing machine 206 and measures the film thickness with the film thickness measuring machines 210-4 and 211-4 arranged near the polishing tables 210-1 and 211-1. In that case, load / unload unit 201
It is stored in the cassette 201-1 placed on the unload port. When measuring the film thickness of the multilayer film, it is necessary to measure the film thickness in a dry state. Therefore, the film thickness is once measured by the dry film thickness measuring device 213.
【００５４】図５は、本発明の半導体装置を製造する半
導体製造装置の他の例の平面配置図を示す。この半導体
製造装置では、図４に示す基板処理装置と同様、シード
層７が形成された半導体基板Ｗに銅膜６を形成し、研磨
し、更に配線８を保護膜９で保護した回路配線を形成す
る基板処理装置である。FIG. 5 is a plan layout view of another example of the semiconductor manufacturing apparatus for manufacturing the semiconductor device of the present invention. In this semiconductor manufacturing apparatus, similarly to the substrate processing apparatus shown in FIG. 4, a copper film 6 is formed on the semiconductor substrate W on which the seed layer 7 is formed, polished, and circuit wiring in which the wiring 8 is protected by the protective film 9 is formed. It is a substrate processing apparatus to form.
【００５５】この半導体製造装置は、第１ポリッシング
装置２１０と第２ポリッシング装置２１１に接近してプ
ッシャーインデクサー２２５を配置し、第２洗浄装置２
０７と第２めっき装置２２７の近傍にそれぞれ基板載置
台２２１,２２２を配置し、第２めっき装置２２７と第
１めっき装置２０２に接近してロボット２２３（以下、
「第２ロボット２２３」と記す）を配置し、第１洗浄装
置２０９と第２洗浄装置２０７の近傍にロボット２２４
（以下、「第３ロボット２２４」と記す）を配置し、更
にロードアンロード部２０１と第１ロボット２０３の近
傍に乾燥状態膜厚測定機２１３を配置している。In this semiconductor manufacturing apparatus, a pusher indexer 225 is arranged close to the first polishing device 210 and the second polishing device 211, and the second cleaning device 2 is provided.
07 and the second plating apparatus 227 are provided with substrate mounting tables 221 and 222, respectively, and the robot 223 (hereinafter, referred to as the robot 223 near the second plating apparatus 227 and the first plating apparatus 202).
“Second robot 223”) is arranged, and the robot 224 is provided near the first cleaning device 209 and the second cleaning device 207.
(Hereinafter, referred to as “third robot 224”), and a dry state film thickness measuring instrument 213 is further arranged in the vicinity of the load / unload unit 201 and the first robot 203.
【００５６】第１ロボット２０３でロードアンロード部
２０１のロードポートに載置されているカセット２０１
−１から、シード層６が形成されている半導体基板Ｗを
取り出して基板載置台２２１に載せる。次に第２ロボッ
ト２２３は、半導体基板Ｗを第１めっき装置２０２に搬
送し、銅層７（図１（ｂ）参照）を成膜する。第２ロボ
ット２２３は、銅層７の形成された半導体基板Ｗをめっ
き前後膜厚測定機２１２に搬送し、ここで銅層７の膜厚
を測定する。膜厚測定後、プッシャーインデクサー２２
５に移送する。The cassette 201 placed on the load port of the load / unload unit 201 by the first robot 203
From -1, the semiconductor substrate W on which the seed layer 6 is formed is taken out and placed on the substrate platform 221. Next, the second robot 223 carries the semiconductor substrate W to the first plating apparatus 202 and deposits the copper layer 7 (see FIG. 1B). The second robot 223 conveys the semiconductor substrate W on which the copper layer 7 is formed to the pre- and post-plating film thickness measuring instrument 212, and measures the film thickness of the copper layer 7 here. After film thickness measurement, pusher indexer 22
Transfer to 5.
【００５７】トップリング２１０−２又は２１１−２
は、プッシャーインデクサー２２５上の半導体基板Ｗを
吸着し、研磨テーブル２１０−１又は２１１−１に移送
し研磨する。研磨後、トップリング２１０−２又は２１
１−２は、半導体基板Ｗを膜厚測定機２１０−４又は２
１１−４に移送し、膜厚を測定し、プッシャーインデク
サー２２５に移送して載せる。Top ring 210-2 or 211-2
Absorbs the semiconductor substrate W on the pusher indexer 225 and transfers it to the polishing table 210-1 or 211-1 for polishing. After polishing, top ring 210-2 or 21
1-2, the semiconductor substrate W is a film thickness measuring machine 210-4 or 2
11-4, measure the film thickness, and transfer to the pusher indexer 225 for mounting.
【００５８】次に、第３ロボット２２４は、プッシャー
インデクサー２２５から半導体基板Ｗを取り上げ、第１
洗浄装置２０９に搬入する。第３ロボット２２４は、第
１洗浄ユニット２０９から洗浄された半導体基板Ｗを取
り上げ、第２めっき装置２２７に搬入し、例えば無電解
めっきを施して、配線８の表面に保護膜９を選択的に形
成して配線８を保護する（図１（ｃ）参照）。しかる
後、第３ロボット２２４は、半導体基板Ｗを第２洗浄装
置２０７に搬送し、洗浄・乾燥後の半導体基板Ｗを基板
載置台２２２上に載置する。次に、第１ロボット２０３
は半導体基板Ｗを取り上げ、乾燥状態膜厚測定機２１３
で膜厚を測定し、ロードアンロード部２０１のアンロー
ドポートに載置されているカセット２０１−１に収納す
る。Next, the third robot 224 picks up the semiconductor substrate W from the pusher indexer 225,
It is carried into the cleaning device 209. The third robot 224 picks up the cleaned semiconductor substrate W from the first cleaning unit 209, carries it in to the second plating apparatus 227, performs electroless plating, for example, and selectively forms the protective film 9 on the surface of the wiring 8. The wiring 8 is formed and protected (see FIG. 1C). Then, the third robot 224 conveys the semiconductor substrate W to the second cleaning device 207, and mounts the semiconductor substrate W after cleaning and drying on the substrate mounting table 222. Next, the first robot 203
Picks up the semiconductor substrate W, and measures the dry state film thickness 213
Then, the film thickness is measured and stored in the cassette 201-1 placed on the unload port of the load / unload unit 201.
【００５９】図６は、本発明の半導体装置を製造する半
導体製造装置の更に他の例を示す平面配置図である。こ
の半導体製造装置は、バリア層成膜ユニット１１１、シ
ード層成膜ユニット１１２、めっき膜成膜ユニット１１
３、アニールユニット１１４、第１洗浄ユニット装置１
１５、ベベル・裏面洗浄ユニット１１６、例えば図２又
は図３に示す無電解めっき装置を有する蓋めっきユニッ
ト１１７、第２洗浄ユニット１１８、第１アライナ兼膜
厚測定器１４１、第２アライナ兼膜厚測定器１４２、第
１基板反転機１４３、第２基板反転機１４４、基板仮置
き台１４５、第３膜厚測定器１４６、ロードアンロード
ユニット１２０、第１ポリッシング装置１２１、第２ポ
リッシング装置１２２、第１ロボット１３１、第２ロボ
ット１３２、第３ロボット１３３、第４ロボット１３４
を有している。なお、膜厚測定器１４１，１４２，１４
６はユニットになっており、他のユニット（めっき、洗
浄、アニール等のユニット）の間口寸法と同一サイズに
しているため、入れ替え自在である。FIG. 6 is a plan layout view showing still another example of the semiconductor manufacturing apparatus for manufacturing the semiconductor device of the present invention. This semiconductor manufacturing apparatus includes a barrier layer film forming unit 111, a seed layer film forming unit 112, and a plating film film forming unit 11
3, annealing unit 114, first cleaning unit device 1
15, a bevel / back surface cleaning unit 116, for example, a lid plating unit 117 having the electroless plating apparatus shown in FIG. 2 or 3, a second cleaning unit 118, a first aligner / film thickness measuring device 141, a second aligner / film thickness Measuring instrument 142, first substrate reversing machine 143, second substrate reversing machine 144, substrate temporary holder 145, third film thickness measuring instrument 146, load / unload unit 120, first polishing device 121, second polishing device 122, First robot 131, second robot 132, third robot 133, fourth robot 134
have. The film thickness measuring devices 141, 142, 14
6 is a unit, and can be replaced because it has the same size as the front dimension of other units (units for plating, cleaning, annealing, etc.).
【００６０】この例では、バリア層成膜装置１１１とし
て無電解Ｒｕめっき装置を、シード層成膜ユニット１１
２として無電解Ｃｕめっき装置を、めっき膜成膜ユニッ
ト１１３として電解めっき装置を用いることができる。In this example, an electroless Ru plating apparatus is used as the barrier layer film forming apparatus 111, and the seed layer film forming unit 11 is used.
An electroless Cu plating device can be used as 2, and an electrolytic plating device can be used as the plating film forming unit 113.
【００６１】次に、この半導体製造装置内での各工程に
ついて説明する。まず、第１ロボット１３１によりロー
ドアンロードユニット１２０に載置されたカセット１２
０ａから取り出された半導体基板は、第１アライナ兼膜
厚測定器１４１内に被めっき面を上にして配置される。
ここで、膜厚計測を行うポジションの基準点を定めるた
めに、膜厚計測用のノッチアライメントを行った後、銅
膜形成前の半導体基板の膜厚データを得る。Next, each process in this semiconductor manufacturing apparatus will be described. First, the cassette 12 placed on the load / unload unit 120 by the first robot 131
The semiconductor substrate taken out from 0a is placed in the first aligner / film thickness measuring device 141 with the surface to be plated facing up.
Here, in order to determine the reference point of the position for measuring the film thickness, after performing notch alignment for film thickness measurement, film thickness data of the semiconductor substrate before the copper film formation is obtained.
【００６２】次に、半導体基板は、第１ロボット１３１
により、バリア層成膜ユニット１１１へ搬送される。こ
のバリア層成膜ユニット１１１は、無電解Ｒｕめっきに
より半導体基板上にバリア層５（図１（ａ）参照）を形
成する装置で、半導体装置の層間絶縁膜（例えば、Ｓｉ
Ｏ２）へのＣｕ拡散防止膜としてＲｕを成膜する。洗
浄、乾燥工程を経て払い出された半導体基板は、第１ロ
ボット１３１により第１アライナ兼膜厚測定器１４１に
搬送され、半導体基板の膜厚、即ちバリア層の膜厚を測
定される。Next, the semiconductor substrate is the first robot 131.
Thus, it is conveyed to the barrier layer film forming unit 111. The barrier layer deposition unit 111 is a device that forms the barrier layer 5 (see FIG. 1A) on a semiconductor substrate by electroless Ru plating, and is an interlayer insulating film (for example, Si) of a semiconductor device.
Ru is formed as a Cu diffusion preventing film for O 2 ). The semiconductor substrate discharged through the cleaning and drying steps is conveyed to the first aligner / film thickness measuring device 141 by the first robot 131, and the film thickness of the semiconductor substrate, that is, the film thickness of the barrier layer is measured.
【００６３】膜厚測定された半導体基板は、第２ロボッ
ト１３２でシード層成膜ユニット１１２へ搬入され、前
記バリア層上に無電解Ｃｕめっきによりシード層６（図
１（ａ）参照）が成膜される。洗浄、乾燥工程を経て払
い出された半導体基板は、第２ロボット１３２によりめ
っき膜成膜ユニット１１３に搬送される前に、ノッチ位
置を定めるために第２アライナ兼膜厚測定器１４２に搬
送され、銅めっき用のノッチのアライメントを行う。こ
こで、必要に応じて銅膜形成前の半導体基板の膜厚を再
計測してもよい。The semiconductor substrate whose film thickness has been measured is carried into the seed layer film forming unit 112 by the second robot 132, and the seed layer 6 (see FIG. 1A) is formed on the barrier layer by electroless Cu plating. Be filmed. The semiconductor substrate delivered through the cleaning and drying steps is transferred to the second aligner / film thickness measuring device 142 for determining the notch position before being transferred to the plating film forming unit 113 by the second robot 132. Align the notch for copper plating. Here, the film thickness of the semiconductor substrate before forming the copper film may be remeasured, if necessary.
【００６４】ノッチアライメントが完了した半導体基板
は、第３ロボット１３３によりめっき膜成膜ユニット１
１３へ搬送され、銅めっきが施される。洗浄、乾燥工程
を経て払い出された半導体基板は、第３ロボット１３３
により半導体基板端部の不要な銅膜（シード層）を除去
するためにベベル・裏面洗浄ユニット１１６へ搬送され
る。ベベル・裏面洗浄ユニット１１６では、予め設定さ
れた時間でベベルのエッチングを行うとともに、半導体
基板裏面に付着した銅をフッ酸等の薬液により洗浄す
る。この時、ベベル・裏面洗浄ユニット１１６へ搬送す
る前に第２アライナ兼膜厚測定器１４２にて半導体基板
の膜厚測定を実施してめっきにより形成された銅膜厚の
値を得ておき、その結果により、ベベルのエッチング時
間を任意に変えてエッチングを行っても良い。なお、ベ
ベルエッチングによりエッチングされる領域は、基板の
周縁部であって回路が形成されない領域、または回路が
形成されていても最終的にチップとして利用されない領
域である。この領域にはベベル部分が含まれる。The semiconductor substrate on which the notch alignment has been completed is processed by the third robot 133 by the plating film forming unit 1.
It is conveyed to 13 and copper plating is performed. The semiconductor substrate discharged through the cleaning and drying process is the third robot 133.
Then, the wafer is transferred to the bevel / back surface cleaning unit 116 to remove an unnecessary copper film (seed layer) on the edge of the semiconductor substrate. In the bevel / back surface cleaning unit 116, the bevel is etched for a preset time, and the copper attached to the back surface of the semiconductor substrate is cleaned with a chemical solution such as hydrofluoric acid. At this time, before being conveyed to the bevel / back surface cleaning unit 116, the film thickness of the semiconductor substrate is measured by the second aligner / film thickness measuring device 142 to obtain the value of the copper film thickness formed by plating. Depending on the result, the bevel etching time may be arbitrarily changed to perform the etching. The region to be etched by bevel etching is a region where the circuit is not formed in the peripheral portion of the substrate or a region where the circuit is not finally used as a chip. This area includes the bevel portion.
【００６５】ベベル・裏面洗浄ユニット１１６で洗浄、
乾燥工程を経て払い出された半導体基板は、第３ロボッ
ト１３３で基板反転機１４３に搬送され、該基板反転機
１４３にて反転され、被めっき面を下方に向けた後、第
４ロボット１３４により配線部を安定化させるためにア
ニールユニット１１４へ投入される。アニール処理前及
び／又は処理後、半導体基板を第２アライナ兼膜厚測定
器１４２に搬入し、半導体基板に形成された、銅膜７
（図１（ｂ）参照）の膜厚を計測する。この後、半導体
基板は第４ロボット１３４により、第１ポリッシング装
置１２１に搬入され、半導体基板の銅層７、シード層６
（図１（ａ）参照）の研磨を行う。Cleaning with the bevel / back surface cleaning unit 116,
The semiconductor substrate discharged through the drying process is conveyed to the substrate reversing machine 143 by the third robot 133, is reversed by the substrate reversing machine 143, and the surface to be plated is turned downward, and then the fourth robot 134. It is put into the annealing unit 114 in order to stabilize the wiring portion. Before and / or after the annealing treatment, the semiconductor substrate is carried into the second aligner / film thickness measuring device 142, and the copper film 7 formed on the semiconductor substrate
The film thickness (see FIG. 1B) is measured. Then, the semiconductor substrate is carried into the first polishing apparatus 121 by the fourth robot 134, and the copper layer 7 and the seed layer 6 of the semiconductor substrate are loaded.
Polishing (see FIG. 1A) is performed.
【００６６】この際、砥粒等は所望のものが用いられる
が、ディッシングを防ぎ、表面の平面度を出すために、
固定砥粒を用いることもできる。第１ポリッシング終了
後、半導体基板は第４ロボット１３４により第１洗浄ユ
ニット１１５に搬送され、洗浄される。この洗浄は、半
導体基板直径とほぼ同じ長さを有するロールを半導体基
板の表面と裏面に配置し、半導体基板及びロールを回転
させつつ、純水又は脱イオン水を流しながら洗浄するス
クラブ洗浄である。At this time, desired abrasive grains are used, but in order to prevent dishing and to obtain flatness of the surface,
Fixed abrasive grains can also be used. After the completion of the first polishing, the semiconductor substrate is transferred to the first cleaning unit 115 by the fourth robot 134 and cleaned. This cleaning is a scrub cleaning in which rolls having a length substantially the same as the diameter of the semiconductor substrate are arranged on the front surface and the back surface of the semiconductor substrate, and the semiconductor substrate and the roll are rotated and cleaned while flowing pure water or deionized water. .
【００６７】第１の洗浄終了後、半導体基板は第４ロボ
ット１３４により第２ポリッシング装置１２２に搬入さ
れ、半導体基板上のバリア層５が研磨される。この際、
砥粒等は所望のものが用いられるが、ディッシングを防
ぎ、表面の平面度を出すために、固定砥粒を用いること
もできる。第２ポリッシング終了後、半導体基板は第４
ロボット１３４により、再度第１洗浄ユニット１１５に
搬送され、スクラブ洗浄される。洗浄終了後、半導体基
板は第４ロボット１３４により第２基板反転機１４４に
搬送され反転されて、被めっき面を上方に向けられ、更
に第３ロボットにより基板仮置き台１４５に置かれる。After the completion of the first cleaning, the semiconductor substrate is carried into the second polishing device 122 by the fourth robot 134, and the barrier layer 5 on the semiconductor substrate is polished. On this occasion,
Although desired abrasive grains or the like are used, fixed abrasive grains may be used to prevent dishing and to obtain flatness of the surface. After completion of the second polishing, the semiconductor substrate is
The robot 134 carries the scrub cleaning to the first cleaning unit 115 again. After the cleaning is completed, the semiconductor substrate is conveyed to the second substrate reversing device 144 by the fourth robot 134 and inverted, the surface to be plated is directed upward, and further placed on the temporary substrate rest 145 by the third robot.
【００６８】半導体基板は、第２ロボット１３２により
基板仮置き台１４５から蓋めっきユニット１１７に搬送
され、銅の大気による酸化防止を目的に、配線８の表面
に、例えばニッケル・ボロンめっき（蓋めっき）を行
う。この蓋めっきによって、配線８の表面に保護膜９
（図１（ｃ）参照）を形成して配線８を保護した半導体
基板は、第２ロボット１３２により蓋めっきユニット１
１７から第３膜厚測定器１４６に搬入され、銅膜厚が測
定される。その後、半導体基板は第１ロボット１３１に
より第２洗浄ユニット１１８に搬入され、純水又は脱イ
オン水により洗浄される。洗浄が終了した半導体基板は
ロードアンロードユニット１２０に載置されたカセット
１２０ａ内に戻される。The semiconductor substrate is transferred from the temporary substrate rest 145 to the lid plating unit 117 by the second robot 132, and for the purpose of preventing the oxidation of copper by the atmosphere, for example, nickel / boron plating (lid plating) is performed on the surface of the wiring 8. )I do. By this lid plating, the protective film 9 is formed on the surface of the wiring 8.
The semiconductor substrate on which the wiring 8 is protected by forming (see FIG. 1C) the lid plating unit 1 by the second robot 132.
It is carried in from 17 to the 3rd film thickness measuring device 146, and a copper film thickness is measured. Then, the semiconductor substrate is carried into the second cleaning unit 118 by the first robot 131 and cleaned with pure water or deionized water. The cleaned semiconductor substrate is returned to the cassette 120a mounted on the load / unload unit 120.
【００６９】（実施例）絶縁膜の内部に、φ０．５μｍ
×深さ０．５μｍ（アスペスト比：１.０）のホールを
所定のピッチで形成し、このホールの内部に銅を埋込ん
だ後、表面にＣＭＰ処理を施して平坦化した３ｃｍ×４
ｃｍ（６パターン形成領域分位）の試料（半導体ウェ
ハ）を用意した。そして、下記の表１に示す組成のめっ
き液を使用して、２００ｍｌ／チップの浴負荷で６０秒
の無電解めっきを行った。(Example) Inside the insulating film, φ0.5 μm
× Hole having a depth of 0.5 μm (aspest ratio: 1.0) was formed at a predetermined pitch, copper was embedded in the hole, and then the surface was subjected to CMP treatment to be flattened 3 cm × 4
A sample (semiconductor wafer) of cm (6 pattern formation area quantiles) was prepared. Then, using the plating solution having the composition shown in Table 1 below, electroless plating was performed for 60 seconds with a bath load of 200 ml / chip.
【表１】 [Table 1]
【００７０】無電解めっき終了後、試料を水洗し乾燥さ
せた。そして、ＳＥＭ観察したところ、パターン形成領
域に選択的にＣｏ−Ｗ−Ｂめっき膜の成長が観察され
た。このめっき膜の成長は、約１００ｎｍ／ｍｉｎで、
めっき膜の分析値は、Ｃｏ：約９８．４ａｔ％、Ｗ：約
１．０ａｔ％、Ｂ：約０．６ａｔ％であった。この時の
ＳＥＭ写真を図面化したものを図７（ａ）及び図７
（ｂ）に示す。同図に示すように、絶縁膜１０の内部に
形成したホール１２の内部に埋込んだ銅層１４の内部に
は、ボイドが生成されておらず、また絶縁膜１０の表面
にめっき膜（Ｃｏ−Ｗ−Ｂめっき膜）が析出することな
く、銅層１４の表面、すなわち配線の表面のみがＣｏ−
Ｗ−Ｂめっき膜による保護膜１６で覆われて、選択性が
良好であることが判る。After completion of electroless plating, the sample was washed with water and dried. Then, as a result of SEM observation, selective growth of the Co-WB plating film was observed in the pattern formation region. The growth of this plating film is about 100 nm / min.
The analysis values of the plated film were Co: about 98.4 at%, W: about 1.0 at%, and B: about 0.6 at%. Drawings of SEM photographs at this time are shown in FIGS.
It shows in (b). As shown in the figure, voids are not generated inside the copper layer 14 buried inside the holes 12 formed inside the insulating film 10, and a plating film (Co -WB plating film) is not deposited, and only the surface of the copper layer 14, that is, the surface of the wiring is Co-
It can be seen that the selectivity is good because the protective film 16 is covered with the WB plating film.
【００７１】（比較例）実施例と同様な試料を用意し、
この試料を、先ずＰｄＣ１２（０．００５ｇ／Ｌ）＋Ｈ
Ｃｌ（０．２ｍｌ／Ｌ）、２５℃の溶液に１分間浸漬さ
せてパラジウム触媒を付与した。次に、このパラジウム
触媒付与後の試料を、下記の表２に示す組成で、９０℃
のめっき液に浸漬させ、２００ｍｌ／チップの浴負荷で
無電解めっきを行った。(Comparative Example) A sample similar to the example was prepared,
This sample is first subjected to PdC1 2 (0.005 g / L) + H
It was immersed in a solution of Cl (0.2 ml / L) at 25 ° C. for 1 minute to give a palladium catalyst. Next, the sample after applying this palladium catalyst was made to have a composition shown in Table 2 below at 90 ° C.
Was immersed in the plating solution of and electroless plating was performed with a bath load of 200 ml / chip.
【表２】 [Table 2]
【００７２】無電解めっき終了後、試料を水洗し乾燥さ
せた。そして、ＳＥＭ観察したところ、パターン形成領
域に選択的にＣｏ−Ｗ−Ｐめっき膜の成長が観察され
た。このめっき膜の成長は、約７０ｎｍ／ｍｉｎで、め
っき膜の分析値は、Ｃｏ：約８９ａｔ％、Ｗ：約５ａｔ
％、Ｐ：約６ａｔ％であった。After completion of the electroless plating, the sample was washed with water and dried. Then, as a result of SEM observation, selective growth of the Co-WP plating film was observed in the pattern formation region. The growth of this plating film was about 70 nm / min, and the analysis values of the plating film were Co: about 89 at% and W: about 5 at.
%, P: about 6 at%.
【００７３】この時のＳＥＭ写真を図面化したものを図
８（ａ）及び図８（ｂ）に示す。同図に示すように、絶
縁膜１０の内部に形成したホール１２の内部に埋込んだ
銅層１４の内部には、ボイドＶが生成され、しかも、絶
縁膜１０の表面にめっき膜（Ｃｏ−Ｗ−Ｂ合金膜）が析
出して、銅層１４の表面、すなわち配線の表面が保護膜
１６で覆われているのみならず、ホール１２の周辺の不
要な部分にもＣｏ−Ｗ−Ｂ合金膜１６ａが析出して、選
択性が悪いことが判る。FIG. 8 (a) and FIG. 8 (b) show the SEM photographs of this case in the form of drawings. As shown in the figure, voids V are generated inside the copper layer 14 buried inside the holes 12 formed inside the insulating film 10, and a plating film (Co- (W-B alloy film) is deposited and not only the surface of the copper layer 14, that is, the surface of the wiring is covered with the protective film 16, but also the Co-W-B alloy is applied to unnecessary portions around the holes 12. It can be seen that the film 16a is deposited and the selectivity is poor.
【００７４】[0074]
【発明の効果】以上説明したように、本発明によれば、
還元剤として、例えば銅、銅合金、銀または銀合金に対
して酸化電流を流せて直接無電解めっきが可能で、ナト
リウムを含有しないアルキルアミンボランを用いること
で、半導体装置のアルカリ金属による汚染が防止し、し
かもパラジウム触媒の付与を不要となして、工程を短縮
させてスループットを向上させ、更に配線の内部にボイ
ドが生成されることを防止して信頼性を向上させ、かつ
パラジウム拡散による配線抵抗の上昇をなくすことがで
きる。また、アルキルアミンボランを還元剤とするめっ
き液を使用することで、配線形成領域のみの選択的めっ
きが可能となる。As described above, according to the present invention,
As a reducing agent, for example, copper, a copper alloy, silver or a silver alloy can be directly subjected to electroless plating by applying an oxidizing current, and by using sodium-free alkylamine borane, contamination of semiconductor devices with alkali metals can be prevented. In addition, the addition of a palladium catalyst is not required, the process is shortened to improve the throughput, and voids are not generated inside the wiring to improve the reliability, and the wiring is formed by palladium diffusion. The rise in resistance can be eliminated. Further, by using a plating solution containing alkylamine borane as a reducing agent, selective plating of only the wiring formation region becomes possible.
【図１】本発明の電子デバイス装置における銅配線形成
例を工程順に示す図である。FIG. 1 is a view showing an example of copper wiring formation in an electronic device device of the present invention in the order of steps.
【図２】無電解めっき装置の一例を示す概略構成図であ
る。FIG. 2 is a schematic configuration diagram showing an example of an electroless plating apparatus.
【図３】無電解めっき装置の他の例を示す概略構成図で
ある。FIG. 3 is a schematic configuration diagram showing another example of an electroless plating apparatus.
【図４】本発明の半導体装置を製造する半導体製造装置
の一例を示す平面配置図である。FIG. 4 is a plan layout view showing an example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device of the present invention.
【図５】本発明の半導体装置を製造する半導体製造装置
の他の例を示す平面配置図である。FIG. 5 is a plan layout view showing another example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device of the present invention.
【図６】本発明の半導体装置を製造する半導体製造装置
の更に他の例を示す平面配置図である。FIG. 6 is a plan layout view showing still another example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device of the present invention.
【図７】本発明の実施例におけるＳＥＭ写真を図面化し
た図である。FIG. 7 is a drawing in which an SEM photograph in an example of the present invention is shown.
【図８】比較例におけるＳＥＭ写真を図面化した図であ
る。FIG. 8 is a drawing of an SEM photograph in a comparative example.
１ 基板 ２，１０ 絶縁膜 ３ コンタクトホール ４ 溝 ７，１４ 銅層 ８ 配線 ９，１６ 保護膜 1 substrate 2,10 insulating film 3 contact holes 4 grooves 7,14 Copper layer 8 wiring 9,16 protective film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 憲二 神奈川県藤沢市善行坂１−１−６ 荏原ユ ージライト株式会社内 (72)発明者 松本 守治 神奈川県藤沢市善行坂１−１−６ 荏原ユ ージライト株式会社内 Ｆターム(参考） 4K022 AA02 AA05 AA37 AA41 BA04 BA06 BA12 BA16 BA22 BA23 BA24 BA32 BA35 DA01 DB01 DB03 DB04 DB08 4M104 BB04 BB16 BB18 BB32 DD53 FF18 FF22 5F033 HH11 HH12 HH14 HH15 HH32 JJ11 JJ12 JJ14 JJ32 MM02 MM05 MM12 MM13 NN06 NN07 PP27 PP28 QQ09 QQ48 RR04 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Kenji Nakamura Yuzawa Ebara 1-1-6 Zenyokozaka, Fujisawa City, Kanagawa Prefecture -Inside Zelite Co., Ltd. (72) Inventor Moriji Matsumoto Yuzawa Ebara 1-1-6 Zenyokozaka, Fujisawa City, Kanagawa Prefecture -Inside Zelite Co., Ltd. F-term (reference) 4K022 AA02 AA05 AA37 AA41 BA04 BA06 BA12 BA16 BA22 BA23 BA24 BA32 BA35 DA01 DB01 DB03 DB04 DB08 4M104 BB04 BB16 BB18 BB32 DD53 FF18 FF22 5F033 HH11 HH12 HH14 HH15 HH32 JJ11 JJ12 JJ14 JJ32 MM02 MM05 MM12 MM13 NN06 NN07 PP27 PP28 QQ09 QQ48 RR04
Claims (16)
露出配線の表面に無電解めっき膜を選択的に形成する無
電解めっき液であって、 コバルトイオン、錯化剤、及びアルカリ金属を含まない
還元剤を含有することを特徴とする無電解めっき液。1. An electroless plating solution for selectively forming an electroless plating film on the surface of an exposed wiring of a semiconductor device having a buried wiring structure, the reduction not containing cobalt ions, a complexing agent, and an alkali metal. An electroless plating solution containing an agent.
露出配線の表面に無電解めっき膜を選択的に形成する無
電解めっき液であって、 コバルトイオン、錯化剤、高融点金属を含む化合物、及
びアルカリ金属を含まない還元剤を含有することを特徴
とする無電解めっき液。2. An electroless plating solution for selectively forming an electroless plating film on a surface of an exposed wiring of a semiconductor device having a buried wiring structure, the compound including cobalt ions, a complexing agent, and a refractory metal, And an electroless plating solution containing a reducing agent containing no alkali metal.
たはモリブデンであることを特徴とする請求項２記載の
無電解めっき液。3. The electroless plating solution according to claim 2, wherein the refractory metal is tungsten and / or molybdenum.
あることを特徴とする請求項１乃至３のいずれかに記載
の無電解めっき液。4. The electroless plating solution according to claim 1, wherein the reducing agent is alkylamine borane.
化合物の１種または２種以上、または界面活性剤の少な
くとも一方を更に含有することを特徴とする請求項１乃
至４のいずれかに記載の無電解めっき液。5. The stabilizer according to claim 1, further comprising at least one of a heavy metal compound or a sulfur compound as a stabilizer, or a surfactant. Electrolytic plating solution.
いてｐＨを５〜１４に調整したことを特徴とする請求項
１乃至５のいずれかに記載の無電解めっき液。6. The electroless plating solution according to claim 1, wherein the pH is adjusted to 5 to 14 by using a pH adjuster containing no alkali metal.
とした埋め込み配線構造を有し、コバルトイオン、錯化
剤、及びアルカリ金属を含まない還元剤を含有する無電
解めっき液を用いた無電解めっきを施して、露出配線の
表面を保護膜で選択的に覆ったことを特徴とする半導体
装置。7. An electroless plating solution having a buried wiring structure using copper, a copper alloy, silver or a silver alloy as a wiring material and containing a cobalt ion, a complexing agent, and a reducing agent containing no alkali metal. The semiconductor device is characterized in that the surface of the exposed wiring is selectively covered with a protective film by electroless plating.
とした埋め込み配線構造を有し、コバルトイオン、錯化
剤、高融点金属を含む化合物、及びアルカリ金属を含ま
ない還元剤を含有する無電解めっき液を用いた無電解め
っきを施して、露出配線の表面を保護膜で選択的に覆っ
たことを特徴とする半導体装置。8. An embedded wiring structure using copper, a copper alloy, silver or a silver alloy as a wiring material, and containing cobalt ions, a complexing agent, a compound containing a refractory metal, and a reducing agent containing no alkali metal. The semiconductor device is characterized in that the surface of the exposed wiring is selectively covered with a protective film by performing electroless plating using an electroless plating solution.
たはモリブデンであることを特徴とする請求項８記載の
半導体装置。9. The semiconductor device according to claim 8, wherein the refractory metal is tungsten and / or molybdenum.
であることを特徴とする請求項７乃至９のいずれかに記
載の半導体装置。10. The semiconductor device according to claim 7, wherein the reducing agent is alkylamine borane.
黄化合物の１種または２種以上、または界面活性剤の少
なくとも一方を更に含有することを特徴とする請求項７
乃至１０のいずれかに記載の半導体装置。11. The stabilizer according to claim 7, further comprising at least one of a heavy metal compound or a sulfur compound as a stabilizer, or a surfactant.
11. The semiconductor device according to any one of 1 to 10.
用いてｐＨを５〜１４に調整したことを特徴とする請求
項７乃至１１のいずれかに記載の半導体装置。12. The semiconductor device according to claim 7, wherein the pH is adjusted to 5 to 14 by using a pH adjusting agent containing no alkali metal.
の露出配線の表面が、コバルトを含有する金属膜からな
る保護膜で選択的に覆われていることを特徴とする半導
体装置。13. A semiconductor device, wherein a surface of an exposed wiring of a semiconductor device having a buried wiring structure is selectively covered with a protective film made of a metal film containing cobalt.
の露出配線の表面が、コバルトと、高融点金属を含む金
属の合金からなる保護膜で選択的に覆われていることを
特徴とする半導体装置。14. A semiconductor device, wherein a surface of an exposed wiring of a semiconductor device having a buried wiring structure is selectively covered with a protective film made of an alloy of cobalt and a metal containing a refractory metal.
／又はモリブデンであることを特徴とする請求項１４記
載の半導体装置。15. The semiconductor device according to claim 14, wherein the refractory metal is tungsten and / or molybdenum.
０ｎｍの範囲内にあることを特徴とする請求項１３乃至
１５のいずれかに記載の半導体装置。16. The protective film has a thickness of 0.1 to 50.
16. The semiconductor device according to claim 13, wherein the semiconductor device is in the range of 0 nm.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001179341A JP2003049280A (en) | 2001-06-01 | 2001-06-13 | Electroless plating solution and semiconductor device |
| PCT/JP2002/005250 WO2002099164A2 (en) | 2001-06-01 | 2002-05-30 | Electroless-plating solution and semiconductor device |
| CNB028111192A CN1285764C (en) | 2001-06-01 | 2002-05-30 | Electroless-plating solution and semiconductor device |
| TW091111514A TW543091B (en) | 2001-06-01 | 2002-05-30 | Electroless-plating solution and semiconductor device |
| KR1020037015760A KR100891344B1 (en) | 2001-06-01 | 2002-05-30 | Electroless-plating solution and semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001167355 | 2001-06-01 | ||
| JP2001-167355 | 2001-06-01 | ||
| JP2001179341A JP2003049280A (en) | 2001-06-01 | 2001-06-13 | Electroless plating solution and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003049280A true JP2003049280A (en) | 2003-02-21 |
| JP2003049280A5 JP2003049280A5 (en) | 2005-02-17 |
Family
ID=26616238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001179341A Pending JP2003049280A (en) | 2001-06-01 | 2001-06-13 | Electroless plating solution and semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP2003049280A (en) |
| KR (1) | KR100891344B1 (en) |
| CN (1) | CN1285764C (en) |
| TW (1) | TW543091B (en) |
| WO (1) | WO2002099164A2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004260106A (en) * | 2003-02-27 | 2004-09-16 | Ebara Corp | Method and apparatus for treating substrate |
| JP2004304021A (en) * | 2003-03-31 | 2004-10-28 | Ebara Corp | Manufacturing method and manufacturing device of semiconductor device |
| JP2007246981A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246979A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246978A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246980A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| KR100774651B1 (en) | 2006-07-21 | 2007-11-08 | 동부일렉트로닉스 주식회사 | Manufacturing method of copper metalization for semiconductor device and structure thereof |
| WO2008047578A1 (en) * | 2006-09-29 | 2008-04-24 | Wako Pure Chemical Industries, Ltd. | Composition for electroless plating and method for forming metal protection film by using the composition |
| JP2010513720A (en) * | 2006-12-22 | 2010-04-30 | ラム リサーチ コーポレーション | Electroless deposition of cobalt alloys |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005015885A (en) * | 2003-06-27 | 2005-01-20 | Ebara Corp | Substrate processing method and apparatus |
| KR100859259B1 (en) | 2005-12-29 | 2008-09-18 | 주식회사 엘지화학 | Cobalt-base alloy electroless-plating solution and electroless-plating by using the same |
| US9496145B2 (en) | 2014-03-19 | 2016-11-15 | Applied Materials, Inc. | Electrochemical plating methods |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55102297A (en) * | 1979-01-22 | 1980-08-05 | Richardson Chemical Co | Method of controlling to electrolessly plate surface of support and product fabricated thereby |
| JPH04503378A (en) * | 1989-02-17 | 1992-06-18 | ポリメタルズ テクノロジィ リミテッド | Plating composition and plating method |
| JPH051384A (en) * | 1991-06-21 | 1993-01-08 | Nec Corp | Electroless plating bath |
| JPH07220921A (en) * | 1994-01-27 | 1995-08-18 | Tetsuya Aisaka | Soft magnet thin film, its manufacture and electroless plating bath |
| WO2001008213A1 (en) * | 1999-07-27 | 2001-02-01 | International Business Machines Corporation | REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3917464A (en) * | 1973-07-20 | 1975-11-04 | Us Army | Electroless deposition of cobalt boron |
| US5203911A (en) * | 1991-06-24 | 1993-04-20 | Shipley Company Inc. | Controlled electroless plating |
| US5240497A (en) * | 1991-10-08 | 1993-08-31 | Cornell Research Foundation, Inc. | Alkaline free electroless deposition |
| US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
| KR19990015599A (en) * | 1997-08-07 | 1999-03-05 | 윤종용 | Method of forming dual damascene metal wiring layer of semiconductor device using electroless plating |
-
2001
- 2001-06-13 JP JP2001179341A patent/JP2003049280A/en active Pending
-
2002
- 2002-05-30 KR KR1020037015760A patent/KR100891344B1/en active IP Right Grant
- 2002-05-30 TW TW091111514A patent/TW543091B/en not_active IP Right Cessation
- 2002-05-30 WO PCT/JP2002/005250 patent/WO2002099164A2/en active Application Filing
- 2002-05-30 CN CNB028111192A patent/CN1285764C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55102297A (en) * | 1979-01-22 | 1980-08-05 | Richardson Chemical Co | Method of controlling to electrolessly plate surface of support and product fabricated thereby |
| JPH04503378A (en) * | 1989-02-17 | 1992-06-18 | ポリメタルズ テクノロジィ リミテッド | Plating composition and plating method |
| JPH051384A (en) * | 1991-06-21 | 1993-01-08 | Nec Corp | Electroless plating bath |
| JPH07220921A (en) * | 1994-01-27 | 1995-08-18 | Tetsuya Aisaka | Soft magnet thin film, its manufacture and electroless plating bath |
| WO2001008213A1 (en) * | 1999-07-27 | 2001-02-01 | International Business Machines Corporation | REDUCED ELECTROMIGRATION AND STRESS INDUCED MIGRATION OF Cu WIRES BY SURFACE COATING |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004260106A (en) * | 2003-02-27 | 2004-09-16 | Ebara Corp | Method and apparatus for treating substrate |
| JP4663965B2 (en) * | 2003-02-27 | 2011-04-06 | 株式会社荏原製作所 | Substrate processing method and substrate processing apparatus |
| JP2004304021A (en) * | 2003-03-31 | 2004-10-28 | Ebara Corp | Manufacturing method and manufacturing device of semiconductor device |
| JP2007246981A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246979A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246978A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| JP2007246980A (en) * | 2006-03-15 | 2007-09-27 | Jsr Corp | Electroless plating liquid |
| KR100774651B1 (en) | 2006-07-21 | 2007-11-08 | 동부일렉트로닉스 주식회사 | Manufacturing method of copper metalization for semiconductor device and structure thereof |
| WO2008047578A1 (en) * | 2006-09-29 | 2008-04-24 | Wako Pure Chemical Industries, Ltd. | Composition for electroless plating and method for forming metal protection film by using the composition |
| JP2010513720A (en) * | 2006-12-22 | 2010-04-30 | ラム リサーチ コーポレーション | Electroless deposition of cobalt alloys |
| KR101518519B1 (en) | 2006-12-22 | 2015-05-07 | 램 리써치 코포레이션 | Electroless deposition of cobalt alloys |
Also Published As
| Publication number | Publication date |
|---|---|
| TW543091B (en) | 2003-07-21 |
| KR20040008205A (en) | 2004-01-28 |
| CN1285764C (en) | 2006-11-22 |
| WO2002099164A2 (en) | 2002-12-12 |
| WO2002099164A3 (en) | 2004-05-21 |
| CN1527888A (en) | 2004-09-08 |
| KR100891344B1 (en) | 2009-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6717189B2 (en) | Electroless plating liquid and semiconductor device | |
| US7172979B2 (en) | Substrate processing apparatus and method | |
| US7279408B2 (en) | Semiconductor device, method for manufacturing the same, and plating solution | |
| US6936302B2 (en) | Electroless Ni-B plating liquid, electronic device and method for manufacturing the same | |
| JP2003115474A (en) | Substrate processor and processing method | |
| US20070224811A1 (en) | Substrate processing method and substrate processing apparatus | |
| JP4127926B2 (en) | Polishing method | |
| JP2003049280A (en) | Electroless plating solution and semiconductor device | |
| US20040235237A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP3963661B2 (en) | Electroless plating method and apparatus | |
| US7344986B2 (en) | Plating solution, semiconductor device and method for manufacturing the same | |
| JP3821709B2 (en) | Pretreatment method of electroless plating | |
| EP1780306A2 (en) | Apparatus and method for electroless plating | |
| JP4139124B2 (en) | Plating apparatus and method | |
| JP2002285343A (en) | Electroless plating apparatus | |
| JP3871613B2 (en) | Electroless plating apparatus and method | |
| US20040186008A1 (en) | Catalyst-imparting treatment solution and electroless plating method | |
| WO2006095881A1 (en) | Substrate processing method and substrate processing apparatus | |
| JP2005002443A (en) | Plating method and apparatus | |
| JP2003034876A (en) | Catalytic treatment liquid and method for electroless plating | |
| JP4076335B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20070214620A1 (en) | Substrate processing apparatus and substrate processing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040130 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040311 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070116 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070522 |