JP2003046260A - Multilayer circuit board and its manufacturing method - Google Patents

Multilayer circuit board and its manufacturing method

Info

Publication number
JP2003046260A
JP2003046260A JP2001228942A JP2001228942A JP2003046260A JP 2003046260 A JP2003046260 A JP 2003046260A JP 2001228942 A JP2001228942 A JP 2001228942A JP 2001228942 A JP2001228942 A JP 2001228942A JP 2003046260 A JP2003046260 A JP 2003046260A
Authority
JP
Japan
Prior art keywords
layer
circuit board
multilayer circuit
polyimide film
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001228942A
Other languages
Japanese (ja)
Other versions
JP4684483B2 (en
Inventor
Daisuke Mizutani
大輔 水谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2001228942A priority Critical patent/JP4684483B2/en
Publication of JP2003046260A publication Critical patent/JP2003046260A/en
Application granted granted Critical
Publication of JP4684483B2 publication Critical patent/JP4684483B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To appropriately inhibit high-frequency noise without mounting a capacitor to a multilayer circuit board, by easily increasing capacitance in the capacitor using the interlayer insulating layer of the multilayer circuit board as a dielectric layer, and by increasing and reducing the density and thickness of a circuit, respectively. SOLUTION: In the multilayer circuit board, a polyimide film 14 is sandwiched by ground and power supply layers 13 and 15, and a lamination structure comprising a glass epoxy insulating layer 11 for covering them is included.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、高周波ノイズを発
生し難く、又、回路を高密度化及び微細化するのに好適
な多層回路基板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board which is less likely to generate high frequency noise and is suitable for increasing the density and size of a circuit, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】一般に、電子機器に使用される多層回路
基板に於いては、回路のスイッチング等に依って電源に
高周波ノイズを発生するので、この高周波ノイズを除去
するには、回路にコンデンサを付加し、キャパシタンス
を増加させることで、特性インピーダンスを低下させる
ことが行われている。
2. Description of the Related Art Generally, in a multilayer circuit board used in electronic equipment, high frequency noise is generated in a power supply due to switching of the circuit, etc. Therefore, in order to remove this high frequency noise, a capacitor should be provided in the circuit. The characteristic impedance is reduced by adding the capacitance and increasing the capacitance.

【0003】然しながら、そのコンデンサの必要搭載数
は、回路の高密度化及び微細化が進展するにつれ、多く
しなければならなず、従って、回路の高密度化及び微細
化を妨げることになる。
However, the required number of capacitors to be mounted must be increased as the circuit becomes higher in density and finer, and therefore, the density of the circuit and finer the circuit are impeded.

【0004】ところで、キャパシタンスを大きくする為
には、キャパシタ誘電体層に相当する絶縁層の厚さを小
さくするか、面積を大きくするか、或いは、絶縁層材料
の誘電率を高めるかの何れかの手段を採ることが必要と
なる。
In order to increase the capacitance, the thickness of the insulating layer corresponding to the capacitor dielectric layer is reduced, the area is increased, or the dielectric constant of the insulating layer material is increased. It is necessary to take the means of.

【0005】然しながら、面積を増加させる手段を採っ
た場合、回路基板の外形を同一にするのであれば、キャ
パシタンスを得る為に使われる層の数を増加させなけれ
ばならず、それは直ちにコストの増加に結び付くことに
なる。
However, if the means for increasing the area is adopted and the outer shapes of the circuit boards are the same, the number of layers used for obtaining the capacitance must be increased, which immediately increases the cost. Will be tied to.

【0006】従って、他の手段、即ち、層間絶縁層の層
厚を小さくするか、或いは、絶縁層材料の誘電率を向上
させるかの手段を採ることになる。
Therefore, other means, that is, reducing the layer thickness of the interlayer insulating layer or improving the dielectric constant of the insulating layer material is adopted.

【0007】従来、多層回路基板中の絶縁層をキャパシ
タ誘電体層としてキャパシタンスを得る構成に於いて、
キャパシタンスを大きくする為の手段として、電源層と
グランド層との層間絶縁層に於ける厚さを小さくする技
術が提案されている(特許第2738590号を参
照)。
Conventionally, in a structure for obtaining capacitance by using an insulating layer in a multilayer circuit board as a capacitor dielectric layer,
As a means for increasing the capacitance, a technique of reducing the thickness of the interlayer insulating layer between the power supply layer and the ground layer has been proposed (see Japanese Patent No. 2738590).

【0008】図5は従来の技術を説明する為の公知の多
層回路基板を表す要部切断側面図であり、図に於いて、
1はガラスエポキシ複合材からなる絶縁層、2は信号
層、3はグランド層、4は電源層をそれぞれ示してい
る。
FIG. 5 is a side sectional view showing a known multi-layer circuit board for explaining a conventional technique. In the figure,
Reference numeral 1 is an insulating layer made of a glass epoxy composite material, 2 is a signal layer, 3 is a ground layer, and 4 is a power supply layer.

【0009】前記公知の発明に於いては、グランド層3
及び電源層4に挟まれたキャパシタ誘電体層にガラスエ
ポキシ複合材を用いていて、この材料で50〔μm〕未
満の絶縁層を構成した場合、絶縁の信頼性や層厚の均一
性を実現することが困難となり、また、工業的に多量生
産した場合、絶縁層の欠陥に起因する不良が増加するの
で、高い製造歩留りで安定した製造が困難である旨の問
題がある。
In the above-mentioned known invention, the ground layer 3
Also, when a glass epoxy composite material is used for the capacitor dielectric layer sandwiched between the power supply layer 4 and an insulating layer of less than 50 [μm] is formed of this material, reliability of insulation and uniformity of layer thickness are realized. In addition, when industrially mass-produced, defects due to defects in the insulating layer increase, and there is a problem that stable production is difficult with a high production yield.

【0010】更にまた、キャパシタンスを増加させる
為、材料中に無機強誘電体材料を混合して誘電率を高め
ようとしているが、そのようにした場合、材料の機械的
強度が低下し、製品の信頼性保持、及び、安定した工業
的製造が困難である旨の大きな問題がある。
Furthermore, in order to increase the capacitance, an attempt is made to increase the dielectric constant by mixing an inorganic ferroelectric material into the material. However, in such a case, the mechanical strength of the material is lowered and the product There is a big problem that it is difficult to maintain reliability and stable industrial production.

【0011】[0011]

【発明が解決しようとする課題】本発明では、多層回路
基板にコンデンサを搭載することなく、高周波ノイズを
良好に抑止できるようにする為、多層回路基板の層間絶
縁層を誘電体層とするキャパシタに於けるキャパシタン
スを容易に増大させることができるようにし、回路の高
密度化及び微細化を進めることを可能にする。
SUMMARY OF THE INVENTION In the present invention, a capacitor having an interlayer insulating layer of a multilayer circuit board as a dielectric layer in order to suppress high frequency noise well without mounting the capacitor on the multilayer circuit board. It is possible to easily increase the capacitance in the circuit, and to increase the density and miniaturization of the circuit.

【0012】[0012]

【課題を解決するための手段】本発明に於いては、前記
公知発明で採用されているガラスエポキシ複合材層の層
厚が100〔μm〕〜50〔μm〕であるのに対し、5
0〔μm〕未満の厚さで安定した絶縁特性をもつ材料の
選定及び評価を繰り返し実施した結果、ポリイミド・フ
ィルムが最良であることを見出した。
In the present invention, the glass epoxy composite material layer employed in the above-mentioned known invention has a layer thickness of 100 [μm] to 50 [μm], whereas
As a result of repeatedly selecting and evaluating a material having a stable insulating property with a thickness of less than 0 [μm], it was found that the polyimide film is the best.

【0013】図1は本発明の原理を説明するための多層
回路基板を表す要部切断側面図であり、図に於いて、1
1はガラスエポキシ複合材からなる絶縁層、12は信号
層、13はグランド層、14はポリイミドからなる絶縁
層、即ち、ポリイミド・フィルム、15は電源層をそれ
ぞれ示している。
FIG. 1 is a cutaway side view of an essential part showing a multilayer circuit board for explaining the principle of the present invention. In FIG.
Reference numeral 1 is an insulating layer made of a glass epoxy composite material, 12 is a signal layer, 13 is a ground layer, 14 is an insulating layer made of polyimide, that is, a polyimide film, and 15 is a power supply layer.

【0014】本発明では、前記のように、グランド層1
3及び電源層15に挟まれた絶縁層をポリイミド・フィ
ルム14で構成することに依り、その厚さを小さくして
キャパシタンスを大きくすると共に回路インダクタンス
を低減している。
In the present invention, as described above, the ground layer 1
3 and the insulating layer sandwiched between the power supply layer 15 and the polyimide film 14 reduce the thickness to increase the capacitance and the circuit inductance.

【0015】ところで、図示の多層回路基板に於いて、
キャパシタの誘電体層として作用するポリイミド・フィ
ルム14を用いるについては、解決しなければならない
問題が存在する。
By the way, in the illustrated multilayer circuit board,
With the polyimide film 14 acting as the dielectric layer of the capacitor, there are problems that must be resolved.

【0016】即ち、図示の多層回路基板は、ごく一部を
表したものであるため、信号線に比較して大面積である
グランド層13及び電源層15はポリイミド・フィルム
14の全面に接触しているように見えるが、実際には、
信号線と同様にパターニングされて線状をなしているこ
とから、その線状のグランド層13並びに電源層15の
側方では、ポリイミド・フィルム14がガラスエポキシ
複合材からなる絶縁層11と直接密着しなければならな
い。
That is, since the multilayer circuit board shown in the drawing shows only a part, the ground layer 13 and the power supply layer 15, which have a larger area than the signal line, contact the entire surface of the polyimide film 14. It looks like
Since it is patterned similarly to the signal line and has a linear shape, the polyimide film 14 is directly adhered to the insulating layer 11 made of the glass epoxy composite material on the side of the linear ground layer 13 and the power supply layer 15. Must.

【0017】然しながら、ポリイミド・フィルム14
は、他の材料に対して密着力が弱く、勿論、ガラスエポ
キシ複合材からなる絶縁層11についても同様なのであ
るが、ガラスエポキシ複合材からなる絶縁層11を用い
ることは、従来の多層回路基板との互換性、材料コス
ト、製造コストなどの面で大変有利であって、現状では
不可欠である。
However, the polyimide film 14
Has weak adhesion to other materials, and of course, the same applies to the insulating layer 11 made of a glass epoxy composite material. It is very advantageous in terms of compatibility with, material cost, manufacturing cost, etc., and is indispensable at present.

【0018】本発明では、ポリイミド・フィルムとし
て、両表面に熱可塑接着性を有するものを用い、しか
も、それ等表面に凹凸を形成し、粗面にすることでガラ
スエポキシ複合材からなる絶縁層との密着性を向上させ
ることが基本になっている。
In the present invention, as the polyimide film, one having thermoplastic adhesiveness on both surfaces is used, and the insulating layer made of glass epoxy composite material is formed by forming irregularities on those surfaces to make them rough. The basic idea is to improve the adhesion with.

【0019】前記手段を採ることに依り、キャパシタの
誘電体層として作用する絶縁層にポリイミド・フィルム
を用いることが可能になり、従って、その厚さは従来の
ものに比較して薄くすることができ、大きなキャパシタ
ンスの実現、回路インダクタンスの低減、絶縁信頼性の
向上が可能となり、そして、従来、高周波ノイズを除去
する為に搭載していたコンデンサは不要となるので、回
路の高密度化及び微細化に大きく寄与することができ
る。
By adopting the above means, it becomes possible to use a polyimide film for the insulating layer which acts as the dielectric layer of the capacitor, and therefore its thickness can be made thinner than the conventional one. It is possible to realize a large capacitance, reduce circuit inductance, improve insulation reliability, and eliminate the need for a capacitor that was conventionally mounted to remove high frequency noise. Can greatly contribute to realization.

【0020】[0020]

【発明の実施の形態】図2は本発明に於ける基本的な実
施の形態を説明する為の工程要所に於ける多層回路基板
を表す要部切断側面図であり、以下、図を参照しつつ説
明する。尚、本発明では、ポリイミド・フィルムとガラ
スエポキシ複合材層のエポキシ樹脂との密着性を重視し
ているので、その部分を主として示してある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a sectional side view showing the essential parts of a multi-layer circuit board in the process steps for explaining the basic embodiment of the present invention. I will explain. Incidentally, in the present invention, since the adhesion between the polyimide film and the epoxy resin of the glass epoxy composite material layer is emphasized, that portion is mainly shown.

【0021】図2(A)参照 (1)厚さ25〔μm〕の熱可塑性ポリイミド・フィル
ム22を少なくとも一面を粗面にした厚さ18〔μm〕
の電解銅箔21及び23で挟むように積層し、温度を3
00〔℃〕にして5〔MPa〕の圧力を加えて熱圧着し
てポリイミド・フィルム両面銅張板材料を作製する。
See FIG. 2A. (1) A thermoplastic polyimide film 22 having a thickness of 25 μm, at least one surface of which is roughened, has a thickness of 18 μm.
The electrolytic copper foils 21 and 23 are laminated so that the temperature is 3
The temperature is set to 00 [° C.] and a pressure of 5 [MPa] is applied to perform thermocompression bonding to prepare a polyimide film double-sided copper clad board material.

【0022】図2(B)参照 (2)リソグラフィ技術を適用することに依り、銅箔2
1及び23のパターニングを行ってグランド層及び電源
層を形成する。
See FIG. 2B. (2) By applying the lithography technique, the copper foil 2
Patterning 1 and 23 is performed to form a ground layer and a power supply layer.

【0023】図では銅箔21及び23がパターニングさ
れてなるグランド層及び電源層が存在しない部分の切断
面が表されているので、表面に銅箔21及び23の凹凸
が転写されて粗面になっている熱可塑性ポリイミド・フ
ィルム22のみが表されている。
In the drawing, the cut surface of the portion where the ground layer and the power supply layer formed by patterning the copper foils 21 and 23 does not exist is shown. Therefore, the unevenness of the copper foils 21 and 23 is transferred to the surface and the rough surface is formed. Only the thermoplastic polyimide film 22 is shown.

【0024】図2(C)参照 (3)グランド層並びに電源層をもつポリイミド・フィ
ルム22をエポキシ樹脂層24で挟むように積層し、ま
た、信号層などその他必要な層を積層して一括積層プレ
ス工程で加圧して多層回路基板を形成する。
Referring to FIG. 2C, (3) a polyimide film 22 having a ground layer and a power supply layer is laminated so as to be sandwiched between epoxy resin layers 24, and other necessary layers such as a signal layer are laminated together to form a laminated layer. A multilayer circuit board is formed by applying pressure in a pressing process.

【0025】前記説明した工程と同じ工程に依って、同
じ多層回路基板を10枚作製し、これとは別に厚さ50
〔μm〕のガラスエポキシ複合材両面銅張板を用い、前
記説明した工程と同様な工程に依って多層回路基板を比
較例として10枚作製し、 120〔℃〕 85〔%〕RH 20〔V〕 で100〔時間〕の絶縁信頼性評価を行った結果、電源
層−グランド層の間にガラスエポキシ複合材層を用いた
比較例では、基板の絶縁抵抗が10〔MΩ〕以下となっ
て不良品と判定されたものが6点存在したのに対し、本
発明の多層回路基板では、全数が試験前と変化がない絶
縁抵抗を維持していた。
According to the same process as described above, 10 identical multilayer circuit boards are manufactured, and a thickness of 50 is separately prepared.
Using a glass-epoxy composite material double-sided copper clad board of [μm], 10 multi-layer circuit boards were prepared as comparative examples by the same steps as those described above, and 120 [° C.] 85 [%] RH 20 [V ] As a result of performing the insulation reliability evaluation for 100 hours, in the comparative example using the glass epoxy composite material layer between the power supply layer and the ground layer, the insulation resistance of the substrate is 10 [MΩ] or less and While there were 6 points judged to be non-defective, all of the multilayer circuit boards of the present invention maintained the insulation resistance unchanged from that before the test.

【0026】図3及び図4は本発明に於ける具体的な実
施の形態を説明する為の工程要所に於ける多層回路基板
を表す要部切断側面図であり、以下、図を参照しつつ説
明する。
FIGS. 3 and 4 are side sectional views showing essential parts of a multilayer circuit board in process steps for explaining a specific embodiment of the present invention. While explaining.

【0027】図3参照 (1)表裏両面に貼着した銅箔をリソグラフィ技術を適
用して必要パターンに加工した銅配線31A及び31B
をもつポリイミドフィルム32を用意する。
See FIG. 3 (1) Copper wirings 31A and 31B in which copper foils attached to both front and back surfaces are processed into a required pattern by applying a lithography technique.
A polyimide film 32 having is prepared.

【0028】(2)プリプレグと呼ばれる半硬化状態の
ガラスエポキシ複合材層33及び34を用意する。
(2) Prepare glass epoxy composite layers 33 and 34 in a semi-cured state called prepreg.

【0029】(3)表裏両面に貼着した銅箔をリソグラ
フィ技術を適用して必要パターンに加工した銅配線35
A及び35Bをもつガラスエポキシ複合材層36と銅配
線37A及び37Bをもつガラスエポキシ複合材層38
を用意する。
(3) Copper wiring 35 in which copper foils attached to both front and back surfaces are processed into a required pattern by applying a lithographic technique.
Glass epoxy composite layer 36 with A and 35B and glass epoxy composite layer 38 with copper wiring 37A and 37B
To prepare.

【0030】(4)図示してあるように、ガラスエポキ
シ複合材層36、ガラスエポキシ複合材層33、ポリイ
ミドフィルム32、ガラスエポキシ複合材層34、ガラ
スエポキシ複合材層38を前記順序で積み重ねる。
(4) As shown in the figure, the glass epoxy composite material layer 36, the glass epoxy composite material layer 33, the polyimide film 32, the glass epoxy composite material layer 34, and the glass epoxy composite material layer 38 are stacked in the above order.

【0031】図4参照 (5)積み重ねた前記各層を真空加熱プレスを適用した
一括積層プレス工程に依って一体化することで多層回路
基板を形成する。6層の配線層をもつ多層回路基板を形
成する。
(5) A multilayer circuit board is formed by integrating the stacked layers by a collective laminating press process using a vacuum heating press. A multilayer circuit board having 6 wiring layers is formed.

【0032】前記工程に依って形成された多層回路基板
は6層の配線層を備え、そして、半硬化状態であったガ
ラスエポキシ複合材層33及び34は硬化されたものと
なる。
The multi-layer circuit board formed by the above process has six wiring layers, and the glass epoxy composite material layers 33 and 34 in the semi-cured state are cured.

【0033】(6)この後、ドリル加工に依る貫通穴の
形成、めっき等に依って配線層間の導電接続を行う。
(6) Thereafter, through holes are formed by drilling, and conductive connection between wiring layers is made by plating or the like.

【0034】[0034]

【発明の効果】本発明に依る多層回路基板に於いては、
ポリイミド・フィルムをグランド層と電源層とで挟み且
つそれ等を覆う樹脂絶縁層からなる積層構造が含まれて
いる。
In the multilayer circuit board according to the present invention,
A laminated structure including a resin insulating layer sandwiching a polyimide film between a ground layer and a power supply layer and covering them is included.

【0035】前記構成を採ることに依り、キャパシタの
誘電体層として作用する絶縁層にポリイミド・フィルム
を用いることが可能になり、従って、その厚さは従来の
ものに比較して薄くすることができ、大きなキャパシタ
ンスの実現、回路インダクタンスの低減、絶縁信頼性の
向上が可能となり、そして、従来、高周波ノイズを除去
する為に搭載していたコンデンサは不要となるので、回
路の高密度化及び微細化に大きく寄与することができ
る。
By adopting the above structure, it becomes possible to use a polyimide film for the insulating layer which acts as the dielectric layer of the capacitor, and therefore its thickness can be made thinner than the conventional one. It is possible to realize a large capacitance, reduce the circuit inductance, improve the insulation reliability, and eliminate the need for a capacitor that was conventionally mounted to remove high frequency noise. Can greatly contribute to realization.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理を説明するための多層回路基板を
表す要部切断側面図である。
FIG. 1 is a cutaway side view showing a main part of a multilayer circuit board for explaining the principle of the present invention.

【図2】本発明に於ける一実施の形態を説明する為の工
程要所に於ける多層回路基板を表す要部切断側面図であ
る。
FIG. 2 is a side sectional view showing a main part of a multi-layer circuit board at a process step for explaining an embodiment of the present invention.

【図3】本発明に於ける具体的な実施の形態を説明する
為の工程要所に於ける多層回路基板を表す要部切断側面
図である。
FIG. 3 is a side sectional view showing a main part of a multilayer circuit board at a process step for explaining a specific embodiment according to the present invention.

【図4】本発明に於ける具体的な実施の形態を説明する
為の工程要所に於ける多層回路基板を表す要部切断側面
図である。
FIG. 4 is a side sectional view showing an essential part of a multi-layer circuit board at a process step for explaining a specific embodiment of the present invention.

【図5】従来の技術を説明する為の公知の多層回路基板
を表す要部切断側面図である。
FIG. 5 is a cutaway side view of a main part of a known multilayer circuit board for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

11 ガラスエポキシからなる絶縁層 12 信号層 13 グランド層 14 ポリイミドからなる絶縁層(ポリイミド・フィル
ム) 15 電源層
11 Insulating Layer Made of Glass Epoxy 12 Signal Layer 13 Ground Layer 14 Insulating Layer Made of Polyimide (Polyimide Film) 15 Power Supply Layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】ポリイミド・フィルムをグランド層と電源
層とで挟み且つそれ等を覆う樹脂絶縁層からなる積層構
造が含まれてなることを特徴とする多層回路基板。
1. A multi-layer circuit board comprising a laminated structure including a resin film sandwiching a polyimide film between a ground layer and a power supply layer and covering them.
【請求項2】表面に凹凸を形成して粗面にした銅箔の該
粗面側をポリイミド・フィルムと対向させて挟み熱圧着
する工程と、 次いで、銅箔をパターニングしてグランド層及び電源層
を形成すると共に銅箔の凹凸が転写されたポリイミド・
フィルムの一部を表出させる工程と、 次いで、グランド層及び電源層及び表出されたポリイミ
ド・フィルムの一部を覆う樹脂絶縁層を重ね更に信号層
など所要の層を重ね一括積層プレスして多層回路基板と
する工程とが含まれてなることを特徴とする多層回路基
板の製造方法。
2. A step of thermocompression sandwiching a rough surface of a copper foil having a roughened surface with a rough surface side facing a polyimide film, followed by thermocompression bonding, and then patterning the copper foil to form a ground layer and a power supply. A polyimide layer on which the concavities and convexities of the copper foil are transferred while forming the layer.
A step of exposing a part of the film, and then a resin insulation layer covering a ground layer, a power supply layer and a part of the exposed polyimide film, and further stacking a required layer such as a signal layer and performing a collective lamination press. And a step of forming a multilayer circuit board.
【請求項3】ポリイミド・フィルムの他の樹脂絶縁層が
ガラスエポキシ複合材層であることを特徴とする請求項
2記載の多層回路基板の製造方法。
3. The method for manufacturing a multilayer circuit board according to claim 2, wherein the other resin insulation layer of the polyimide film is a glass epoxy composite material layer.
JP2001228942A 2001-07-30 2001-07-30 Multilayer circuit board manufacturing method Expired - Fee Related JP4684483B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001228942A JP4684483B2 (en) 2001-07-30 2001-07-30 Multilayer circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001228942A JP4684483B2 (en) 2001-07-30 2001-07-30 Multilayer circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JP2003046260A true JP2003046260A (en) 2003-02-14
JP4684483B2 JP4684483B2 (en) 2011-05-18

Family

ID=19061366

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP4684483B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356917B2 (en) 2003-04-04 2008-04-15 Denso Corporation Method for manufacturing multi-layer printed circuit board
WO2016060051A1 (en) * 2014-10-18 2016-04-21 豊田鉄工株式会社 Circuit substrate equipped with heat sink, and method for manufacuring circuit substrate equipped with heat sink

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265494A (en) * 1987-04-23 1988-11-01 Matsushita Electric Works Ltd Multilayer interconnection board
JPH01189997A (en) * 1988-01-26 1989-07-31 Matsushita Electric Works Ltd Multilayer board
JPH04290495A (en) * 1991-03-19 1992-10-15 Fujitsu Ltd Multi-layer flexible printed circuit board and its manufacture
JPH06338587A (en) * 1993-05-28 1994-12-06 Hitachi Chem Co Ltd Manufacture of memory module
JPH08153975A (en) * 1994-11-30 1996-06-11 Oki Electric Ind Co Ltd Multilayered printed wiring board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265494A (en) * 1987-04-23 1988-11-01 Matsushita Electric Works Ltd Multilayer interconnection board
JPH01189997A (en) * 1988-01-26 1989-07-31 Matsushita Electric Works Ltd Multilayer board
JPH04290495A (en) * 1991-03-19 1992-10-15 Fujitsu Ltd Multi-layer flexible printed circuit board and its manufacture
JPH06338587A (en) * 1993-05-28 1994-12-06 Hitachi Chem Co Ltd Manufacture of memory module
JPH08153975A (en) * 1994-11-30 1996-06-11 Oki Electric Ind Co Ltd Multilayered printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356917B2 (en) 2003-04-04 2008-04-15 Denso Corporation Method for manufacturing multi-layer printed circuit board
WO2016060051A1 (en) * 2014-10-18 2016-04-21 豊田鉄工株式会社 Circuit substrate equipped with heat sink, and method for manufacuring circuit substrate equipped with heat sink
JP2016082108A (en) * 2014-10-18 2016-05-16 豊田鉄工株式会社 Circuit board with heat sink, and manufacturing method of circuit board with heat sink

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