JP2003046242A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JP2003046242A
JP2003046242A JP2001226640A JP2001226640A JP2003046242A JP 2003046242 A JP2003046242 A JP 2003046242A JP 2001226640 A JP2001226640 A JP 2001226640A JP 2001226640 A JP2001226640 A JP 2001226640A JP 2003046242 A JP2003046242 A JP 2003046242A
Authority
JP
Japan
Prior art keywords
conductor
insulating layer
multilayer wiring
wiring board
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001226640A
Other languages
Japanese (ja)
Inventor
Katsura Hayashi
Isao Miyatani
Tadashi Nagasawa
勲 宮谷
桂 林
忠 長澤
Original Assignee
Kyocera Corp
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp, 京セラ株式会社 filed Critical Kyocera Corp
Priority to JP2001226640A priority Critical patent/JP2003046242A/en
Publication of JP2003046242A publication Critical patent/JP2003046242A/en
Application status is Pending legal-status Critical

Links

Abstract

PROBLEM TO BE SOLVED: To resolve the problem of generation of power supply noise caused by an inductance element of a through conductor in a high frequency region of 1 GHz or more in a multilayer wiring board with a built-in capacity element.
SOLUTION: In a multilayer wiring board 4, insulation layers 1a to 1e consisting of an organic material are laminated and a wiring conductor 2 is formed in the surface of the insulation layers 1a to 1e, dielectric powder of 20 or more specific inductive capacity is incorporated in at least one layer of the insulation layers 1a to 1e, and a capacitor element A is formed by holding the wiring conductor 2 coated with the insulation layer 1c up and down as an electrode 2a in opposition. In the multilayer wiring board 4, the capacity element A is connected to a wiring conductor 3 via two through conductors 3 per one electrode 2a. It is possible to reduce power source noise generated by an inductance element of the through conductor 3 negligibly and to obtain the multilayer wiring board 4 which is excellent in noise reduction.
COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、各種AV機器や家電機器・通信機器・コンピュータやその周辺機器等の電子機器に使用される多層配線基板に関する。 BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention relates to a multilayer wiring board for use in various types of AV equipment and household electrical appliances, communication equipment, computers and electronic devices such as peripheral devices. 【0002】 【従来の技術】従来、半導体素子等の能動部品や容量素子・抵抗素子等の受動部品を多数搭載し、所定の電子回路を構成するように成した混成集積回路等の電子部品モジュールは、通常、アルミナ等のセラミックス材料から成る絶縁基板の内部および表面にタングステン・モリブデン等の高融点金属粉末から成る複数の配線導体を形成して成る配線基板の表面に、半導体素子や容量素子・抵抗素子等を搭載取着するとともにこれらの電極を各配線導体に接続することによって形成されている。 [0004] Conventionally, an electronic component modules such as hybrid integrated circuit passive components mounted a large number of such active component, a capacitor-resistor element such as a semiconductor element, spaced along its constituting a predetermined electronic circuit typically, the surface of the wiring substrate obtained by forming a plurality of wiring conductors inside and on the surface of the insulating substrate made of ceramics material such as alumina made of a high melting point metal powder such as tungsten, molybdenum, semiconductor device, a capacitor these electrodes while mounted attaching the resistance element or the like is formed by connecting the respective wiring conductors. 【0003】しかしながら、このような配線基板は、配線導体がタングステンやモリブデン等の高融点金属粉末から成る導電ペーストをスクリーン印刷等の厚膜手法を採用し所定パターンに印刷塗布することによって形成されていることから、配線導体の微細化が困難で配線導体を高密度に形成することができないという問題点を有していた。 However, such a wiring board is formed by the wiring conductor is print-coated on employing predetermined pattern a thick film technique such as screen printing a conductive paste made of refractory metal powders of tungsten and molybdenum since you are, miniaturization of the wiring conductor had a problem that it is impossible to densely form a difficult wiring conductor. 【0004】また、従来の配線基板は、表面に半導体素子等の能動部品や容量素子・抵抗素子等の受動部品を多数搭載した場合、部品の搭載数に応じて基板が大型化してしまうという問題点も有していた。 Further, the conventional wiring board, the case of mounting a large number of passive components such as an active component, a capacitor-resistor element such as semiconductor devices on the surface, a problem that the substrate is increased in size in accordance with the number of mounted components point even had. 【0005】このような問題点を解決するために、特開平11-68319号公報には、複数の有機材料絶縁層と複数の薄膜配線導体とを交互に多層に積層するとともに、高誘電率粉末を含有する有機材料絶縁層とそれを挟む対向電極を用いて内部に容量素子を形成した多層配線基板が提案されている。 [0005] In order to solve such problems, JP-A-11-68319, as well as stacked in multiple layers alternately and a plurality of organic material insulating layers and a plurality of thin film wiring conductor, a high dielectric constant powder multilayer wiring board has been proposed that the formation of the capacitor element therein with an organic material insulating layer and a counter electrode sandwiching the containing. 【0006】この多層配線基板によれば、配線導体を薄膜で形成したことから配線の微細化が可能となり、配線を極めて高密度に形成することができ、また、多層配線基板内部に容量素子を形成したことから多層配線基板に半導体素子や容量素子・抵抗素子等の電子部品を搭載して混成集積回路装置等の多層配線基板を製作する場合に、多層配線基板に別途、容量素子を多数実装する必要はなく、その結果、多層配線基板に実装される部品の数が減り小型化することができるというものである。 [0006] According to the multilayer wiring board, the wiring conductor enables miniaturization of the wiring because the formation of a thin film, the wiring can be made extremely high density form, also a capacitive element inside the multilayer wiring board when the formed which by mounting electronic components such as semiconductor devices, a capacitor-resistor element on the multilayer wiring board since fabricating a multilayer wiring substrate such as hybrid integrated circuit device separately in a multilayer wiring board, a large number implement capacitive element need not be, as a result, it is that it is possible to reduce the size of reducing the number of components mounted on the multilayer wiring board. なお、内部に形成された容量素子の各電極は、内部に形成された貫通導体を介して多層配線基板の表面および裏面に形成された配線導体に電気的に接続されている。 Each electrode of the capacitor formed therein is electrically connected to a wiring conductor formed on the front and back surfaces of the multilayer wiring board via a through conductor formed therein. 【0007】 【発明が解決しようとする課題】しかしながら、近年、 [0007] The object of the invention is to be Solved However, in recent years,
通信速度の高速化に伴い通信機器等の電子機器類は周波数が1GHz以上の高周波領域で使用されるようになってきており、このような高周波領域では多層配線基板の貫通導体のインダクタンス成分が大きくなり、△V=L Electronic equipment such as communication equipment along with the speed of communication frequency has come to be used in the above high-frequency range 1 GHz, a large inductance component of the penetrating conductor of the multilayer wiring board in such a high frequency range now, △ V = L
dI/dt(△Vは電源ノイズ、Lはインダクタンス、Iは電流値、tは時間)で定義されるインダクタンス成分により発生する電源ノイズ△Vが無視できないほど大きくなってしまい、通信機器等の電子機器類に誤動作を発生させてしまうという問題点を有していた。 dI / dt (△ V power supply noise, L is the inductance, I is the current value, t is time) becomes larger as the power supply noise △ V is not negligible generated by the inductance components as defined in the electronic and telecommunications equipment We had a problem that caused the malfunction equipment. 【0008】本発明はかかる従来技術の問題点に鑑み案出されたものであり、その目的は、1GHz以上の高周波領域においてもノイズの発生が少なく、通信機器等の電子機器類に誤動作を発生させてしまうことのない多層配線基板を提供することにある。 [0008] The present invention has been devised in view of the problems of the prior art, and its object is less noise generation even more high frequency range 1 GHz, generating malfunctions in electronic equipment such as communication equipment It is to provide a multilayer wiring board never result by. 【0009】 【課題を解決するための手段】本発明の多層配線基板は、有機材料から成る複数の絶縁層を積層するとともにこれら絶縁層の表面に配線導体を形成し、絶縁層を挟んで上下に位置する配線導体間を絶縁層に形成された貫通導体を介し電気的に接続して成る多層配線基板の少なくとも一層に比誘電率が20以上の誘電体粉末を含有させるとともに、この絶縁層の上下両面に被着した配線導体を電極として対向挟持することによって容量素子を形成した多層配線基板において、容量素子が1つの電極につき2個以上の貫通導体を介して配線導体と接続していることを特徴とするものである。 [0009] [Means for Solving the Problems A multilayer wiring board of the present invention is to laminate a plurality of insulating layers composed of an organic material to form a wiring conductor on the surface of the insulating layer, sandwiching the insulating layer vertically between positions wiring conductors with at least one layer in the dielectric constant of the multilayer wiring substrate formed by electrically connecting through a through conductor formed in the insulating layer to contain 20 or more dielectric powder in, the insulating layer in the multilayer wiring substrate formed with the capacitive element by the opposing clamping the wire conductors deposited on both upper and lower surfaces as electrodes, the capacitance element is connected to the wiring conductors via two or more through-conductors per electrode the one in which the features. 【0010】また、本発明の多層配線基板は、上記構成において、容量素子の電極に接続する貫通導体の絶縁層の厚み方向の断面形状が、絶縁層の上下面に位置する底辺の長さが互いに異なる台形状であるとともに、隣接するものの上下の底辺の長さの大小関係が逆転していることを特徴とするものである。 Further, the multilayer wiring board of the present invention having the above structure, the cross-sectional shape in the thickness direction of the insulating layer of the through conductors connected to the electrodes of the capacitor, the length of the base located on the upper and lower surfaces of the insulating layer as well as a different trapezoidal shapes, the magnitude relation of the length of the upper and lower bases of those adjacent and is characterized in that it is reversed. 【0011】本発明の多層配線基板によれば、容量素子を1つの電極につき2個以上の貫通導体を介して配線導体と接続させたことから、インダクタンス成分Lを小さなものとすることができ、その結果、1GHz以上の高周波領域においてもノイズの発生が少なく、通信機器等の電子機器類に誤動作を発生させてしまうことのない多層配線基板とすることができる。 According to the multilayer wiring board of the present invention, since it has to be connected to the wiring conductors via two or more through-conductors per electrode capacitance element, can be an inductance component L and small, as a result, it is possible occurrence of noise in the above high frequency range 1GHz less, a multilayer wiring substrate never would generate a malfunction in electronic equipment such as communication equipment. 【0012】また、本発明の多層配線基板によれば、容量素子の電極に接続する貫通導体の絶縁層の厚み方向における断面形状を、絶縁層の上下面に位置する底辺の長さが互いに異なる台形状としたことから、貫通孔に導電性ペーストを充填して貫通導体を形成する際に、導電性ペーストを貫通孔の底辺が長い方から充填することにより良好に充填することができ、その結果、導電性ペーストの充填率を高め貫通導体の抵抗を小さくすることができるとともにインダクタンス成分を小さくすることができる。 Further, according to the multilayer wiring board of the present invention, the cross-sectional shape in the thickness direction of the insulating layer of the through conductors connected to the electrodes of the capacitor element, are different from each other the length of the base located on the upper and lower surfaces of the insulating layer from what has been a trapezoidal shape, when forming the through conductor by filling a conductive paste into the through-hole, it is possible to a conductive paste bottom of the through hole is well filled by filling the longer, the result, it is possible to reduce the inductance component it is possible to reduce the resistance of the through conductors increase the filling rate of the conductive paste. さらに、隣接する貫通導体の上下の底辺の長さの大小関係を逆転させたことから、貫通導体を高密度に配設することが可能となって単位面積当りに配設可能な貫通導体の数を増やすことができるため容量素子の電極に接続する貫通導体のインダクタンス成分を小さくすることができ、その結果、ノイズ低減の効果が大きい多層配線基板とすることができる。 Furthermore, the number of the upper and lower lengths magnitude relation from the reversed of the base, disposed possible through conductor per unit area is possible to dispose the through conductor at a high density of adjacent through conductor inductance component of the penetrating conductor connecting the electrode of the capacitor it is possible to increase the can be reduced, as a result, it is possible to effect the noise reduction is greater multilayer wiring board. 【0013】 【発明の実施の形態】次に本発明の多層配線基板を添付の図面に基づいて詳細に説明する。 [0013] will be described in detail with reference to the embodiment of the invention Next, a multilayer wiring board of the present invention attached drawings. 【0014】図1は、本発明の多層配線基板の実施の形態の一例を示す断面図であり、この図の例では多層配線基板に電子部品として半導体素子を搭載した場合を示している。 [0014] Figure 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention, in the example of this figure shows the case of mounting the semiconductor device as an electronic component in the multilayer wiring board. この図において1は複数の絶縁層から成る絶縁基体、2は配線導体、3は貫通導体で、主にこれらで本発明の多層配線基板4が構成されている。 Insulating substrate 1 composed of a plurality of insulating layers in this figure, 2 is the wiring conductor, 3 a through conductor, mainly the multilayer wiring board 4 of the present invention in these is constructed. 【0015】絶縁基体1は、本例では5層の有機材料から成る絶縁層1a・1b・1c・1d・1eが積層されて構成されており、絶縁基体1表面には、半導体素子等の電子部品5が半田等の接続材6を介して接続固定される。 [0015] The insulating substrate 1 is an insulating layer 1a · 1b · 1c · 1d · 1e made of an organic material five layers are stacked in this example, the insulating substrate 1 surface, electrons such as a semiconductor element component 5 is connected and fixed via a connection member 6 such as solder. また、 Also,
本例では、絶縁基体1を構成する絶縁層1a・1b・1c・1d In this example, the insulating layer 1a · 1b · 1c · 1d constituting the insulating substrate 1
・1eのうち少なくとも一層(この図の例では絶縁層1c) · 1e at least one layer of the (insulating layer 1c in the example in this figure)
は、比誘電率が20以上の誘電体粉末を含有しており、さらに絶縁層1cをその上下面に被着した配線導体2の一部から成る電極2aで対向挟持することにより容量素子Aを形成している。 The ratio has dielectric constant contains 20 or more dielectric powder, a capacitive element A by opposing nip further insulating layer 1c with the electrode 2a made of a part of the wiring conductor 2 that is deposited on the upper and lower surfaces It is formed. 【0016】絶縁基体1は、半導体素子等の電子部品5 [0016] The insulating substrate 1, the electronic component 5 such as a semiconductor element
を支持する支持体としての機能を有し、この絶縁基体1 Has a function as a support for supporting, the insulating base 1
を構成する絶縁層1a・1b・1c・1d・1eは有機材料により形成されている。 Insulating layer 1a · 1b · 1c · 1d · 1e constituting a is formed of an organic material. 【0017】絶縁層1a・1b・1d・1eを形成する有機材料としては、エポキシ樹脂・フェノール樹脂・ポリイミド樹脂・アリル変性ポリフェニレンエーテル樹脂・ビスマレイミドトリアジン樹脂等の熱硬化性樹脂や液晶ポリエステル・フッ素樹脂・ポリフェニレンエーテル樹脂・ポリエステル樹脂等の熱可塑性樹脂が用いられ、とりわけ、絶縁層1a・1b・1d・1eを形成する際の作業性や絶縁層1a・1b・1d・1eの絶縁特性・耐熱特性・機械的特性等の観点からは、エポキシ樹脂やポリイミド樹脂・アリル変性ポリフェニレンエーテル樹脂等の熱硬化性樹脂が好ましい。 [0017] As the organic material for forming the insulating layer 1a, 1b, 1d, 1e, epoxy resin, phenol resin, polyimide resin, an allyl-modified polyphenylene ether resin, bis thermosetting resin or a liquid crystal polyester fluoride such as maleimide triazine resin thermoplastic resins such as a resin-polyphenylene ether resin, a polyester resin is used, inter alia, insulating properties and heat of workability and insulation layer 1a, 1b, 1d, 1e at the time of forming the insulating layer 1a, 1b, 1d, 1e from the standpoint of a characteristic and mechanical properties, a thermosetting resin such as an epoxy resin or a polyimide resin, an allyl-modified polyphenylene ether resin is preferable. 【0018】また、絶縁層1a・1b・1d・1eには、熱膨張係数を調整する目的および/または機械的強度を向上する目的で酸化アルミニウム・窒化珪素・窒化アルミニウム・炭化珪素・酸化チタン・酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム・ゼオライト等の無機絶縁粉末や繊維状ガラスを布状に織り込んだガラスクロスあるいは繊維状有機材料からなる不織布等の充填材や、有機材料と無機絶縁粉末の親和性を高めこれらの接合性向上と絶縁基体1の機械的強度を高める目的でシラン系カップリング剤・チタネート系カップリング剤等のカップリング剤、熱安定性を改善する目的で酸化防止剤、耐光性を改善する目的で紫外線吸収剤等の光安定剤、難燃性を改善する目的でハロゲン系・リン酸系の難燃性剤および Further, the insulating layer 1a, 1b, 1d, 1e, objects and / or objects with aluminum oxide aluminum silicon nitride-nitride-silicon carbide, titanium oxide, to improve the mechanical strength adjusting the thermal expansion coefficient the inorganic insulating powder and fibrous glass such as barium oxide, strontium oxide, zirconium oxide calcium oxide, zeolite or filler such as a nonwoven fabric made of glass cloth or fibrous organic material interwoven into fabric-like, organic material and an inorganic insulating powder affinity enhanced coupling agents such as silane coupling agent, titanate coupling agent for the purpose of increasing the mechanical strength of the insulating base 1 and these junctions improving thermal stability antioxidant for the purpose of improving the a light stabilizer of the ultraviolet absorber or the like in order to improve the light resistance, flame retardant halogen-phosphate system for the purpose of improving the flame retardancy and ンチモン系化合物・ホウ酸亜鉛・ Nchimon compounds, zinc borate,
メタホウ酸バリウム・酸化ジルコニウム等の難燃助剤、 Flame retardant aid such as barium metaborate, zirconium oxide,
潤滑性を改善する目的で高級脂肪酸・高級脂肪酸エステル・高級脂肪酸金属塩・フルオロカーボン系界面活性剤等の外部滑剤効果を有するもの等を1種以上、必要に応じて添加してもよい。 Such as those for the purpose of improving the lubricity having external lubricant effect such as higher fatty acids, higher fatty acid ester-metal salts of higher fatty acids, fluorocarbon-based surfactant one or more may be added if necessary. 【0019】このような絶縁基体1は、例えば粒径が0. [0019] The insulating substrate 1, for example, particle size 0.
1〜15μm程度の酸化アルミニウム・窒化珪素・窒化アルミニウム・炭化珪素・酸化チタン・酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム等の無機絶縁粉末に、エポキシ樹脂・フェノール樹脂・ The inorganic insulating powder such as aluminum oxide, silicon nitride-aluminum nitride carbide, titanium-barium oxide, strontium oxide, zirconium oxide calcium oxide of approximately 1 to 15 m, an epoxy resin, a phenolic resin,
ポリイミド樹脂・ビスマレイミド樹脂・アリル変性ポリフェニレンエーテル樹脂等の熱硬化性樹脂または液晶ポリエステル・ポリフェニレンエーテル樹脂等の熱可塑性樹脂と溶剤・可塑剤・分散剤等を添加混合して得たペーストを従来周知のドクタブレード法等のシート成型法を採用してシート状となすことによって絶縁基体1における絶縁層1a・1b・1d・1eとなる複数の前駆体シートを得るとともにこの絶縁層1a・1b・1d・1eとなる前駆体シートと後述する絶縁層1cとなる前駆体シートの各々に必要に応じて穿設加工を従来周知のレーザ加工法を採用して施し、これらの穿設加工が施された絶縁層1a・1b・1c・ Conventionally known polyimide resins, bismaleimide resins, allyl-modified polyphenylene ether resin of the thermosetting resin or liquid crystal polyester polyphenylene ether resin of thermoplastic resin and a solvent, a plasticizer and dispersing agent obtained by adding and mixing a paste the insulating layer 1a · 1b · 1d with obtaining a plurality of precursor sheet by forming a doctor blade method or the like of the sheet molding method adopted by sheet becomes an insulating layer 1a · 1b · 1d · 1e of the insulating base 1 · 1e precursor sheet and if necessary in each of the precursor sheet formed of an insulating layer 1c to be described later subjected employ conventionally known laser processing method bored processing which is, these bored processing is performed insulating layer 1a · 1b · 1c ·
1d・1eを所定の順に積層圧着し、最後に、積層圧着された絶縁層1a・1b・1c・1d・1eを温度が約100〜300℃で圧力が0.4〜10MPaの条件で30分〜24時間ホットプレスして加熱硬化させることによって製作される。 The 1d · 1e laminated crimped in a predetermined order, finally, 30 minutes the pressure in the conditions of 0.4~10MPa stacked crimped insulating layer 1a · 1b · 1c · 1d · 1e at a temperature of about 100 to 300 ° C. to 24 It is fabricated by heating and curing by time hot pressing. 【0020】また、絶縁層1cは、有機材料から成るとともに比誘電率が20以上の誘電体粉末を10〜70体積%含有しており、さらにその上下面に被着した後述する配線導体2の一部から成る電極2aで対向挟持することにより容量素子Aを形成している。 Further, the insulating layer 1c has a specific dielectric constant with an organic material are contained more than 20 dielectric powder 10 to 70 vol%, further wiring conductors 2 described below was applied to the upper and lower surfaces forming a capacitor element a by opposing sandwiching the electrode 2a made of a part. 【0021】本発明の多層配線基板4によれば、このような容量素子Aを内部に形成したことから、多層配線基板4に半導体素子や容量素子・抵抗器等の電子部品5を混載して混成集積回路等の電子部品モジュールを製作する場合に、多層配線基板4に別途容量素子を多数実装する必要はなく、その結果、多層配線基板4に実装される部品の数が減り、多層配線基板4や電子部品モジュールを小型化することができる。 According to the multilayer wiring board 4 of the present invention, since the formation of such a capacitor element A inside, and mixed electronic components 5 of the semiconductor device, a capacitor, resistor or the like to the multilayer wiring board 4 when fabricating the electronic component module such as a hybrid integrated circuit, it is not necessary to implement a large number of separate capacitive elements in the multilayer wiring board 4, as a result, reduce the number of components mounted on the multilayer wiring board 4, the multilayer wiring board 4 and the electronic component module can be miniaturized. 【0022】絶縁層1cに含有される比誘電率が20以上の誘電体粉末としては、酸化チタンや酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム等の無機系誘電体粉末やこれらの化合物・混合物、チタン酸カリウムウィスカ・ホウ酸アルミニウムウィスカ・針状酸化チタン・シリカアルミナ繊維・アルミナ繊維等の繊維状高誘電体粉末・チタン酸バリウム・チタン酸カルシウム・チタン酸ストロンチウム・スズ酸バリウム・ジルコン酸バリウム・ジルコン酸ストロンチウム等の高誘電体粉末が用いられ、その比誘電率が20(室温1MH Examples of the dielectric powder relative dielectric constant of 20 or more contained in the insulating layer 1c, inorganic dielectric powders and these compounds, a mixture such as titanium oxide or barium oxide, strontium oxide, zirconium oxide calcium oxide , potassium titanate whisker, aluminum borate whisker, needle-like titanium oxide-silica-alumina fibers, fibrous high dielectric powder, barium titanate, calcium titanate, strontium titanate, barium stannate, barium zirconate alumina fibers and high dielectric powder, such as strontium zirconate is used, the relative dielectric constant of 20 (room temperature 1MH
z)より小さいと、絶縁層1cの比誘電率が小さくなって容量素子Aが実用に供することができないものとなってしまう傾向がある。 z) and smaller, there is a tendency that the capacity element A becomes what can not be put into practical use in the dielectric constant of the insulating layer 1c is decreased. 従って、絶縁層1cに含有される誘電体粉末は、その比誘電率を20以上とすることが重要である。 Therefore, the dielectric powder contained in the insulating layer 1c, it is important that the relative dielectric constant of 20 or higher. 【0023】また、誘電体粉末は、その含有量が絶縁層 Further, dielectric powder, the content of insulating layer
1cに対して10体積%未満であると絶縁層1cの比誘電率が小さくなり、実用に供することができる容量素子Aを形成することが困難となる傾向があり、70体積%を超えると有機材料の混練性が低下し絶縁層1cの製作が困難となる傾向がある。 Is less than 10% by volume relative dielectric constant of the insulating layer 1c is reduced relative to 1c, there is a tendency to be difficult to form a capacitor element A can be subjected to practical use, when it exceeds 70% by volume organic there is a tendency that kneading of the material is difficult to manufacture a reduced insulating layer 1c. 従って、誘電体粉末の含有率は10〜70体積%の範囲とすることが好ましい。 Accordingly, the content of the dielectric powder is preferably in the range of 10 to 70 vol%. 【0024】さらに、誘電体粉末の平均粒径は、0.1〜1 Furthermore, the average particle size of the dielectric powder is 0.1 to 1
5μmの範囲であることが好ましく、平均粒径が0.1μm It is preferably in the range of 5 [mu] m, an average particle diameter of 0.1μm
未満であるとその比表面積が大きくなって誘電体粉末を添加混合した混練物の粘度が高いものとなり、その結果、絶縁層1cを形成する際に絶縁層1cの厚みが不均一となり、所定の均一厚みとすることが困難となる傾向がある。 In some When the specific surface area thereof is increased less than would those high viscosity of the kneaded product was added and mixed dielectric powder, so that the thickness of the insulating layer 1c in forming the insulating layer 1c is not uniform, predetermined there is a tendency that it is difficult to uniform thickness. 他方、平均粒径が15μmを超えると絶縁層1cの表面に誘電体粉末による凹凸が形成され、容量素子Aが形成される領域における比誘電率にバラツキを生じたり、絶縁層1cに穿設加工を施す際の加工精度が低下してしまう傾向がある。 On the other hand, the average particle size is formed irregularities due dielectric powder on the surface of the insulating layer 1c exceeds 15 [mu] m, or cause variations in the dielectric constant in the region where the capacitor element A is formed, drilled processed into insulation layer 1c machining accuracy when performing tends to decrease. 従って、絶縁層1cに含有される誘電体粉末は、その平均粒径を0.1〜15μmの範囲とすることが好ましく、好適には0.3〜10μmの範囲とすることが好ましい。 Therefore, the dielectric powder contained in the insulating layer 1c is preferably to an average particle size in the range of 0.1-15, preferably is preferably in a range of 0.3 to 10 [mu] m. 【0025】このような絶縁層1cと成る前駆体シートは、例えば、平均粒径が0.1〜15μm程度の酸化チタンやチタン酸ストロンチウム・チタン酸カルシウム・チタン酸マグネシウム・チタン酸カリウム等の誘電体粉末に、アリル変性ポリフェニレンエーテルやシアネート樹脂等の有機材料と、適当な溶剤・可塑剤・分散剤等を添加して得たペーストを従来周知のドクタブレード法等のシート形成法を採用してシート状となすとともに、60〜 The precursor sheet comprising such a dielectric layer 1c is, for example, an average particle size of titanium oxide, potassium titanate strontium titanate calcium titanate magnesium titanate of about 0.1~15μm dielectric powder the allyl modified poly and organic materials such as polyphenylene ether and a cyanate resin, a suitable solvent, plasticizer and dispersing agent paste obtained by adding employ sheet forming method such as conventionally known doctor blade method sheet with eggplant and, 60
100℃の温度で5分〜3時間加熱することにより製作される。 It is manufactured by heating at a temperature of 100 ° C. 5 minutes to 3 hours. 【0026】また、絶縁層1a・1b・1c・1d・1eからなる絶縁基体1には、絶縁層1a・1b・1c・1d・1e表面に配線導体2が形成されているとともに配線導体2の一部から成る電極2aで絶縁層1cを対向挟持して成る容量素子Aが形成されている。 Further, the insulating substrate 1 made of an insulating layer 1a · 1b · 1c · 1d · 1e, of the wiring conductor 2 with the wiring conductor 2 to the insulating layer 1a · 1b · 1c · 1d · 1e surface is formed capacitive element a formed by opposed sandwiching the insulating layer 1c is formed by the electrode 2a made of a part. さらに、絶縁層1a・1b・1c・1d・1eを挟んで上下に位置する配線導体2間(電極2a間は除く) Moreover, between the wiring conductor 2 located vertically sandwiching the dielectric layer 1a · 1b · 1c · 1d · 1e (except between the electrodes 2a)
を電気的に接続する貫通導体3が形成されている。 Through conductors 3 for electrically connecting it is formed a. 【0027】配線導体2および貫通導体3は、多層配線基板4に実装される半導体素子等の電子部品5を外部電気回路(図示せず)に電気的に接続する機能を有し、また、配線導体2の一部は容量素子Aの電極2aとしての機能も有する。 The wiring conductors 2 and the through conductors 3 have a function of electrically connecting the electronic component 5 such as a semiconductor element mounted on the multilayer wiring board 4 to the external electric circuit (not shown), also, the wiring part of the conductor 2 also functions as an electrode 2a of the capacitor a. 【0028】このような配線導体2は、絶縁層1a・1b・ [0028] Such wiring conductor 2, insulating layer 1a · 1b ·
1c・1d・1eとなる複数の前駆体シートの表面に、銅・銀・金等の低抵抗金属を従来周知のスクリーン印刷法により形成する方法やパターン形成した銅・金等から成る金属箔を転写法等により被着形成する方法・無電解めっき法・蒸着法・スパッタリング法等の薄膜形成方法を採用することにより形成される。 A plurality of precursor surface of the sheet to be 1c, 1d, 1e, a metal foil made of a method and patterned copper-gold or the like to form a low resistance metal such as copper, silver and gold by conventional well-known screen printing method It is formed by employing a thin film formation method such as a method, an electroless plating method, an evaporation method, a sputtering method to deposit formed by a transfer method or the like. また、配線導体2は、1G The wiring conductors 2, 1G
Hz以上の高周波領域の信号をより損失を低減して伝送する目的で、従来周知のストリップ線路・マイクロストリップ線路・コプレーナ線路・誘電体導波管線路等の線路で構成してもよい。 For the purpose of transmitting signals Hz or more frequency region by reducing the more losses, it may be constituted by a conventionally known stripline microstrip line, coplanar line, the dielectric waveguide line such as the line. 【0029】本発明の多層配線基板4では、上記のように配線導体2を薄膜で形成したことから配線導体2の微細化が可能となり、配線導体2を極めて高密度に形成することができ、小型の多層配線基板4とすることができる。 [0029] In the multilayer wiring board 4 of the present invention, the wiring conductor 2 as described above enables miniaturization of the wiring conductor 2 because it was formed by a thin film, it is possible to wiring conductors 2 very densely formed, it can be a small multi-layer wiring board 4. 【0030】なお、容量素子Aの容量値は、多層配線基板4に要求される機能により決定され、含有される誘電体粉末の比誘電率や含有量・絶縁層1cの厚み・容量素子Aの電極2aの面積等を適宜決めることにより決定される。 [0030] Incidentally, the capacitance of the capacitor A is determined by the required function to the multilayer wiring board 4, the thickness and capacity element A relative dielectric constant and the content-insulating layer 1c of the dielectric powder contained It is determined by determining the area of ​​the electrode 2a or the like as appropriate. 【0031】また、貫通導体3は、絶縁層1a・1b・1c・ Further, the through conductors 3, the insulating layer 1a · 1b · 1c ·
1d・1eとなる複数の前駆体シートにレーザ加工法により穿設加工を施し貫通孔を形成した後、この貫通孔に銅・ After forming the through-holes subjected to drilling work by the laser processing method in a plurality of precursor sheet comprising a 1d-1e, copper in the through-hole
銀・金等から成る導電性ペーストをスクリーン印刷法等により埋め込むことにより形成される。 It is formed by burying a conductive paste made of silver, gold or the like by screen printing or the like. 【0032】そして本発明の多層配線基板4においては、容量素子Aが1つの電極2aにつき2個以上の貫通導体3を介して配線導体2と接続していることが好ましく、また、このことが重要である。 [0032] Then, in the multilayer wiring board 4 of the present invention, it is preferable that the capacitive element A is connected two or more through the through conductor 3 and the wiring conductors 2 per one electrode 2a, also this is is important. 【0033】本発明の多層配線基板4によれば、容量素子Aが1つの電極2aにつき2個以上の貫通導体3を介して配線導体2と接続していることから、例えば、多層配線基板4に半導体素子5を搭載し、容量素子Aを形成する一方の電極2aを半導体素子5の電源端子に、他方の電極2aを半導体素子5の接地端子に接続した場合、容量素子Aの一方の電極2aに接続している貫通導体3の合計のインダクタンスLの逆数が各貫通導体3のインダクタンスlの逆数の和となり(インダクタンスlの貫通導体3 According to the multilayer wiring board 4 of the [0033] present invention, since the capacitance elements A are connected two or more through the through conductor 3 and the wiring conductors 2 per one electrode 2a, for example, the multilayer wiring board 4 the semiconductor element 5 is mounted on, one electrode 2a to form a capacitor element a to the power supply terminal of the semiconductor element 5, when connecting the other electrode 2a to the ground terminal of the semiconductor element 5, one electrode of the capacitor a reciprocal of the sum of the inductance L of the through conductors 3 connected to 2a becomes the sum of the reciprocal of the inductance l of each through conductor 3 (through conductor inductance l 3
をn個形成した場合、合計のインダクタンスをLとすると1/L=1/l 1 +1/l 2 +・・・+1/l n 、すなわちL=l/nとなる)、貫通導体3のインダクタンス成分Lは、容量素子Aの電極2aに1個の貫通導体3を介して配線導体2と接続させた時よりも小さなものとすることができ、その結果、1GHz以上の高周波領域においてもノイズの発生が少なく、通信機器等の電子機器類に誤動作を発生させてしまうことのない多層配線基板4 The case where the n pieces formed, the inductance of the sum and L 1 / L = 1 / l 1 + 1 / l 2 + ··· + 1 / l n, i.e. the L = l / n), the inductance of the through conductors 3 component L through the one through conductor 3 to the electrode 2a of the capacitive element a can be smaller than the time that was connected to the wiring conductor 2, as a result, the noise in the above high-frequency region 1GHz generation is small, the multilayer wiring board 4 never causes to generate a malfunction in electronic equipment such as communication equipment
とすることができる。 It can be. 【0034】また、本発明の多層配線基板4においては、容量素子Aの電極2aに接続する貫通導体3の絶縁層 Further, in the multilayer wiring board 4 of the present invention, the insulating layer of the through conductors 3 to be connected to the electrode 2a of the capacitive element A
1b・1d の厚み方向における断面形状を、絶縁層1b・1d The cross-sectional shape in the thickness direction of the 1b · 1d, an insulating layer 1b · 1d
の上下面に位置する底辺の長さが互いに異なる台形状とすることが好ましい。 It is preferred that the length of the base located on the upper and lower surfaces is different trapezoidal shapes. 【0035】本発明の多層配線基板4によれば、容量素子Aの電極2aに接続する貫通導体3の絶縁層1b・1d の厚み方向における断面形状を、絶縁層1b・1d の上下面に位置する底辺の長さが互いに異なる台形状としたことから、貫通孔に導電性ペーストを充填して貫通導体3を形成する際に、導電性ペーストを貫通孔の底辺が長い方から充填することにより良好に充填することができ、その結果、導電性ペーストの充填率を高め貫通導体3の抵抗を小さくすることができるとともにインダクタンス成分を小さくすることができる。 According to the multilayer wiring board 4 of the [0035] present invention, the cross-sectional shape in the thickness direction of the insulating layer 1b · 1d of the through conductors 3 to be connected to the electrode 2a of the capacitor A, located on the upper and lower surfaces of the insulating layer 1b · 1d since the length of the base is different trapezoidal shapes that, when forming the through conductors 3 by filling a conductive paste into the through-hole, by a conductive paste bottom of the through hole is filled from the longer can be satisfactorily filled, as a result, it is possible to reduce the inductance component it is possible to reduce the resistance of the through conductors 3 increases the filling rate of the conductive paste. 【0036】さらに、本発明の多層配線基板4においては、隣接する貫通導体3の上下の底辺の長さの大小関係を逆転させて貫通導体3を形成することが好ましく、また、このことが重要である。 Furthermore, in the multilayer wiring board 4 of the present invention, it is preferable to form the through conductors 3 and below the bottom of the length magnitude relationship by reverse rotation of the through conductors 3 adjacent, also important that this it is. 【0037】本発明の多層配線基板4においては、隣接する貫通導体3の上下の底辺の長さの大小関係を逆転させて貫通導体3を形成したことから、貫通導体3を高密度に配設することが可能となって単位面積当りに配設可能な貫通導体3の数を増やすことができるため、容量素子Aの電極2aに接続する貫通導体3のインダクタンス成分を小さくすることができ、その結果、ノイズ低減の効果が大きい多層配線基板4とすることができる。 In [0037] multilayer wiring board 4 of the present invention, since the formation of the through conductor 3 by reversing the length magnitude of the upper and lower base of the through conductor 3 adjacent the through conductors 3 densely disposed it is possible to increase the number of disposed possible through conductor 3 per unit area is possible to, it is possible to reduce the inductance component of the penetrating conductor 3 connected to the electrode 2a of the capacitor a, the result may be a multilayer wiring substrate 4 is larger effect of noise reduction. 【0038】このような貫通導体3は、レーザ加工法を用いて、レーザのエネルギーを調整したり、絶縁層の厚みを調整することにより、絶縁層1b・1dの厚み方向の断面形状を所望の台形状とすることができる。 [0038] Such vias 3, using the laser processing method, to adjust the energy of the laser, by adjusting the thickness of the insulating layer, the thickness direction of the insulating layer 1b · 1d sectional shape of the desired it can be a trapezoidal shape. そして、絶縁層1b・1dの一方の表面側よりレーザ穿設加工を施して貫通孔を形成するとともに導電性ペーストを埋め込んで貫通導体3を形成した後、続けて絶縁層1b・1dの他方の表面側よりレーザ穿設加工を施して貫通孔を形成するとともに導電性ペーストを埋め込み貫通導体3を形成することにより隣接する貫通導体3の断面形状の上下の底辺の長さの大小関係を逆転させた複数の貫通導体3を形成することができる。 Then, after forming the through conductors 3 by embedding a conductive paste to form a through hole by applying laser drilling process from the one surface of the insulating layer 1b · 1d, followed by the other of the insulating layer 1b · 1d reversed the length magnitude of the upper and lower base of the cross-sectional shape of the through conductors 3 adjacent by forming the through conductors 3 buried conductive paste to form a through hole by applying laser drilling process from the surface side it is possible to form a plurality of through conductors 3. 【0039】なお、電極2aに接続する貫通導体3は、抵抗値を低減して導電性を良好にするという観点からは、 [0039] The through conductors 3 connected to the electrodes 2a, the terms of to reduce the resistance to improve conductivity,
直径が20μm以上であることが好ましい。 It is preferred diameter is 20μm or more. また、貫通導体3を高密度に配設するという観点からは、直径が250 From the viewpoint of disposing the through conductors 3 at high density, diameter 250
μm以下であることが好ましい。 It is preferable μm is less than or equal to. 従って、電極2aに接続する貫通導体3の直径は20〜250μmであることが好ましい。 Accordingly, the diameter of the through conductors 3 to be connected to the electrode 2a is preferably 20 to 250. 【0040】また、貫通導体3の断面形状の長い方の底辺の長さが短い方の底辺の長さに対して1.2倍未満であると、導電性ペーストの充填率が低下して貫通導体3の抵抗値が増大しノイズの要因となる傾向がある。 Further, when it is less than 1.2 times the length of the base of the shorter length of the base of the longer of the cross-sectional shape of the through conductors 3, through conductor 3 filling of the conductive paste is decreased there is a tendency that the resistance value of the factor of increased noise. 他方、 On the other hand,
3倍を超えると、レーザ穿設加工後のデスミアが困難となり導通不良となる危険性が高い。 When more than 3-fold, at high risk desmear the becomes difficult conduction failure after laser drilling processing. 従って、貫通導体3 Therefore, the through conductors 3
の断面形状の長い方の底辺の長さは短い方の底辺の長さに対して1.2〜3倍であることが好ましい。 It is preferred that the cross-section the longer base length of the shape of a 1.2 to 3 times the shorter base length of. 【0041】さらに、配線導体2・貫通導体3は、その露出する表面にニッケル・金等の耐蝕性に優れ、かつ良導電性の金属をめっき法により1.0〜20μmの厚みに被着させておくと配線導体2・貫通導体3の酸化腐蝕を有効に防止することができるとともに配線導体2・貫通導体3と半導体素子等の電子部品5や外部電気回路の配線導体(図示せず)とを強固に電気的に接続させることができる。 [0041] Further, the wiring conductor 2, through conductors 3, keep the exposed surface excellent in corrosion resistance such as nickel-gold, and is deposited to a thickness of 1.0~20μm by plating a highly conductive metal the wiring conductor 2, (not shown) effectively it is possible to prevent the wiring conductors 2, through conductors 3 and the electronic components such as semiconductor devices 5 and the external electric circuit of the wiring conductor oxidation corrosion of the through conductors 3 a strong it can be electrically connected to. 従って、配線導体2・貫通導体3の露出する表面には、ニッケルや金等の耐蝕性に優れ、かつ良導電性の金属をめっき法により1.0〜20μmの厚みに被着させておくことが好ましい。 Accordingly, the exposed surface of the wiring conductor 2, through conductors 3 are excellent in corrosion resistance such as nickel or gold, and is preferably allowed deposited to a thickness of 1.0~20μm by plating a highly conductive metal . 【0042】かくして本発明の多層配線基板4によれば、容量素子Aを1つの電極2aにつき2個以上の貫通導体3を介して配線導体2と接続させたことから、インダクタンス成分Lを小さなものとすることができ、その結果、1GHz以上の高周波領域においてもノイズの発生が少なく、通信機器等の電子機器類に誤動作を発生させてしまうことのない多層配線基板4とすることができる。 [0042] Thus, according to the multilayer wiring board 4 of the present invention, since it has a capacitive element A is connected one with the wiring conductor 2 via two or more feed-through conductors 3 per electrode 2a, small things an inductance component L and it is possible to, as a result, can also occur in the noise in the above high frequency range 1GHz less, a multilayer wiring board 4 never causes to generate a malfunction in electronic equipment such as communication equipment. また、容量素子Aの電極2aに接続する貫通導体3の絶縁層1b・1dの厚み方向における断面形状を、絶縁層1b Further, the sectional shape in the thickness direction of the insulating layer 1b · 1d of the through conductors 3 to be connected to the electrode 2a of the capacitor A, the insulating layer 1b
・1dの上下面に位置する底辺の長さが互いに異なる台形状としたことから、貫通孔に導電性ペーストを充填して貫通導体3を形成する際に、導電性ペーストを貫通孔の底辺が長い方から充填することにより良好に充填することができ、その結果、導電性ペーストの充填率を高め貫通導体3の抵抗を小さくすることができるとともにインダクタンス成分を小さくすることができる。 Since the length of the base located on the upper and lower surfaces of the · 1d is different trapezoidal shapes, when forming the through conductors 3 by filling a conductive paste into the through-hole, the conductive paste bottom of the through hole can be satisfactorily filled by filling the longer, as a result, it is possible to reduce the inductance component it is possible to reduce the resistance of the through conductors 3 increases the filling rate of the conductive paste. さらに、隣接する貫通導体3の上下の底辺の長さの大小関係を逆転させたことから、貫通導体3を高密度に配設することが可能となって単位面積当りに配設可能な貫通導体3の数を増やすことができるため容量素子Aの電極に接続する貫通導体のインダクタンス成分を小さくすることができ、その結果、ノイズ低減の効果が大きい多層配線基板4とすることができる。 Further, since the reversed the length magnitude of the upper and lower base of the through conductor 3 of adjacent through conductor 3 can be disposed of per unit area and can be disposed at a high density through-conductors inductance component of the penetrating conductor connecting the electrode of the capacitor a it is possible to increase the number of 3 can be reduced, as a result, may be a multi-layer wiring board 4 is large effect of noise reduction. 【0043】なお、本発明の多層配線基板4は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では5層の絶縁層1a・1b・1c・1d・1eを積層することによって絶縁基体1を製作したが、3層や4 Incidentally, the multilayer wiring board 4 of the present invention is not intended to be limited to the embodiments described above, various modifications as long as it does not depart from the gist of the present invention can be, for example, in the above embodiments in has been fabricated an insulating substrate 1 by laminating an insulating layer 1a · 1b · 1c · 1d · 1e of five layers, three layers or four
層、あるいは6層以上の絶縁層を積層して絶縁基体1を製作してもよい。 Layer or by stacking 6 or more insulating layers may be fabricated insulating substrate 1. また、上述の実施例では誘電体粉末を含む絶縁層を1層としたが、2層(連続層を含む)以上としてもよい。 Further, although the above embodiment was one layer of insulating layer including the dielectric powder may be two or more layers (including a continuous layer). 【0044】また、上述の実施例では容量素子Aは、電極2aが誘電体粉末を含む絶縁層1cを1層挟持して形成されているが、2層以上挟持して形成されていてもよい。 [0044] The capacitor A in the embodiment described above, the electrode 2a is formed by 1 Sokyoji the insulating layer 1c containing dielectric powder, may be formed by sandwiching two or more layers . 【0045】 【発明の効果】本発明の多層配線基板によれば、容量素子を1つの電極につき2個以上の貫通導体を介して配線導体と接続させたことから、インダクタンス成分Lを小さなものとすることができ、その結果、1GHz以上の高周波領域においてもノイズの発生が少なく、通信機器等の電子機器類に誤動作を発生させてしまうことのない多層配線基板とすることができる。 [0045] According to the multilayer wiring board of the present invention, since it has to be connected to the wiring conductors via two or more through-conductors per electrode a capacitor, and an inductance component L smaller ones it can be, as a result, can also occur in the noise in the above high frequency range 1GHz less, a multilayer wiring substrate never would generate a malfunction in electronic equipment such as communication equipment. 【0046】また、本発明の多層配線基板によれば、容量素子の電極に接続する貫通導体の絶縁層の厚み方向における断面形状を、絶縁層の上下面に位置する底辺の長さが互いに異なる台形状としたことから、貫通孔に導電性ペーストを充填して貫通導体を形成する際に、導電性ペーストを貫通孔の底辺が長い方から充填することにより良好に充填することができ、その結果、導電性ペーストの充填率を高め貫通導体の抵抗を小さくすることができるとともにインダクタンス成分を小さくすることができる。 Further, according to the multilayer wiring board of the present invention, the cross-sectional shape in the thickness direction of the insulating layer of the through conductors connected to the electrodes of the capacitor element, are different from each other the length of the base located on the upper and lower surfaces of the insulating layer from what has been a trapezoidal shape, when forming the through conductor by filling a conductive paste into the through-hole, it is possible to a conductive paste bottom of the through hole is well filled by filling the longer, the result, it is possible to reduce the inductance component it is possible to reduce the resistance of the through conductors increase the filling rate of the conductive paste. さらに、隣接する貫通導体の上下の底辺の長さの大小関係を逆転させたことから、貫通導体を高密度に配設することが可能となって単位面積当りに配設可能な貫通導体の数を増やすことができるため容量素子の電極に接続する貫通導体のインダクタンス成分を小さくすることができ、その結果、ノイズ低減の効果が大きい多層配線基板とすることができる。 Furthermore, the number of the upper and lower lengths magnitude relation from the reversed of the base, disposed possible through conductor per unit area is possible to dispose the through conductor at a high density of adjacent through conductor inductance component of the penetrating conductor connecting the electrode of the capacitor it is possible to increase the can be reduced, as a result, it is possible to effect the noise reduction is greater multilayer wiring board.

【図面の簡単な説明】 【図1】本発明の多層配線基板の実施の一例を示す断面図であり、電子部品を搭載した例である。 A cross-sectional view showing an example of implementation of a multilayer wiring board BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] The present invention is an example of mounting an electronic component. 【符号の説明】 1・・・・・・・・・絶縁基体1a・1b・1d・1e ・・絶縁層1c・・・・・・・・・絶縁層(誘電体粉末含有絶縁層) 2・・・・・・・・・配線導体2a・・・・・・・・・電極3・・・・・・・・・貫通導体4・・・・・・・・・多層配線基板A・・・・・・・・・容量素子 [EXPLANATION OF SYMBOLS] 1 ......... insulating substrate 1a, 1b, 1d, 1e · · insulating layer 1c ......... insulating layer (dielectric powder containing insulating layer) 2 · ........ conductor 2a ......... electrode 3 ......... through conductor 4 ......... multilayer wiring board A · · · ...... capacity element

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 BB02 BB03 BB12 BB13 BB14 CC22 CC25 CD21 CD32 GG11 5E346 AA12 AA13 AA43 CC04 CC05 CC08 CC09 CC10 CC32 CC38 CC39 DD02 DD17 DD23 EE04 FF18 GG15 GG28 HH02 HH06 ────────────────────────────────────────────────── ─── front page of continued F-term (reference) 5E317 AA24 BB02 BB03 BB12 BB13 BB14 CC22 CC25 CD21 CD32 GG11 5E346 AA12 AA13 AA43 CC04 CC05 CC08 CC09 CC10 CC32 CC38 CC39 DD02 DD17 DD23 EE04 FF18 GG15 GG28 HH02 HH06

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 有機材料から成る複数の絶縁層を積層するとともにこれら絶縁層の表面に配線導体を形成し、前記絶縁層を挟んで上下に位置する前記配線導体間を前記絶縁層に形成された貫通導体を介し電気的に接続して成る多層配線基板の少なくとも一層に比誘電率が20以上の誘電体粉末を含有させるとともに、この絶縁層の上下両面に被着した前記配線導体を電極として対向挟持することによって容量素子を形成した多層配線基板において、前記容量素子は1つの前記電極につき2個以上の前記貫通導体を介して前記配線導体と接続していることを特徴とする多層配線基板。 Claims We claim: 1. A with stacking a plurality of insulating layers formed of an organic material to form a wiring conductor on the surface of the insulating layer, between the wiring conductors located vertically across said insulating layer at least one layer in the dielectric constant, together with the inclusion of 20 or more dielectric powder of the multilayer wiring board formed by connecting the electrically via formed through conductors in the insulating layer was deposited on the upper and lower surfaces of the insulating layer in the multilayer wiring substrate formed with the capacitive element by the opposing clamping the conductor as an electrode, said capacitor element is connected to the wiring conductor through at least two said through-conductors per said electrodes multilayer wiring substrate which is characterized. 【請求項2】 前記電極に接続する前記貫通導体の前記絶縁層の厚み方向の断面形状は、前記絶縁層の上下面に位置する底辺の長さが互いに異なる台形状であるとともに、隣接するものの上下の底辺の長さの大小関係が逆転していることを特徴とする請求項1記載の多層配線基板。 Wherein the thickness direction of the insulating layer of the through conductors connected to the electrode cross-sectional shape, with the length of the base located on the upper and lower surfaces of the insulating layer are different trapezoidal shapes, although the adjacent multilayer wiring board according to claim 1, wherein the magnitude relation of the length of the upper and lower base is characterized in that it reversed.
JP2001226640A 2001-07-26 2001-07-26 Multilayer wiring board Pending JP2003046242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001226640A JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001226640A JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JP2003046242A true JP2003046242A (en) 2003-02-14

Family

ID=19059416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001226640A Pending JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2003046242A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006521708A (en) * 2003-03-28 2006-09-21 ジョージア テック リサーチ コーポレーション The method for manufacturing a three-dimensional total organic interconnect structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08116174A (en) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd Circuit formation board and manufacture thereof
JPH0946047A (en) * 1995-08-04 1997-02-14 Sumitomo Kinzoku Electro Device:Kk Multilayered circuit board with built-in capacitor
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2000077568A (en) * 1998-08-28 2000-03-14 Nippon Circuit Kogyo Kk Structure of printed wiring board and manufacture there
JP2001044591A (en) * 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd Wiring board
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08116174A (en) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd Circuit formation board and manufacture thereof
JPH0946047A (en) * 1995-08-04 1997-02-14 Sumitomo Kinzoku Electro Device:Kk Multilayered circuit board with built-in capacitor
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2000077568A (en) * 1998-08-28 2000-03-14 Nippon Circuit Kogyo Kk Structure of printed wiring board and manufacture there
JP2001044591A (en) * 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd Wiring board
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006521708A (en) * 2003-03-28 2006-09-21 ジョージア テック リサーチ コーポレーション The method for manufacturing a three-dimensional total organic interconnect structure

Similar Documents

Publication Publication Date Title
JP3910387B2 (en) The semiconductor package and its manufacturing method and a semiconductor device
JP3051700B2 (en) Manufacturing method of the head protection multilayer wiring board
JP3400677B2 (en) Methods of making capacitors embedded in printed circuit board printed circuit board having, and the embedded capacitors
EP1250033B1 (en) Printed circuit board and electronic component
US8130507B2 (en) Component built-in wiring board
JP3687041B2 (en) Wiring board, a method of manufacturing a wiring board, and semiconductor package
JP3112059B2 (en) Thin-film multilayer wiring board and its manufacturing method
EP1675447A1 (en) Devices comprising a power core and methods of making thereof
CN1856218B (en) Printed circuit board having embedded capacitors using hybrid material and method of manufacturing the same
US7821795B2 (en) Multilayer wiring board
US6184477B1 (en) Multi-layer circuit substrate having orthogonal grid ground and power planes
US6370013B1 (en) Electric element incorporating wiring board
US20080248596A1 (en) Method of making a circuitized substrate having at least one capacitor therein
JP3729092B2 (en) Conductive bonding material, a method for manufacturing a multilayer type printed wiring board and multilayer printed wiring board
JP4568718B2 (en) The method for manufacturing a three-dimensional total organic interconnect structure
JP4332533B2 (en) Capacitor-embedded printed circuit board and a manufacturing method thereof
JP3236818B2 (en) Manufacturing method of the head protection multilayer wiring board
US7701052B2 (en) Power core devices
JP3059568B2 (en) Method for manufacturing a multilayer printed circuit board
US7235745B2 (en) Resistor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said ciruitized substrate, and information handling system utilizing said ciruitized substrate
JP2007096258A (en) Wiring substrate and ceramic capacitor
US7025607B1 (en) Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate
CN101720165A (en) Component built-in wiring substrate and manufacturing method thereof
CN1806329A (en) Dielectric composite material comprising benzocyclobutene which contains a filler in order to decrease the coefficient of thermal expansion.
CN1822358B (en) Capacitor material for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized subs

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080314

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100810

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100812

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101012

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20101207