JP2003046242A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JP2003046242A
JP2003046242A JP2001226640A JP2001226640A JP2003046242A JP 2003046242 A JP2003046242 A JP 2003046242A JP 2001226640 A JP2001226640 A JP 2001226640A JP 2001226640 A JP2001226640 A JP 2001226640A JP 2003046242 A JP2003046242 A JP 2003046242A
Authority
JP
Japan
Prior art keywords
wiring board
conductor
multilayer wiring
conductors
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001226640A
Other languages
Japanese (ja)
Inventor
Tadashi Nagasawa
忠 長澤
Katsura Hayashi
桂 林
Isao Miyatani
勲 宮谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001226640A priority Critical patent/JP2003046242A/en
Publication of JP2003046242A publication Critical patent/JP2003046242A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To resolve the problem of generation of power supply noise caused by an inductance element of a through conductor in a high frequency region of 1 GHz or more in a multilayer wiring board with a built-in capacity element. SOLUTION: In a multilayer wiring board 4, insulation layers 1a to 1e consisting of an organic material are laminated and a wiring conductor 2 is formed in the surface of the insulation layers 1a to 1e, dielectric powder of 20 or more specific inductive capacity is incorporated in at least one layer of the insulation layers 1a to 1e, and a capacitor element A is formed by holding the wiring conductor 2 coated with the insulation layer 1c up and down as an electrode 2a in opposition. In the multilayer wiring board 4, the capacity element A is connected to a wiring conductor 3 via two through conductors 3 per one electrode 2a. It is possible to reduce power source noise generated by an inductance element of the through conductor 3 negligibly and to obtain the multilayer wiring board 4 which is excellent in noise reduction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、各種AV機器や家
電機器・通信機器・コンピュータやその周辺機器等の電
子機器に使用される多層配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer wiring board used for electronic equipment such as various kinds of AV equipment, home electric appliances, communication equipment, computers and peripheral equipments thereof.

【0002】[0002]

【従来の技術】従来、半導体素子等の能動部品や容量素
子・抵抗素子等の受動部品を多数搭載し、所定の電子回
路を構成するように成した混成集積回路等の電子部品モ
ジュールは、通常、アルミナ等のセラミックス材料から
成る絶縁基板の内部および表面にタングステン・モリブ
デン等の高融点金属粉末から成る複数の配線導体を形成
して成る配線基板の表面に、半導体素子や容量素子・抵
抗素子等を搭載取着するとともにこれらの電極を各配線
導体に接続することによって形成されている。
2. Description of the Related Art Conventionally, an electronic component module such as a hybrid integrated circuit, in which a large number of active components such as semiconductor elements and passive components such as capacitance elements and resistance elements are mounted to form a predetermined electronic circuit, is usually A semiconductor element, a capacitive element, a resistance element, etc. are formed on the surface of an insulating substrate made of a ceramic material such as alumina, and a plurality of wiring conductors made of a refractory metal powder such as tungsten and molybdenum formed inside and on the surface. Are mounted and attached, and these electrodes are connected to each wiring conductor.

【0003】しかしながら、このような配線基板は、配
線導体がタングステンやモリブデン等の高融点金属粉末
から成る導電ペーストをスクリーン印刷等の厚膜手法を
採用し所定パターンに印刷塗布することによって形成さ
れていることから、配線導体の微細化が困難で配線導体
を高密度に形成することができないという問題点を有し
ていた。
However, such a wiring substrate is formed by printing and applying a conductive paste whose wiring conductor is made of a refractory metal powder such as tungsten or molybdenum in a predetermined pattern by using a thick film technique such as screen printing. Therefore, there is a problem that it is difficult to miniaturize the wiring conductor and the wiring conductor cannot be formed at a high density.

【0004】また、従来の配線基板は、表面に半導体素
子等の能動部品や容量素子・抵抗素子等の受動部品を多
数搭載した場合、部品の搭載数に応じて基板が大型化し
てしまうという問題点も有していた。
Further, in the conventional wiring board, when a large number of active components such as semiconductor elements and passive components such as capacitance elements and resistance elements are mounted on the surface, the board becomes large according to the number of mounted components. He also had points.

【0005】このような問題点を解決するために、特開
平11-68319号公報には、複数の有機材料絶縁層と複数の
薄膜配線導体とを交互に多層に積層するとともに、高誘
電率粉末を含有する有機材料絶縁層とそれを挟む対向電
極を用いて内部に容量素子を形成した多層配線基板が提
案されている。
In order to solve such a problem, Japanese Unexamined Patent Publication No. 11-68319 discloses that a plurality of organic material insulating layers and a plurality of thin film wiring conductors are alternately laminated in a multi-layer structure, and a high dielectric constant powder is used. There has been proposed a multilayer wiring board in which a capacitive element is formed inside by using an organic material insulating layer containing OH and counter electrodes sandwiching the insulating layer.

【0006】この多層配線基板によれば、配線導体を薄
膜で形成したことから配線の微細化が可能となり、配線
を極めて高密度に形成することができ、また、多層配線
基板内部に容量素子を形成したことから多層配線基板に
半導体素子や容量素子・抵抗素子等の電子部品を搭載し
て混成集積回路装置等の多層配線基板を製作する場合
に、多層配線基板に別途、容量素子を多数実装する必要
はなく、その結果、多層配線基板に実装される部品の数
が減り小型化することができるというものである。な
お、内部に形成された容量素子の各電極は、内部に形成
された貫通導体を介して多層配線基板の表面および裏面
に形成された配線導体に電気的に接続されている。
According to this multilayer wiring board, since the wiring conductor is formed of a thin film, the wiring can be miniaturized, the wiring can be formed with extremely high density, and the capacitive element is provided inside the multilayer wiring board. Since electronic components such as semiconductor elements, capacitors and resistors are mounted on the multilayer wiring board to form a multilayer wiring board such as a hybrid integrated circuit device, many capacitive elements are separately mounted on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board can be reduced and the size can be reduced. The electrodes of the capacitive element formed inside are electrically connected to the wiring conductors formed on the front surface and the back surface of the multilayer wiring board through the penetrating conductors formed inside.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、近年、
通信速度の高速化に伴い通信機器等の電子機器類は周波
数が1GHz以上の高周波領域で使用されるようになっ
てきており、このような高周波領域では多層配線基板の
貫通導体のインダクタンス成分が大きくなり、△V=L
dI/dt(△Vは電源ノイズ、Lはインダクタンス、Iは
電流値、tは時間)で定義されるインダクタンス成分に
より発生する電源ノイズ△Vが無視できないほど大きく
なってしまい、通信機器等の電子機器類に誤動作を発生
させてしまうという問題点を有していた。
However, in recent years,
With the increase in communication speed, electronic devices such as communication devices have come to be used in a high frequency range of 1 GHz or higher. In such a high frequency range, the inductance component of the through conductor of the multilayer wiring board is large. And ΔV = L
The power supply noise ΔV generated by the inductance component defined by dI / dt (ΔV is power supply noise, L is inductance, I is current value, and t is time) becomes too large to be ignored, and electronic devices such as communication equipment There was a problem that malfunctions were caused in the devices.

【0008】本発明はかかる従来技術の問題点に鑑み案
出されたものであり、その目的は、1GHz以上の高周
波領域においてもノイズの発生が少なく、通信機器等の
電子機器類に誤動作を発生させてしまうことのない多層
配線基板を提供することにある。
The present invention has been devised in view of the problems of the prior art, and an object thereof is to generate a small amount of noise even in a high frequency region of 1 GHz or higher and to cause malfunctions in electronic equipment such as communication equipment. It is to provide a multi-layer wiring board that does not cause it.

【0009】[0009]

【課題を解決するための手段】本発明の多層配線基板
は、有機材料から成る複数の絶縁層を積層するとともに
これら絶縁層の表面に配線導体を形成し、絶縁層を挟ん
で上下に位置する配線導体間を絶縁層に形成された貫通
導体を介し電気的に接続して成る多層配線基板の少なく
とも一層に比誘電率が20以上の誘電体粉末を含有させる
とともに、この絶縁層の上下両面に被着した配線導体を
電極として対向挟持することによって容量素子を形成し
た多層配線基板において、容量素子が1つの電極につき
2個以上の貫通導体を介して配線導体と接続しているこ
とを特徴とするものである。
In a multilayer wiring board of the present invention, a plurality of insulating layers made of an organic material are laminated, wiring conductors are formed on the surfaces of these insulating layers, and the wiring conductors are located above and below the insulating layers. At least one layer of a multilayer wiring board formed by electrically connecting wiring conductors through a through conductor formed in an insulating layer contains a dielectric powder having a relative dielectric constant of 20 or more, and the upper and lower surfaces of this insulating layer are both In a multi-layer wiring board in which a capacitive element is formed by sandwiching the deposited wiring conductor as an electrode, the capacitive element is connected to the wiring conductor through two or more penetrating conductors per electrode. To do.

【0010】また、本発明の多層配線基板は、上記構成
において、容量素子の電極に接続する貫通導体の絶縁層
の厚み方向の断面形状が、絶縁層の上下面に位置する底
辺の長さが互いに異なる台形状であるとともに、隣接す
るものの上下の底辺の長さの大小関係が逆転しているこ
とを特徴とするものである。
In the multilayer wiring board of the present invention having the above structure, the cross-sectional shape in the thickness direction of the insulating layer of the through conductor connected to the electrode of the capacitive element is such that the lengths of the bases located on the upper and lower surfaces of the insulating layer are the same. It is characterized in that the shapes are different trapezoids, and the sizes of the lengths of the upper and lower bases of the adjacent ones are reversed.

【0011】本発明の多層配線基板によれば、容量素子
を1つの電極につき2個以上の貫通導体を介して配線導
体と接続させたことから、インダクタンス成分Lを小さ
なものとすることができ、その結果、1GHz以上の高
周波領域においてもノイズの発生が少なく、通信機器等
の電子機器類に誤動作を発生させてしまうことのない多
層配線基板とすることができる。
According to the multilayer wiring board of the present invention, since the capacitive element is connected to the wiring conductor through two or more penetrating conductors per electrode, the inductance component L can be made small. As a result, it is possible to obtain a multi-layer wiring board that generates less noise even in a high frequency region of 1 GHz or higher and does not cause malfunctions in electronic devices such as communication devices.

【0012】また、本発明の多層配線基板によれば、容
量素子の電極に接続する貫通導体の絶縁層の厚み方向に
おける断面形状を、絶縁層の上下面に位置する底辺の長
さが互いに異なる台形状としたことから、貫通孔に導電
性ペーストを充填して貫通導体を形成する際に、導電性
ペーストを貫通孔の底辺が長い方から充填することによ
り良好に充填することができ、その結果、導電性ペース
トの充填率を高め貫通導体の抵抗を小さくすることがで
きるとともにインダクタンス成分を小さくすることがで
きる。さらに、隣接する貫通導体の上下の底辺の長さの
大小関係を逆転させたことから、貫通導体を高密度に配
設することが可能となって単位面積当りに配設可能な貫
通導体の数を増やすことができるため容量素子の電極に
接続する貫通導体のインダクタンス成分を小さくするこ
とができ、その結果、ノイズ低減の効果が大きい多層配
線基板とすることができる。
Further, according to the multilayer wiring board of the present invention, the cross-sectional shape of the through conductor connected to the electrode of the capacitive element in the thickness direction of the insulating layer is such that the lengths of the bases located on the upper and lower surfaces of the insulating layer are different from each other. From the trapezoidal shape, when forming the through conductor by filling the through hole with the conductive paste, the conductive paste can be satisfactorily filled by filling the bottom of the through hole from the longer side. As a result, the filling factor of the conductive paste can be increased, the resistance of the through conductor can be reduced, and the inductance component can be reduced. Further, since the size relation of the lengths of the upper and lower bases of the adjacent through conductors is reversed, it is possible to arrange the through conductors at a high density, and the number of through conductors that can be arranged per unit area. Therefore, it is possible to reduce the inductance component of the through conductor connected to the electrode of the capacitive element, and as a result, it is possible to obtain a multilayer wiring board having a large noise reduction effect.

【0013】[0013]

【発明の実施の形態】次に本発明の多層配線基板を添付
の図面に基づいて詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Next, a multilayer wiring board of the present invention will be described in detail with reference to the accompanying drawings.

【0014】図1は、本発明の多層配線基板の実施の形
態の一例を示す断面図であり、この図の例では多層配線
基板に電子部品として半導体素子を搭載した場合を示し
ている。この図において1は複数の絶縁層から成る絶縁
基体、2は配線導体、3は貫通導体で、主にこれらで本
発明の多層配線基板4が構成されている。
FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention. In the example of this figure, a semiconductor element is mounted as an electronic component on the multilayer wiring board. In this figure, 1 is an insulating substrate composed of a plurality of insulating layers, 2 is a wiring conductor, 3 is a through conductor, and these mainly constitute the multilayer wiring board 4 of the present invention.

【0015】絶縁基体1は、本例では5層の有機材料か
ら成る絶縁層1a・1b・1c・1d・1eが積層されて構成され
ており、絶縁基体1表面には、半導体素子等の電子部品
5が半田等の接続材6を介して接続固定される。また、
本例では、絶縁基体1を構成する絶縁層1a・1b・1c・1d
・1eのうち少なくとも一層(この図の例では絶縁層1c)
は、比誘電率が20以上の誘電体粉末を含有しており、さ
らに絶縁層1cをその上下面に被着した配線導体2の一部
から成る電極2aで対向挟持することにより容量素子Aを
形成している。
In this example, the insulating substrate 1 is formed by laminating five layers of insulating layers 1a, 1b, 1c, 1d and 1e made of an organic material. On the surface of the insulating substrate 1, electrons such as semiconductor elements are formed. The component 5 is connected and fixed via a connecting material 6 such as solder. Also,
In this example, the insulating layers 1a, 1b, 1c, 1d constituting the insulating substrate 1
.At least one layer of 1e (insulating layer 1c in the example of this figure)
Contains a dielectric powder having a relative permittivity of 20 or more, and further sandwiches an insulating layer 1c with electrodes 2a made of a part of the wiring conductor 2 adhered to the upper and lower surfaces thereof to form a capacitive element A. Is forming.

【0016】絶縁基体1は、半導体素子等の電子部品5
を支持する支持体としての機能を有し、この絶縁基体1
を構成する絶縁層1a・1b・1c・1d・1eは有機材料により
形成されている。
The insulating substrate 1 is an electronic component 5 such as a semiconductor element.
This insulating base 1 has a function as a support for supporting
The insulating layers 1a, 1b, 1c, 1d, and 1e forming the are made of an organic material.

【0017】絶縁層1a・1b・1d・1eを形成する有機材料
としては、エポキシ樹脂・フェノール樹脂・ポリイミド
樹脂・アリル変性ポリフェニレンエーテル樹脂・ビスマ
レイミドトリアジン樹脂等の熱硬化性樹脂や液晶ポリエ
ステル・フッ素樹脂・ポリフェニレンエーテル樹脂・ポ
リエステル樹脂等の熱可塑性樹脂が用いられ、とりわ
け、絶縁層1a・1b・1d・1eを形成する際の作業性や絶縁
層1a・1b・1d・1eの絶縁特性・耐熱特性・機械的特性等
の観点からは、エポキシ樹脂やポリイミド樹脂・アリル
変性ポリフェニレンエーテル樹脂等の熱硬化性樹脂が好
ましい。
As the organic material for forming the insulating layers 1a, 1b, 1d, 1e, thermosetting resin such as epoxy resin, phenol resin, polyimide resin, allyl-modified polyphenylene ether resin, bismaleimide triazine resin, liquid crystal polyester, fluorine Thermoplastic resin such as resin, polyphenylene ether resin, polyester resin, etc. are used. Above all, workability when forming the insulating layers 1a, 1b, 1d, 1e and insulation characteristics and heat resistance of the insulating layers 1a, 1b, 1d, 1e Thermosetting resins such as epoxy resin, polyimide resin, and allyl-modified polyphenylene ether resin are preferable from the viewpoint of characteristics and mechanical characteristics.

【0018】また、絶縁層1a・1b・1d・1eには、熱膨張
係数を調整する目的および/または機械的強度を向上す
る目的で酸化アルミニウム・窒化珪素・窒化アルミニウ
ム・炭化珪素・酸化チタン・酸化バリウム・酸化ストロ
ンチウム・酸化ジルコニウム・酸化カルシウム・ゼオラ
イト等の無機絶縁粉末や繊維状ガラスを布状に織り込ん
だガラスクロスあるいは繊維状有機材料からなる不織布
等の充填材や、有機材料と無機絶縁粉末の親和性を高め
これらの接合性向上と絶縁基体1の機械的強度を高める
目的でシラン系カップリング剤・チタネート系カップリ
ング剤等のカップリング剤、熱安定性を改善する目的で
酸化防止剤、耐光性を改善する目的で紫外線吸収剤等の
光安定剤、難燃性を改善する目的でハロゲン系・リン酸
系の難燃性剤およびアンチモン系化合物・ホウ酸亜鉛・
メタホウ酸バリウム・酸化ジルコニウム等の難燃助剤、
潤滑性を改善する目的で高級脂肪酸・高級脂肪酸エステ
ル・高級脂肪酸金属塩・フルオロカーボン系界面活性剤
等の外部滑剤効果を有するもの等を1種以上、必要に応
じて添加してもよい。
The insulating layers 1a, 1b, 1d, 1e are made of aluminum oxide / silicon nitride / aluminum nitride / silicon carbide / titanium oxide for the purpose of adjusting the thermal expansion coefficient and / or improving the mechanical strength. Inorganic insulating powder such as barium oxide, strontium oxide, zirconium oxide, calcium oxide, zeolite, etc., filler such as glass cloth woven with cloth-like glass or non-woven fabric made of fibrous organic material, organic material and inorganic insulating powder Coupling agents such as silane-based coupling agents and titanate-based coupling agents for the purpose of improving the bonding property of the insulating substrate 1 and the mechanical strength of the insulating substrate 1, and an antioxidant for improving the thermal stability. , A light stabilizer such as an ultraviolet absorber for the purpose of improving light resistance, a halogen-based / phosphoric acid-based flame retardant for the purpose of improving flame retardancy, and Nchimon compounds, zinc borate,
Flame retardant aids such as barium metaborate and zirconium oxide,
For the purpose of improving lubricity, one or more kinds of substances having an external lubricant effect such as higher fatty acid, higher fatty acid ester, higher fatty acid metal salt, fluorocarbon-based surfactant and the like may be added if necessary.

【0019】このような絶縁基体1は、例えば粒径が0.
1〜15μm程度の酸化アルミニウム・窒化珪素・窒化ア
ルミニウム・炭化珪素・酸化チタン・酸化バリウム・酸
化ストロンチウム・酸化ジルコニウム・酸化カルシウム
等の無機絶縁粉末に、エポキシ樹脂・フェノール樹脂・
ポリイミド樹脂・ビスマレイミド樹脂・アリル変性ポリ
フェニレンエーテル樹脂等の熱硬化性樹脂または液晶ポ
リエステル・ポリフェニレンエーテル樹脂等の熱可塑性
樹脂と溶剤・可塑剤・分散剤等を添加混合して得たペー
ストを従来周知のドクタブレード法等のシート成型法を
採用してシート状となすことによって絶縁基体1におけ
る絶縁層1a・1b・1d・1eとなる複数の前駆体シートを得
るとともにこの絶縁層1a・1b・1d・1eとなる前駆体シー
トと後述する絶縁層1cとなる前駆体シートの各々に必要
に応じて穿設加工を従来周知のレーザ加工法を採用して
施し、これらの穿設加工が施された絶縁層1a・1b・1c・
1d・1eを所定の順に積層圧着し、最後に、積層圧着され
た絶縁層1a・1b・1c・1d・1eを温度が約100〜300℃で圧
力が0.4〜10MPaの条件で30分〜24時間ホットプレス
して加熱硬化させることによって製作される。
Such an insulating substrate 1 has, for example, a grain size of 0.
Inorganic insulating powder such as aluminum oxide, silicon nitride, aluminum nitride, silicon carbide, titanium oxide, barium oxide, strontium oxide, zirconium oxide, calcium oxide, etc. of 1 to 15 μm, epoxy resin, phenol resin,
Conventionally well-known pastes obtained by adding and mixing thermosetting resins such as polyimide resins, bismaleimide resins, allyl-modified polyphenylene ether resins, etc. or thermoplastic resins such as liquid crystal polyesters, polyphenylene ether resins, etc. with solvents, plasticizers, dispersants, etc. A plurality of precursor sheets to be the insulating layers 1a, 1b, 1d, and 1e in the insulating base 1 are obtained by adopting a sheet forming method such as the doctor blade method described above to obtain a plurality of insulating sheets 1a, 1b, 1d.・ The precursor sheet to be 1e and the precursor sheet to be the insulating layer 1c to be described later were subjected to perforation processing, if necessary, by employing a conventionally known laser processing method, and the perforation processing was performed. Insulation layer 1a ・ 1b ・ 1c ・
1d and 1e are laminated and pressure-bonded in a predetermined order, and finally, the laminated and pressure-bonded insulating layers 1a, 1b, 1c, 1d and 1e are heated for 30 minutes to 24 at a temperature of about 100 to 300 ° C and a pressure of 0.4 to 10 MPa. It is manufactured by hot pressing for a period of time and heat curing.

【0020】また、絶縁層1cは、有機材料から成るとと
もに比誘電率が20以上の誘電体粉末を10〜70体積%含有
しており、さらにその上下面に被着した後述する配線導
体2の一部から成る電極2aで対向挟持することにより容
量素子Aを形成している。
The insulating layer 1c is made of an organic material and contains 10 to 70% by volume of dielectric powder having a relative dielectric constant of 20 or more. The capacitive element A is formed by being sandwiched between the electrodes 2a, which are partially formed.

【0021】本発明の多層配線基板4によれば、このよ
うな容量素子Aを内部に形成したことから、多層配線基
板4に半導体素子や容量素子・抵抗器等の電子部品5を
混載して混成集積回路等の電子部品モジュールを製作す
る場合に、多層配線基板4に別途容量素子を多数実装す
る必要はなく、その結果、多層配線基板4に実装される
部品の数が減り、多層配線基板4や電子部品モジュール
を小型化することができる。
According to the multi-layer wiring board 4 of the present invention, since such a capacitive element A is formed inside, electronic components 5 such as semiconductor elements, capacitive elements and resistors are mixedly mounted on the multi-layer wiring board 4. When manufacturing an electronic component module such as a hybrid integrated circuit, it is not necessary to separately mount a large number of capacitive elements on the multilayer wiring board 4, and as a result, the number of components mounted on the multilayer wiring board 4 is reduced, resulting in a multilayer wiring board. 4 and the electronic component module can be downsized.

【0022】絶縁層1cに含有される比誘電率が20以上の
誘電体粉末としては、酸化チタンや酸化バリウム・酸化
ストロンチウム・酸化ジルコニウム・酸化カルシウム等
の無機系誘電体粉末やこれらの化合物・混合物、チタン
酸カリウムウィスカ・ホウ酸アルミニウムウィスカ・針
状酸化チタン・シリカアルミナ繊維・アルミナ繊維等の
繊維状高誘電体粉末・チタン酸バリウム・チタン酸カル
シウム・チタン酸ストロンチウム・スズ酸バリウム・ジ
ルコン酸バリウム・ジルコン酸ストロンチウム等の高誘
電体粉末が用いられ、その比誘電率が20(室温1MH
z)より小さいと、絶縁層1cの比誘電率が小さくなって
容量素子Aが実用に供することができないものとなって
しまう傾向がある。従って、絶縁層1cに含有される誘電
体粉末は、その比誘電率を20以上とすることが重要であ
る。
As the dielectric powder having a relative dielectric constant of 20 or more contained in the insulating layer 1c, inorganic dielectric powders such as titanium oxide, barium oxide, strontium oxide, zirconium oxide, calcium oxide, etc., and their compounds / mixtures are used. Fibrous high dielectric powder such as potassium titanate whisker, aluminum borate whisker, acicular titanium oxide, silica alumina fiber, alumina fiber, barium titanate, calcium titanate, strontium titanate, barium stannate, barium zirconate・ High dielectric powder such as strontium zirconate is used, and its dielectric constant is 20 (room temperature 1 MH
If it is smaller than z), the relative dielectric constant of the insulating layer 1c becomes small, and the capacitive element A tends to become unusable. Therefore, it is important that the dielectric powder contained in the insulating layer 1c has a relative dielectric constant of 20 or more.

【0023】また、誘電体粉末は、その含有量が絶縁層
1cに対して10体積%未満であると絶縁層1cの比誘電率が
小さくなり、実用に供することができる容量素子Aを形
成することが困難となる傾向があり、70体積%を超える
と有機材料の混練性が低下し絶縁層1cの製作が困難とな
る傾向がある。従って、誘電体粉末の含有率は10〜70体
積%の範囲とすることが好ましい。
Further, the content of the dielectric powder is an insulating layer.
If it is less than 10% by volume with respect to 1c, the relative dielectric constant of the insulating layer 1c tends to be small, and it tends to be difficult to form the capacitor A that can be put to practical use. The kneadability of the materials tends to decrease, and it tends to be difficult to manufacture the insulating layer 1c. Therefore, the content of the dielectric powder is preferably in the range of 10 to 70% by volume.

【0024】さらに、誘電体粉末の平均粒径は、0.1〜1
5μmの範囲であることが好ましく、平均粒径が0.1μm
未満であるとその比表面積が大きくなって誘電体粉末を
添加混合した混練物の粘度が高いものとなり、その結
果、絶縁層1cを形成する際に絶縁層1cの厚みが不均一と
なり、所定の均一厚みとすることが困難となる傾向があ
る。他方、平均粒径が15μmを超えると絶縁層1cの表面
に誘電体粉末による凹凸が形成され、容量素子Aが形成
される領域における比誘電率にバラツキを生じたり、絶
縁層1cに穿設加工を施す際の加工精度が低下してしまう
傾向がある。従って、絶縁層1cに含有される誘電体粉末
は、その平均粒径を0.1〜15μmの範囲とすることが好
ましく、好適には0.3〜10μmの範囲とすることが好ま
しい。
Further, the average particle diameter of the dielectric powder is 0.1 to 1
The average particle size is preferably 0.1 μm, preferably in the range of 5 μm.
If it is less than that, the specific surface area becomes large and the viscosity of the kneaded product in which the dielectric powder is added and mixed becomes high, and as a result, the thickness of the insulating layer 1c becomes uneven when the insulating layer 1c is formed, and the predetermined It tends to be difficult to obtain a uniform thickness. On the other hand, if the average particle diameter exceeds 15 μm, irregularities due to the dielectric powder are formed on the surface of the insulating layer 1c, the relative permittivity varies in the region where the capacitive element A is formed, or the insulating layer 1c is perforated. There is a tendency that the processing accuracy at the time of applying is reduced. Therefore, the dielectric powder contained in the insulating layer 1c preferably has an average particle size in the range of 0.1 to 15 μm, and more preferably 0.3 to 10 μm.

【0025】このような絶縁層1cと成る前駆体シート
は、例えば、平均粒径が0.1〜15μm程度の酸化チタン
やチタン酸ストロンチウム・チタン酸カルシウム・チタ
ン酸マグネシウム・チタン酸カリウム等の誘電体粉末
に、アリル変性ポリフェニレンエーテルやシアネート樹
脂等の有機材料と、適当な溶剤・可塑剤・分散剤等を添
加して得たペーストを従来周知のドクタブレード法等の
シート形成法を採用してシート状となすとともに、60〜
100℃の温度で5分〜3時間加熱することにより製作さ
れる。
The precursor sheet to be the insulating layer 1c is, for example, a dielectric powder such as titanium oxide or strontium titanate / calcium titanate / magnesium titanate / potassium titanate having an average particle size of about 0.1 to 15 μm. In addition, an organic material such as allyl-modified polyphenylene ether or cyanate resin, and a paste obtained by adding an appropriate solvent, plasticizer, dispersant, etc. are used to form a sheet using a conventionally known sheet forming method such as a doctor blade method. With eggplant, 60 ~
It is manufactured by heating at a temperature of 100 ° C. for 5 minutes to 3 hours.

【0026】また、絶縁層1a・1b・1c・1d・1eからなる
絶縁基体1には、絶縁層1a・1b・1c・1d・1e表面に配線
導体2が形成されているとともに配線導体2の一部から
成る電極2aで絶縁層1cを対向挟持して成る容量素子Aが
形成されている。さらに、絶縁層1a・1b・1c・1d・1eを
挟んで上下に位置する配線導体2間(電極2a間は除く)
を電気的に接続する貫通導体3が形成されている。
In addition, on the insulating substrate 1 composed of the insulating layers 1a, 1b, 1c, 1d, 1e, the wiring conductor 2 is formed on the surface of the insulating layers 1a, 1b, 1c, 1d, 1e and The capacitive element A is formed by sandwiching the insulating layer 1c between the electrodes 2a which are partially formed. Furthermore, between the wiring conductors 2 located above and below with the insulating layers 1a, 1b, 1c, 1d, 1e interposed (excluding between the electrodes 2a)
Through conductors 3 for electrically connecting the above are formed.

【0027】配線導体2および貫通導体3は、多層配線
基板4に実装される半導体素子等の電子部品5を外部電
気回路(図示せず)に電気的に接続する機能を有し、ま
た、配線導体2の一部は容量素子Aの電極2aとしての機
能も有する。
The wiring conductor 2 and the penetrating conductor 3 have a function of electrically connecting an electronic component 5 such as a semiconductor element mounted on the multilayer wiring board 4 to an external electric circuit (not shown). A part of the conductor 2 also has a function as the electrode 2a of the capacitive element A.

【0028】このような配線導体2は、絶縁層1a・1b・
1c・1d・1eとなる複数の前駆体シートの表面に、銅・銀
・金等の低抵抗金属を従来周知のスクリーン印刷法によ
り形成する方法やパターン形成した銅・金等から成る金
属箔を転写法等により被着形成する方法・無電解めっき
法・蒸着法・スパッタリング法等の薄膜形成方法を採用
することにより形成される。また、配線導体2は、1G
Hz以上の高周波領域の信号をより損失を低減して伝送
する目的で、従来周知のストリップ線路・マイクロスト
リップ線路・コプレーナ線路・誘電体導波管線路等の線
路で構成してもよい。
Such a wiring conductor 2 has insulating layers 1a, 1b,
On the surface of multiple precursor sheets 1c, 1d, and 1e, a low resistance metal such as copper, silver, and gold is formed by a conventionally known screen printing method, or a metal foil made of patterned copper, gold, etc. is formed. It is formed by adopting a thin film forming method such as a deposition method by a transfer method, an electroless plating method, a vapor deposition method, a sputtering method or the like. In addition, the wiring conductor 2 is 1G
For the purpose of transmitting a signal in a high frequency region of Hz or higher with a further reduced loss, a line such as a conventionally known strip line, microstrip line, coplanar line, or dielectric waveguide line may be used.

【0029】本発明の多層配線基板4では、上記のよう
に配線導体2を薄膜で形成したことから配線導体2の微
細化が可能となり、配線導体2を極めて高密度に形成す
ることができ、小型の多層配線基板4とすることができ
る。
In the multilayer wiring board 4 of the present invention, since the wiring conductor 2 is formed of a thin film as described above, the wiring conductor 2 can be miniaturized, and the wiring conductor 2 can be formed with extremely high density. It is possible to make a small multilayer wiring board 4.

【0030】なお、容量素子Aの容量値は、多層配線基
板4に要求される機能により決定され、含有される誘電
体粉末の比誘電率や含有量・絶縁層1cの厚み・容量素子
Aの電極2aの面積等を適宜決めることにより決定され
る。
The capacitance value of the capacitive element A is determined by the function required of the multilayer wiring board 4, and the relative permittivity and content of the dielectric powder contained, the thickness of the insulating layer 1c, the capacitance element A It is determined by appropriately determining the area and the like of the electrode 2a.

【0031】また、貫通導体3は、絶縁層1a・1b・1c・
1d・1eとなる複数の前駆体シートにレーザ加工法により
穿設加工を施し貫通孔を形成した後、この貫通孔に銅・
銀・金等から成る導電性ペーストをスクリーン印刷法等
により埋め込むことにより形成される。
The penetrating conductor 3 has insulating layers 1a, 1b, 1c,
After forming a through hole by laser drilling on multiple precursor sheets that will be 1d and 1e, copper.
It is formed by embedding a conductive paste made of silver, gold or the like by a screen printing method or the like.

【0032】そして本発明の多層配線基板4において
は、容量素子Aが1つの電極2aにつき2個以上の貫通導
体3を介して配線導体2と接続していることが好まし
く、また、このことが重要である。
In the multilayer wiring board 4 of the present invention, it is preferable that the capacitive element A is connected to the wiring conductor 2 via two or more penetrating conductors 3 for each electrode 2a. is important.

【0033】本発明の多層配線基板4によれば、容量素
子Aが1つの電極2aにつき2個以上の貫通導体3を介し
て配線導体2と接続していることから、例えば、多層配
線基板4に半導体素子5を搭載し、容量素子Aを形成す
る一方の電極2aを半導体素子5の電源端子に、他方の電
極2aを半導体素子5の接地端子に接続した場合、容量素
子Aの一方の電極2aに接続している貫通導体3の合計の
インダクタンスLの逆数が各貫通導体3のインダクタン
スlの逆数の和となり(インダクタンスlの貫通導体3
をn個形成した場合、合計のインダクタンスをLとする
と1/L=1/l1+1/l2+・・・+1/ln、すな
わちL=l/nとなる)、貫通導体3のインダクタンス
成分Lは、容量素子Aの電極2aに1個の貫通導体3を介
して配線導体2と接続させた時よりも小さなものとする
ことができ、その結果、1GHz以上の高周波領域にお
いてもノイズの発生が少なく、通信機器等の電子機器類
に誤動作を発生させてしまうことのない多層配線基板4
とすることができる。
According to the multilayer wiring board 4 of the present invention, since the capacitive element A is connected to the wiring conductor 2 through two or more penetrating conductors 3 for each electrode 2a, for example, the multilayer wiring board 4 is used. In the case where the semiconductor element 5 is mounted on, and one electrode 2a forming the capacitive element A is connected to the power supply terminal of the semiconductor element 5 and the other electrode 2a is connected to the ground terminal of the semiconductor element 5, one electrode of the capacitive element A is connected. The reciprocal of the total inductance L of the through conductors 3 connected to 2a is the sum of the reciprocals of the inductances 1 of the respective through conductors 3 (the through conductor 3 of the inductance 1
In the case where n are formed, assuming that the total inductance is L, 1 / L = 1 / l 1 + 1 / l 2 + ... + 1 / l n , that is, L = 1 / n), and the inductance of the through conductor 3 The component L can be smaller than that when the electrode 2a of the capacitive element A is connected to the wiring conductor 2 through one penetrating conductor 3, and as a result, noise components are generated even in a high frequency region of 1 GHz or higher. Multi-layer wiring board 4 that rarely occurs and does not cause malfunctions in electronic devices such as communication devices
Can be

【0034】また、本発明の多層配線基板4において
は、容量素子Aの電極2aに接続する貫通導体3の絶縁層
1b・1d の厚み方向における断面形状を、絶縁層1b・1d
の上下面に位置する底辺の長さが互いに異なる台形状と
することが好ましい。
Further, in the multilayer wiring board 4 of the present invention, the insulating layer of the through conductor 3 connected to the electrode 2a of the capacitive element A is formed.
Insulating layers 1b and 1d are
It is preferable that the bases located on the upper and lower surfaces have different trapezoidal shapes.

【0035】本発明の多層配線基板4によれば、容量素
子Aの電極2aに接続する貫通導体3の絶縁層1b・1d の
厚み方向における断面形状を、絶縁層1b・1d の上下面
に位置する底辺の長さが互いに異なる台形状としたこと
から、貫通孔に導電性ペーストを充填して貫通導体3を
形成する際に、導電性ペーストを貫通孔の底辺が長い方
から充填することにより良好に充填することができ、そ
の結果、導電性ペーストの充填率を高め貫通導体3の抵
抗を小さくすることができるとともにインダクタンス成
分を小さくすることができる。
According to the multilayer wiring board 4 of the present invention, the cross-sectional shape in the thickness direction of the insulating layers 1b and 1d of the through conductor 3 connected to the electrode 2a of the capacitive element A is located on the upper and lower surfaces of the insulating layers 1b and 1d. Since the bases having different lengths have different trapezoidal shapes, by filling the conductive paste into the through holes to form the through conductors 3, the conductive paste is filled from the longer bottom side. The filling can be excellently performed, and as a result, the filling rate of the conductive paste can be increased, the resistance of the through conductor 3 can be reduced, and the inductance component can be reduced.

【0036】さらに、本発明の多層配線基板4において
は、隣接する貫通導体3の上下の底辺の長さの大小関係
を逆転させて貫通導体3を形成することが好ましく、ま
た、このことが重要である。
Further, in the multilayer wiring board 4 of the present invention, it is preferable that the penetrating conductor 3 is formed by reversing the magnitude relationship between the lengths of the upper and lower bases of the adjacent penetrating conductors 3, and this is important. Is.

【0037】本発明の多層配線基板4においては、隣接
する貫通導体3の上下の底辺の長さの大小関係を逆転さ
せて貫通導体3を形成したことから、貫通導体3を高密
度に配設することが可能となって単位面積当りに配設可
能な貫通導体3の数を増やすことができるため、容量素
子Aの電極2aに接続する貫通導体3のインダクタンス成
分を小さくすることができ、その結果、ノイズ低減の効
果が大きい多層配線基板4とすることができる。
In the multilayer wiring board 4 of the present invention, since the through conductors 3 are formed by reversing the magnitude relation of the lengths of the upper and lower bases of the adjacent through conductors 3, the through conductors 3 are arranged at high density. Since it is possible to increase the number of through conductors 3 that can be arranged per unit area, it is possible to reduce the inductance component of the through conductor 3 connected to the electrode 2a of the capacitive element A. As a result, the multilayer wiring board 4 having a large noise reduction effect can be obtained.

【0038】このような貫通導体3は、レーザ加工法を
用いて、レーザのエネルギーを調整したり、絶縁層の厚
みを調整することにより、絶縁層1b・1dの厚み方向の断
面形状を所望の台形状とすることができる。そして、絶
縁層1b・1dの一方の表面側よりレーザ穿設加工を施して
貫通孔を形成するとともに導電性ペーストを埋め込んで
貫通導体3を形成した後、続けて絶縁層1b・1dの他方の
表面側よりレーザ穿設加工を施して貫通孔を形成すると
ともに導電性ペーストを埋め込み貫通導体3を形成する
ことにより隣接する貫通導体3の断面形状の上下の底辺
の長さの大小関係を逆転させた複数の貫通導体3を形成
することができる。
The through conductor 3 as described above has a desired cross-sectional shape in the thickness direction of the insulating layers 1b and 1d by adjusting the laser energy or the thickness of the insulating layer by using a laser processing method. It can be trapezoidal. Then, laser drilling is performed from one surface side of the insulating layers 1b and 1d to form a through hole and a conductive paste is embedded to form a through conductor 3, and then the other of the insulating layers 1b and 1d is continuously formed. Laser drilling is performed from the front surface side to form a through hole and a conductive paste is embedded to form a through conductor 3, thereby reversing the magnitude relationship between the lengths of the upper and lower bases of the cross sectional shape of the adjacent through conductors 3. It is possible to form a plurality of penetrating conductors 3.

【0039】なお、電極2aに接続する貫通導体3は、抵
抗値を低減して導電性を良好にするという観点からは、
直径が20μm以上であることが好ましい。また、貫通導
体3を高密度に配設するという観点からは、直径が250
μm以下であることが好ましい。従って、電極2aに接続
する貫通導体3の直径は20〜250μmであることが好ま
しい。
The through conductor 3 connected to the electrode 2a has a reduced resistance and a good conductivity.
The diameter is preferably 20 μm or more. From the viewpoint of arranging the through conductors 3 at a high density, the diameter is 250
It is preferably μm or less. Therefore, the diameter of the through conductor 3 connected to the electrode 2a is preferably 20 to 250 μm.

【0040】また、貫通導体3の断面形状の長い方の底
辺の長さが短い方の底辺の長さに対して1.2倍未満であ
ると、導電性ペーストの充填率が低下して貫通導体3の
抵抗値が増大しノイズの要因となる傾向がある。他方、
3倍を超えると、レーザ穿設加工後のデスミアが困難と
なり導通不良となる危険性が高い。従って、貫通導体3
の断面形状の長い方の底辺の長さは短い方の底辺の長さ
に対して1.2〜3倍であることが好ましい。
If the length of the longer bottom side of the through conductor 3 is less than 1.2 times the length of the shorter bottom side, the filling rate of the conductive paste decreases and the through conductor 3 The resistance value of increases and tends to cause noise. On the other hand,
When it exceeds 3 times, there is a high risk that desmear after laser drilling becomes difficult and conduction failure occurs. Therefore, the through conductor 3
The length of the longer bottom side of the cross-sectional shape is preferably 1.2 to 3 times the length of the shorter bottom side.

【0041】さらに、配線導体2・貫通導体3は、その
露出する表面にニッケル・金等の耐蝕性に優れ、かつ良
導電性の金属をめっき法により1.0〜20μmの厚みに被
着させておくと配線導体2・貫通導体3の酸化腐蝕を有
効に防止することができるとともに配線導体2・貫通導
体3と半導体素子等の電子部品5や外部電気回路の配線
導体(図示せず)とを強固に電気的に接続させることが
できる。従って、配線導体2・貫通導体3の露出する表
面には、ニッケルや金等の耐蝕性に優れ、かつ良導電性
の金属をめっき法により1.0〜20μmの厚みに被着させ
ておくことが好ましい。
Further, the wiring conductor 2 and the through conductor 3 are formed by depositing nickel or gold, which has excellent corrosion resistance and a metal of good conductivity, on the exposed surface to a thickness of 1.0 to 20 μm by a plating method. And the wiring conductor 2 and the through conductor 3 can be effectively prevented from being oxidized and corroded, and the wiring conductor 2 and the through conductor 3 and the electronic component 5 such as a semiconductor element or the wiring conductor (not shown) of the external electric circuit can be firmly fixed. Can be electrically connected to. Therefore, it is preferable that the exposed surfaces of the wiring conductors 2 and the through conductors 3 are coated with a metal having excellent corrosion resistance such as nickel or gold and having a good conductivity in a thickness of 1.0 to 20 μm by a plating method. .

【0042】かくして本発明の多層配線基板4によれ
ば、容量素子Aを1つの電極2aにつき2個以上の貫通導
体3を介して配線導体2と接続させたことから、インダ
クタンス成分Lを小さなものとすることができ、その結
果、1GHz以上の高周波領域においてもノイズの発生
が少なく、通信機器等の電子機器類に誤動作を発生させ
てしまうことのない多層配線基板4とすることができ
る。また、容量素子Aの電極2aに接続する貫通導体3の
絶縁層1b・1dの厚み方向における断面形状を、絶縁層1b
・1dの上下面に位置する底辺の長さが互いに異なる台形
状としたことから、貫通孔に導電性ペーストを充填して
貫通導体3を形成する際に、導電性ペーストを貫通孔の
底辺が長い方から充填することにより良好に充填するこ
とができ、その結果、導電性ペーストの充填率を高め貫
通導体3の抵抗を小さくすることができるとともにイン
ダクタンス成分を小さくすることができる。さらに、隣
接する貫通導体3の上下の底辺の長さの大小関係を逆転
させたことから、貫通導体3を高密度に配設することが
可能となって単位面積当りに配設可能な貫通導体3の数
を増やすことができるため容量素子Aの電極に接続する
貫通導体のインダクタンス成分を小さくすることがで
き、その結果、ノイズ低減の効果が大きい多層配線基板
4とすることができる。
Thus, according to the multilayer wiring board 4 of the present invention, since the capacitive element A is connected to the wiring conductor 2 via two or more penetrating conductors 3 for each electrode 2a, the inductance component L is small. As a result, it is possible to obtain the multilayer wiring board 4 in which noise is hardly generated even in a high frequency region of 1 GHz or higher and a malfunction does not occur in electronic devices such as communication devices. Moreover, the cross-sectional shape in the thickness direction of the insulating layers 1b and 1d of the through conductor 3 connected to the electrode 2a of the capacitive element A is shown in FIG.
Since the bases located on the upper and lower surfaces of 1d have trapezoidal shapes having different lengths, when the conductive paste is filled in the through holes to form the through conductors 3, the conductive paste is not It is possible to satisfactorily fill by filling from the longer side. As a result, the filling rate of the conductive paste can be increased, the resistance of the through conductor 3 can be reduced, and the inductance component can be reduced. Further, since the magnitude relation between the lengths of the upper and lower bases of the adjacent through conductors 3 is reversed, the through conductors 3 can be arranged at a high density, and the through conductors can be arranged per unit area. Since the number of 3 can be increased, the inductance component of the through conductor connected to the electrode of the capacitive element A can be reduced, and as a result, the multilayer wiring board 4 having a large noise reduction effect can be obtained.

【0043】なお、本発明の多層配線基板4は上述の実
施例に限定されるものではなく、本発明の要旨を逸脱し
ない範囲であれば種々の変更は可能であり、例えば、上
述の実施例では5層の絶縁層1a・1b・1c・1d・1eを積層
することによって絶縁基体1を製作したが、3層や4
層、あるいは6層以上の絶縁層を積層して絶縁基体1を
製作してもよい。また、上述の実施例では誘電体粉末を
含む絶縁層を1層としたが、2層(連続層を含む)以上
としてもよい。
The multilayer wiring board 4 of the present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the scope of the present invention. Then, the insulating substrate 1 was manufactured by stacking 5 layers of insulating layers 1a, 1b, 1c, 1d, and 1e.
The insulating substrate 1 may be manufactured by stacking layers or 6 or more insulating layers. Further, in the above-mentioned embodiment, the insulating layer containing the dielectric powder is one layer, but it may be two layers (including a continuous layer) or more.

【0044】また、上述の実施例では容量素子Aは、電
極2aが誘電体粉末を含む絶縁層1cを1層挟持して形成さ
れているが、2層以上挟持して形成されていてもよい。
In the above embodiment, the capacitive element A is formed by sandwiching the insulating layer 1c containing the dielectric powder as the electrode 2a by one layer, but may be formed by sandwiching two or more layers. .

【0045】[0045]

【発明の効果】本発明の多層配線基板によれば、容量素
子を1つの電極につき2個以上の貫通導体を介して配線
導体と接続させたことから、インダクタンス成分Lを小
さなものとすることができ、その結果、1GHz以上の
高周波領域においてもノイズの発生が少なく、通信機器
等の電子機器類に誤動作を発生させてしまうことのない
多層配線基板とすることができる。
According to the multilayer wiring board of the present invention, since the capacitive element is connected to the wiring conductor through two or more penetrating conductors per electrode, the inductance component L can be made small. As a result, it is possible to obtain a multi-layer wiring board that hardly generates noise even in a high frequency region of 1 GHz or more and does not cause malfunctions in electronic devices such as communication devices.

【0046】また、本発明の多層配線基板によれば、容
量素子の電極に接続する貫通導体の絶縁層の厚み方向に
おける断面形状を、絶縁層の上下面に位置する底辺の長
さが互いに異なる台形状としたことから、貫通孔に導電
性ペーストを充填して貫通導体を形成する際に、導電性
ペーストを貫通孔の底辺が長い方から充填することによ
り良好に充填することができ、その結果、導電性ペース
トの充填率を高め貫通導体の抵抗を小さくすることがで
きるとともにインダクタンス成分を小さくすることがで
きる。さらに、隣接する貫通導体の上下の底辺の長さの
大小関係を逆転させたことから、貫通導体を高密度に配
設することが可能となって単位面積当りに配設可能な貫
通導体の数を増やすことができるため容量素子の電極に
接続する貫通導体のインダクタンス成分を小さくするこ
とができ、その結果、ノイズ低減の効果が大きい多層配
線基板とすることができる。
Further, according to the multilayer wiring board of the present invention, the cross-sectional shape of the through conductor connected to the electrode of the capacitive element in the thickness direction of the insulating layer is different in the lengths of the bases located on the upper and lower surfaces of the insulating layer from each other. From the trapezoidal shape, when forming the through conductor by filling the through hole with the conductive paste, the conductive paste can be satisfactorily filled by filling the bottom of the through hole from the longer side. As a result, the filling factor of the conductive paste can be increased, the resistance of the through conductor can be reduced, and the inductance component can be reduced. Further, since the size relation of the lengths of the upper and lower bases of the adjacent through conductors is reversed, it is possible to arrange the through conductors at a high density, and the number of through conductors that can be arranged per unit area. Therefore, it is possible to reduce the inductance component of the through conductor connected to the electrode of the capacitive element, and as a result, it is possible to obtain a multilayer wiring board having a large noise reduction effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の多層配線基板の実施の一例を示す断面
図であり、電子部品を搭載した例である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board of the present invention, which is an example in which electronic parts are mounted.

【符号の説明】[Explanation of symbols]

1・・・・・・・・・絶縁基体 1a・1b・1d・1e ・・絶縁層 1c・・・・・・・・・絶縁層(誘電体粉末含有絶縁層) 2・・・・・・・・・配線導体 2a・・・・・・・・・電極 3・・・・・・・・・貫通導体 4・・・・・・・・・多層配線基板 A・・・・・・・・・容量素子 1 ... Insulating substrate 1a ・ 1b ・ 1d ・ 1e ・ ・ Insulating layer Insulation layer (insulation layer containing dielectric powder) 2 ・ ・ ・ ・ ・ ・ Wiring conductor 2a ・ ・ ・ ・ ・ ・ Electrodes 3 ・ ・ ・ ・ ・ ・ Through conductor 4 ... Multi-layer wiring board A ... Capacitive element

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 BB02 BB03 BB12 BB13 BB14 CC22 CC25 CD21 CD32 GG11 5E346 AA12 AA13 AA43 CC04 CC05 CC08 CC09 CC10 CC32 CC38 CC39 DD02 DD17 DD23 EE04 FF18 GG15 GG28 HH02 HH06   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5E317 AA24 BB02 BB03 BB12 BB13                       BB14 CC22 CC25 CD21 CD32                       GG11                 5E346 AA12 AA13 AA43 CC04 CC05                       CC08 CC09 CC10 CC32 CC38                       CC39 DD02 DD17 DD23 EE04                       FF18 GG15 GG28 HH02 HH06

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 有機材料から成る複数の絶縁層を積層す
るとともにこれら絶縁層の表面に配線導体を形成し、前
記絶縁層を挟んで上下に位置する前記配線導体間を前記
絶縁層に形成された貫通導体を介し電気的に接続して成
る多層配線基板の少なくとも一層に比誘電率が20以上
の誘電体粉末を含有させるとともに、この絶縁層の上下
両面に被着した前記配線導体を電極として対向挟持する
ことによって容量素子を形成した多層配線基板におい
て、前記容量素子は1つの前記電極につき2個以上の前
記貫通導体を介して前記配線導体と接続していることを
特徴とする多層配線基板。
1. A plurality of insulating layers made of an organic material are laminated, wiring conductors are formed on the surfaces of these insulating layers, and the insulating layers are formed between the wiring conductors located above and below the insulating layer. At least one layer of a multilayer wiring board electrically connected via through conductors contains dielectric powder having a relative dielectric constant of 20 or more, and the wiring conductors adhered on the upper and lower surfaces of this insulating layer are used as electrodes. In a multilayer wiring board in which a capacitive element is formed by sandwiching it between the capacitive elements, the capacitive element is connected to the wiring conductor via two or more penetrating conductors for each electrode. .
【請求項2】 前記電極に接続する前記貫通導体の前記
絶縁層の厚み方向の断面形状は、前記絶縁層の上下面に
位置する底辺の長さが互いに異なる台形状であるととも
に、隣接するものの上下の底辺の長さの大小関係が逆転
していることを特徴とする請求項1記載の多層配線基
板。
2. The cross-sectional shape in the thickness direction of the insulating layer of the through conductor connected to the electrode is trapezoidal in which the lengths of the bottom sides located on the upper and lower surfaces of the insulating layer are different from each other, and the adjacent ones are adjacent to each other. 2. The multilayer wiring board according to claim 1, wherein the magnitude relationships of the lengths of the upper and lower bases are reversed.
JP2001226640A 2001-07-26 2001-07-26 Multilayer wiring board Pending JP2003046242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001226640A JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001226640A JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JP2003046242A true JP2003046242A (en) 2003-02-14

Family

ID=19059416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001226640A Pending JP2003046242A (en) 2001-07-26 2001-07-26 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2003046242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006521708A (en) * 2003-03-28 2006-09-21 ジョージア テック リサーチ コーポレーション Method for making a three-dimensional all-organic interconnect structure
US12073988B2 (en) 2020-12-10 2024-08-27 Samsung Electro-Mechanics Co., Ltd. Coil component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08116174A (en) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd Circuit formation board and manufacture thereof
JPH0946047A (en) * 1995-08-04 1997-02-14 Sumitomo Kinzoku Electro Device:Kk Multilayered circuit board with built-in capacitor
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2000077568A (en) * 1998-08-28 2000-03-14 Nippon Circuit Kogyo Kk Structure of printed wiring board and manufacture there
JP2001044591A (en) * 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd Wiring board
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08116174A (en) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd Circuit formation board and manufacture thereof
JPH0946047A (en) * 1995-08-04 1997-02-14 Sumitomo Kinzoku Electro Device:Kk Multilayered circuit board with built-in capacitor
JPH1093247A (en) * 1996-09-18 1998-04-10 Kyocera Corp Multilayer wiring board
JP2000077568A (en) * 1998-08-28 2000-03-14 Nippon Circuit Kogyo Kk Structure of printed wiring board and manufacture there
JP2001044591A (en) * 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd Wiring board
JP2001068858A (en) * 1999-08-27 2001-03-16 Shinko Electric Ind Co Ltd Multilayer wiring board, manufacture thereof, and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006521708A (en) * 2003-03-28 2006-09-21 ジョージア テック リサーチ コーポレーション Method for making a three-dimensional all-organic interconnect structure
US12073988B2 (en) 2020-12-10 2024-08-27 Samsung Electro-Mechanics Co., Ltd. Coil component

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