JP2003037457A - Amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize an electronic device and reduce cost thereof by dispensing a by-pass capacitor, and to enhance the stability and reliability in circuit operations. SOLUTION: In a differential amplifier at a first step, one differential input end is connected to a resistor R1 for both matching and biasing, and further, another differential input end is connected to a resistor R2 for biasing. By making these resistors R1 and R2 grounded directly in a chip, the gates of pMOS transistors Q11 , Q12 can be applied with self bias, so that the by-pass capacitor of a large capacity can be dispensed with using outside of the chip, in order to restrict reduction in gain or in generation of noise, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and is particularly suitable for use in a differential amplifier circuit applied to a wireless communication device or the like.

[0002]

2. Description of the Related Art In recent years, in electronic equipment having a wireless communication function such as a radio receiver, a mobile phone, a cordless phone, a television receiver, a car navigation system, and a game machine, the degree of integration of a semiconductor device used has been increased. , More and more circuits are being integrated on one chip.

In general, the above-mentioned electronic equipment uses an amplifier circuit which amplifies and outputs an input signal in order to reproduce a received minute input signal into a rectangular wave. Depending on the application, a differential-type multistage amplifier circuit in which a plurality of differential amplifiers are cascade-connected to obtain a high gain may be used. Conventionally, an IC in which these amplifier circuits are integrated on one chip together with other circuits is also provided.

FIG. 4 is a diagram showing a partial configuration example of an IC constituting an amplifier and its peripheral circuits. This FIG. 4 shows a MOS
It shows an example of the configuration of the circuit. In FIG.
100 is an IF (Intermediate Frequency) filter, 2
00 is a semiconductor chip that constitutes an amplifier. The IF filter 100 and the semiconductor chip 200 are the semiconductor chip 20.
It is electrically connected via the pad 11 of 0. IF
As the filter 100, for example, a ceramic filter or a crystal filter is used. These are elements that are sensitive to signal sources or load impedances.

In this example, the semiconductor chip 200 includes one stage of differential amplifier. This differential amplifier comprises a differential pair consisting of two resistors R ₁₁ and R ₁₂ , two pMOS transistors Q ₁₁ and Q ₁₂ and a constant current circuit 13, a resistor R ₁ , and a bias circuit 14. There is.

In the differential pair, the sources of the two transistors Q ₁₁ and Q ₁₂ are connected to each other in common, and one end of the constant current circuit 13 is connected to these common sources. The other end of the constant current circuit 13 is connected to the power supply VDD. The drains of the transistors Q ₁₁ and Q ₁₂ are grounded via resistors R ₁₁ and R ₁₂ , respectively.
A signal to be amplified is input to the gates of the transistors Q ₁₁ and Q ₁₂ .

The resistor R ₁ inserted between the IF filter 100 and the amplifier (specifically, between the pad 11 of the semiconductor chip 200 and one pMOS transistor Q ₁₁ forming a differential pair) has an impedance of Resistors for matching and bias application. Since the output impedance of the IF filter 100 and the input impedance of the amplifier are different, if they are connected as they are, the band characteristic is deteriorated due to impedance mismatch. Therefore, it is necessary to achieve impedance matching with the resistor R ₁ .

The bias circuit 14 is composed of resistors for supplying gate bias to the pMOS transistors Q ₁₁ and Q ₁₂ . The bias circuit 14 is provided to operate the pMOS transistors Q ₁₁ and Q ₁₂ .

A bypass capacitor C is connected to the bias circuit 14 and the resistor R ₁ via the pad 12 outside the semiconductor chip 200. The bypass capacitor C is necessary for suppressing a decrease in gain and noise generation.

[0010]

When a ceramic filter is used as the IF filter 100, the value of the resistor R ₁ is 330Ω or 2 for impedance matching.
It is necessary to select a value near KΩ. Further, the impedance of the bypass capacitor C needs to be sufficiently smaller than the value of the resistor R ₁ in order to maintain the matching condition. Therefore, it is necessary to use a large capacity bypass capacitor C.

The large-capacity bypass capacitor C itself has a large volume and cannot be integrated in the semiconductor chip 200. Therefore, conventionally, the bypass capacitor C has been externally connected to the semiconductor chip 200. Therefore, there is a problem that it is difficult to downsize an electronic device using the semiconductor chip 200 and the bypass capacitor C and the cost is increased.

Further, since it is necessary to provide the pad 12 dedicated to the bypass capacitor C on the semiconductor chip 200, the chip size becomes large accordingly. In addition, there is a problem in that the defect rate may increase due to the increase in the number of pads, and the reliability of the semiconductor chip 200 may deteriorate.

Furthermore, since the bypass capacitor C is externally attached to the semiconductor chip 200, the semiconductor chip 2
00 and bypass capacitor C must be connected by a bonding wire or the like. In this case, the circuit operation of the semiconductor chip 200 depends on where the bypass capacitor C whose size is significantly larger than that of the semiconductor chip 200 is arranged around the semiconductor chip 200, how to connect to the ground, and the like. There was also the problem of being unstable.

Further, the presence of the bypass capacitor C and the resistor R ₁ provided on one of the differential pairs destroys the impedance balance of the differential amplifier. Therefore, if noise occurs on the substrate or the like in the semiconductor chip 200, it is input to the pMOS transistor Q ₁₁ side and amplified, and there is also a problem that noise characteristics deteriorate.

The present invention has been made to solve such a problem. By eliminating the bypass capacitor C, the electronic device can be downsized and the cost can be reduced, and the circuit operation can be stabilized. It is also intended to improve reliability and noise characteristics.

[0016]

An amplifier circuit of the present invention is connected to a differential amplifier that amplifies and outputs an input signal and one differential input terminal of the differential amplifier to match impedance. A matching / bias resistor that applies a bias to the one differential input terminal, and a bias resistor that is connected to the other differential input terminal of the differential amplifier and applies a bias to the other differential input terminal It is characterized by that.

According to another aspect of the present invention, the matching / bias resistance and the bias resistance are connected between the gate and the ground of a pMOS transistor forming the differential amplifier.

In another aspect of the present invention, the matching / bias resistance and the bias resistance are connected between the gate of an nMOS transistor forming the differential amplifier and a power supply.

According to another aspect of the present invention, the value of the matching / bias resistance and the value of the bias resistance are equal to each other.

In another aspect of the present invention, a differential amplifier for amplifying and outputting an input signal and one differential input terminal of the differential amplifier are connected to each other for impedance matching and for the one differential terminal. A plurality of matching / bias resistors for applying a bias to the input end, and a plurality of bias resistors connected to the other differential input end of the differential amplifier for applying a bias to the other differential input end, The plurality of matching / bias resistors are connected in series between the power supply and the ground, the one differential input terminal is connected to the intermediate node, and the plurality of bias / combining resistors are connected between the power supply and the ground. Is connected in series, and the other differential input terminal is connected to the intermediate node thereof.

According to another aspect of the present invention, a combined resistance value of the plurality of matching / bias resistors connected to the one differential input terminal and the plurality of resistance values connected to the other differential input terminal. It is characterized in that the combined resistance value of the bias resistors is equal to each other.

In another aspect of the present invention, a difference between a differential amplifier circuit in which a differential amplifier for amplifying an input signal from the previous stage and outputting the amplified signal to the next stage is connected in multiple stages and a first stage in the differential amplifier circuit is provided. A matching / bias resistor connected to one of the differential input terminals of the dynamic amplifier for matching impedance and biasing the one differential input terminal, and the other differential input terminal of the first stage differential amplifier. And a bias resistor connected to the other differential input terminal for applying a bias to the other differential input terminal.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a diagram showing a first embodiment, which is an IC configuring an amplifier.
FIG. 4 is a diagram showing a partial configuration example of a peripheral circuit and its peripheral circuit.

Although the example of FIG. 1 shows the configuration of a multistage amplifier circuit in which differential amplifiers for amplifying an input signal from the previous stage and outputting the amplified signal to the next stage are connected in multiple stages, the same as in FIG. The configuration may be such that only one stage of differential amplifier is provided. In FIG. 1, the same components as those shown in FIG. 4 are designated by the same reference numerals.

As shown in FIG. 1, the IF filter 100 and the semiconductor chip 1 of this embodiment are electrically connected via a pad 11. The amplifier in the semiconductor chip 1 is
Several differential amplifiers are connected in multiple stages from the input side to the output side. The differential amplifier in each stage has two resistors R
_i1 , R _i2 (i = 1, 2, ...) And two pMOS transistors Q _i1 , Q _i2 (i = 1, 2, ...) And constant current circuit 13 _-i
(I = 1, 2, ...).

In each differential pair, the sources of the two transistors Q _i1 and Q _i2 are commonly connected to each other,
One _ends of the constant current circuits 13 _-i are connected to these common sources, respectively. The other end of each constant current circuit 13 _-i is connected to the power supply VDD. In addition, each transistor Q _i1 ,
The drain of Q _i2 is grounded via resistors R _i1 and R _i2 , respectively.

The gates of the transistors Q _i1 and Q _i2 are _supplied with the output signals from the differential amplifiers in the preceding stages except the differential amplifier in the initial stage. A signal to be amplified is input to the gates of the transistors Q ₁₁ and Q ₁₂ of the first stage differential amplifier. Capacitors C1 and C2 connected to the output signal lines of the differential amplifier are DC blocking capacitors.

In the amplifier circuit thus constructed,
Transistor Q of the first stage differential amplifier ₁₁, Q₁₂On the base of
The input signal is output after being amplified by a specified level.
It The signal amplified and output here is the differential of the second stage.
Amplifier transistor Q_{twenty one}, Q_{twenty two}Entered in the base of
It is further amplified and output by the second stage differential amplifier.
Be done. In the same manner, the signal is output by the differential amplifier at each stage.
Are sequentially amplified. As a result, the first stage differential amplification
The amplitude of the input signal to the
The output signal amplified to the specified level is finally obtained.
Be done.

One differential input terminal of the first stage differential amplifier (specifically, pMO forming the first stage differential amplifier)
The gate side of the S-transistor Q ₁₁ serves both for matching (matching) the impedance seen from the pad 11 to the left and the impedance seen to the right, and for providing a bias voltage to the gate of the pMOS transistor Q _11. A resistor R ₁ is connected. In this embodiment, the resistance R
₁ is connected between the gate of the pMOS transistor Q ₁₁ and the ground, and is directly grounded within the chip without passing through a bypass capacitor outside the chip.

The other differential input terminal of the first stage differential amplifier (specifically, the gate side of the pMOS transistor Q ₁₂ forming the first stage differential amplifier) is connected to the pMOS.
A bias resistor R ₂ for applying a bias voltage is connected to the gate of the transistor Q ₁₂ . In the present embodiment, the resistor R ₂ is connected between the gate of the pMOS transistor Q ₁₂ and the ground, and is directly grounded in the chip without a bypass capacitor outside the chip.

When the semiconductor chip 1 is used in the low frequency region, the value of the resistor R ₂ is arbitrary. In extreme cases,
The gate of the pMOS transistor Q ₁₂ and the ground may be short-circuited. In the case of a MOS transistor, the resistance R
Regardless of the value of _2, the gate bias voltage Va2 of the pMOS transistor Q ₁₂ is because a constant value.

On the other hand, when the semiconductor chip 1 is used in a high frequency range, it is preferable that the value of the resistor R ₂ be equal to the value of the resistor R ₁ . When used in a high frequency region, the distributed capacitance generated between the gate and drain of each of the transistors Q ₁₁ and Q ₁₂ cannot be ignored. Therefore, R ₁
If you do not set = R ₂ , the differential balance will be lost,
This is because the differential amplifier will not operate correctly.

Each pM constituting the second and subsequent differential amplifiers
Bias resistors R _b1 , R _b2 , R _b3 , and R _b4 are connected to the gates of the OS transistors Q _i1 and Q _i2 (i = 2, 3, ...).

In the case of the above configuration, the gate of the pMOS transistor Q ₁₁ has Va1 = VDD-Vs-Vgs1.
(Vs is the voltage applied to the constant current circuit 13 _-1 , Vgs1 is pM
It is self-biased to a voltage which is the gate-source voltage of the OS transistor Q ₁₁ . The gate of the pMOS transistor Q ₁₂ is, Va2 = VDD-Vs-Vgs2 (Vgs2 the gate of the pMOS transistor Q ₁₂ - source voltage) is self-biased to become voltage.

As a result, it is not necessary to use a large-capacity bypass capacitor in order to suppress a decrease in transistor gain and noise generation. Therefore, it is possible to reduce a large-scale bypass capacitor connected to the outside of the semiconductor chip 1 to reduce the size and cost of the electronic device.

Further, since it is not necessary to provide a pad dedicated to the bypass capacitor on the semiconductor chip 1, the number of pads can be reduced. As a result, the chip size can be reduced, and the defect rate can be reduced to improve the reliability of the semiconductor chip 1. Further, since the processing can be performed in one chip, there is an advantage that the signal flow can flow in one direction and the circuit operation can be stabilized.

Further, according to this embodiment, the gate-source voltage Vgs1 of the pMOS transistor Q ₁₁ and pMO
The gate of the S transistor Q ₁₂ - almost equal to the source voltage Vgs2, the gate bias voltage Va1, Va2 of the transistors Q _11, Q ₁₂ is substantially the same value. Moreover, M
When the OS circuit constitutes the differential pair, its input impedance is very large, and therefore the differential balance is hardly lost. Therefore, the linearity of the amplifier circuit can be favorably maintained, and the noise of the substrate can be canceled by the complete differential to improve the noise characteristic.

In the case where the amplifier circuit as shown in FIG. 1 is composed of bipolar transistors, the base current flows through the transistors, so that the value of the resistance R ₂ cannot be ignored due to the characteristics. Therefore, in order to prevent the differential balance from being lost, the resistors R ₁ and R ₁ connected to both input terminals of the differential pair,
R ₂ must have the same value as each other.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing the second embodiment, and is a diagram showing a partial configuration example of an IC that constitutes an amplifier and its peripheral circuits. In FIG. 2, the same components as those shown in FIG. 1 are designated by the same reference numerals, and the duplicated description will be omitted here.

As shown in FIG. 2, one differential input terminal (specifically, one of the differential input terminals in the first stage differential amplifier constituting the amplifier is
PMOS transistor Q forming the first stage differential amplifier
_On the gate side of ₁₁ ), a resistor R ₃ is used both for matching the impedance seen from the pad 11 to the left and the impedance seen to the right and for biasing the gate of the pMOS transistor Q ₁₁ for biasing. , R ₄ are connected. For impedance matching, the combined resistance value of the resistors R ₃ and R ₄ must be equal to the resistance value of the resistor R ₁ shown in FIG.

In the present embodiment, the resistors R ₃ and R ₄ are connected in series between the power supply VDD and the ground, and the intermediate node thereof is connected to the gate of the pMOS transistor Q ₁₁ . That is, the resistor R ₃ is connected between the gate of the pMOS transistor Q ₁₁ and the power supply VDD. The resistor R ₄ is connected between the gate of the pMOS transistor Q ₁₁ and the ground and is directly grounded in the chip without passing through a bypass capacitor outside the chip.

Further, the pMOS is connected to the other differential input terminal of the first stage differential amplifier (specifically, the gate side of the pMOS transistor Q ₁₂ which constitutes the first stage differential amplifier).
Bias resistors R ₅ and R ₆ for applying a bias to the gate of the transistor Q ₁₂ are connected.

In the present embodiment, the resistors R ₅ and R ₆ are connected in series between the power supply VDD and the ground, and the intermediate node thereof is connected to the gate of the pMOS transistor Q ₁₂ . That is, the resistor R ₅ is connected between the gate of the pMOS transistor Q ₁₂ and the power supply VDD. The resistor R ₆ is connected between the gate of the pMOS transistor Q ₁₂ and the ground, and is directly grounded in the chip without a bypass capacitor outside the chip.

When the semiconductor chip 1 shown in FIG. 2 is used in a low frequency range, if the resistance values R ₃ : R ₄ = R ₅ : R ₆ are satisfied, the values of the resistors R ₅ and R ₆ are It is optional. On the other hand, when the semiconductor chip 1 is used in a high frequency range, the values of the resistors R ₃ and R _{4 and} the values of the resistors R ₅ and R ₆ are determined so that their combined resistance values are equal to each other. preferable. More preferably, R ₃ = R ₅ and R ₄ = R ₆ .

In the case of the above configuration, a voltage obtained by dividing the voltage of the power supply VDD by the resistors R ₃ and R ₄ is applied between the gate and drain of the pMOS transistor Q ₁₁ . Similarly, a voltage obtained by dividing the voltage of the power supply VDD by the resistors R ₅ and R ₆ is applied between the gate and drain of the pMOS transistor Q ₁₂ . In the example of FIG. 1, since the gate-drain voltage is 0 V, the characteristics may deteriorate when a strong signal is input. In contrast,
With the configuration shown in FIG. 2, such an inconvenience can be suppressed.

[0046] Further, in the present embodiment, the gate of the pMOS transistor Q ₁₁ - a source voltage Vgs1, the gate of the pMOS transistor Q ₁₂ - almost equal to the source voltage Vgs2, the gate bias of the transistors Q _11, Q ₁₂ The voltages Va1 and Va2 have almost the same value. Moreover, MOS
When a differential pair is composed of a circuit, its input impedance is so large that the differential balance is hardly lost. Therefore, the linearity of the amplifier circuit can be favorably maintained, and the noise of the substrate can be canceled by the complete differential to improve the noise characteristic.

In the first and second embodiments described above, the amplifier using the p-channel MOS transistor is shown, but the invention can be similarly applied to the amplifier using the n-channel MOS transistor. FIG. 3 is a diagram showing a configuration example in that case, and FIG. 3A shows an example in the case where the first embodiment is configured with n channels.
(B) shows an example in which the second embodiment is configured with n channels.

In FIG. 3A, one differential input terminal of the first stage differential amplifier (specifically, the gate side of the nMOS transistor Q ₁₁ 'that constitutes the first stage differential amplifier) is A resistor R _{1 for both} impedance matching and bias is connected. The resistor R ₁ is directly connected between the gate of the nMOS transistor Q ₁₁ ′ and the power supply VDD without using a bypass capacitor.

At the other differential input terminal of the first stage differential amplifier (specifically, on the gate side of the nMOS transistor Q ₁₂ 'which constitutes the first stage differential amplifier), a bias resistor R is provided. ₂ is connected. This resistance R ₂ is nM
It is directly connected between the gate of the OS transistor Q ₁₂ 'and the power supply VDD without using a bypass capacitor.

Further, in FIG. 3B, one differential input terminal of the first stage differential amplifier (specifically, the gate side of the nMOS transistor Q ₁₁ 'which constitutes the first stage differential amplifier) is connected. Are connected to resistors R ₃ and R ₄ for both impedance matching and biasing.

The resistors R ₃ and R ₄ are connected in series between the power supply VDD and the ground, and the intermediate node thereof is an nMOS.
It is connected to the gate of transistor Q ₁₁ '. That is, the resistor R ₃ is connected between the gate of the nMOS transistor Q ₁₁ ′ and the power supply VDD. Also, the resistance R ₄
Is connected between the gate of the nMOS transistor Q ₁₁ ′ and the ground, and is directly grounded without a bypass capacitor.

At the other differential input terminal of the first stage differential amplifier (specifically, on the gate side of the nMOS transistor Q ₁₂ 'which constitutes the first stage differential amplifier), a bias resistor R is provided. ₅ and R ₆ are connected.

The resistors R ₅ and R ₆ are connected in series between the power supply VDD and the ground, and the intermediate node thereof is an nMOS.
It is connected to the gate of transistor Q ₁₂ '. That is, the resistor R ₅ is connected between the gate of the nMOS transistor Q ₁₂ ′ and the power supply VDD. Also, the resistance R ₆
Is connected between the gate of the nMOS transistor Q ₁₂ ′ and the ground, and is directly grounded without a bypass capacitor.

In addition, each of the embodiments described above is merely an example of the embodiment for carrying out the present invention, and the technical scope of the present invention should not be limitedly interpreted by these. Is. That is, the present invention can be implemented in various forms without departing from the spirit or the main features thereof.

[0055]

As described above, according to the present invention, a matching / bias resistor is connected to one differential input terminal of the differential amplifier, and a bias resistor is connected to the other differential input terminal. Since the resistance is directly connected to the ground or the power supply, the MO that constitutes the differential amplifier is
The gate of the S-transistor can be self-biased. As a result, it is not necessary to use a large-capacity bypass capacitor in order to suppress a decrease in gain and noise, and it is possible to reduce a large-scale capacitor and reduce the size and cost of the electronic device. Further, since it is not necessary to provide a pad dedicated to the bypass capacitor on the semiconductor chip in which the amplifier circuit is integrated, the number of pads can be reduced. As a result, the chip size can be reduced, the defect rate can be reduced, and the reliability of the semiconductor chip can be improved. Furthermore, 1
The circuit operation can be stabilized by allowing signals to flow in one direction in one chip.

According to another feature of the present invention, since the resistance values (combined resistance value) connected to both differential input terminals are made equal to each other, the gates of the MOS transistors forming the differential pair are formed. The bias voltage can be made almost equal. Moreover, by forming a differential pair with MOS circuits and increasing the input impedance thereof, the differential balance is hardly disturbed, the linearity of the amplifier circuit can be maintained well, and the noise characteristics are improved. be able to.

According to another feature of the present invention, a plurality of matching / bias resistors are connected in series between the power supply and the ground, and one differential input terminal of the differential amplifier is connected to the intermediate node thereof. At the same time, since a plurality of bias resistors were connected in series between the power supply and ground, and the other differential input terminal was connected to the intermediate node, the divided voltage of the power supply was applied between the gate and drain of the MOS transistor. Therefore, it is possible to prevent the characteristics from deteriorating even when a strong signal is input.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment and is a diagram showing a partial configuration example of an IC that constitutes an amplifier and its peripheral circuits.

FIG. 2 is a diagram illustrating a second embodiment and is a diagram illustrating a partial configuration example of an IC that constitutes an amplifier and a peripheral circuit thereof.

FIG. 3 shows an n-channel MOS according to the first and second embodiments.
It is a figure which shows the structural example of an amplifier when implement | achieving with a transistor.

FIG. 4 is a diagram showing a configuration of a conventional amplifier circuit.

[Explanation of symbols]

1 semiconductor chip 11 pad for amplifier input 12 pad for bypass capacitor 13 constant current circuit 14 bias circuit Q _i1 , Q _i2 (i = 1, 2, ...) pMOS transistors R _{1 to} R ₆ resistors Q _i1 ′, Q _i2 '(I = 1, 2, ...) nMOS transistor

Continued front page    F term (reference) 5J066 AA01 AA12 CA41 CA87 CA93                       FA10 HA10 HA25 HA29 KA05                       KA12 KA29 KA41 MA08 MA21                       ND01 ND11 ND22 ND23 PD02                       SA13                 5J069 AA01 AA12 CA41 CA87 CA93                       FA10 HA10 HA25 HA29 KA05                       KA12 KA29 KA41 MA08 MA21                       SA13

Claims (7)

[Claims] 1. A differential amplifier that amplifies and outputs an input signal, and is connected to one differential input end of the differential amplifier to match impedance and to apply a bias to the one differential input end. An amplifier circuit comprising: a matching / bias resistor and a bias resistor connected to the other differential input terminal of the differential amplifier and applying a bias to the other differential input terminal. 2. The matching / bias resistance and the bias resistance are pMOS constituting the differential amplifier.
The amplifier circuit according to claim 1, wherein the amplifier circuit is connected between the gate of the transistor and the ground. 3. The matching / bias resistance and the bias resistance are nMOS constituting the differential amplifier.
The amplifier circuit according to claim 1, wherein the amplifier circuit is connected between the gate of the transistor and the power supply. 4. The amplifier circuit according to claim 1, wherein a value of the matching / bias resistance and a value of the bias resistance are equal to each other. 5. A differential amplifier that amplifies and outputs an input signal, and is connected to one of the differential input terminals of the differential amplifier to match impedance and to apply a bias to the one differential input terminal. A plurality of matching / bias resistors, and a plurality of bias resistors connected to the other differential input terminal of the differential amplifier for applying a bias to the other differential input terminal; A dual-purpose resistor is connected in series between the power supply and ground, and the one differential input terminal is connected to the intermediate node thereof, and the plurality of bias-use resistors are connected in series between the power supply and ground, An amplifier circuit having the other differential input terminal connected to an intermediate node thereof. 6. A combined resistance value of the plurality of matching / bias combined resistors connected to the one differential input terminal and a combined resistance value of the plurality of bias resistors connected to the other differential input terminal. The amplifier circuit according to claim 5, wherein the values are equal to each other. 7. A difference between one of a differential amplifier circuit in which differential amplifiers for amplifying an input signal from the previous stage and outputting the amplified signal to the next stage are connected in multiple stages and one of the differential amplifiers in the first stage in the differential amplifier circuit. Connected to the dynamic input end to match the impedance and to apply a bias to one of the differential input ends.
An amplifier circuit comprising: a bias-combining resistor; and a bias resistor that is connected to the other differential input terminal of the first stage differential amplifier and applies a bias to the other differential input terminal.