556417 Α7 Β7 五、發明説明（1) 〔技術領域〕 (請先閲讀背面之注意事項再填寫本頁) 本發明是有關放大電路，特別是非常適合使用於無線 通訊裝置等的差動放大器。 〔背景技術〕 近年來，在無線接收機，行動電話，無線電話，電視 機，汽車導航系統，及遊戲機等之具備無線通訊機能的電 子機器中，隨著所使用之半導體裝置的高集成化，會有更 多的電路集結於1個晶片中。 一般，在上述電子機器中，爲了使接收的微小輸入訊 號再生成矩形波，而使用放大輸入訊號後輸出的放大電路 。依用途，也有使用多段縱連接複數個差動放大器來取得 高增益之差動型的多段放大電路。以往，是以將這些放大 電路與其他的電路一起集成於1個晶片的I C來提供。 第1圖是表示構成放大器的IC及其周邊電路的一部 份構成例。此第1圖是表示Μ〇S電路的構成例。 在第1圖中，元件符號1 0 〇是表示I F ( 經濟部智慧財產局員工消費合作社印製556417 Α7 Β7 V. Description of the Invention (1) [Technical Field] (Please read the notes on the back before filling out this page) The present invention relates to amplifying circuits, and is particularly suitable for differential amplifiers such as wireless communication devices. [Background Art] In recent years, in electronic devices with wireless communication functions such as wireless receivers, mobile phones, wireless phones, televisions, car navigation systems, and game consoles, with the increasing integration of semiconductor devices used , There will be more circuits in one chip. Generally, in the above-mentioned electronic equipment, in order to regenerate a rectangular input wave from a received small input signal, an amplifier circuit that amplifies the input signal and outputs it is used. Depending on the application, there are also differential multistage amplifier circuits that use a plurality of longitudinally connected plural differential amplifiers to obtain a high gain. Conventionally, these ICs are provided by ICs that integrate these amplifier circuits with other circuits on a single chip. Fig. 1 shows a partial configuration example of an IC and peripheral circuits constituting the amplifier. This first figure shows a configuration example of the MOS circuit. In the first figure, the component symbol 1 0 0 indicates I F (printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs).
Intermediate Frequency)濾波器，元件符號2 0 0是表示 構成放大器的半導體晶片。I F濾波器1 〇 〇與半導體晶 片2 0 0是經由半導體晶片2 0 0的腳位（p a d ) 1 1 來電性連接。I F濾波器1 〇 〇是例如使用陶瓷濾波器或 水晶濾波器，該等濾波器爲對訊號源或負荷阻抗敏感的元 件。 在此例中，半導體晶片2 〇 0是包含1段的差動放大 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -4- 556417 A7 B7 五、發明説明（2) (請先閲讀背面之注意事項再填寫本頁) 器。此差動放大器具備：由2個電阻Rii，Ri2與2個 p Μ〇S電晶體Q i !，Q i 2與定電流電路1 3所構成的差 動對，電阻R i及偏壓電路1 4。 在上述差動對中，2個電晶體Q ^ ^，Q ^ 2的源極彼此 會互相相共通連接，且在這些共通源極分別連接定電流電 路1 3的一端。定電流電路1 3的另一端是連接於電源 V D D。又，各電晶體Q i :，Q ! 2的汲極是分別經由電阻 R i i，R ^ 2來接地。並且，在各電晶體Q i i，Q i 2的閘 極中會被輸入放大的訊號。 在I F瀘波器1 〇 〇與放大器之間（具體而言，在半 導體晶片2 0 0的腳位1 1與構成差動對的一方p Μ〇S 電晶體Q ^ ^之間）所被插入的電阻R i爲阻抗整合用及偏 壓施加用的電阻。由於I F濾波器1 〇 〇的輸出阻抗與放 大器的輸出阻抗不同，因此若原封不動地連接，則會因阻 抗未整合而引起頻帶劣化。因此，必須藉由電阻R i來取阻 抗整合。 經濟部智慧財產局員工消費合作社印製 偏壓電路1 4是由p Μ〇S電晶體Q ! :，Q 1 2的閘極 偏壓供給用的電阻來構成。此偏壓電路1 4是供以使 p Μ〇S電晶體Q ^ ，Q ! 2動作。 在上述偏壓電路1 4及電阻R 1經由腳位1 4在半導體 晶片2 0 0的外部連接有旁通電容C。該旁通電容C是供 以抑止增益降低或雜訊發生。 I F濾波器1 0 0，例如爲使用陶瓷濾波器時，爲了 整合阻抗，電阻R 1的値必須選擇3 3 Ο Ω或2 Κ Ω附近的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5- 556417 Α7 Β7 五、發明説明（3) (請先閲讀背面之注意事項再填寫本頁) 値。並且，爲了不破壞整合條件，旁通電容C的阻抗必須 比電阻R i的値還要十分小。因此，就旁通電容C而言必須 使用大容量者。 大容量的旁通電容C本身具有較大的容積，無法集成 於半導體晶片2 0 0內。因此，以往的旁通電容C是外接 於半導體晶片2 0 0。如此一來，使用這些半導體晶片 2 0 0及旁通電容C的電子機器會難以小型化，同時會有 成本增加的問題。 又，由於必須在半導體晶片2 0 0設置旁通電容C專 用的腳位1 2，因此晶片大小會增大。並且，隨著腳位數 的增多，不良率會有增高的可能，導致會有半導體晶片 2 0 0的可靠度降低的問題發生。 又，由於旁通電容C是外接於半導體晶片2 0 0，因 此必須藉由接合線等來連接半導體晶片2 0 0與旁通電容 C。此情況，到底要將比半導體晶片2 0 0還要大的旁通 電容C配置於半導體晶片2 0 0的周邊何處，以及要如何 接地等問題，有可能會造成半導體晶片2 0 0的電路動作 不安定。 經濟部智慧財產局員工消費合作社印製 又，由於存在旁通電容C及設置於差動對一方的電阻 R i，因此會破壞差動放大器的阻抗平衡。如此一來，若在 半導體晶片2 0 0內的基片等中發生雜訊，則該雜訊會被 輸入P Μ〇S電晶體Q 1 1側而放大’因此會有雜訊特性惡 化的問題。 本發明是爲了解決上述問題而硏發者，其目的是在於 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -6 - 556417 A7 ___ B7 五、發明説明（4) 提供一種不需要旁通電容器C ’而可謀求電子機器的小型 化及降低成本，以及提咼電路動作的安定化，可靠度，及 雜訊特性。 (請先閲讀背面之注意事項再填寫本頁) 〔發明之揭示〕 本發明之放大電路的特徵是具備： 差動放大器；該差動放大器是供以放大輸入訊號後輸 出；及 整合•偏壓兼用電阻；該整合•偏壓兼用電阻是連接 於上述差動放大器之一方的差動輸入端，取阻抗的整合， 且對上述一方的差動輸入端賦予偏壓；及 偏壓用電阻；該偏壓用電阻是連接於上述差動放大器 之另一方的差動輸入端，對上述另一方的差動輸入端賦予 偏壓。 本發明之另一態樣爲：上述整合•偏壓兼用電阻及上 述偏壓用電阻是連接於構成上述差動放大器之pM〇 S電 晶體的閘極與接地之間。 經濟部智慧財產局員工消費合作社印製 本發明之另一態樣爲：上述整合•偏壓兼用電阻及上 述偏壓用電阻是連接於構成上述差動放大器之nM〇 S電 晶體的閘極與電源之間。 本發明之另一態樣爲：上述整合•偏壓兼用電阻的値 與上述偏壓用電阻的値是彼此相等。 本發明之另一態樣的放大電路的特徵是具備： 差動放大器；該差動放大器是供以放大輸入訊號後輸 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 556417 A7 B7 五、發明説明（5) 出；及 複數個整合•偏壓兼用電阻；該複數個整合•偏壓兼 用電阻是連接於上述差動放大器之一方的差動輸入端，取 阻抗的整合’且對上述一方的差動輸入端賦予偏壓；及 複數個偏壓用電阻；該複數個偏壓用電阻是連接於上 述差動放大器之另一方的差動輸入端，對上述另一方的差 動輸入端賦予偏壓； 又，將上述複數個整合•偏壓兼用電阻串連於電源與 接地之間，且在其中間節點連接上述一方的差動輸入端； 又，將上述複數個偏壓用電阻串連於電源與接地之間 ’且在其中間節點連接上述另一方的差動輸入端。 本發明之另一態樣爲：連接於上述一方的差動輸入端 之上述複數個整合•偏壓兼用電阻的合成電阻値與連接於 上述另一方的差動輸入端之上述複數個偏壓用電阻的合成 電阻値是彼此相等。 本發明之另一*態樣的放大電路的特徵是具備： 差動放大電路；該差動放大電路是供以放大來自前段 的輸入訊號後輸出至下段；及 整合•偏壓兼用電阻；該整合•偏壓兼用電阻是連接 於上述差動放大電路內之初段的差動放大器之一方的差動 輸入端，取阻抗的整合，且對上述一方的差動輸入端賦予 偏壓；及 偏壓用電阻；該偏壓用電阻是連接於上述初段的差動 放大器之另一方的差動輸入端，對上述另一方的差動輸入 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁)Intermediate Frequency) filter. The component symbol 2 0 0 indicates the semiconductor wafer constituting the amplifier. The IF filter 1 〇 〇 and the semiconductor wafer 2 0 0 are electrically connected via the pin (p a d) 1 1 of the semiconductor wafer 2 0. The I F filter 1 is, for example, a ceramic filter or a crystal filter, and these filters are components sensitive to a signal source or load impedance. In this example, the semiconductor wafer 2000 is a 1-stage differential amplifier. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -4- 556417 A7 B7 V. Description of the invention (2) (please Please read the notes on the back before filling in this page). This differential amplifier includes: a differential pair composed of two resistors Rii, Ri2 and two p MOS transistors Q i!, Q i 2 and a constant current circuit 13, a resistor Ri and a bias circuit 1 4. In the above differential pair, the sources of the two transistors Q ^^, Q ^ 2 are connected to each other in common, and one end of the constant current circuit 13 is connected to these common sources. The other end of the constant current circuit 1 3 is connected to a power source V D D. The drains of the transistors Q i:, Q! 2 are grounded via resistors R i i, R ^ 2, respectively. In addition, an amplified signal is input to the gates of the transistors Q i i and Q i 2. Between the IF amplifier 100 and the amplifier (specifically, between the pin 11 of the semiconductor wafer 2000 and the p MOS transistor Q ^ ^ forming a differential pair) The resistor R i is a resistor for impedance integration and bias application. Since the output impedance of the I F filter is different from that of the amplifier, if it is left intact, the frequency band will be degraded due to unintegrated impedance. Therefore, impedance integration must be achieved by the resistor Ri. The bias circuit 14 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The bias circuit 14 is composed of a resistor for supplying the bias voltage of the gate of the pMOS transistor Q!:, Q 1 2. This bias circuit 14 is used to operate the pMOS transistors Q ^, Q! 2. A bypass capacitor C is connected to the bias circuit 14 and the resistor R1 outside the semiconductor wafer 200 via the pin 14. The bypass capacitor C is used to prevent gain reduction or noise from occurring. IF filter 1 0 0. For example, when using a ceramic filter, in order to integrate the impedance, the resistance of resistor R 1 must be 3 3 Ο Ω or 2 κ Ω. The paper size near this paper applies the Chinese National Standard (CNS) A4 specification (210X297 (Mm) -5- 556417 Α7 Β7 V. Description of the invention (3) (Please read the notes on the back before filling this page) 値. In addition, in order not to damage the integration conditions, the impedance of the bypass capacitor C must be much smaller than 値 of the resistor Ri. Therefore, in terms of the bypass capacitor C, a large capacity must be used. The large-capacity bypass capacitor C itself has a large volume and cannot be integrated into the semiconductor wafer 200. Therefore, the conventional bypass capacitor C is externally connected to the semiconductor chip 200. As a result, it is difficult to miniaturize an electronic device using these semiconductor wafers 200 and a bypass capacitor C, and at the same time, there is a problem that the cost is increased. In addition, since the dedicated pin 12 for the bypass capacitor C must be provided on the semiconductor wafer 200, the wafer size increases. In addition, as the number of pins increases, the defect rate may increase, leading to a problem that the reliability of the semiconductor wafer 200 may decrease. In addition, since the bypass capacitor C is externally connected to the semiconductor wafer 200, it is necessary to connect the semiconductor wafer 200 and the bypass capacitor C by a bonding wire or the like. In this case, if the bypass capacitor C, which is larger than the semiconductor wafer 2000, is arranged around the semiconductor wafer 2000, and how to ground it, it may cause a circuit of the semiconductor wafer 2000. Movements are unstable. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Because of the bypass capacitor C and the resistor R i provided on the differential pair, the impedance balance of the differential amplifier is destroyed. In this way, if noise occurs in the substrate or the like in the semiconductor wafer 200, the noise will be amplified by being input to the P MOS transistor Q 1 1 ', so there will be a problem of deterioration of noise characteristics. . The present invention was developed in order to solve the above problems, and its purpose is to apply the Chinese National Standard (CNS) A4 specification (210 × 297 mm) to this paper size. -6-556417 A7 ___ B7 5. Description of the invention (4) Bypass capacitor C 'is required to reduce the size and cost of electronic equipment, and to improve the stability, reliability, and noise characteristics of circuit operation. (Please read the notes on the back before filling this page) [Disclosure of the invention] The amplifier circuit of the present invention is characterized by: a differential amplifier; the differential amplifier is used to amplify the input signal and output; and integration and bias Combined resistance; The integrated and biased combined resistance is connected to one of the differential input terminals of the differential amplifier, taking the integration of the impedance, and giving a bias to the differential input terminal; and a bias resistor; the The bias resistor is connected to the other differential input terminal of the differential amplifier, and a bias is applied to the other differential input terminal. According to another aspect of the present invention, the integrated and bias resistor and the bias resistor are connected between a gate and a ground of a pMOS transistor constituting the differential amplifier. Another aspect of the invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is that the above-mentioned integration and bias resistors and the above-mentioned resistors for bias are connected to the gates of the nMOS transistor that constitutes the differential amplifier. Between power. According to another aspect of the present invention, 上述 of the integration and bias resistors and 値 of the bias resistors are equal to each other. The amplifying circuit of another aspect of the present invention is provided with: a differential amplifier; the differential amplifier is used to amplify the input signal and output to the paper; the size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm); Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 556417 A7 B7 V. Description of the invention (5); and a plurality of integrated and bias resistors; the plurality of integrated and bias resistors are connected to one of the differential amplifiers mentioned above. The input terminals, take the integration of impedance, and apply bias voltage to the differential input terminal; and a plurality of bias resistors; the plurality of bias resistors are connected to the other differential amplifier. The input terminal is biased to the other differential input terminal; and the plurality of integrated and bias resistors are connected in series between the power source and the ground, and the differential input terminal of the one is connected to the intermediate node. In addition, the plurality of bias resistors are connected in series between the power source and the ground, and the other differential input terminal is connected to an intermediate node thereof. Another aspect of the present invention is: the composite resistor 値 of the plurality of integrated and biasing combined resistors connected to the one differential input terminal and the plurality of biasing resistors connected to the other differential input terminal. The combined resistances 値 of the resistors are equal to each other. Another * aspect of the present invention is characterized in that the amplifier circuit is provided with: a differential amplifier circuit; the differential amplifier circuit is used to amplify an input signal from the previous stage and output to the lower stage; and an integrated and biasing resistor; the integration • Biasing resistor is a differential input terminal connected to one of the differential amplifiers in the initial stage of the differential amplifier circuit, taking impedance integration, and biasing the differential input terminal; and Resistance; The bias resistor is connected to the other differential input terminal of the differential amplifier of the above-mentioned first stage. For the other input of the other differential input, this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm). (Please read the notes on the back before filling this page)
-8- 556417 A7 B7 五、發明説明（6) 端賦予偏壓。 (請先閱讀背面之注意事項再填寫本頁} 〔供以實施發明之最佳形態〕 (第1實施形態） 以下，根據圖面來說明本發明之第1實施形態。 第2圖是表示第1實施形態，爲構成放大器的1 c及 其周邊電路的一部份構成例。 就第2圖例的構成而言，雖是顯示多段連接差動放大 器（放大來自前段的輸入訊號後輸出至下段者）而成的多 段放大電路，但亦可與第1圖同樣的，只具備1段的差動 放大器。並且，在第2圖中，針對與第1圖相同的構成要 件賦予相同的符號。 如第2圖所示，I F濾波器1 〇 0與本實施形態的半 導體晶片1是經由腳位（P a d ) 1 1來電性連接。半導 體晶片1內的放大器是由輸入側往輸出側多段連接複數個 差動放大器而成。各段的差動放大器是具備由2個電阻R ^ i，Rl2(i= 1 ，2， ···）及2個pM〇S電晶體 Q ^ ^，Q ^ 2 ( i = 1，2，· · ·）及定電流電路 經濟部智慧財產局員工消費合作社印製 1 3 - i ( i = 1，2，· · ·）所形成的差動對。 在各個差動對中，2個電晶體Q i i，Q i 2的源極彼此 會互相共通連接，且在這些共通源極分別連接定電流電路 1 3…的一端。各定電流電路1 3 - i的另一端是連接於電 源V D D。又，各電晶體Q i i，Q : 2的汲極是分別經由電 阻R i i，R i 2來接地。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 9 - 556417 Α7 Β7 五、發明説明（7) (請先閲讀背面之注意事項再填寫本頁) 並且，在各電晶體Q i i，Q i 2的閘極中，除了初段的 差動放大器以外，會被輸入來自前段的差動放大器的輸出 訊號。在初段的差動放大器的各電晶體Q i i，Q i 2的閘極 中會被輸入放大的訊號。連接於差動放大器的輸出訊號線 的電容器C 1，C 2爲直流阻止用的電容器。 在如此構成的放大電路中，被輸入初段的差動放大器 的各電晶體Q 1 1，Q 1 2的基極之訊號會只被放大預定的位 準而輸出。在此，所被放大輸出的訊號會被輸入至第2段 的差動放大器的電晶體Q21，Q22的基極，且會在該第2 段的差動放大器中再被放大輸出。以下，同樣的，訊號會 根據各段的差動放大器來依次放大。藉此，往第1段的差 動放大器的輸入訊號會隨著進入後段而振幅變大，最後可 取得被放大至預定位準的輸出訊號。 經濟部智慧財產局員工消費合作社印製 在初段的差動放大器之一方的差動輸入端（具體而言 ，構成第1段的差動放大器之p Μ〇S電晶體Q i 1的閘極 側）連接有兼具整合（匹配）用與偏壓用的電阻R :，該整 合（匹配）用是在於整合由腳位1 1來看左方的阻抗及右 方的阻抗，該偏壓用是在於賦予偏壓電壓給p Μ〇S電晶 體Q : ^的閘極。在本實施形態中，電阻R i是連接於 p Μ〇S電晶體Q i i的閘極與接地之間，不經由晶片外部 的旁通電容器，在晶片內直接接地。 又，在初段的差動放大器之另一方的差動輸入端（具 體而言，構成第1段的差動放大器之pM〇S電晶體Q12 的閘極側）連接有賦予偏壓電壓給p Μ 0 S電晶體Q 1 2的 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -10- 556417 A 7 B7 五、發明説明（8) (請先閲讀背面之注意事項再填寫本頁) 閘極之偏壓用的電阻R 2。在本實施形態中，電阻R 2是連 接於p Μ〇S電晶體Q i 2的閘極與接地之間，不經由晶片 外部的旁通電容器，在晶片內直接接地。 在將半導體晶片1使用於低頻領域的用途時，電阻R 2 的値爲任意。甚至，可短路連接P Μ〇S電晶體Q i 2的閘 極與接地之間。這是因爲在Μ〇S電晶體時，由於閘極電 流幾乎未流動，因此無關電阻R 2的値，Ρ Μ〇S電晶體 Q 1 2的閘極偏壓電壓V a 2會形成一定的値。 在將半導體晶片1使用於高頻領域的用途時，電阻R 2 的値最好是使用與R i的値相等者。使用於高頻領域時，在 各電晶體Q ^ ^，Q i 2的閘極-汲極間所產生的分布容量不 可無視。因此，若不爲R i = R 2，則會失去差動平衡，而 導致差動放大器不會正確地動作。 在構成第2段以後的差動放大器之各Ρ Μ〇S電晶體 Q ΐ 1 ? Q i 2 ( i = 2，3，· · ·）的聞極連接有偏壓用 的電阻 Rbl，Rb2，Rb3，Rb4。 經濟部智慧財產局員工消費合作社印製 如以上所述構成時，Ρ Μ〇S電晶體Q i i的閘極會自 我偏壓成Va 1= VDD— Vs— Vgs 1 (Vs爲施加 於定電流電路1 3-ί的電壓’ V g s 1爲pM〇S電晶體 Q i i的閘極一源極間電壓）之電壓。又，Ρ M〇S電晶體 Q"的閘極會自我偏壓成Va2 = VDD — Vs —-8- 556417 A7 B7 V. Description of the invention (6) The terminal is biased. (Please read the precautions on the back before filling out this page} [Best Mode for Implementing the Invention] (First Embodiment) Hereinafter, the first embodiment of the present invention will be described with reference to the drawings. The second figure shows the first The first embodiment is an example of a part of the configuration of 1 c and its peripheral circuits. The structure of the second example shows a multi-stage differential amplifier (the input signal from the previous stage is amplified and output to the lower stage). ) Is a multi-stage amplifier circuit, but it can also be the same as in Figure 1 and only has a 1-stage differential amplifier. In Figure 2, the same components as in Figure 1 are given the same symbols. As shown in FIG. 2, the IF filter 100 is electrically connected to the semiconductor chip 1 of this embodiment via a pin (P ad) 1 1. The amplifier in the semiconductor chip 1 is connected to a plurality of stages from the input side to the output side. Differential amplifiers. The differential amplifiers in each segment are equipped with two resistors R ^ i, Rl2 (i = 1, 2, ···) and two pMOS transistors Q ^^, Q ^ 2 (i = 1, 2, · · ·) and constant current circuit Differential pairs formed by the production bureau employee consumer cooperatives 1 3-i (i = 1, 2, · · ·). In each differential pair, the sources of the two transistors Q ii and Q i 2 are connected to each other. Will be connected to each other in common, and one end of the constant current circuits 1 3 ... is connected to these common sources. The other ends of the constant current circuits 1 3-i are connected to the power source VDD. Also, the transistors Q ii, Q: 2 The drain terminals are grounded through resistors R ii and R i 2. The paper dimensions are in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 9-556417 Α7 Β7 V. Description of the invention (7) (Please read the back first (Notes on this page, please fill in this page again) In addition, the gates of the transistors Q ii and Q i 2 are inputted with the output signal from the differential amplifier in the previous stage in addition to the differential amplifier in the first stage. Amplified signals are input to the gates of the transistors Q ii and Q i 2 of the amplifier. The capacitors C 1 and C 2 connected to the output signal line of the differential amplifier are DC blocking capacitors. In the amplifier circuit, each of the differential amplifiers input to the initial stage is input. The base signals of the crystals Q 1 1 and Q 1 2 will only be amplified and output at a predetermined level. Here, the amplified output signals will be input to the transistors Q21 and Q22 of the differential amplifier in the second stage. Base, and will be amplified and output again in the differential amplifier of the second stage. Hereinafter, the same, the signal will be amplified sequentially according to the differential amplifier of each stage. Thus, the differential amplifier of the first stage The input signal of will increase in amplitude as it enters the rear section, and finally an output signal that is amplified to a predetermined level can be obtained. The consumer input of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the differential input terminal of one of the differential amplifiers in the initial stage (specifically, the gate side of p MOS transistor Q i 1 constituting the differential amplifier in the first stage ) A resistor R that has both integration (matching) and bias is connected. The integration (matching) is used to integrate the left impedance and the right impedance from pin 11 and the bias is It consists in applying a bias voltage to the gate of the pMOS transistor Q :. In this embodiment, the resistor Ri is connected between the gate of pMOS transistor Qi and the ground, and is directly grounded in the chip without passing through a bypass capacitor outside the chip. Furthermore, a bias voltage is applied to p Μ to the other differential input terminal of the differential amplifier of the first stage (specifically, the gate side of the pMOS transistor Q12 constituting the differential amplifier of the first stage). 0 S transistor Q 1 2 This paper size applies to Chinese National Standard (CNS) A4 specification (210 × 297 mm) -10- 556417 A 7 B7 V. Description of the invention (8) (Please read the precautions on the back before filling in this Page) Resistor R 2 for gate bias. In this embodiment, the resistor R 2 is connected between the gate of the p MOS transistor Q i 2 and the ground, and is directly grounded in the chip without passing through a bypass capacitor outside the chip. When the semiconductor wafer 1 is used in a low-frequency field, the resistance of the resistor R 2 is arbitrary. Furthermore, the gate of the PMOS transistor Q i 2 can be short-circuited to ground. This is because at the time of the MOS transistor, the gate current hardly flows. Therefore, the gate bias voltage V a 2 of the P MOS transistor Q 1 2 will form a certain value. . When the semiconductor wafer 1 is used in a high-frequency field, it is preferable that the value of 値 of the resistor R 2 be equal to the value of i of R i. When used in the high-frequency field, the distributed capacity generated between the gate and the drain of each transistor Q ^ ^ and Q i 2 cannot be ignored. Therefore, if it is not R i = R 2, the differential balance will be lost and the differential amplifier will not operate correctly. Bias resistors Rbl, Rb2 are connected to the sense electrodes of each of the P MOS transistors Q ΐ 1? Q i 2 (i = 2, 3, · · ·) constituting the differential amplifier after the second stage. Rb3, Rb4. When printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as described above, the gate of the PMOS transistor Q ii will self-bias to Va 1 = VDD— Vs— Vgs 1 (Vs is applied to the constant current circuit The voltage of 1 3-ί 'V gs 1 is the voltage between the gate and source of the pMOS transistor Q ii). In addition, the gate of the PMOS transistor Q " will self-bias to Va2 = VDD — Vs —
Vg s 2 CVg s 2爲pM〇S電晶體Q12的閘極一源極 間電壓）之電壓。 藉此，在抑止增益降低或雜訊發生時，不必使用大容 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 556417 Α7 Β7 五、發明説明（9) (請先閱讀背面之注意事項再填寫本頁) 量的旁通電容器。因此，可削減連接於半導體晶片1的外 部之大型的旁通電容器，而來謀求電子機器的小型化及成 本降低。 又，由於不用在半導體晶片1設置旁通電容器專用的 腳位，因此連腳位的數量亦可削減。藉此，可縮小晶片的 尺寸，同時還能夠提高半導體晶片1的可靠度。又，由於 可在1個晶片內進行處理，因此訊號的流通路徑會形成於 一方向，而具有電路動作安定之優點。 又，若利用本實施形態，則P Μ〇S電晶體Q i i的閘 極一源極間電壓V g s 1與p Μ〇S電晶體Q 1 2的閘極一 源極間電壓V g s 2會幾乎形成相等，各電晶體Q 1 1， Q ^ 2的閘極偏壓電壓V a 1 ，V a 2會形成幾乎同等的値 。並且，在以Μ〇S電路來構成差動對時，其輸入阻抗非 常大，所以幾乎不會有失去差動平衡的情況。因此，可使 放大電路的線性維持良好，同時還能夠藉由完全差動來消 除基片的雜訊，進而提升雜訊特性。 經濟部智慧財產局員工消費合作社印製 又，以雙極電晶體來構成第2圖所示的放大電路時， 因爲基極電流會流入電晶體，所以在特性上不可無視電阻 R 2的値。因此，爲了不失去差動平衡，連接於差動對雙方 的輸入端的電阻R 1，R 2必須彼此形成相同的値。 (第2實施形態） 其次，根據圖面來說明本發明之第2實施形態。 第3圖是表示第2實施形態，爲構成放大器的I C及 -12- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210x297公釐） 556417 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（β 其周邊電路的一部份構成例。並且，在第3圖中，針對與 第2圖相同的構成要件賦予相同的符號，在此省略重複說 明。 如第3圖所示，在構成放大器的初段的差動放大器之 一方的差動輸入端（具體而言，構成第1段的差動放大器 之ρ Μ〇S電晶體Q : i的閘極側）連接有兼具整合（匹配 )用與偏壓用的電阻R 3，R 4，該整合（匹配）用是在於 整合由腳位1 1來看左方的阻抗及右方的阻抗，該偏壓用 是在於賦予偏壓電壓給p Μ〇S電晶體Q i i的閘極。爲了 阻抗整合，電阻R 3，R 4的合成電阻値必須與第2圖所示 之電阻R i的電阻値相等。 在本實施形態中，電阻R 3，R 4是串連於電源V D D 與接地之間，其中間節點會連接於p Μ〇S電晶體Q i i的 閘極。亦即，電阻R 3是連接於p Μ〇S電晶體Q i i的閘 極與電源V D D之間。又，阻R 4是連接於p Μ〇S電晶體 Q 1 i的閘極與接地之間，不經由晶片外部的旁通電容器， 在晶片內直接接地。 又，在初段的差動放大器之另一方的差動輸入端（具 體而言，構成第1段的差動放大器之pM〇S電晶體Q" 的閘極側）連接有賦予偏壓電壓給p Μ 0 S電晶體Q i 2的 閘極之偏壓用的電阻R 5，R 6。 在本實施形態中，電阻R 5，R 6是串連於電源V D D 與接地之間，其中間節點會連接於p Μ〇S電晶體Q 1 2的 閘極。亦即，電阻R 5是連接於ρ Μ 0 S電晶體Q ^ 2的聞 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -13- 556417 Α7 Β7 五、發明説明（1) (請先閱讀背面之注意事項再填寫本頁) 極與電源V D D之間。又，阻R 6是連接於p Μ〇s電晶體 Q i 2的閘極與接地之間，不經由晶片外部的旁通電容器’ 在晶片內直接接地。 在將第3圖所示之半導體晶片1使用於低頻領域的用 途時，若形成電阻値R 3 : R 4 = R 5 : R 6的關係，則電阻 R 5，R 6的値爲任意。 另一方面，在將半導體晶片1使用於高頻領域的用途 時，電阻R 3，R 4的値與電阻R 5，R 6的値，最好各個合 成電阻値爲彼此形成相等。更理想是R 3 = R 5，R 4 = R 6 0 經濟部智慧財產局員工消費合作社印製 如以上所述構成時，在p Μ〇S電晶體Q 1 1的蘭極-汲極間會被施加根據電阻R 3，R 4來分壓電源V D D的電 壓後之電壓。同樣的，在pM〇S電晶體Q 12的聞極一汲 極間會被施加根據電阻R 5，R 6來分壓電源V D D的電壓 後之電壓。就第2圖例而言，由於閘極-汲極間電壓形成 〇V，因此當較強的訊號被輸入時，特性恐會有劣化之虞 。因應於此，若利用第3圖所示的構成，則可抑止如此不 良的情況。 又，在本實施形態中，Ρ Μ〇S電晶體Q i i的閘極一 源極間電壓V g s 1與p Μ〇S電晶體Q : 2的閘極一源極 間電壓V g s 2幾乎會形成相等，各電晶體Q : i，Q ^ 2的 閘極偏壓電壓V a 1 ，V a 2會幾乎形成同等値。並且， 在以Μ 0 S電路來構成差動對時，其輸入阻抗非常大，所 以幾乎不會有失去差動平衡的情況。因此，可使放大電路 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -14- 556417 A7 B7 五、發明説明（吟 的線性維持良好，同時還能夠藉由完全差動來消除基片的 雜訊，進而提升雜訊特性。 (請先閲讀背面之注意事項再填寫本頁) 在上述第1及第2實施形態中，雖是針對使用P通道 的Μ〇S電晶體之放大器，但同樣亦可適用於使用η通道 的Μ 0 S電晶體之放大器。第4圖是表示該情況的構成例 ，第4 ( a )圖是表示以η通道來構成第1實施形態時的 例子，第4 ( b )圖是表示以η通道來構成第2實施形態 時的例子。 在第4 ( a )圖中，在初段的差動放大器之一方的差 動輸入端（具體而言，構成第1段的差動放大器之 η Μ 0 S電晶體Q i i ’的閘極側）連接有阻抗整合及偏壓 兼用的電阻R !。此電阻R i是連接於η Μ〇S電晶體 Q ! ^ ’的閘極與接地之間，不使用旁通電容器，直接連接 〇 經濟部智慧財產局員工消費合作社印製 又，在初段的差動放大器之另一方的差動輸入端（具 體而言，構成第1段的差動放大器之nM〇S電晶體Q12 ，的閘極側）連接有偏壓用的電阻R 2。此電阻R 2是連接 於η Μ〇S電晶體Q i 2 ’的閘極與接地之間，不使用旁通 電容器，直接連接。 在第4 ( b )圖中，在初段的差動放大器之一方的差 動輸入端（具體而言，構成第1段的差動放大器之 η Μ 0 S電晶體Q i ! ’的閘極側）連接有阻抗整合及偏壓 兼用的電阻R 3，R 4。 此電阻R 3，R 4是串連於電源V D D與接地之間，其 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 556417 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（' 中間節點會連接於η Μ〇S電晶體Q i : ’的閘極。亦即， 電阻R 3是連接於η Μ〇S電晶體Q i : ’的閘極與電源 V D D之間。又，阻R 4是連接於η Μ〇S電晶體Q 1 1，的 閘極與接地之間，不經由旁通電容器，直接接地。 又，在初段的差動放大器之另一方的差動輸入端（具 體而言，構成第1段的差動放大器之η Μ〇S電晶體 Q i 2 ’的閘極側）連接有偏壓用的電阻R 5，R 6。 此電阻R 5，R 6是串連於電源V D D與接地之間，其 中間節點會連接於η Μ〇S電晶體Q i 2 ’的閘極。亦即， 電阻R 5是連接於η Μ〇S電晶體Q i 2 ’的閘極與電源 V D D之間。又，阻R 6是連接於n Μ〇S電晶體Q i 2 ’的 閘極與接地之間，不經由旁通電容器，直接接地。 此外，上述所述的各實施形態，只不過是爲了實施本 發明而舉的具體化例，實際上本發明並非只限於這些實施 例，只要不脫離本發明的主要特徵範圍，亦可實施其他種 種的實施形態。 本發明如以上所述，由於本發明在差動放大器之一方 的差動輸入端連接整合·偏壓兼用電阻，同時在另一方的 差動輸入端連接偏壓用電阻，且將這些電阻直接接地或連 接於電源，因此能夠在構成差動放大器的Μ ◦ S電晶體的 閘極施加自我偏壓。藉此，而能夠在抑止增益降低或雜訊 發生時，不必使用大容量的旁通電容器，亦即可削減大型 的旁通電容器，而來謀求電子機器的小型化及成本降低。 又，由於不用在集成放大電路的半導體晶片設置旁通 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中·國國家標準（CNS ) Α4規格（210Χ297公釐） 16- 556417 Α7 Β7 五、發明説明（1夺 (請先閲讀背面之注意事項再填寫本頁) 電容器專用的腳位，因此連腳位的數量亦可削減。藉此， 可縮小晶片的尺寸，同時還能夠降低不良率，提高半導體 晶片的可靠度。又，可在1個晶片內使訊號的流通路徑流 動於一方向，因此可使電路動作安定。 又，本發明之其他特徵，由於可使連接於雙方的差動 輸入端的電阻値（合成電阻値）彼此形成相等，因此能使 構成差動對的各Μ ◦ S電晶體的閘極偏壓電壓幾乎形成相 等。並且，在以Μ ◦ S電路來構成差動對時，其輸入阻抗 非常大，所以幾乎不會有失去差動平衡的情況，因此可使 放大電路的線性維持良好，同時還能夠提升雜訊特性。 又，本發明之另外其他特徵，由於是將複數個整合· 偏壓兼用電阻串連於電源與接地之間，且在其中間節點連 接差動放大器之一方的差動輸入端，同時將複數個偏壓用 電阻串連於電源與接地之間，且在其中間節點連接差動放 大器之另一方的差動輸入端，因此可在Μ〇S電晶體的閘 極-汲極間施加電源的分壓電壓，即使在較強的訊號被輸 入時，特性也不會劣化。 經濟部智慧財產局員工消費合作社印製 〔產業上之利用可能性〕 由於本發明不需要旁通電容器C，因此對於謀求小型 化，降低成本，電路動作的安定化，以及提高可靠度’雜 訊特性之電子機器極爲有用。 〔圖面之簡單說明〕 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -17- 556417 A7 五、發明説明（1多 第1圖是表示習知之放大電路的構成圖。 第2圖是表示第1實施形態，爲構成放大器的I C及 其周邊電路的一部份構成例。 第3圖是表示第2實施形態，爲構成放大器的1 c及 其周邊電路的一部份構成例。 第4圖是表示使用η通道Μ〇S電晶體來實現第1及 第2貫施形態時的放大器構成例。 〔符號之說明〕 1 1，1 2 :腳位 13:定電流電路 14:偏壓電路 1 0 0 : I F濾波器 2 0 〇 :半導體晶片 R :電阻 經 濟 部 智 慧 財 產 局 (請先閱讀背面之注意事項再填寫本頁) Q :電晶體 V D D :電源 C :電容器 消 費 合 作 社 印 製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -18 -Vg s 2 CVg s 2 is the voltage between the gate and source of pMOS transistor Q12). Therefore, it is not necessary to use large-capacity paper when the reduction of gain reduction or noise occurs. This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-556417 Α7 Β7 5. Description of the invention (9) (please first Read the notes on the back and fill out this page). Therefore, it is possible to reduce the size of a large bypass capacitor connected to the outside of the semiconductor wafer 1, and to reduce the size and cost of an electronic device. In addition, since it is not necessary to provide pins for the bypass capacitor on the semiconductor wafer 1, the number of connected pins can be reduced. Thereby, the size of the wafer can be reduced, and at the same time, the reliability of the semiconductor wafer 1 can be improved. In addition, since processing can be performed in a single chip, a signal flow path is formed in one direction, which has the advantage of stable circuit operation. In addition, according to this embodiment, the gate-source voltage V gs 1 of the P MOS transistor Q ii and the gate-source voltage V gs 2 of the p MOS transistor Q 1 2 will be Almost equal, the gate bias voltages V a 1 and V a 2 of the transistors Q 1 1 and Q ^ 2 will form almost the same voltage. In addition, when a differential pair is constituted by a MOS circuit, the input impedance is very large, so there is almost no possibility of losing the differential balance. Therefore, the linearity of the amplifying circuit can be maintained well, and at the same time, the noise of the substrate can be eliminated by complete differential, thereby improving the noise characteristics. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the amplifier circuit shown in Fig. 2 is constituted by a bipolar transistor, since the base current flows into the transistor, the characteristics of the resistor R 2 must not be ignored. Therefore, in order not to lose the differential balance, the resistors R 1 and R 2 connected to the input terminals of both differential pairs must form the same 彼此 with each other. (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. Figure 3 shows the second embodiment of the IC and -12 which constitute the amplifier. This paper size applies the Chinese National Standard (CNS) A4 specification (210x297 mm) 556417 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. Description of the Invention (β is a configuration example of a part of the peripheral circuit. In FIG. 3, the same reference numerals are given to the same constituent elements as in FIG. 2 and repeated description is omitted here. As shown in FIG. 3, The differential input terminal of one of the differential amplifiers constituting the first stage of the amplifier (specifically, the gate side of ρ MOS transistor Q: i constituting the differential amplifier of the first stage) is connected with integration ( The matching (matching) resistors R 3 and R 4 are used for the bias. The integration (matching) is used to integrate the left impedance and the right impedance viewed from pin 11 and the bias is used to impart a bias voltage. The voltage is applied to the gate of p MOS transistor Q ii. For impedance integration, the combined resistance 値 of resistors R 3 and R 4 must be equal to the resistance 値 of resistor R i shown in FIG. 2. In this embodiment, The resistors R 3 and R 4 are connected in series between the power supply VDD and ground. The intermediate node is connected to the gate of p MOS transistor Q ii. That is, the resistor R 3 is connected between the gate of p MOS transistor Q ii and the power source VDD. Furthermore, the resistance R 4 It is connected between the gate and ground of p MOS transistor Q 1 i, and is directly grounded in the chip without a bypass capacitor outside the chip. The differential input of the other side of the differential amplifier in the first stage The gate (specifically, the gate side of the pM0S transistor Q " constituting the differential amplifier of the first stage) is connected to a bias voltage that applies a bias voltage to the gate of the pM0S transistor Qi2. The resistors R 5, R 6. In this embodiment, the resistors R 5 and R 6 are connected in series between the power source VDD and the ground, and the intermediate node is connected to the gate of the p MOS transistor Q 1 2. That is, the resistor R 5 is connected to the ρ Μ 0 S transistor Q ^ 2 (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -13- 556417 Α7 Β7 V. Description of the invention (1) (Please read the precautions on the back before filling this page) Between the pole and the power supply VDD. The resistor R 6 is connected between the gate of the p MOS transistor Q i 2 and the ground, and is directly grounded in the chip without a bypass capacitor external to the chip. The semiconductor chip 1 shown in FIG. 3 is connected. When used in low-frequency applications, if the relationship of resistance 値 R 3: R 4 = R 5: R 6 is established, the resistance 5 of R 5 and R 6 is arbitrary. On the other hand, when semiconductor wafer 1 is used at high For applications in the frequency domain, it is preferable that the 値 of the resistors R 3 and R 4 and the 値 of the resistors R 5 and R 6 are equal to each other. More ideally, R 3 = R 5 and R 4 = R 6 0 When printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as described above, the blue-to-drain meeting between p MOS transistor Q 1 1 A voltage obtained by dividing the voltage of the power supply VDD by the resistors R 3 and R 4 is applied. Similarly, a voltage after dividing the voltage of the power source V D D according to the resistors R 5 and R 6 is applied between the sense and the drain of the pMOS transistor Q 12. In the second example, the gate-drain voltage is 0V, so when a strong signal is input, the characteristics may be deteriorated. For this reason, by using the configuration shown in Fig. 3, such a situation can be suppressed. Furthermore, in this embodiment, the gate-source voltage V gs 1 of the P MOS transistor Q ii and the gate-source voltage V gs 2 of the p MOS transistor Q: 2 are almost equal. The formation is equal, and the gate bias voltages V a 1 and V a 2 of each transistor Q: i, Q ^ 2 will be almost equal. In addition, when a differential pair is constituted by an M 0 S circuit, the input impedance is very large, so that the differential balance is hardly lost. Therefore, the paper size of the amplifying circuit can be adapted to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -14- 556417 A7 B7 V. Description of the invention (the linearity of Yin is maintained well, and at the same time, it can be achieved by full differential Eliminate the noise of the substrate, thereby improving the noise characteristics. (Please read the precautions on the back before filling this page.) In the first and second embodiments described above, although it is for the MOS transistor using the P channel, The amplifier is also applicable to an amplifier using an M 0 S transistor with n channels. Fig. 4 shows a configuration example in this case, and Fig. 4 (a) shows a case where the first embodiment is constituted with an n channel. For example, Fig. 4 (b) shows an example in which the second embodiment is configured with an η channel. In Fig. 4 (a), the differential input terminal (specifically, Η Μ 0 S transistor Q ii ′ (gate side of the differential amplifier constituting the first stage) is connected to a resistor R for both impedance integration and bias. This resistor R i is connected to η MOS transistor Q ! ^ 'Bypass capacitor between gate and ground Directly connected to the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed on the other side of the differential input of the differential amplifier in the initial stage (specifically, the nM0S transistor Q12 constituting the differential amplifier of the first stage, On the gate side) is connected to a resistor R 2 for bias. This resistor R 2 is connected between the gate of η MOS transistor Q i 2 ′ and the ground, and is directly connected without using a bypass capacitor. In Figure 4 (b), the differential input terminal of one of the differential amplifiers in the first stage (specifically, the gate side of the η Μ 0 S transistor Q i! 'Of the differential amplifier in the first stage) The resistors R 3 and R 4 which are used for both impedance integration and bias are connected. The resistors R 3 and R 4 are connected in series between the power supply VDD and ground. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). -15- 556417 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description ('Intermediate node will be connected to the gate of η MOS transistor Q i:'. That is, the resistance R 3 is Connected between the gate of η MOS transistor Q i: 'and the power supply VDD. The resistor R 4 is connected between the gate of the η MOS transistor Q 1 1 and the ground, and is directly connected to the ground without going through a bypass capacitor. In addition, the other differential input terminal of the differential amplifier in the initial stage ( Specifically, η MOS transistor Q i 2 ′ (gate side of the differential amplifier constituting the first stage) is connected with a resistor R 5 and R 6 for bias. These resistors R 5 and R 6 are strings. Connected between the power supply VDD and ground, the intermediate node will be connected to the gate of the ηMOS transistor Q i 2 ′. That is, the resistor R 5 is connected between the gate of the ηMOS transistor Q i 2 ′ and the power source V D D. The resistor R 6 is connected between the gate of the n MOS transistor Q i 2 ′ and the ground, and is directly grounded without a bypass capacitor. In addition, the above-mentioned embodiments are merely specific examples for implementing the present invention. Actually, the present invention is not limited to these embodiments, as long as it does not depart from the scope of the main features of the present invention, various other embodiments may be implemented. Implementation form. According to the present invention, as described above, since the present invention is connected to one of the differential input terminals of the differential amplifier, the integration and bias resistors are connected, and the other is connected to a bias resistor, and these resistors are directly grounded. Or it can be connected to a power source, so it can apply a self-bias to the gate of the M ◦ S transistor that makes up the differential amplifier. This makes it possible to reduce the size and cost of an electronic device without using a large-capacity bypass capacitor and reducing a large bypass capacitor when suppressing a reduction in gain or occurrence of noise. In addition, because bypassing is not required on the semiconductor chip with integrated amplifier circuit (please read the precautions on the back before filling this page) This paper is applicable to the national standard of China (CNS) Α4 specification (210 × 297 mm) 16- 556417 Α7 Β7 V. Description of the invention (1 win (please read the precautions on the back before filling this page) The pin dedicated to the capacitor, so the number of connected pins can also be reduced. This can reduce the size of the chip and reduce the size of the chip. The failure rate improves the reliability of the semiconductor wafer. In addition, the signal flow path can be flowed in one direction within one chip, so that the circuit operation can be stabilized. In addition, the other feature of the present invention is that it can be connected to both sides. The resistance 値 (combined resistance 値) of the differential input terminals are equal to each other, so that the gate bias voltages of the respective M ◦ S transistors constituting the differential pair can be almost equal. In addition, the difference When moving pairs, the input impedance is very large, so there is almost no loss of differential balance, so the linearity of the amplifier circuit can be maintained well, and at the same time, Noise characteristics. In addition, another feature of the present invention is that a plurality of integrated and biasing resistors are connected in series between the power source and the ground, and a differential input terminal of one of the differential amplifiers is connected to the intermediate node. At the same time, a plurality of bias resistors are connected in series between the power source and the ground, and the other node's differential input terminal of the differential amplifier is connected at the middle node, so it can be used at the gate-drain of the MOS transistor. The voltage divided by the power supply voltage will not deteriorate even when a strong signal is input. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs [Industrial use possibility] Since the present invention does not require a bypass capacitor C. Therefore, it is extremely useful for electronic devices that seek to reduce size, reduce costs, stabilize circuit operation, and improve reliability. Noise characteristics. [Simplified description of the drawing] This paper standard applies to China National Standard (CNS) A4 specifications (210X 297mm) -17- 556417 A7 V. Description of the Invention (1) The first figure shows the structure of a conventional amplifier circuit. The second figure shows the first embodiment. Fig. 3 shows an example of a part of the IC and its peripheral circuits constituting the amplifier. Fig. 3 shows a second embodiment, showing an example of a part of the 1c and its peripheral circuits constituting the amplifier. Fig. 4 shows the use Example of amplifier configuration when the n-channel MOS transistor realizes the first and second implementations. [Explanation of Symbols] 1 1, 12 2: Pin 13: Constant current circuit 14: Bias circuit 1 0 0 : IF filter 2 0 〇: Semiconductor chip R: Intellectual property bureau of the Ministry of Economics and Resistance (please read the precautions on the back before filling out this page) Q: Transistor VDD: Power supply C: Printed by capacitor consumer cooperatives Paper size applicable to China National Standard (CNS) Α4 Specification (210X 297mm) -18-