JP3417792B2 - Analog signal selection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog signal selection circuit that selects any one of a plurality of analog signals and amplifies and outputs it.

[0002]

2. Description of the Related Art An audio device or the like is provided with an analog multiplexer for selecting any one of a plurality of analog signals. For example, a multiplexer for an audio device arbitrarily selects any one of a plurality of analog signals output from a CD reproducing device, a tuner, etc., and amplifies and outputs it according to an instruction from an operator. The signal output from this multiplexer is sent to the speaker and output as voice.

Since this type of analog multiplexer is constructed by combining analog switches and operational amplifiers, it can be relatively easily formed on a semiconductor substrate.

FIG. 5 is a circuit diagram of a conventional analog multiplexer that can be formed on a semiconductor substrate (chip). The analog multiplexer of FIG. 5 includes an input selection circuit 1 including a plurality of analog switches 1a to 1d, an amplification circuit 2 that amplifies an analog signal selected by the input selection circuit 1,
A bias resistor R connected to the output terminals of the analog switches 1a to 1d and a decoder circuit 4 for controlling the analog switches 1a to 1d are provided.

Analog switch 1a in the input selection circuit 1
1d are provided corresponding to each of a plurality of analog signals, and these analog switches 1a to 1d are on / off controlled by a control signal from the decoder circuit 4, respectively. The amplifier circuit 2 includes an operational amplifier OP and resistors r1 and
r2 and r2 to form a non-inverting amplifier. The bias resistor R changes the input voltage of the amplifier circuit 2 based on the reference voltage. In FIG. 5, the other end of the bias resistor R is connected to the analog ground terminal, and the above-mentioned reference voltage is set to the analog ground level.

The input selection circuit 1, the amplification circuit 2 and the bias resistor R described above are formed on the chip, and the analog signal from the outside of the chip is input to the input selection circuit in the chip through the coupling capacitor C1 for cutting the DC voltage. Input to 1.

Next, the operation of the analog multiplexer shown in FIG. 5 will be described. The analog signals IN1 to IN4 are input to the input terminals AIN1 to AIN4 in the chip after the DC voltage component is cut by the coupling capacitor C1 outside the chip.

On the other hand, a decoder circuit 4 for outputting a control signal for controlling ON / OFF of the analog switches 1a-1d is provided in the chip and outputs each control signal so that a plurality of analog switches are not simultaneously turned on. . For example, when the illustrated analog switch 1a is on, the other analog switches 1b to 1d are all off,
The analog signal IN1 is input to the non-inverted input terminal of the operational amplifier OP in the amplifier circuit 2. This analog signal IN1 is
After being amplified by the amplifier circuit 2 which constitutes a non-inverting amplifier, it is output from the output terminal OUT.

[0009]

In the conventional analog multiplexer shown in FIG. 5, analog switches 1a to 1d are used.
Since the bias resistance R is connected to the output terminal of the analog switch, the voltage at the output terminal of the analog switches 1a to 1d is a voltage divided by the on resistance of the analog switch and the bias resistance R. That is, the input voltage amplitude of the amplifier circuit 2 becomes lower than the voltage amplitude of the analog signal input to the chip. Further, since the on-resistances of the analog switches 1a to 1d are not constant and change non-linearly, the amplifier circuit 2
There is a problem that the input voltage of is distorted.

The present invention has been made in view of the above points, and an object thereof is to arbitrarily select and amplify and output any one of a plurality of analog signals without distorting the waveform. An object is to provide an analog signal selection circuit.

[0011]

In order to solve the above-mentioned problems, the invention of claim 1 is provided corresponding to each of a plurality of analog signals, and determines whether or not to pass the corresponding analog signal. In an analog signal selection circuit including a plurality of first switch means for switching and an amplifier circuit for amplifying the analog signal that has passed through the first switch means, an input voltage of the amplifier circuit is set to a desired value based on a reference voltage. A bias circuit for adjusting is provided, and the bias circuit is connected to each input terminal of the plurality of first switch means.

According to a second aspect of the present invention, in the analog signal selection circuit according to the first aspect, the bias circuit includes a bias resistor whose one end is set to the reference voltage, and the plurality of first switch means. A plurality of second switch means that are provided correspondingly and are on / off controlled in conjunction with the corresponding first switch means, and the corresponding analog terminals are respectively provided at the input ends of the second switch means. A signal is input, and the output terminals of the second switch means are both connected to the other end of the bias resistor.

According to a third aspect of the present invention, in the analog signal selection circuit according to the first or second aspect, each of the analog signals corresponds to the corresponding first switch means via a capacitor for removing a DC voltage. Entered in.

According to a fourth aspect of the present invention, in the analog signal selection circuit according to any one of the first to third aspects, each of the first and second switch means is an analog switch.

According to a fifth aspect of the present invention, in the analog signal selection circuit according to any one of the first to fourth aspects, the first switch means, the second switch means, the bias resistor and the amplifier circuit are provided on a semiconductor substrate. To form.

The invention of claim 1 will be described with reference to FIG. 1, for example. The "first switch means" is the analog switches 1a to 1d, the "amplifier circuit" is the amplifier circuit 2, and the "bias circuit" is the bias. Each corresponds to the circuit 3.

The invention of claim 2 will be described with reference to FIG. 1, for example.
The "second switch means" is the analog switches 3a to 3d.
, Respectively.

The invention of claim 3 will be described with reference to FIG. 1, for example. "Capacitor" corresponds to the coupling capacitor C1.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION An analog signal selection circuit to which the present invention is applied will be specifically described below with reference to the drawings. The analog signal selection circuit described below is used, for example, in audio equipment and the like, and selects and outputs any one of a plurality of analog signals output from a CD reproducing device, a tuner, and the like. The signal output from the analog signal selection circuit is sent to, for example, a speaker for voice output.

FIG. 1 is a circuit diagram of an embodiment of an analog signal selection circuit (hereinafter referred to as an analog multiplexer) according to the present invention. In FIG. 1, the same components as those in FIG. 5 are designated by the same reference numerals.

Similar to FIG. 5, the analog signal selection circuit of FIG. 1 includes a coupling capacitor C1 for cutting a DC voltage component included in an analog signal, an input selection circuit 1 including a plurality of analog switches 1a to 1d, Amplifier circuit 2 for amplifying the analog signal selected by the input selection circuit 1.
And a decoder circuit 4 for controlling the plurality of analog switches 1a to 1d.

In addition to this, the analog signal selection circuit of FIG.
A bias circuit 3 connected to the input terminal of the input selection circuit 1 is provided. The bias circuit 3 is composed of analog switches 3a to 3d provided corresponding to each analog signal, and a bias resistor R connected to the output terminals of these analog switches 3a to 3d.

Analog switch 1a in the input selection circuit 1
~ 1d and the analog switch 3a in the bias circuit 3 ~
3d is on / off controlled by a control signal output from the decoder circuit 4. More specifically, the analog switches 1a and 3a and the analog switches 1b and 3b
The analog switches 1c and 3c and the analog switches 1d and 3d are turned on and off in conjunction with each other. The control signal is output from the decoder circuit 4, and the four sets of analog switches (1a, 3a), (1b, 3b) described above,
Of (1c, 3c) and (1d, 3d), only one set is turned on.

The output terminals of the analog switches 3a to 3d are all connected to one end of a bias resistor R, and the other end of the bias resistor R is connected to an analog ground terminal.
Therefore, when any of the analog switches 3a to 3d is turned on, the voltage at the input end of the analog switch changes with reference to the analog ground level.

In the circuit of FIG. 1, the components other than the coupling capacitor C1 are formed on a semiconductor chip,
The analog signals IN1 to IN4 are input from outside the chip. Also, a decoder circuit 4 that generates a control signal is provided in the chip.

The analog switches 1a to 1d shown in FIG.
The circuit configurations of 3a to 3d may all be the same, for example, as shown in FIG.
It is composed of a circuit like. The analog switch shown in FIG. 2 is composed of a circuit having a CMOS structure including a pair of PMOS transistor P1 and NMOS transistor N1. The drain terminal of the NMOS transistor N1 and PM
The source terminals of the OS transistors P1 are connected to each other,
This connection point becomes the input end of the analog switch. Also,
The source terminal of the NMOS transistor N1 and the drain terminal of the PMOS transistor P1 are connected to each other, and this connection point serves as an output terminal.

In FIG. 1, one type of control signal is input to each analog switch, but actually, as shown in FIG. 3, the control signal and its inverted signal are input to each analog switch. More specifically, the control signal is directly input to the gate terminal of the NMOS transistor N1 in FIG. 2, whereas the inverted signal of the control signal is input to the gate terminal of the PMOS transistor P1.

For example, in FIG. 2, when the control signal X is high level, the NMOS transistors N1 and PMO are connected.
Both the S transistors P1 are turned on, and the analog switch is turned on. Conversely, when the control signal X becomes low level, both the NMOS transistor N1 and the PMOS transistor P1 are turned off, and the analog switch is turned off.

On the other hand, FIG. 4 shows the operational amplifier OP shown in FIG.
3 is a circuit diagram showing an internal configuration of FIG. Operational amplifier OP shown
Is composed of a differential amplifier 11 and an output amplifier 12. The differential amplifier 11 includes PMOS transistors P2 and P2.
3, the NMOS transistors N2 and N3, and the constant current source 13, and the output amplification unit 12 has the NMOS transistor N4, the capacitor C2, and the constant current source 14. The gate terminal of the PMOS transistor P3 corresponds to the non-inverting input terminal of the operational amplifier OP, and the gate terminal of the PMOS transistor P2 corresponds to the inverting input terminal of the operational amplifier OP.

Here, when the normal input terminal voltage VIN (+) is higher than the inverting input terminal voltage VIN (-), the constant current source 1
The current from 3 flows to the PMOS transistor P2, and NM
The OS transistors N2 and N3 are turned on. Therefore, N
The MOS transistor N4 is turned off, and the output voltage VOUT becomes the power supply voltage level VDD. On the other hand, forward input terminal voltage VIN
When (+) is lower than the inverting input terminal voltage VIN (-),
The current from the constant current source 13 flows to the PMOS transistor P3, the gate terminal of the NMOS transistor N4 rises, the NMOS transistor N4 turns on, and the output voltage VOUT
Goes to ground level.

As described above, the analog switches 1a to 1d, 3a to 3d and the operational amplifier OP shown in FIG.
Since the S transistor and the PMOS transistor can be combined and configured, the entire circuit of FIG. 1 can be easily formed on the semiconductor substrate.

Next, the operation of the circuit shown in FIG. 1 will be described. For example, when the analog switches 1a and 3a are on, all the other analog switches are off. At this time, the input end of the analog switch 1a is connected to the bias resistor R via the analog switch 3a.
The voltage at the input end of a changes with reference to the analog ground level.

Therefore, the analog signal IN1 which changes with the analog ground level as a reference is input to the non-inverting input terminal of the amplifier circuit 2. The amplifier circuit 2 has an analog signal IN
1 is amplified and output according to the resistance ratio of the resistors r1 and r2.

In the case of the circuit of FIG. 1, the analog switch 1a
Since the bias resistor R is not connected to the output terminals of the to 1d, no current flows to the output terminals of the analog switches 1a to 1d (the non-inverted input terminals of the amplifier circuit 2). That is, the impedance seen from the amplifier circuit 2 side becomes infinite. Therefore, the voltage at the non-inverted input terminal of the amplifier circuit 2 is not lowered by the influence of the ON resistance of the analog switches 1a to 1d, and the voltage waveform at the non-inverted input terminal of the amplifier circuit 2 is not distorted.

Strictly speaking, although some current flows through the analog switch and a slight voltage drop occurs at both ends of the analog switch, the voltage drop is small enough to cause no problem as compared with FIG. The waveform distortion is small enough to be ignored.

As described above, in the analog multiplexer of this embodiment, since the bias circuit 3 is provided on the input side of the analog switches 1a to 1d for selecting any one of the plurality of analog signals, the outputs of the analog switches 1a to 1d are output. Bias current does not flow to the side. Therefore, the analog signal can be amplified without being affected by the non-linearity of the ON resistance of the analog switches 1a to 1d, and the analog amplified signal faithful to the original waveform without distortion can be obtained.

The analog multiplexer of this embodiment is
Not only the above-mentioned audio equipment but also various applications, for example, it can be widely applied to signal switching of analog communication equipment such as a telephone line.

Although FIGS. 2 and 4 show an example of the circuit configuration of the analog switch and the operational amplifier OP, the circuit configuration is not limited to those shown. Further, in the above-described embodiment, the example in which the analog multiplexer is formed on the semiconductor chip has been described, but the analog multiplexer may be configured on a printed circuit board or the like using discrete components.
In that case, the operational amplifier OP and the analog switch may be configured by using, for example, an IC, or may be configured by combining transistors and the like.

In FIG. 1, an example in which one is selected from four types of analog signals has been described, but the number of input analog signals is not particularly limited.

Further, although one end of the bias resistor R is connected to the analog ground terminal in FIG. 1, one end of the bias resistor R may be set to a predetermined level other than the analog ground level. However, in that case, it is also necessary to adjust the voltage level of the inverting input terminal of the operational amplifier OP.

[0041]

As described in detail above, according to the present invention, the bias circuit is connected to the input terminal of the first switch means for selecting any one of the plurality of analog signals. The impedance viewed from the output end side can be set to infinity, and no current flows to the output end of the first switch means. Therefore, the waveform is not distorted under the influence of the non-linearity of the ON resistance of the first switch means, and an arbitrary analog signal can be amplified and output faithfully to the original waveform.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of an analog signal selection circuit according to the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of the analog switch shown in FIG.

FIG. 3 is a diagram showing a connection state of analog switches.

FIG. 4 is a circuit diagram showing an internal configuration of the operational amplifier shown in FIG.

FIG. 5 is a circuit diagram of a conventional analog multiplexer.

[Explanation of symbols]

1 Input selection circuit 2 amplifier circuit 3 bias circuit 4 Decoder circuit 1a-1d, 3a-3d analog switch R bias resistance C1 coupling capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takao Uchiyama 25-1, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Association In-house (56) References Japanese Patent Publication 1-55763 (JP, B2) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/00-3/72

Claims (5)

(57) [Claims] 1. A plurality of first switch means provided corresponding to each of a plurality of analog signals and switching whether or not to pass the corresponding analog signal, and the analog signal passed through the first switch means. In an analog signal selection circuit including an amplifier circuit for amplifying a signal, a bias circuit for adjusting an input voltage of the amplifier circuit to a desired value based on a reference voltage is provided, and the bias circuit is provided for each of the plurality of first switch means. An analog signal selection circuit, which is connected to an input terminal. 2. The bias circuit is provided so as to correspond to a bias resistor having one end set to the reference voltage and each of the plurality of first switch means, and is linked to the corresponding first switch means. on·
A plurality of second switch means controlled to be turned off, the corresponding analog signals are input to the input terminals of the second switch means, and the output terminals of the second switch means are both bias resistors. The analog signal selection circuit according to claim 1, being connected to the other end of the analog signal selection circuit. 3. Each of the analog signals is input to the corresponding first switch means via a capacitor for removing a DC voltage.
Alternatively, the analog signal selection circuit described in 2. 4. The analog signal selection circuit according to claim 1, wherein each of the first and second switch means is an analog switch. 5. The analog signal selection according to claim 1, wherein the first switch means, the second switch means, the bias resistor and the amplifier circuit are formed on a semiconductor substrate. circuit.