JP2003037202A - Package for accommodating semiconductor element - Google Patents

Package for accommodating semiconductor element

Info

Publication number
JP2003037202A
JP2003037202A JP2001224109A JP2001224109A JP2003037202A JP 2003037202 A JP2003037202 A JP 2003037202A JP 2001224109 A JP2001224109 A JP 2001224109A JP 2001224109 A JP2001224109 A JP 2001224109A JP 2003037202 A JP2003037202 A JP 2003037202A
Authority
JP
Japan
Prior art keywords
semiconductor element
weight
copper
frame
shaped insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001224109A
Other languages
Japanese (ja)
Inventor
Yoshihiro Basho
義博 芭蕉
Masaaki Iguchi
公明 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001224109A priority Critical patent/JP2003037202A/en
Publication of JP2003037202A publication Critical patent/JP2003037202A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent thermal destruction of a semiconductor element caused by inefficient dissipation of generated heat to the outside, when the element is actuated. SOLUTION: The package for accommodation of a semiconductor element 4 includes a substrate 1, a frame-shaped insulator 2 having a wiring layer 6 connected with each electrode of the element 4, and a lid member 3 mounted on the insulator 2 to seal the inside of the insulator 2 airtightly. The insulator 2 is a glass ceramic sintered compact having a relative permittivity of not larger than 7 and a thermal expansion coefficient of 4 to 8 ppm/ deg.C. The wiring layer 6 has electrical resistivity of not larger than 2.5 μΩ.cm. The substrate 1 has a three-layered structure of tungsten and copper, that is, a middle layer 1c containing 70-95 wt.% of tungsten and 5-30 wt.% of copper, and upper and lower layers 1b and 1d provided on upper and lower sides of the middle layer and containing 25-65 wt.% of tungsten and 35-75 wt.% of copper.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はLSI(大規模集積
回路素子)や光半導体素子等の半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element such as an LSI (Large Scale Integrated Circuit Element) or an optical semiconductor element.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは、上面に半導体素子が載置さ
れる載置部を有する銅−タングステン合金や銅−モリブ
デン合金等の金属材料からなる基体と、該基体の上面に
前記載置部を囲繞するようにして取着された酸化アルミ
ニウム質焼結体等の電気絶縁材料からなる枠状絶縁体
と、該枠状絶縁体の内周部から外周部にかけて被着導出
されているタングステン、モリブデン、マンガン等の高
融点金属からなる複数個の配線層と、前記枠状絶縁体の
上面に取着され、絶縁体の内側の穴を塞ぐ蓋体とから構
成されており、基体の半導体素子載置部に半導体素子を
接着剤を介して接着固定するとともに該半導体素子の各
電極をボンディングワイヤを介して枠状絶縁体に形成し
た配線層に電気的に接続し、しかる後、枠状絶縁体に蓋
体を該枠状絶縁体の内側の穴を塞ぐようにしてガラス、
樹脂、ロウ材等から成る封止材を介して接合させ、基体
と枠状絶縁体と蓋体とからなる容器内部に半導体素子を
気密に収容することによって製品としての半導体装置と
なる。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating a semiconductor element is made of a metal material such as a copper-tungsten alloy or a copper-molybdenum alloy having a mounting portion on which the semiconductor element is mounted. A base body, a frame-shaped insulator made of an electrically insulating material such as an aluminum oxide sintered body attached to the upper surface of the base body so as to surround the mounting portion, and an inner peripheral portion of the frame-shaped insulator A plurality of wiring layers made of refractory metal such as tungsten, molybdenum, manganese, etc., which are adhered and led from the outer periphery to the outer peripheral portion, and a lid which is attached to the upper surface of the frame-shaped insulator and closes the hole inside the insulator. The semiconductor element is bonded and fixed to the semiconductor element mounting portion of the base body with an adhesive, and each electrode of the semiconductor element is formed on the wiring layer formed on the frame-shaped insulator through the bonding wire. Electrically Continued, and thereafter, the glass and the lid to the frame-shaped insulating member so as to close the inner hole of the frame-shaped insulator,
A semiconductor device as a product is obtained by joining them through a sealing material made of resin, a brazing material, etc., and hermetically housing the semiconductor element in a container made of a base, a frame-shaped insulator, and a lid.

【0003】なお上述の半導体素子収納用パッケージに
おいては、半導体素子が載置される基体が銅−タングス
テン合金や銅−モリブデン合金等の金属材料で形成され
ており、該銅−タングステン合金や銅−モリブデン合金
等は熱伝導率が約180W/m・Kと高く熱伝導性に優
れていることから基体は半導体素子の作動時に発する熱
を良好に吸収するとともに大気中に良好に放散させるこ
とができ、これによって半導体素子を常に適温とし半導
体素子に熱破壊が発生したり、特性に熱劣化が発生した
りするのを有効に防止している。
In the above-mentioned package for housing a semiconductor element, the base on which the semiconductor element is mounted is made of a metal material such as a copper-tungsten alloy or a copper-molybdenum alloy, and the copper-tungsten alloy or copper-tungsten alloy is used. Since the molybdenum alloy has a high thermal conductivity of about 180 W / m · K and is excellent in thermal conductivity, the base body can well absorb the heat generated during the operation of the semiconductor element and can dissipate it into the atmosphere. As a result, the semiconductor element is always kept at an appropriate temperature, and the semiconductor element is effectively prevented from suffering thermal breakdown or thermal deterioration of its characteristics.

【0004】また上述の半導体素子収納用パッケージの
基体として使用されている銅−タングステン合金や銅−
モリブデン合金はタングステン粉末やモリブデン粉末を
焼成して焼結多孔体を得、次に前記焼結多孔体の空孔内
に溶融させることによって製作されており、例えば、タ
ングステンから成る焼結多孔体に銅を含浸させる場合は
焼結多孔体が75乃至90重量%、銅が10乃至25重
量%の範囲に、モリブデンから成る焼結多孔体に銅を含
浸させる場合は焼結多孔体が80乃至90重量%、銅が
10乃至20重量%の範囲となっている。
Further, copper-tungsten alloys and copper-based materials used as the base body of the above-mentioned package for accommodating semiconductor elements.
The molybdenum alloy is manufactured by firing tungsten powder or molybdenum powder to obtain a sintered porous body, and then melting the sintered porous body in the pores of the sintered porous body. When impregnated with copper, the sintered porous body has a range of 75 to 90% by weight and copper has a range of 10 to 25% by weight. When the sintered porous body made of molybdenum has been impregnated with copper, the sintered porous body has a range of 80 to 90% by weight. % By weight, and copper is in the range of 10 to 20% by weight.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、基体がタ
ングステン粉末やモリブデン粉末を焼成して焼結多孔体
を得るとともに該焼結多孔体の空孔内に溶融させた銅を
含浸させることによって形成されており、前記銅の量を
増加させればさせるほど前記基体の熱伝導率は高くなる
が、それにつれて基体の線熱膨張係数も大きくなる。前
記基体は上面に取着される酸化アルミニウム質焼結体か
ら成る枠状絶縁体の線熱膨張係数(7.0ppm/℃:
室温〜800℃)と大きく相違すると、両者の線熱膨張
係数の相違により発生する応力が両者の接合界面に働
き、該応力により前記接合界面にクラックがはいった
り、ひどい場合には両者の接合界面に剥離が発生したり
して、半導体素子収納用パッケージの気密封止の信頼性
が損なわれ、内部に収容する半導体素子を信頼性よく正
常に作動させることができなくなると言う問題が発生し
てしまうことから、前記基体の線熱膨張係数は前記枠状
絶縁体の線熱膨張係数と近似させる必要があり、前記基
体の銅の含有率は10乃至25重量%(基体が銅−タン
グステン合金から成る場合は銅の含有率は10乃至25
重量%、銅−モリブデン合金から成る場合は銅の含有率
は10乃至20重量%)の範囲に限定されることとな
り、前記基体の熱伝導率は最大でも約180W/m・K
程度であった。
However, in this conventional package for accommodating semiconductor elements, the base body fires tungsten powder or molybdenum powder to obtain a sintered porous body, and the sintered porous body has pores inside. It is formed by impregnating molten copper, and the thermal conductivity of the base increases as the amount of copper increases, but the linear thermal expansion coefficient of the base also increases accordingly. The substrate has a linear thermal expansion coefficient (7.0 ppm / ° C .:
Temperature is different from room temperature to 800 ° C.), the stress generated by the difference in linear thermal expansion coefficient between the two acts on the joint interface between the two, and the stress causes cracks in the joint interface, or in severe cases, the joint interface between the two. If peeling occurs, the reliability of the hermetic sealing of the semiconductor element housing package is impaired, and the problem occurs that the semiconductor elements housed inside cannot be reliably and normally operated. Therefore, it is necessary to approximate the linear thermal expansion coefficient of the base to the linear thermal expansion coefficient of the frame-shaped insulator, and the copper content of the base is 10 to 25% by weight (the base is made of a copper-tungsten alloy). If the content of copper is 10 to 25
In the case of a copper-molybdenum alloy, the content of copper is limited to the range of 10 to 20% by weight, and the thermal conductivity of the substrate is about 180 W / mK at the maximum.
It was about.

【0006】そのためこの従来の半導体素子収納用パッ
ケージ内に近時の高密度化、高集積化が大きく進み、作
動時に多量の熱を発する半導体素子を収容した場合、半
導体素子が作動時に発する熱は基体を介して外部に完全
に放散させることができなくなり、その結果、半導体素
子が該素子自身の発する熱によって高温となり、半導体
素子に熱破壊を招来させたり、特性にばらつきを生じ安
定に作動させることができないという欠点を有してい
た。
Therefore, in the conventional package for accommodating semiconductor elements, the density and the degree of integration have greatly increased in recent years, and when a semiconductor element which generates a large amount of heat during operation is accommodated, the heat generated during operation of the semiconductor element is The semiconductor element cannot be completely diffused to the outside, and as a result, the semiconductor element becomes high temperature due to the heat generated by the element itself, causing thermal damage to the semiconductor element or causing a variation in characteristics to operate stably. It had the drawback of not being able to.

【0007】またこの従来の半導体素子収納用パッケー
ジにおいては、枠状絶縁体を形成する酸化アルミニウム
質焼結体の比誘電率が9〜10(室温、1MHz)と高
いことから枠状絶縁体に設けた配線層を伝わる電気信号
の伝搬速度が遅く、そのため信号の高速伝搬を要求する
半導体素子は収容が不可となる欠点を有していた。
Further, in this conventional package for accommodating semiconductor elements, since the relative permittivity of the aluminum oxide sintered body forming the frame-shaped insulator is as high as 9 to 10 (room temperature, 1 MHz), the frame-shaped insulator is used. The propagation speed of the electric signal transmitted through the provided wiring layer is slow, and therefore, there is a drawback that a semiconductor element that requires high-speed signal propagation cannot be accommodated.

【0008】更にこの従来の半導体素子収納用パッケー
ジにおいては、枠状絶縁体に形成されている配線層はタ
ングステンやモリブデン、マンガン等の高融点金属材料
により形成されており、該タングステン等はその比電気
抵抗が5.4μΩ・cm(20℃)以上と高いことから
配線層に電気信号を伝搬させた場合、電気信号に大きな
減衰が生じ、電気信号を正確、かつ確実に伝搬させるこ
とができないという欠点も有していた。
Further, in this conventional package for accommodating semiconductor elements, the wiring layer formed on the frame-shaped insulator is formed of a refractory metal material such as tungsten, molybdenum, manganese, etc. Since the electric resistance is as high as 5.4 μΩ · cm (20 ° C.) or more, when the electric signal is propagated to the wiring layer, the electric signal is greatly attenuated, and the electric signal cannot be accurately and reliably propagated. It also had drawbacks.

【0009】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に高速駆動を行う半導体素子を収容
することができ、かつ収容する半導体素子を長期間にわ
たり正常、かつ安定に作動させることができる半導体素
子収納用パッケージを提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to accommodate therein a semiconductor element which is driven at high speed, and to operate the accommodated semiconductor element normally and stably for a long period of time. Another object of the present invention is to provide a package for accommodating a semiconductor element.

【0010】[0010]

【課題を解決するための手段】本発明は、上面に半導体
素子が載置される載置部を有する基体と、前記基体上に
半導体素子載置部を囲繞するようにして取着され、半導
体素子の各電極が接続される配線層を有する枠状絶縁体
と、前記枠状絶縁体上に取着され、枠状絶縁体の内側を
気密に封止する蓋体とから成る半導体素子収納用パッケ
ージであって、前記枠状絶縁体は比誘電率が7以下、線
熱膨張係数が4ppm/℃〜8ppm/℃のガラスセラ
ミックス焼結体で、配線層は電気抵抗率が2.5μΩ・
cm以下の金属材料で、基体はタングステンと銅とから
成り、タングステンが70乃至95重量%、銅が5乃至
30重量%から成る中間層の上下両面にタングステンが
25乃至65重量%、銅が35乃至75重量%から成る
上下層を配した3層構造を有していることを特徴とする
ものである。
SUMMARY OF THE INVENTION According to the present invention, a base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the semiconductor element are mounted. A semiconductor element housing comprising a frame-shaped insulator having a wiring layer to which each electrode of the element is connected, and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator In the package, the frame-shaped insulator is a glass-ceramic sintered body having a relative dielectric constant of 7 or less and a linear thermal expansion coefficient of 4 ppm / ° C to 8 ppm / ° C, and the wiring layer has an electric resistivity of 2.5 μΩ.
cm or less, the substrate is composed of tungsten and copper, and the intermediate layer of 70 to 95 wt% tungsten and 5 to 30 wt% tungsten has 25 to 65 wt% tungsten and 35 wt% tungsten. It is characterized by having a three-layer structure in which upper and lower layers made up of 75 to 75% by weight are arranged.

【0011】また本発明は、上面に半導体素子が載置さ
れる載置部を有する基体と、前記基体上に半導体素子載
置部を囲繞するようにして取着され、半導体素子の各電
極が接続される配線層を有する枠状絶縁体と、前記枠状
絶縁体上に取着され、枠状絶縁体の内側を気密に封止す
る蓋体とから成る半導体素子収納用パッケージであっ
て、前記枠状絶縁体は比誘電率が7以下、線熱膨張係数
が4ppm/℃〜8ppm/℃のガラスセラミックス焼
結体で、配線層は電気抵抗率が2.5μΩ・cm以下の
金属材料で、基体はモリブデンと銅とから成り、モリブ
デンが75乃至95重量%、銅が5乃至25重量%から
成る中間層の上下両面にモリブデンが30乃至60重量
%、銅が40乃至70重量%から成る上下層を配した3
層構造を有していることを特徴とするものである。
Further, according to the present invention, a base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion are mounted on the base so as to surround the semiconductor element mounting electrode. A semiconductor element storage package comprising a frame-shaped insulator having a wiring layer to be connected, and a lid body attached to the frame-shaped insulator and hermetically sealing the inside of the frame-shaped insulator, The frame-shaped insulator is a glass ceramics sintered body having a relative dielectric constant of 7 or less and a linear thermal expansion coefficient of 4 ppm / ° C to 8 ppm / ° C, and the wiring layer is made of a metal material having an electrical resistivity of 2.5 μΩ · cm or less. The base is composed of molybdenum and copper, and molybdenum is composed of 30 to 60% by weight and copper is composed of 40 to 70% by weight on the upper and lower surfaces of an intermediate layer composed of 75 to 95% by weight of molybdenum and 5 to 25% by weight of copper. 3 with upper and lower layers
It is characterized by having a layered structure.

【0012】本発明の半導体素子収納用パッケージによ
れば、枠状絶縁体を比誘電率が7以下のガラスセラミッ
クス焼結体で形成したことから枠状絶縁体に設けた配線
層を伝わる電気信号の伝搬速度を速いものとして信号の
高速伝搬を要求する半導体素子の収容が可能となる。
According to the package for accommodating semiconductor elements of the present invention, since the frame-shaped insulator is made of a glass ceramic sintered body having a relative dielectric constant of 7 or less, an electric signal transmitted through the wiring layer provided on the frame-shaped insulator. It is possible to accommodate a semiconductor element that requires high-speed signal propagation with a high propagation speed.

【0013】また本発明の半導体素子収納用パッケージ
によれば、枠状絶縁体を低温焼成(約800℃〜900
℃)が可能なガラスセラミックス焼結体で形成したこと
から枠状絶縁体と同時焼成により形成される配線層を比
電気抵抗が2.5μΩ・cm以下と低い銅や銀、金で形
成することができ、その結果、配線層に電気信号を伝搬
させた場合、電気信号に大きな減衰が生じることはな
く、電気信号を正確、かつ確実に伝搬させることが可能
となる。
According to the package for housing a semiconductor element of the present invention, the frame-shaped insulator is fired at a low temperature (about 800 ° C. to 900 ° C.).
Since it is made of a glass-ceramics sintered body that can be used at a temperature of (.degree. As a result, when an electric signal is propagated to the wiring layer, the electric signal is not attenuated significantly, and the electric signal can be accurately and reliably propagated.

【0014】更に本発明の半導体素子収納用パッケージ
によれば、基体をタングステンが70乃至95重量%、
銅が5乃至30重量%から成る中間層の上下両面にタン
グステンが25乃至65重量%、銅が35乃至75重量
%から成る上下層を配した3層構造、またはモリブデン
が75乃至95重量%、銅が5乃至25重量%から成る
中間層の上下両面にモリブデンが30乃至60重量%、
銅が40乃至70重量%から成る上下層を配した3層構
造となしたことから基体の半導体素子載置部である上層
の熱伝導率を250W/m・K以上の高いものとし、基
体上に載置される半導体素子が作動時に多量の熱を発し
たとしてもその熱は基体の半導体素子載置部で平面方向
に素早く広がらせるとともに基体の上層、中間層、下層
を順次介して外部に効率よく確実に放散させることがで
き、これによって半導体素子は常に適温となり、半導体
素子を長期間にわたり安定かつ正常に作動させることが
可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the base contains 70 to 95% by weight of tungsten,
A three-layer structure in which an upper layer and a lower layer each containing 25 to 65% by weight of tungsten and 35 to 75% by weight of copper are arranged on the upper and lower surfaces of an intermediate layer of 5 to 30% by weight of copper, or 75 to 95% by weight of molybdenum, 30 to 60% by weight of molybdenum on both upper and lower surfaces of the intermediate layer composed of 5 to 25% by weight of copper,
Since the upper and lower layers, which are the semiconductor element mounting portions of the base, have a high thermal conductivity of 250 W / m · K or more, the upper layer of the base has a high thermal conductivity of 250 W / m · K or more. Even if the semiconductor element mounted on the substrate emits a large amount of heat during operation, the heat is quickly spread in the plane direction at the semiconductor element mounting portion of the base body, and the upper layer, the intermediate layer, and the lower layer of the base body are sequentially exposed to the outside. It is possible to efficiently and surely disperse the semiconductor element, whereby the semiconductor element is always kept at an appropriate temperature, and the semiconductor element can be stably and normally operated for a long period of time.

【0015】また更に本発明の半導体素子収納用パッケ
ージによれば、基体をタングステンが70乃至95重量
%、銅が5乃至30重量%から成る中間層の上下両面に
タングステンが25乃至65重量%、銅が35乃至75
重量%から成る上下層を配した3層構造、またモリブデ
ンが75乃至95重量%、銅が5乃至25重量%から成
る中間層の上下両面にモリブデンが30乃至60重量
%、銅が40乃至70重量%から成る上下層を配した3
層構造となし、線熱膨張係数が小さい中間層を線熱膨張
係数の大きい上下層で挟み込むことにより基体全体の線
熱膨張係数を枠状絶縁体の線熱膨張係数に近似させるこ
とができ、その結果、基体上に枠状絶縁体を取着させる
際や半導体素子が作動した際等において基体と枠状絶縁
体の両者に熱が作用したとしても基体と枠状絶縁体との
間には両者の線熱膨張係数の相違に起因する大きな熱応
力が発生することはなく、これによって半導体素子を収
納する空所の気密封止が常に完全となり、半導体素子を
安定かつ正常に作動させることが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the base is an intermediate layer consisting of 70 to 95% by weight of tungsten and 5 to 30% by weight of copper, and 25 to 65% by weight of tungsten is formed on both upper and lower surfaces of the intermediate layer. 35 to 75 copper
A three-layer structure in which upper and lower layers of 50% by weight are arranged, and 30 to 60% by weight of molybdenum and 40 to 70% of copper are provided on both upper and lower surfaces of an intermediate layer of 75 to 95% by weight of molybdenum and 5 to 25% by weight of copper. 3 with upper and lower layers consisting of wt%
With a layered structure, by sandwiching an intermediate layer having a small linear thermal expansion coefficient between upper and lower layers having a large linear thermal expansion coefficient, the linear thermal expansion coefficient of the entire substrate can be approximated to the linear thermal expansion coefficient of the frame-shaped insulator, As a result, even when heat is applied to both the base and the frame-shaped insulator when the frame-shaped insulator is attached to the base or when the semiconductor element is operated, there is a gap between the base and the frame-shaped insulator. Large thermal stress due to the difference in linear thermal expansion coefficient between the two does not occur, and thus the airtight sealing of the space for housing the semiconductor element is always perfect, and the semiconductor element can be operated stably and normally. It will be possible.

【0016】[0016]

【発明の実施の形態】次に、本発明を添付図面に示す実
施例に基づき詳細に説明する。図1は本発明の半導体素
子収納用パッケージの一実施例を示す断面図であり、図
1において、1は基体、2は枠状絶縁体、3は蓋体であ
る。この基体1と枠状絶縁体2と蓋体3とにより内部に
半導体素子4を気密に収容する容器5が構成される。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention. In FIG. 1, 1 is a base, 2 is a frame-shaped insulator, and 3 is a lid. The base 1, the frame-shaped insulator 2 and the lid 3 constitute a container 5 that hermetically houses the semiconductor element 4 therein.

【0017】前記基体1はその上面に半導体素子4が載
置される載置部1aを有するとともに上面外周部に該基
体1の上面に設けた半導体素子4が載置される載置部1
aを囲繞するようにして枠状絶縁体2がロウ材やガラ
ス、樹脂等の接着剤を介して取着されている。
The base 1 has a mounting portion 1a on which the semiconductor element 4 is mounted, and the mounting portion 1 on which the semiconductor element 4 provided on the upper surface of the base 1 is mounted on the outer peripheral portion of the upper surface.
The frame-shaped insulator 2 is attached so as to surround a through an adhesive such as a brazing material, glass, or resin.

【0018】前記基体1は半導体素子4を支持する支持
部材として作用するとともに半導体素子4が作動時に発
する熱を良好に吸収するとともに大気中に効率よく放散
させ、半導体素子4を常に適温とする作用をなし、枠状
絶縁体2に囲まれた基体1の載置部1a上に半導体素子
4がガラス、樹脂、ロウ材等の接着剤を介して固定され
る。
The substrate 1 acts as a support member for supporting the semiconductor element 4, and also absorbs heat generated by the semiconductor element 4 during operation and efficiently dissipates the heat into the atmosphere to keep the semiconductor element 4 at an appropriate temperature. The semiconductor element 4 is fixed on the mounting portion 1a of the base 1 surrounded by the frame-shaped insulator 2 with an adhesive such as glass, resin, or brazing material.

【0019】なお前記基体1はタングステンと銅とから
成り、タングステン粉末を焼成して得られる焼結多孔体
の空孔内に溶融させた銅を含浸させることによって製作
されている。
The substrate 1 is composed of tungsten and copper, and is manufactured by impregnating molten copper into the pores of a sintered porous body obtained by firing tungsten powder.

【0020】また前記基体1の上面外周部には該基体1
の上面に設けた半導体素子4が載置される載置部1aを
囲繞するようにして枠状絶縁体2がロウ材やガラス、樹
脂等の接着剤を介して取着されており、基体1と枠状絶
縁体2とで半導体素子4を収容するための空所が内部に
形成される。
Further, on the outer peripheral portion of the upper surface of the base body 1, the base body 1 is provided.
The frame-shaped insulator 2 is attached via an adhesive such as a brazing material, glass, or resin so as to surround the mounting portion 1a on which the semiconductor element 4 mounted on the upper surface of the base 1 is mounted. With the frame-shaped insulator 2, a space for housing the semiconductor element 4 is formed inside.

【0021】前記基体1に取着される枠状絶縁体2はガ
ラスセラミックス焼結体から成り、具体的には、 1)硼珪酸ガラスにアルミナもしくはムライトを添加し
てなる原料粉末より製作されるガラスセラミックス焼結
体(比誘電率5〜6) 2)コージェライト系結晶化ガラスにアルミナもしくは
ムライトを添加して成る原料粉末より製作されるガラス
セラミックス焼結体(比誘電率5〜6) 3)ムライト系結晶化ガラスにアルミナもしくはムライ
トを添加して成る原料粉末より製作されるガラスセラミ
ックス焼結体(比誘電率5〜6) 等で形成されている。
The frame-shaped insulator 2 attached to the base 1 is made of a glass-ceramics sintered body. Specifically, it is made of 1) a raw material powder obtained by adding alumina or mullite to borosilicate glass. Glass-ceramics sintered body (relative permittivity 5 to 6) 2) Glass-ceramics sintered body (relative permittivity 5 to 6) made from raw material powder made by adding alumina or mullite to cordierite-based crystallized glass 3 ) A glass-ceramic sintered body (having a relative dielectric constant of 5 to 6) made of a raw material powder formed by adding alumina or mullite to mullite-based crystallized glass.

【0022】前記枠状絶縁体2は、例えば、硼珪酸ガラ
スにアルミナもしくはムライトを添加してなる原料粉末
より製作されるガラスセラミックス焼結体から成る場
合、原料粉末の組成が重量比で72〜76%のシリカ、
15〜17%の酸化硼素、2〜4%の酸化アルミニウ
ム、1.5%以下の酸化マグネシウム、1.1〜1.4
%の酸化ジルコニウム、酸化ナトリウム、酸化カリウム
及び酸化リチウムの合計量2.0〜3.0%から成る硼
珪酸ガラス粉末にアルミナ、石英及びコージェライトの
各粉末とアクリル樹脂を主成分とするバインダー及び分
散剤、可塑剤、有機溶媒を加えて泥漿物を作るとともに
該泥漿物をドクターブレード法やカレンダーロール法を
採用することによってグリーンシート(生シート)とな
し、しかる後、前記グリーンシートに適当な打ち抜き加
工を施すとともにこれを複数枚積層し、約800℃〜9
00℃の温度で焼成することによって製作される。
When the frame-shaped insulator 2 is made of, for example, a glass-ceramics sintered body made of a raw material powder obtained by adding alumina or mullite to borosilicate glass, the composition of the raw material powder is 72-70 by weight. 76% silica,
15-17% boron oxide, 2-4% aluminum oxide, 1.5% or less magnesium oxide, 1.1-1.4
% Of zirconium oxide, sodium oxide, potassium oxide and lithium oxide in a total amount of 2.0 to 3.0%, borosilicate glass powder, alumina, quartz and cordierite powder, and a binder containing an acrylic resin as a main component, and A dispersant, a plasticizer, and an organic solvent are added to make a sludge, and the sludge is made into a green sheet (raw sheet) by adopting a doctor blade method or a calendar roll method. Punching is performed and a plurality of these are laminated, and the temperature is about 800 ° C-9
It is manufactured by firing at a temperature of 00 ° C.

【0023】また前記枠状絶縁体2はその内周部から上
部にかけて導出する複数の配線層6が被着形成されてお
り、枠状絶縁体2の内周部に露出する配線層6の一端に
は半導体素子4の各電極がボンディングワイヤ7を介し
て電気的に接続され、また枠状絶縁体2の上面に導出さ
れた部位には外部電気回路と接続される外部リードピン
8が銀ロウ等のロウ材を介してロウ付け取着されてい
る。
A plurality of wiring layers 6 extending from the inner peripheral portion to the upper portion of the frame-shaped insulator 2 are adhered and formed, and one end of the wiring layer 6 exposed at the inner peripheral portion of the frame-shaped insulator 2 is attached. The electrodes of the semiconductor element 4 are electrically connected to each other via the bonding wires 7, and the external lead pins 8 connected to an external electric circuit are connected to an external electric circuit at a portion led out to the upper surface of the frame-shaped insulator 2. It is attached by brazing through the brazing material.

【0024】前記配線層6は半導体素子4の各電極を外
部電気回路に接続する際の導電路として作用し、銅、
銀、金等の金属粉末により形成されている。
The wiring layer 6 acts as a conductive path when connecting each electrode of the semiconductor element 4 to an external electric circuit, and copper,
It is formed of a metal powder such as silver or gold.

【0025】前記配線層6は銅、銀、金等の金属粉末に
適当な有機バインダー、溶剤等を添加混合して得られた
金属ペーストを枠状絶縁体2となるグリーンシートに予
め従来周知のスクリーン印刷法等の印刷法を用いること
により所定パターンに印刷塗布しておくことによって枠
状絶縁体2の内周部から上面にかけて被着形成される。
For the wiring layer 6, a metal paste obtained by adding and mixing a suitable organic binder, a solvent, etc. to a metal powder such as copper, silver, gold or the like is previously known to a green sheet as the frame-shaped insulator 2 in advance. By printing and applying a predetermined pattern by using a printing method such as a screen printing method, the frame-shaped insulator 2 is adhered and formed from the inner peripheral portion to the upper surface.

【0026】前記配線層6を形成する銅、銀、金等はそ
の融点が約1000℃と低いものの枠状絶縁体2を構成
するガラスセラミックス焼結体の焼成温度が低いことか
ら枠状絶縁体2に所定パターンに被着形成することが可
能となる。
Although the melting point of copper, silver, gold, etc. forming the wiring layer 6 is as low as about 1000 ° C., the firing temperature of the glass-ceramics sintered body constituting the frame-shaped insulator 2 is low, so that the frame-shaped insulator is formed. It is possible to deposit and form a predetermined pattern on 2.

【0027】また前記配線層6を形成する銅や銀、金等
はその比電気抵抗が2.5μΩ・cm以下と低いことか
ら配線層6を介して容器内部に収容する半導体素子4と
外部電気回路との間に電気信号の出し入れをしたとして
も配線層6において電気信号が大きく減衰することはな
く、その結果、半導体素子4に正確、かつ確実な駆動を
行わせることができる。
Since the specific electric resistance of copper, silver, gold or the like forming the wiring layer 6 is as low as 2.5 μΩ · cm or less, the semiconductor element 4 housed inside the container via the wiring layer 6 and the external electric Even if an electric signal is taken in and out of the circuit, the electric signal is not greatly attenuated in the wiring layer 6, and as a result, the semiconductor element 4 can be driven accurately and surely.

【0028】更に前記配線層6は、該配線層6の被着さ
れている枠状絶縁体2の比誘電率が7以下(室温、1M
Hz)と低いことから配線層6を伝わる電気信号の伝搬
速度が速いものとなり、その結果、配線層6を介して容
器内部に収容する半導体素子4と外部電気回路との間に
電気信号の出し入れをしたとしても、電気信号の伝搬に
遅延を生じることなく、半導体素子4に正確、かつ確実
に電気信号を出し入れすることができる。
Further, the wiring layer 6 has a relative dielectric constant of 7 or less (at room temperature, 1 M) of the frame-shaped insulator 2 to which the wiring layer 6 is adhered.
Since the electric signal propagates through the wiring layer 6 at a high speed, the electric signal is transmitted and received between the semiconductor element 4 housed inside the container and the external electric circuit via the wiring layer 6. Even if this is done, the electric signal can be accurately and surely taken in and out of the semiconductor element 4 without causing a delay in the propagation of the electric signal.

【0029】なお、前記配線層6は銅や銀からなる場
合、その露出表面に耐蝕性に優れる金属をメッキ法によ
り1μm〜20μmの厚みに被着させておくと、配線層
6の酸化腐蝕を有効に防止することができるとともに配
線層6とボンディングワイヤ7との接続及び配線層6へ
の外部リードピン8の取着を強固となすことができる。
従って、前記配線層6は銅や銀からなる場合、配線層6
の酸化腐蝕を防止し、配線層6とボンディングワイヤ7
及び外部リードピン8との取着を強固とするには配線層
6の露出表面に金等の耐蝕性に優れる金属を1μm〜2
0μmの厚みに被着させておくことが好ましい。
When the wiring layer 6 is made of copper or silver, if a metal having excellent corrosion resistance is deposited on the exposed surface to a thickness of 1 μm to 20 μm by a plating method, the wiring layer 6 will be oxidized and corroded. This can be effectively prevented, and the connection between the wiring layer 6 and the bonding wire 7 and the attachment of the external lead pin 8 to the wiring layer 6 can be strengthened.
Therefore, when the wiring layer 6 is made of copper or silver,
To prevent oxidative corrosion of the wiring layer 6 and the bonding wire 7
In order to strengthen the attachment to the external lead pin 8, a metal having excellent corrosion resistance such as gold is used on the exposed surface of the wiring layer 6 in a range of 1 μm to 2 μm.
It is preferable to deposit it to a thickness of 0 μm.

【0030】また前記枠状絶縁体2に被着した配線層6
にロウ付けされる外部リードピン8は鉄−ニッケル−コ
バルト合金や鉄−ニッケル合金等の金属材料から成り、
半導体素子4の各電極を外部電気回路に電気的に接続す
る作用をなす。
The wiring layer 6 adhered to the frame-shaped insulator 2
The external lead pin 8 brazed to is made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy,
It serves to electrically connect the respective electrodes of the semiconductor element 4 to an external electric circuit.

【0031】前記外部リードピン8は、例えば、鉄−ニ
ッケル−コバルト合金等の金属から成るインゴット
(塊)に圧延加工法や打ち抜き加工法等、従来周知の金
属加工法を施すことによって所定形状に形成される。
The external lead pin 8 is formed in a predetermined shape by subjecting an ingot (lump) made of a metal such as an iron-nickel-cobalt alloy to a conventionally known metal working method such as a rolling working method or a punching working method. To be done.

【0032】本発明の半導体素子収納用パッケージにお
いては、前記基体1をタングステンが70乃至95重量
%、銅が5乃至30重量%から成る中間層1cの上下両
面にタングステンが25乃至65重量%、銅が35乃至
75重量%から成る上下層1b、1dを配した3層構造
としておくことが重要である。
In the package for accommodating semiconductor elements of the present invention, the substrate 1 comprises 25 to 65% by weight of tungsten on the upper and lower surfaces of the intermediate layer 1c comprising 70 to 95% by weight of tungsten and 5 to 30% by weight of copper. It is important to have a three-layer structure in which upper and lower layers 1b and 1d composed of 35 to 75% by weight of copper are arranged.

【0033】前記基体1をタングステンが70乃至95
重量%、銅が5乃至30重量%から成る中間層1cの上
下両面にタングステンが25乃至65重量%、銅が35
乃至75重量%から成る上下層1b、1dを配した3層
構造としたことから基体1の半導体素子載置部1aであ
る上層1bの熱伝導率を250W/m・K以上の高いも
のとし、基体1上に載置される半導体素子4が作動時に
多量の熱を発したとしてもその熱は基体1の半導体素子
載置部1a平面方向に素早く広がらせるとともに基体1
の上層1b、中間層1c、下層1dを順次介して外部に
効率よく確実に放散させることができ、これによって半
導体素子4は常に適温となり、半導体素子4を長期間に
わたり安定かつ正常に作動させることが可能となる。
The substrate 1 is made of tungsten 70 to 95.
% Of tungsten and 5 to 30% by weight of copper, 25 to 65% by weight of tungsten and 35% of copper on the upper and lower surfaces of the intermediate layer 1c.
Since the upper layer 1b, which is the semiconductor element mounting portion 1a of the base 1, has a high thermal conductivity of 250 W / m · K or higher, the upper layer 1b of the base 1 has a high thermal conductivity of 250 W / m · K or more. Even if the semiconductor element 4 mounted on the base 1 generates a large amount of heat during operation, the heat is quickly spread in the plane direction of the semiconductor element mounting portion 1a of the base 1 and the base 1
The upper layer 1b, the intermediate layer 1c, and the lower layer 1d can be sequentially and efficiently diffused to the outside, whereby the semiconductor element 4 is always kept at an appropriate temperature, and the semiconductor element 4 can be stably and normally operated for a long period of time. Is possible.

【0034】また前記基体1はタングステンが70乃至
95重量%、銅が5乃至30重量%から成る中間層1c
の上下両面にタングステンが25乃至65重量%、銅が
35乃至75重量%から成る上下層1b、1dを配した
3層構造となし、線熱膨張係数が小さい中間層1cを線
熱膨張係数の大きい上下層1b、1dで挟み込み基体1
全体の線熱膨張係数を枠状絶縁体2の線熱膨張係数に近
似させたことから、基体1上に枠状絶縁体2を取着させ
る際や半導体素子4が作動した際において基体1と枠状
絶縁体2の両者に熱が作用したとしても基体1と枠状絶
縁体2との間には両者の線熱膨張係数の相違に起因する
大きな熱応力が発生することはなく、これによって半導
体素子4を収納する空所の気密封止が常に完全となり、
半導体素子4を安定かつ正常に作動させることが可能と
なる。
The substrate 1 is an intermediate layer 1c composed of 70 to 95% by weight of tungsten and 5 to 30% by weight of copper.
It has a three-layer structure in which upper and lower layers 1b and 1d composed of 25 to 65% by weight of tungsten and 35 to 75% by weight of copper are arranged on both upper and lower sides of the intermediate layer 1c having a small linear thermal expansion coefficient. Substrate 1 sandwiched between large upper and lower layers 1b and 1d
Since the coefficient of linear thermal expansion of the whole is approximated to the coefficient of linear thermal expansion of the frame-shaped insulator 2, when the frame-shaped insulator 2 is attached onto the substrate 1 or when the semiconductor element 4 operates, Even if heat acts on both of the frame-shaped insulators 2, a large thermal stress due to the difference in linear thermal expansion coefficient between the base 1 and the frame-shaped insulator 2 does not occur between them. The airtight sealing of the space for housing the semiconductor element 4 is always complete,
It is possible to operate the semiconductor element 4 stably and normally.

【0035】なお前記基体1はその中間層1cのタング
ステンの量が70重量%未満の場合、或いは95重量%
を超えた場合、基体1の線熱膨張係数が枠状絶縁体2の
線熱膨張係数に対して大きく相違することとなり、その
結果、基体1に枠状絶縁体2を強固に取着させておくこ
とができなくなってしまう。従って、前記基体1の中間
層1cはそれを形成するタングステンの量は70乃至9
5重量%の範囲に特定される。
The substrate 1 has an intermediate layer 1c in which the amount of tungsten is less than 70% by weight, or 95% by weight.
If it exceeds, the coefficient of linear thermal expansion of the base body 1 greatly differs from the coefficient of linear thermal expansion of the frame-shaped insulator 2, and as a result, the frame-shaped insulator 2 is firmly attached to the base body 1. I can't keep it. Therefore, the amount of tungsten forming the intermediate layer 1c of the substrate 1 is 70-9.
It is specified in the range of 5% by weight.

【0036】また前記上下層1b、1dのタングステン
の量が25重量%未満となると、言い換えれば銅が75
重量%を超えると、基体1の線熱膨張係数が枠状絶縁体
2の線熱膨張係数に対して大きく相違して基体1に枠状
絶縁体2を強固に取着させておくことができなくなって
しまい、またタングステンの量が65重量%を超える
と、言い換えれば銅が35重量%未満となると上下層1
b、1dの熱伝導率を250W/m・K以上の高いもの
と成すことができず、半導体素子4が作動時に多量の熱
を発した場合、その熱を基体1を介して外部に完全に放
散させることができなくなり、その結果、半導体素子4
を高温として、半導体素子4に熱破壊を招来させたり、
特性にばらつきが生じ安定に作動させることができなく
なってしまう。従って前記基体1の上下層1b、1dは
タングステンが25乃至65重量%、銅が35乃至75
重量%に特定される。
If the amount of tungsten in the upper and lower layers 1b and 1d is less than 25% by weight, in other words, the amount of copper is 75%.
If it exceeds 5% by weight, the linear thermal expansion coefficient of the substrate 1 is greatly different from the linear thermal expansion coefficient of the frame-shaped insulator 2, so that the frame-shaped insulator 2 can be firmly attached to the substrate 1. When the amount of tungsten exceeds 65% by weight, that is, when the amount of copper is less than 35% by weight, the upper and lower layers 1
When the thermal conductivity of b and 1d cannot be made as high as 250 W / m · K or more and the semiconductor element 4 generates a large amount of heat during operation, the heat is completely transmitted to the outside through the base body 1. Cannot be dissipated, and as a result, the semiconductor device 4
To a high temperature to cause thermal damage to the semiconductor element 4,
The characteristics vary, and it becomes impossible to operate stably. Therefore, the upper and lower layers 1b and 1d of the base 1 are made of 25 to 65% by weight of tungsten and 35 to 75% of copper.
Specified in% by weight.

【0037】更に前記上下層1b、1dはその組成、厚
みを略同一に形成しておくと上層1bと中間層1cの間
に発生する応力と、下層1dと中間層1cとの間に発生
する応力が相殺されて基体1の平坦度が良好となり、そ
の結果、基体1に枠状絶縁体2を極めて強固に接合させ
ることができ、容器5の気密封止の信頼性をより確実な
ものとして、容器5内部に収納する半導体素子4の作動
信頼性を安定、確実なものと成すことができる。
Further, if the upper and lower layers 1b and 1d are formed to have substantially the same composition and thickness, the stress generated between the upper layer 1b and the intermediate layer 1c and the stress generated between the lower layer 1d and the intermediate layer 1c. The flatness of the substrate 1 is improved by offsetting the stress, and as a result, the frame-shaped insulator 2 can be bonded to the substrate 1 extremely firmly, and the reliability of the hermetic sealing of the container 5 is further ensured. The operation reliability of the semiconductor element 4 housed in the container 5 can be made stable and reliable.

【0038】また更に前記上下層1b、1dと中間層1
cの厚みは前記上下層1b、1dの厚みをX、中間層1
cの厚みをYとした場合、0.5Y≦X≦Yの範囲とし
ておくと基体1を介して半導体素子4の発する熱をより
良好に外部に放散することができる。前記上下層1b、
1dの厚みをX、中間層1cの厚みをYとした場合、
0.5Y>Xとなると250W/m・K以上の高熱伝導
率である上下層1b、1dが薄くなり半導体素子4の発
する熱を外部に効率よく放散することができなくなる危
険性があり、Y<Xとなると線熱膨張係数の大きな上下
層の基体1全体に及ぼす影響が大きくなり、基体1の線
熱膨張係数を前記枠状絶縁体2の線熱膨張係数と近似さ
せることが困難となる危険性があることから、前記上下
層1b、1dと中間層1cの厚みは前記上下層1b、1
dの厚みをX、中間層1cの厚みをYとした場合、0.
5Y≦X≦Yの範囲が望ましい。
Furthermore, the upper and lower layers 1b and 1d and the intermediate layer 1
c is the thickness of the upper and lower layers 1b and 1d, and X is the thickness of the intermediate layer 1.
When the thickness of c is Y, the heat generated by the semiconductor element 4 via the base 1 can be radiated to the outside better by setting the range of 0.5Y ≦ X ≦ Y. The upper and lower layers 1b,
When the thickness of 1d is X and the thickness of the intermediate layer 1c is Y,
If 0.5Y> X, the upper and lower layers 1b and 1d having a high thermal conductivity of 250 W / m · K or more become thin and there is a risk that the heat generated by the semiconductor element 4 cannot be efficiently dissipated to the outside. When <X, the influence on the entire upper and lower base bodies 1 having a large linear thermal expansion coefficient becomes large, and it becomes difficult to approximate the linear thermal expansion coefficient of the base body 1 to the linear thermal expansion coefficient of the frame-shaped insulator 2. Since there is a risk, the thicknesses of the upper and lower layers 1b and 1d and the intermediate layer 1c are the same as the upper and lower layers 1b and 1d.
When the thickness of d is X and the thickness of the intermediate layer 1c is Y, 0.
The range of 5Y ≦ X ≦ Y is desirable.

【0039】なお前記3層構造の基体1は、中間層1c
となる所定量のタングステン焼結体に所定量の銅を含浸
させた所定厚みの板体と、上下層1b、1dとなる所定
量のタングステン焼結体に所定量の銅を含浸させた所定
厚みの板体とを準備し、前記中間層1cとなる板体の上
下を上下層となる板体で挟み込んだ後、銅の溶融温度
(1083℃)より20℃程度高い温度にて真空中もし
くは中性、還元雰囲気中で加圧しながら積層することに
よって製作される。
The substrate 1 having the three-layer structure is the intermediate layer 1c.
A plate body having a predetermined thickness obtained by impregnating a predetermined amount of tungsten sintered body with a predetermined amount of copper, and a predetermined thickness obtained by impregnating a predetermined amount of tungsten sintered body serving as the upper and lower layers 1b and 1d with a predetermined amount of copper. And the upper and lower plates of the intermediate layer 1c are sandwiched between the upper and lower plates, and then in a vacuum or in a medium at a temperature about 20 ° C. higher than the melting temperature of copper (1083 ° C.). It is manufactured by stacking under pressure in a reducing atmosphere.

【0040】かくして上述の半導体素子収納用パッケー
ジによれば、基体1の半導体素子載置部1a上に半導体
素子4をガラス、樹脂、ロウ材等の接着剤を介して接着
固定するとともに該半導体素子4の各電極をボンディン
グワイヤ7を介して所定の配線層6に接続させ、しかる
後、前記枠状絶縁体2の上面に蓋体3をガラス、樹脂、
ロウ材等から成る封止材を介して接合させ、基体1、枠
状絶縁体2及び蓋体3とから成る容器5内部に半導体素
子4を気密に収容することによって製品としての半導体
装置となる。
Thus, according to the above-mentioned package for housing a semiconductor element, the semiconductor element 4 is adhered and fixed on the semiconductor element mounting portion 1a of the base body 1 via an adhesive such as glass, resin, or brazing material, and the semiconductor element is mounted. Each electrode 4 is connected to a predetermined wiring layer 6 through a bonding wire 7, and then the lid 3 is attached to the upper surface of the frame-shaped insulator 2 with glass, resin,
A semiconductor device as a product is obtained by airtightly housing the semiconductor element 4 inside a container 5 made up of a base body 1, a frame-shaped insulator 2 and a lid body 3 by joining them through a sealing material made of a brazing material or the like. .

【0041】次に本発明の他の実施例について説明す
る。
Next, another embodiment of the present invention will be described.

【0042】上述の半導体素子収納用パッケージでは基
体1をタングステンが70乃至95重量%、銅が5乃至
30重量%から成る中間層1cの上下両面にタングステ
ンが25乃至65重量%、銅が35乃至75重量%から
成る上下層1b、1dを配した3層構造としたが、これ
をモリブデンが75乃至95重量%、銅が5乃至25重
量%から成る中間層1cの上下両面にモリブデンが30
乃至60重量%、銅が40乃至70重量%から成る上下
層1b、1dを配した3層構造としてもよい。前記基体
1をモリブデンが75乃至95重量%、銅が5乃至25
重量%から成る中間層1cの上下両面にモリブデンが3
0乃至60重量%、銅が40乃至70重量%から成る上
下層1b、1dを配した3層構造とした場合、基体1の
半導体素子載置部1aである上層1bの熱伝導率を25
0W/m・K以上の高いものとし、基体1上に載置され
る半導体素子4が作動時に多量の熱を発したとしてもそ
の熱は基体1の半導体素子載置部1aで平面方向に素早
く広がらせるとともに基体1の上層1b、中間層1c、
下層1dを順次介して外部に効率よく確実に放散させる
ことができ、これによって半導体素子4は常に適温とな
り、半導体素子4を長期間にわたり安定かつ正常に作動
させることが可能となる。
In the above-mentioned package for accommodating semiconductor elements, the base 1 is 25 to 65% by weight of tungsten and 35 to 65% by weight of tungsten on the upper and lower surfaces of the intermediate layer 1c composed of 70 to 95% by weight of tungsten and 5 to 30% by weight of copper. The upper and lower layers 1b and 1d made up of 75% by weight are arranged in a three-layer structure, and this is composed of 75 to 95% by weight of molybdenum and 5 to 25% by weight of copper.
It is also possible to have a three-layer structure in which the upper and lower layers 1b and 1d composed of 60 to 60% by weight and 40 to 70% by weight of copper are arranged. The substrate 1 contains 75 to 95% by weight of molybdenum and 5 to 25 of copper.
3% molybdenum is formed on both upper and lower surfaces of the intermediate layer 1c, which is made up by weight.
When the upper and lower layers 1b and 1d composed of 0 to 60% by weight and 40 to 70% by weight of copper are arranged in a three-layer structure, the thermal conductivity of the upper layer 1b which is the semiconductor element mounting portion 1a of the substrate 1 is 25%.
Even if the semiconductor element 4 mounted on the base 1 emits a large amount of heat during operation, the heat is swift in the plane direction in the semiconductor element mounting portion 1a of the base 1. The upper layer 1b of the substrate 1, the intermediate layer 1c,
The lower layer 1d can be sequentially and efficiently dissipated to the outside, whereby the semiconductor element 4 is always kept at an appropriate temperature, and the semiconductor element 4 can be stably and normally operated for a long period of time.

【0043】また前記モリブデンが75乃至95重量
%、銅が5乃至25重量%から成る中間層1cの上下両
面にモリブデンが30乃至60重量%、銅が40乃至7
0重量%から成る上下層1b、1dを配した3層構造の
基体1は線熱膨張係数が小さい中間層1cを線熱膨張係
数の大きい上下層1b、1dで挟み込み基体1全体の線
熱膨張係数を枠状絶縁体2の線熱膨張係数に近似させた
ことから基体1上に枠状絶縁体2を取着させる際や半導
体素子4が作動した際において基体1と枠状絶縁体2の
両者に熱が作用したとしても基体1と枠状絶縁体2との
間には両者の線熱膨張係数の相違に起因する大きな熱応
力が発生することはなく、これによって半導体素子4を
収納する空所の気密封止が常に完全となり、半導体素子
4を安定かつ正常に作動させることが可能となる。
Further, molybdenum is 30 to 60% by weight and copper is 40 to 7 on both upper and lower surfaces of the intermediate layer 1c composed of 75 to 95% by weight of molybdenum and 5 to 25% by weight of copper.
The base body 1 having a three-layer structure in which the upper and lower layers 1b and 1d of 0 wt% are arranged has the intermediate layer 1c having a small linear thermal expansion coefficient sandwiched between the upper and lower layers 1b and 1d having a large linear thermal expansion coefficient, and the linear thermal expansion of the entire base body 1 is performed. Since the coefficient is approximated to the linear thermal expansion coefficient of the frame-shaped insulator 2, when the frame-shaped insulator 2 is attached onto the substrate 1 or when the semiconductor element 4 is operated, the base 1 and the frame-shaped insulator 2 are separated. Even if heat is applied to both, a large thermal stress due to the difference in linear thermal expansion coefficient between the base 1 and the frame-shaped insulator 2 does not occur, and the semiconductor element 4 is housed thereby. The airtight sealing of the void is always complete, and the semiconductor element 4 can be stably and normally operated.

【0044】なお前記基体1はその中間層1cのモリブ
デンの量が75重量%未満の場合、或いは95重量%を
超えた場合、基体1の線熱膨張係数が枠状絶縁体2の線
熱膨張係数に対して大きく相違することとなり、その結
果、基体1に枠状絶縁体2を強固に取着させておくこと
ができなくなってしまう。従って、前記基体1の中間層
1cはそれを形成するモリブデンの量は75乃至95重
量%の範囲に特定される。
When the amount of molybdenum in the intermediate layer 1c of the substrate 1 is less than 75% by weight or exceeds 95% by weight, the coefficient of linear thermal expansion of the substrate 1 is linear thermal expansion of the frame-shaped insulator 2. This greatly differs from the coefficient, and as a result, the frame-shaped insulator 2 cannot be firmly attached to the base body 1. Therefore, the amount of molybdenum forming the intermediate layer 1c of the substrate 1 is specified in the range of 75 to 95% by weight.

【0045】また前記上下層1b、1dのモリブデンの
量が30重量%未満となると、言い換えれば銅が70重
量%を超えると、基体1の線熱膨張係数が枠状絶縁体2
の線熱膨張係数に対して大きく相違して、基体1に枠状
絶縁体2を強固に取着させておくことができなくなって
しまい、またモリブデンの量が60重量%を超えると、
言い換えれば銅が40重量%未満となると上下層1b、
1dの熱伝導率を250W/m・K以上の高いものと成
すことができず、半導体素子4が作動時に多量の熱を発
した場合、その熱を基体1を介して外部に完全に放散さ
せることができなくなり、その結果、半導体素子4を高
温として、半導体素子4に熱破壊を招来させたり、特性
にばらつきが生じ安定に作動させることができなくなっ
てしまう。従って前記基体1の上下層1b、1dはモリ
ブデンが30乃至60重量%、銅が40乃至70重量%
に特定される。
When the amount of molybdenum in the upper and lower layers 1b and 1d is less than 30% by weight, in other words, when the amount of copper exceeds 70% by weight, the coefficient of linear thermal expansion of the substrate 1 is the frame-shaped insulator 2.
The coefficient of linear thermal expansion is significantly different from that of the frame-shaped insulator 2 and it becomes impossible to firmly attach the frame-shaped insulator 2 to the substrate 1. If the amount of molybdenum exceeds 60% by weight,
In other words, when the copper content is less than 40% by weight, the upper and lower layers 1b,
When the thermal conductivity of 1d cannot be made as high as 250 W / m · K or more and the semiconductor element 4 generates a large amount of heat during operation, the heat is completely dissipated to the outside through the base body 1. As a result, the semiconductor element 4 is heated to a high temperature, causing thermal damage to the semiconductor element 4 or variation in characteristics, which makes it impossible to operate the semiconductor element 4 stably. Therefore, the upper and lower layers 1b and 1d of the substrate 1 contain molybdenum of 30 to 60% by weight and copper of 40 to 70% by weight.
Specified in.

【0046】更に前記上下層1b、1dはその組成、厚
みを略同一に形成しておくと上層1bと中間層1cの間
に発生する応力と、下層1dと中間層1cとの間に発生
する応力が相殺されて、基体1の平坦度が良好となり、
その結果、基体1に枠状絶縁体2を極めて強固に接合さ
せることができ、容器5の気密封止の信頼性をより確実
なものとして、容器5内部に収納する半導体素子4の作
動信頼性を安定、確実なものと成すことができる。
Further, if the upper and lower layers 1b and 1d are formed to have substantially the same composition and thickness, the stress generated between the upper layer 1b and the intermediate layer 1c and the stress generated between the lower layer 1d and the intermediate layer 1c. The stress is canceled out, and the flatness of the substrate 1 is improved,
As a result, the frame-shaped insulator 2 can be bonded to the base body 1 extremely firmly, and the reliability of the hermetic sealing of the container 5 is further ensured, and the operation reliability of the semiconductor element 4 housed inside the container 5 is improved. Can be stable and reliable.

【0047】また更に前記上下層1b、1dと中間層1
cの厚みは前記上下層1b、1dの厚みをX、中間層1
cの厚みをYとした場合、0.5Y≦X≦Yの範囲とし
ておくと基体1を介して半導体素子4の発する熱をより
良好に外部に放散することができる。前記上下層1b、
1dの厚みをX、中間層1cの厚みをYとした場合、
0.5Y>Xとなると250W/m・K以上の高熱伝導
率である上下層1b、1dが薄くなり半導体素子4の発
する熱を外部に効率よく放散することができなくなる危
険性があり、Y<Xとなると線熱膨張係数の大きな上下
層の基体1全体に及ぼす影響が大きくなり、基体1の線
熱膨張係数を前記枠状絶縁体2の線熱膨張係数と近似さ
せることが困難となる危険性があることから、前記上下
層1b、1dと中間層1cの厚みは前記上下層1b、1
dの厚みをX、中間層1cの厚みをYとした場合、0.
5Y≦X≦Yの範囲が望ましい。
Furthermore, the upper and lower layers 1b and 1d and the intermediate layer 1
c is the thickness of the upper and lower layers 1b and 1d, and X is the thickness of the intermediate layer 1.
When the thickness of c is Y, the heat generated by the semiconductor element 4 via the base 1 can be radiated to the outside better by setting the range of 0.5Y ≦ X ≦ Y. The upper and lower layers 1b,
When the thickness of 1d is X and the thickness of the intermediate layer 1c is Y,
If 0.5Y> X, the upper and lower layers 1b and 1d having a high thermal conductivity of 250 W / m · K or more become thin and there is a risk that the heat generated by the semiconductor element 4 cannot be efficiently dissipated to the outside. When <X, the influence on the entire upper and lower base bodies 1 having a large linear thermal expansion coefficient becomes large, and it becomes difficult to approximate the linear thermal expansion coefficient of the base body 1 to the linear thermal expansion coefficient of the frame-shaped insulator 2. Since there is a risk, the thicknesses of the upper and lower layers 1b and 1d and the intermediate layer 1c are the same as the upper and lower layers 1b and 1d.
When the thickness of d is X and the thickness of the intermediate layer 1c is Y, 0.
The range of 5Y ≦ X ≦ Y is desirable.

【0048】なお前記3層構造の基体1は、中間層1c
となる所定量のモリブデン焼結体に所定量の銅を含浸さ
せた所定厚みの板体と、上下層1b、1dとなる所定量
のモリブデン焼結体に所定量の銅を含浸させた所定厚み
の板体とを準備し、前記中間層となる板体の上下を上下
層となる板体で挟み込んだ後、銅の溶融温度(1083
℃)より20℃程度高い温度にて真空中もしくは中性、
還元雰囲気中で加圧しながら積層することによって製作
される。
The substrate 1 having the three-layer structure is the intermediate layer 1c.
A plate body having a predetermined thickness obtained by impregnating a predetermined amount of molybdenum sintered body with a predetermined amount of copper and a predetermined thickness obtained by impregnating a predetermined amount of molybdenum sintered body serving as the upper and lower layers 1b and 1d with a predetermined amount of copper. And the upper and lower plates of the intermediate layer are sandwiched by the plate layers of the upper and lower layers, and then the melting temperature of copper (1083
In vacuum or at a temperature about 20 ° C higher than
It is manufactured by stacking under pressure in a reducing atmosphere.

【0049】また、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.

【0050】[0050]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、枠状絶縁体を比誘電率が7以下のガラスセラミ
ックス焼結体で形成したことから枠状絶縁体に設けた配
線層を伝わる電気信号の伝搬速度を速いものとして信号
の高速伝搬を要求する半導体素子の収容が可能となる。
According to the package for accommodating a semiconductor element of the present invention, the frame-shaped insulator is formed of a glass ceramic sintered body having a relative dielectric constant of 7 or less, so that the wiring layer provided on the frame-shaped insulator is transmitted. It is possible to accommodate a semiconductor element that requires high-speed signal propagation by increasing the electrical signal propagation speed.

【0051】また本発明の半導体素子収納用パッケージ
によれば、枠状絶縁体を低温焼成(約800℃〜900
℃)が可能なガラスセラミックス焼結体で形成したこと
から枠状絶縁体と同時焼成により形成される配線層を比
電気抵抗が2.5μΩ・cm以下と低い銅や銀、金で形
成することができ、その結果、配線層に電気信号を伝搬
させた場合、電気信号に大きな減衰が生じることはな
く、電気信号を正確、かつ確実に伝搬させることが可能
となる。
According to the package for housing a semiconductor element of the present invention, the frame-shaped insulator is fired at a low temperature (about 800 ° C. to 900 ° C.).
Since it is made of a glass-ceramics sintered body that can be used at a temperature of (.degree. As a result, when an electric signal is propagated to the wiring layer, the electric signal is not attenuated significantly, and the electric signal can be accurately and reliably propagated.

【0052】更に本発明の半導体素子収納用パッケージ
によれば、基体をタングステンが70乃至95重量%、
銅が5乃至30重量%から成る中間層の上下両面にタン
グステンが25乃至65重量%、銅が35乃至75重量
%から成る上下層を配した3層構造、またはモリブデン
が75乃至95重量%、銅が5乃至25重量%から成る
中間層の上下両面にモリブデンが30乃至60重量%、
銅が40乃至70重量%から成る上下層を配した3層構
造となしたことから基体の半導体素子載置部である上層
の熱伝導率を250W/m・K以上の高いものとし、基
体上に載置される半導体素子が作動時に多量の熱を発し
たとしてもその熱は基体の半導体素子載置部で平面方向
に素早く広がらせるとともに基体の上層、中間層、下層
を順次介して外部に効率よく確実に放散させることがで
き、これによって半導体素子は常に適温となり、半導体
素子を長期間にわたり安定かつ正常に作動させることが
可能となる。
Further, according to the package for accommodating semiconductor elements of the present invention, the base contains 70 to 95% by weight of tungsten,
A three-layer structure in which an upper layer and a lower layer each containing 25 to 65% by weight of tungsten and 35 to 75% by weight of copper are arranged on the upper and lower surfaces of an intermediate layer of 5 to 30% by weight of copper, or 75 to 95% by weight of molybdenum, 30 to 60% by weight of molybdenum on both upper and lower surfaces of the intermediate layer composed of 5 to 25% by weight of copper,
Since the upper and lower layers, which are the semiconductor element mounting portions of the base, have a high thermal conductivity of 250 W / m · K or more, the upper layer of the base has a high thermal conductivity of 250 W / m · K or more. Even if the semiconductor element mounted on the substrate emits a large amount of heat during operation, the heat is quickly spread in the plane direction at the semiconductor element mounting portion of the base body, and the upper layer, the intermediate layer, and the lower layer of the base body are sequentially exposed to the outside. It is possible to efficiently and surely disperse the semiconductor element, whereby the semiconductor element is always kept at an appropriate temperature, and the semiconductor element can be stably and normally operated for a long period of time.

【0053】また更に本発明の半導体素子収納用パッケ
ージによれば、基体をタングステンが70乃至95重量
%、銅が5乃至30重量%から成る中間層の上下両面に
タングステンが25乃至65重量%、銅が35乃至75
重量%から成る上下層を配した3層構造、またモリブデ
ンが75乃至95重量%、銅が5乃至25重量%から成
る中間層の上下両面にモリブデンが30乃至60重量
%、銅が40乃至70重量%から成る上下層を配した3
層構造となし、線熱膨張係数が小さい中間層を線熱膨張
係数の大きい上下層で挟み込むことにより基体全体の線
熱膨張係数を枠状絶縁体の線熱膨張係数に近似する4.
0ppm/℃乃至8.0ppm/℃(室温〜800℃)
となすことができ、その結果、基体上に枠状絶縁体を取
着させる際や半導体素子が作動した際において基体と枠
状絶縁体の両者に熱が作用したとしても基体と枠状絶縁
体との間には両者の線熱膨張係数の相違に起因する大き
な熱応力が発生することはなく、これによって半導体素
子を収納する空所の気密封止が常に完全となり、半導体
素子を安定かつ正常に作動させることが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the base is an intermediate layer consisting of 70 to 95% by weight of tungsten and 5 to 30% by weight of copper, and 25 to 65% by weight of tungsten on the upper and lower surfaces of the intermediate layer. 35 to 75 copper
A three-layer structure in which upper and lower layers of 50% by weight are arranged, and 30 to 60% by weight of molybdenum and 40 to 70% of copper are provided on both upper and lower surfaces of an intermediate layer of 75 to 95% by weight of molybdenum and 5 to 25% by weight of copper. 3 with upper and lower layers consisting of wt%
3. It has a layered structure, and an intermediate layer having a small coefficient of linear thermal expansion is sandwiched by upper and lower layers having a large coefficient of linear thermal expansion to approximate the coefficient of linear thermal expansion of the entire substrate to the coefficient of linear thermal expansion of the frame-shaped insulator.
0 ppm / ° C to 8.0 ppm / ° C (room temperature to 800 ° C)
As a result, even when heat is applied to both the base and the frame-shaped insulator when the frame-shaped insulator is attached to the base or when the semiconductor element is operated, the base and the frame-shaped insulator are There is no large thermal stress due to the difference in the linear thermal expansion coefficient between the two, and this ensures that the air-tight seal of the space that houses the semiconductor element is always perfect, and the semiconductor element is stable and normal. Can be activated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・基体 1a・・・・載置部 1b・・・・上層 1c・・・・中間層 1d・・・・下層 2・・・・・枠状絶縁体 3・・・・・蓋体 4・・・・・半導体素子 5・・・・・容器 6・・・・・配線層 7・・・・・ボンディングワイヤ 8・・・・・外部リードピン 1 ... Base 1a ... ・ Mounting part 1b ... upper layer 1c ... Middle layer 1d ... Lower layer 2 ... Frame-shaped insulator 3 ... Lid 4 ... Semiconductor element 5 ... Container 6 ... Wiring layer 7 ... Bonding wire 8: External lead pin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子が載置される載置部を有
する基体と、前記基体上に半導体素子載置部を囲繞する
ようにして取着され、半導体素子の各電極が接続される
配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着
され、枠状絶縁体の内側を気密に封止する蓋体とから成
る半導体素子収納用パッケージであって、前記枠状絶縁
体は比誘電率が7以下、線熱膨張係数が4ppm/℃〜
8ppm/℃のガラスセラミックス焼結体で、配線層は
電気抵抗率が2.5μΩ・cm以下の金属材料で、基体
はタングステンと銅とから成り、タングステンが70乃
至95重量%、銅が5乃至30重量%から成る中間層の
上下両面にタングステンが25乃至65重量%、銅が3
5乃至75重量%から成る上下層を配した3層構造を有
していることを特徴とする半導体素子収納用パッケー
ジ。
1. A base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the semiconductor element, and each electrode of the semiconductor element is connected. A package for accommodating a semiconductor element, comprising: a frame-shaped insulator having a wiring layer; and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator. The insulator has a relative permittivity of 7 or less and a linear thermal expansion coefficient of 4 ppm / ° C.
It is a glass-ceramics sintered body of 8 ppm / ° C., the wiring layer is a metal material having an electric resistivity of 2.5 μΩ · cm or less, and the base is made of tungsten and copper. Tungsten is 70 to 95% by weight and copper is 5 to 5 wt%. 25 to 65% by weight of tungsten and 3% of copper on the upper and lower surfaces of the intermediate layer consisting of 30% by weight.
A package for accommodating a semiconductor element, which has a three-layer structure in which upper and lower layers of 5 to 75% by weight are arranged.
【請求項2】上面に半導体素子が載置される載置部を有
する基体と、前記基体上に半導体素子載置部を囲繞する
ようにして取着され、半導体素子の各電極が接続される
配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着
され、枠状絶縁体の内側を気密に封止する蓋体とから成
る半導体素子収納用パッケージであって、前記枠状絶縁
体は比誘電率が7以下、線熱膨張係数が4ppm/℃〜
8ppm/℃のガラスセラミックス焼結体で、配線層は
電気抵抗率が2.5μΩ・cm以下の金属材料で、基体
はモリブデンと銅とから成り、モリブデンが75乃至9
5重量%、銅が5乃至25重量%から成る中間層の上下
両面にモリブデンが30乃至60重量%、銅が40乃至
70重量%から成る上下層を配した3層構造を有してい
ることを特徴とする半導体素子収納用パッケージ。
2. A base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the base, and each electrode of the semiconductor element is connected. A package for accommodating a semiconductor element, comprising: a frame-shaped insulator having a wiring layer; and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator. The insulator has a relative permittivity of 7 or less and a linear thermal expansion coefficient of 4 ppm / ° C.
It is a glass-ceramics sintered body of 8 ppm / ° C., the wiring layer is a metal material having an electric resistivity of 2.5 μΩ · cm or less, and the substrate is made of molybdenum and copper.
It has a three-layer structure in which upper and lower layers of molybdenum of 30 to 60% by weight and copper of 40 to 70% by weight are disposed on both upper and lower surfaces of an intermediate layer of 5% by weight and 5 to 25% by weight of copper. A package for semiconductor device storage characterized by.
JP2001224109A 2001-07-25 2001-07-25 Package for accommodating semiconductor element Pending JP2003037202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001224109A JP2003037202A (en) 2001-07-25 2001-07-25 Package for accommodating semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001224109A JP2003037202A (en) 2001-07-25 2001-07-25 Package for accommodating semiconductor element

Publications (1)

Publication Number Publication Date
JP2003037202A true JP2003037202A (en) 2003-02-07

Family

ID=19057331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001224109A Pending JP2003037202A (en) 2001-07-25 2001-07-25 Package for accommodating semiconductor element

Country Status (1)

Country Link
JP (1) JP2003037202A (en)

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