JP3748399B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements Download PDF

Info

Publication number
JP3748399B2
JP3748399B2 JP2001314224A JP2001314224A JP3748399B2 JP 3748399 B2 JP3748399 B2 JP 3748399B2 JP 2001314224 A JP2001314224 A JP 2001314224A JP 2001314224 A JP2001314224 A JP 2001314224A JP 3748399 B2 JP3748399 B2 JP 3748399B2
Authority
JP
Japan
Prior art keywords
semiconductor element
frame
insulator
copper
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001314224A
Other languages
Japanese (ja)
Other versions
JP2003124375A (en
Inventor
伸 松田
公明 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001314224A priority Critical patent/JP3748399B2/en
Publication of JP2003124375A publication Critical patent/JP2003124375A/en
Application granted granted Critical
Publication of JP3748399B2 publication Critical patent/JP3748399B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明はLSI(大規模集積回路素子)や光半導体素子等の半導体素子を収容するための半導体素子収納用パッケージに関するものである。
【0002】
【従来の技術】
従来、半導体素子を収容するための半導体素子収納用パッケージは、上面に半導体素子が載置される載置部を有する銅−タングステン合金や銅−モリブデン合金等の金属材料からなる基体と、該基体の上面に前記載置部を囲繞するようにして取着された酸化アルミニウム質焼結体等の電気絶縁材料からなる枠状絶縁体と、該枠状絶縁体の内周部から外周部にかけて被着導出されているタングステン、モリブデン、マンガン等の高融点金属からなる複数個の配線層と、前記枠状絶縁体の上面に取着され、絶縁体の内側の穴を塞ぐ蓋体とから構成されており、基体の半導体素子載置部に半導体素子を接着剤を介して接着固定するとともに該半導体素子の各電極をボンディングワイヤを介して枠状絶縁体に形成した配線層に電気的に接続し、しかる後、枠状絶縁体に蓋体を該枠状絶縁体の内側の穴を塞ぐようにしてガラス、樹脂、ロウ材等から成る封止材を介して接合させ、基体と枠状絶縁体と蓋体とからなる容器内部に半導体素子を気密に収容することによって製品としての半導体装置となる。
【0003】
なお上述の半導体素子収納用パッケージにおいては、半導体素子が載置される基体が銅−タングステン合金や銅−モリブデン合金等の金属材料で形成されており、該銅−タングステン合金や銅−モリブデン合金等は熱伝導率が約180W/m・Kと高く熱伝導性に優れていることから基体は半導体素子の作動時に発する熱を良好に吸収するとともに大気中に良好に放散させることができ、これによって半導体素子を常に適温とし半導体素子に熱破壊が発生したり、特性に熱劣化が発生したりするのを有効に防止している。
【0004】
また上述の半導体素子収納用パッケージの基体として使用されている銅−タングステン合金や銅−モリブデン合金はタングステン粉末やモリブデン粉末を焼成して焼結多孔体を得、次に前記焼結多孔体の空孔内に溶融させることによって製作されており、例えば、タングステンから成る焼結多孔体に銅を含浸させる場合は焼結多孔体が75乃至90重量%、銅が10乃至25重量%の範囲に、モリブデンから成る焼結多孔体に銅を含浸させる場合は焼結多孔体が80乃至90重量%、銅が10乃至20重量%の範囲となっている。
【0005】
【発明が解決しようとする課題】
しかしながら、この従来の半導体素子収納用パッケージにおいては、基体がタングステン粉末やモリブデン粉末を焼成して焼結多孔体を得るとともに該焼結多孔体の空孔内に溶融させた銅を含浸させることによって形成されており、前記銅の量を増加させればさせるほど前記基体の熱伝導率は高くなるが、それにつれて基体の線熱膨張係数も大きくなる。前記基体は上面に取着される酸化アルミニウム質焼結体から成る枠状絶縁体の線熱膨張係数(7ppm/℃:室温〜800℃)と大きく相違すると、両者の線熱膨張係数の相違により発生する応力が両者の接合界面に働き、該応力により前記接合界面にクラックがはいったり、ひどい場合には両者の接合界面に剥離が発生したりして、半導体素子収納用パッケージの気密封止の信頼性が損なわれ、内部に収容する半導体素子を信頼性よく正常に作動させることができなくなると言う問題が発生してしまうことから、前記基体の線熱膨張係数は前記枠状絶縁体の線熱膨張係数と近似させる必要があり、前記基体の銅の含有率は10乃至25重量%(基体が銅−タングステン合金から成る場合は銅の含有率は10乃至25重量%、銅−モリブデン合金から成る場合は銅の含有率は10乃至20重量%)の範囲に限定されることとなり、前記基体の熱伝導率は最大でも約180W/m・K程度であった。
【0006】
そのためこの従来の半導体素子収納用パッケージ内に近時の高密度化、高集積化が大きく進み、作動時に多量の熱を発する半導体素子を収容した場合、半導体素子が作動時に発する熱は基体を介して外部に完全に放散させることができなくなり、その結果、半導体素子が該素子自身の発する熱によって高温となり、半導体素子に熱破壊を招来させたり、特性にばらつきを生じ安定に作動させることができないという欠点を有していた。
【0007】
またこの従来の半導体素子収納用パッケージにおいては、枠状絶縁体を形成する酸化アルミニウム質焼結体の比誘電率が9〜10(室温、1MHz)と高いことから枠状絶縁体に設けた配線層を伝わる電気信号の伝搬速度が遅く、そのため信号の高速伝搬を要求する半導体素子は収容が不可となる欠点を有していた。
【0008】
更にこの従来の半導体素子収納用パッケージにおいては、枠状絶縁体に形成されている配線層はタングステンやモリブデン、マンガン等の高融点金属材料により形成されており、該タングステン等はその比電気抵抗が5.4μΩ・cm(20℃)以上と高いことから配線層に電気信号を伝搬させた場合、電気信号に大きな減衰が生じ、電気信号を正確、かつ確実に伝搬させることができないという欠点も有していた。
【0009】
本発明は上記欠点に鑑み案出されたもので、その目的は内部に高速駆動を行う半導体素子を収容することができ、かつ収容する半導体素子を長期間にわたり正常、かつ安定に作動させることができる半導体素子収納用パッケージを提供することにある。
【0010】
【課題を解決するための手段】
本発明は、上面に半導体素子が載置される載置部を有する基体と、前記基体上に半導体素子載置部を囲繞するようにして取着され、半導体素子の各電極が接続される配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着され、枠状絶縁体の内側を気密に封止する蓋体とから成る半導体素子収納用パッケージであって、前記枠状絶縁体は比誘電率が7以下、熱膨張係数が4ppm/℃〜8ppm/℃のガラスセラミックス焼結体で、前記配線層は電気抵抗率が2.5μΩ・cm(20℃)以下の金属材料で、前記基体は65乃至95重量%の炭化珪素と、5乃至35重量%の銅とで形成されており、溶融した銅に炭化珪素粉末が分散混入されて形成されたものであることを特徴とするものである。
【0011】
本発明の半導体素子収納用パッケージによれば、枠状絶縁体を比誘電率が7以下のガラスセラミックス焼結体で形成したことから枠状絶縁体に設けた配線層を伝わる電気信号の伝搬速度を速いものとして信号の高速伝搬を要求する半導体素子の収容が可能となる。
【0012】
また本発明の半導体素子収納用パッケージによれば、枠状絶縁体を低温焼成(約800℃〜900℃)が可能なガラスセラミックス焼結体で形成したことから枠状絶縁体と同時焼成により形成される配線層を比電気抵抗が2.5μΩ・cm(20℃)以下と低い銅や銀、金で形成することができ、その結果、配線層に電気信号を伝搬させた場合、電気信号に大きな減衰が生じることはなく、電気信号を正確、かつ確実に伝搬させることが可能となる。
【0013】
更に本発明の半導体素子収納用パッケージによれば、基体を炭化珪素が65乃至95重量%、銅が5乃至35重量%とで形成し熱伝導率を230W/m・K以上の高いものとなしたことから、基体上に載置される半導体素子が作動時に多量の熱を発したとしてもその熱は基体の半導体素子載置部平面方向に素早く広がらせるとともに基体の厚さ方向に良好に伝搬させて外部に効率よく確実に放散させることができ、これによって半導体素子は常に適温となり、半導体素子を長期間にわたり安定かつ正常に作動させることが可能となる。
【0014】
また更に本発明の半導体素子収納用パッケージによれば、基体を65乃至95重量%の炭化珪素と、5乃至35重量%の銅とで形成し、その線熱膨張係数をガラスセラミックス焼結体から成る枠状絶縁体の線熱膨張係数(ppm/℃乃至8ppm/℃:室温〜800℃)に近似するものとなしたことから基体上に枠状絶縁体を取着させる際や半導体素子が作動した際等において基体と枠状絶縁体の両者に熱が作用したとしても基体と枠状絶縁体との間には両者の線熱膨張係数の相違に起因する大きな熱応力が発生することはなく、これによって半導体素子を収納する空所の気密封止が常に完全となり、半導体素子を安定かつ正常に作動させることが可能となる。
【0015】
【発明の実施の形態】
次に、本発明を添付図面に示す実施例に基づき詳細に説明する。
図1は本発明の半導体素子収納用パッケージの一実施例を示す断面図であり、図1において、1は基体、2は枠状絶縁体、3は蓋体である。この基体1と枠状絶縁体2と蓋体3とにより内部に半導体素子4を気密に収容する容器5が構成される。
【0016】
前記基体1はその上面に半導体素子4が載置される載置部1aを有するとともに上面外周部に該基体1の上面に設けた半導体素子4が載置される載置部1aを囲繞するようにして枠状絶縁体2がロウ材やガラス、樹脂等の接着剤を介して取着されている。
【0017】
前記基体1は半導体素子4を支持する支持部材として作用するとともに半導体素子4が作動時に発する熱を良好に吸収して大気中に効率よく放散させ、半導体素子4を常に適温とする作用をなし、枠状絶縁体2に囲まれた基体1の載置部1a上に半導体素子4がガラス、樹脂、ロウ材等の接着剤を介して固定される。
【0018】
なお前記基体1は炭化珪素と銅とから成り、溶融させた銅に平均粒径5μm程度の炭化珪素粉末を分散混入させることによって製作されている。
【0019】
また前記基体1の上面外周部には該基体1の上面に設けた半導体素子4が載置される載置部1aを囲繞するようにして枠状絶縁体2がロウ材やガラス、樹脂等の接着剤を介して取着されており、基体1と枠状絶縁体2とで半導体素子4を収容するための空所が内部に形成される。
【0020】
前記基体1に取着される枠状絶縁体2は比誘電率が7以下のガラスセラミックス焼結体(線熱膨張係数:ppm/℃乃至8ppm/℃)から成り、具体的には、
1)硼珪酸ガラスにアルミナもしくはムライトを添加してなる原料粉末より製作されるガラスセラミックス焼結体(比誘電率5〜6)
2)コージェライト系結晶化ガラスにアルミナもしくはムライトを添加して成る原料粉末より製作されるガラスセラミックス焼結体(比誘電率5〜6)
3)ムライト系結晶化ガラスにアルミナもしくはムライトを添加して成る原料粉末より製作されるガラスセラミックス焼結体(比誘電率5〜6)
等で形成されている。
【0021】
前記枠状絶縁体2は、例えば、硼珪酸ガラスにアルミナもしくはムライトを添加してなる原料粉末より製作されるガラスセラミックス焼結体から成る場合、原料粉末の組成が重量比で72〜76%のシリカ、15〜17%の酸化硼素、2〜4%の酸化アルミニウム、1.5%以下の酸化マグネシウム、1.1〜1.4%の酸化ジルコニウム、酸化ナトリウム、酸化カリウム及び酸化リチウムの合計量2.0〜3.0%から成る硼珪酸ガラス粉末にアルミナもしくはムライトの各粉末とアクリル樹脂を主成分とするバインダー及び分散剤、可塑剤、有機溶媒を加えて泥漿物を作るとともに該泥漿物をドクターブレード法やカレンダーロール法を採用することによってグリーンシート(生シート)となし、しかる後、前記グリーンシートに適当な打ち抜き加工を施すとともにこれを複数枚積層し、約800℃〜900℃の温度で焼成することによって製作される。
【0022】
また前記枠状絶縁体2はその内周部から上部にかけて導出する複数の配線層6が被着形成されており、枠状絶縁体2の内周部に露出する配線層6の一端には半導体素子4の各電極がボンディングワイヤ7を介して電気的に接続され、また枠状絶縁体2の上面に導出された部位には外部電気回路と接続される外部リードピン8が銀ロウ等のロウ材を介してロウ付け取着されている。
【0023】
前記配線層6は半導体素子4の各電極を外部電気回路に接続する際の導電路として作用し、銅、銀、金等の金属粉末により形成されている。
【0024】
前記配線層6は銅、銀、金等の金属粉末に適当な有機バインダー、溶剤等を添加混合して得られた金属ペーストを枠状絶縁体2となるグリーンシートに予め従来周知のスクリーン印刷法等の印刷法を用いることにより所定パターンに印刷塗布しておくことによって枠状絶縁体2の内周部から上面にかけて被着形成される。
【0025】
前記配線層6を形成する銅、銀、金等はその融点が約1000℃と低いものの枠状絶縁体2を構成するガラスセラミックス焼結体の焼成温度が低いことから枠状絶縁体2に所定パターンに被着形成することが可能となる。
【0026】
また前記配線層6を形成する銅や銀、金等はその比電気抵抗が2.5μΩ・cm以下と低いことから配線層6を介して容器内部に収容する半導体素子4と外部電気回路との間に電気信号の出し入れをしたとしても配線層6において電気信号が大きく減衰することはなく、その結果、半導体素子4に正確、かつ確実な駆動を行わせることができる。
【0027】
更に前記配線層6は、該配線層6の被着されている枠状絶縁体2の比誘電率が7以下(室温、1MHz)、好適には5.5〜6と低いことから配線層6を伝わる電気信号の伝搬速度が速いものとなり、その結果、配線層6を介して容器内部に収容する半導体素子4と外部電気回路との間に電気信号の出し入れをしたとしても、電気信号の伝搬に遅延を生じることなく、半導体素子4に正確、かつ確実に電気信号を出し入れすることができる。
【0028】
なお、前記配線層6は銅や銀からなる場合、その露出表面に耐蝕性に優れる金属をメッキ法により1μm〜20μmの厚みに被着させておくと、配線層6の酸化腐蝕を有効に防止することができるとともに配線層6とボンディングワイヤ7との接続及び配線層6への外部リードピン8の取着を強固となすことができる。従って、前記配線層6は銅や銀からなる場合、配線層6の酸化腐蝕を防止し、配線層6とボンディングワイヤ7及び外部リードピン8との取着を強固とするには配線層6の露出表面に金等の耐蝕性に優れる金属を1μm〜20μmの厚みに被着させておくことが好ましい。
【0029】
また前記枠状絶縁体2に被着した配線層6にロウ付けされる外部リードピン8は鉄−ニッケル−コバルト合金や鉄−ニッケル合金等の金属材料から成り、半導体素子4の各電極を外部電気回路に電気的に接続する作用をなす。
【0030】
前記外部リードピン8は、例えば、鉄−ニッケル−コバルト合金等の金属から成るインゴット(塊)に圧延加工法や打ち抜き加工法等、従来周知の金属加工法を施すことによって所定形状に形成される。
【0031】
本発明の半導体素子収納用パッケージにおいては、前記基体1を65乃至95重量%の炭化珪素と、5乃至35重量%の銅とで形成しておくことが重要である。
【0032】
前記基体1を65乃至95重量%の炭化珪素と、5乃至35重量%の銅とで形成しておくと基体1の熱伝導率を230W/m・K以上の高いものなり、その結果、基体1上に載置される半導体素子4が作動時に多量の熱を発したとしてもその熱は基体1の半導体素子載置部1a平面方向に素早く広がらせるとともに基体1の厚さ方向を良好に伝搬させて外部に効率よく確実に放散させることができ、これによって半導体素子4は常に適温となり、半導体素子4を長期間にわたり安定かつ正常に作動させることが可能となる。
【0033】
また上述の65乃至95重量%の炭化珪素と、5乃至35重量%の銅とから成る基体1はその線熱膨張係数がガラスセラミックス焼結体から成る枠状絶縁体2の線熱膨張係数(ppm/℃乃至8ppm/℃:室温〜800℃)に近似する6ppm/℃乃至8ppm/℃となり、その結果、基体1上に枠状絶縁体2を取着させる際や半導体素子4が作動した際において基体1と枠状絶縁体2の両者に熱が作用したとしても基体1と枠状絶縁体2との間には両者の線熱膨張係数の相違に起因する大きな熱応力が発生することはなく、これによって半導体素子4を収納する空所の気密封止が常に完全となり、半導体素子4を安定かつ正常に作動させることが可能となる。
【0034】
なお前記基体1は炭化珪素の量が65重量%未満となると、言い換えれば銅が35重量%を超えると基体1の線熱膨張係数が枠状絶縁体2の線熱膨張係数に対して大きく相違することとなり、その結果、基体1に枠状絶縁体2を強固に取着させておくことができなくなってしまい、また炭化珪素の量が95重量%を超えると、言い換えれば銅が5重量%未満となると基体1の熱伝導率が大きく劣化し、半導体素子4が作動時に多量の熱を発した場合、その熱を基体1を介して外部に完全に放散させることができなくなり、その結果、半導体素子4を高温として半導体素子4に熱破壊を招来させたり、特性にばらつきが生じ安定に作動させることができなくなってしまう。従って、前記基体1は炭化珪素の量が65乃至95重量%の範囲に、銅の量が5乃至35重量%の範囲に特定される。
【0035】
また前記65乃至95重量%の炭化珪素と、5乃至35重量%の銅とから成る基体1は炭化珪素の表面に酸化物膜、例えばSiO2等の膜を0.05μm乃至1μm程度の厚みに被着させておけば炭化珪素と銅との密着強度が大きく向上して基体1としての信頼性が大幅に向上する。従って前記基体1は表面に酸化物膜を0.05μm乃至1μmの厚みに被着させた炭化珪素と銅とで形成しておくことが好ましい。
【0036】
前記炭化珪素の表面に酸化物膜を被着させる方法としては、例えば、炭化珪素の粉末を大気中で約1200℃の温度で加熱することによって行われる。
【0037】
更に、前記基体1は溶融させた銅に炭化珪素粉末を分散混入させて形成した場合、基体1のヤング率が銅のヤング率に依存する100GPa程度の軟質なものとなり、その結果、基体1上に半導体素子4を載置させた後、基体1と半導体素子4に熱が作用して両者間に熱応力が発生したとしても、その熱応力は基体1を若干変形させることによって効率よく吸収され、半導体素子4が基体1より剥離したり、半導体素子4に割れやクラックを発生したりすることがなく、半導体素子4を常に正常かつ安定に作動させることができる。
【0038】
かくして上述の半導体素子収納用パッケージによれば、基体1の半導体素子載置部1a上に半導体素子4をガラス、樹脂、ロウ材等の接着剤を介して接着固定するとともに該半導体素子4の各電極をボンディングワイヤ7を介して所定の配線層6に接続させ、しかる後、前記枠状絶縁体2の上面に蓋体3をガラス、樹脂、ロウ材等から成る封止材を介して接合させ、基体1、枠状絶縁体2及び蓋体3とから成る容器5内部に半導体素子4を気密に収容することによって製品としての半導体装置となる。
【0039】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【0040】
【発明の効果】
本発明の半導体素子収納用パッケージによれば、枠状絶縁体を比誘電率が7以下のガラスセラミックス焼結体で形成したことから枠状絶縁体に設けた配線層を伝わる電気信号の伝搬速度を速いものとして信号の高速伝搬を要求する半導体素子の収容が可能となる。
【0041】
また本発明の半導体素子収納用パッケージによれば、枠状絶縁体を低温焼成(約800℃〜900℃)が可能なガラスセラミックス焼結体で形成したことから枠状絶縁体と同時焼成により形成される配線層を比電気抵抗が2.5μΩ・cm(20℃)以下と低い銅や銀、金で形成することができ、その結果、配線層に電気信号を伝搬させた場合、電気信号に大きな減衰が生じることはなく、電気信号を正確、かつ確実に伝搬させることが可能となる。
【0042】
更に本発明の半導体素子収納用パッケージによれば、基体を炭化珪素が65乃至95重量%、銅が5乃至35重量%とで形成し熱伝導率を230W/m・K以上の高いものとなしたことから、基体上に載置される半導体素子が作動時に多量の熱を発したとしてもその熱は基体の半導体素子載置部平面方向に素早く広がらせるとともに基体の厚さ方向に良好に伝搬させて外部に効率よく確実に放散させることができ、これによって半導体素子は常に適温となり、半導体素子を長期間にわたり安定かつ正常に作動させることが可能となる。
【0043】
また更に本発明の半導体素子収納用パッケージによれば、基体を65乃至95重量%の炭化珪素と、5乃至35重量%の銅とで形成し、その線熱膨張係数をガラスセラミックス焼結体から成る枠状絶縁体の線熱膨張係数(ppm/℃乃至8ppm/℃:室温〜800℃)に近似するものとなしたことから基体上に枠状絶縁体を取着させる際や半導体素子が作動した際等において基体と枠状絶縁体の両者に熱が作用したとしても基体と枠状絶縁体との間には両者の線熱膨張係数の相違に起因する大きな熱応力が発生することはなく、これによって半導体素子を収納する空所の気密封止が常に完全となり、半導体素子を安定かつ正常に作動させることが可能となる。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージの一実施例を示す断面図である。
【符号の説明】
1・・・・・基体
1a・・・・載置部
2・・・・・枠状絶縁体
3・・・・・蓋体
4・・・・・半導体素子
5・・・・・容器
6・・・・・配線層
7・・・・・ボンディングワイヤ
8・・・・・外部リードピン
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element housing package for housing semiconductor elements such as LSIs (Large Scale Integrated Circuit Elements) and optical semiconductor elements.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a package for housing a semiconductor element for housing a semiconductor element includes a base made of a metal material such as a copper-tungsten alloy or a copper-molybdenum alloy having a placement portion on which the semiconductor element is placed, and the base. A frame-like insulator made of an electrically insulating material such as an aluminum oxide sintered body attached so as to surround the mounting portion on the upper surface of the frame, and a covering from the inner peripheral portion to the outer peripheral portion of the frame-like insulator. A plurality of wiring layers made of refractory metals such as tungsten, molybdenum, and manganese, and a lid that is attached to the upper surface of the frame-like insulator and closes a hole inside the insulator. The semiconductor element is bonded and fixed to the semiconductor element mounting portion of the base via an adhesive, and each electrode of the semiconductor element is electrically connected to a wiring layer formed on the frame-like insulator via a bonding wire. Sir The base body, the frame-like insulator, and the lid body are joined to the frame-like insulator through a sealing material made of glass, resin, brazing material or the like so as to close the hole inside the frame-like insulator. A semiconductor device as a product is obtained by airtightly housing a semiconductor element in a container formed of
[0003]
In the semiconductor element storage package described above, the base on which the semiconductor element is placed is formed of a metal material such as a copper-tungsten alloy or a copper-molybdenum alloy, and the copper-tungsten alloy, copper-molybdenum alloy, or the like. Has a high thermal conductivity of about 180 W / m · K and is excellent in thermal conductivity, so that the substrate can absorb the heat generated during the operation of the semiconductor element and dissipate it well into the atmosphere. The semiconductor element is always kept at an appropriate temperature, and it is possible to effectively prevent the semiconductor element from being thermally destroyed and the characteristics from being thermally deteriorated.
[0004]
The copper-tungsten alloy or copper-molybdenum alloy used as the base of the above-mentioned package for housing semiconductor elements is obtained by firing tungsten powder or molybdenum powder to obtain a sintered porous body, and then emptying the sintered porous body. For example, when impregnating copper into a sintered porous body made of tungsten, the sintered porous body is in the range of 75 to 90% by weight and copper is in the range of 10 to 25% by weight. When the sintered porous body made of molybdenum is impregnated with copper, the sintered porous body is in the range of 80 to 90% by weight and copper is in the range of 10 to 20% by weight.
[0005]
[Problems to be solved by the invention]
However, in this conventional package for housing semiconductor elements, the substrate is obtained by firing a tungsten powder or molybdenum powder to obtain a sintered porous body, and impregnating the molten copper into the pores of the sintered porous body. As the amount of copper is increased, the thermal conductivity of the substrate increases, but the linear thermal expansion coefficient of the substrate increases accordingly. The substrate is greatly different from the linear thermal expansion coefficient (7 ppm / ° C .: room temperature to 800 ° C.) of the frame-like insulator made of the aluminum oxide sintered body attached to the upper surface. The generated stress acts on the joint interface between the two, and the stress causes cracks in the joint interface or, if it is severe, peeling occurs on the joint interface between the two. Since the reliability is impaired and the problem that the semiconductor element accommodated in the semiconductor device cannot be operated normally with high reliability occurs, the linear thermal expansion coefficient of the base body is the wire of the frame-like insulator. It is necessary to approximate the thermal expansion coefficient, and the copper content of the base is 10 to 25% by weight (if the base is made of a copper-tungsten alloy, the copper content is 10 to 25% by weight, copper-molybdenum If made of gold content in copper will be limited to a range of 10 to 20 wt%), the thermal conductivity of the base was about 180 W / m · K at most.
[0006]
For this reason, in the conventional package for storing semiconductor elements, the recent increase in density and integration has greatly progressed, and when semiconductor elements that generate a large amount of heat during operation are accommodated, the heat generated during operation of the semiconductor elements passes through the substrate. As a result, the semiconductor element becomes high temperature due to the heat generated by the element itself, resulting in thermal destruction of the semiconductor element or variation in characteristics, which makes it impossible to operate stably. Had the disadvantages.
[0007]
Further, in this conventional package for housing semiconductor elements, since the relative permittivity of the aluminum oxide sintered body forming the frame-like insulator is as high as 9 to 10 (room temperature, 1 MHz), the wiring provided on the frame-like insulator The propagation speed of the electric signal transmitted through the layers is slow, so that a semiconductor element that requires high-speed signal propagation has the disadvantage that it cannot be accommodated.
[0008]
Further, in this conventional package for housing semiconductor elements, the wiring layer formed on the frame-like insulator is formed of a refractory metal material such as tungsten, molybdenum, manganese, etc., which has a specific electric resistance. Since the electrical signal is propagated to the wiring layer due to its high value of 5.4 μΩ · cm (20 ° C.) or more, there is a disadvantage that the electrical signal is greatly attenuated and the electrical signal cannot be propagated accurately and reliably. Was.
[0009]
The present invention has been devised in view of the above drawbacks, and its purpose is to accommodate a semiconductor element that can be driven at a high speed inside, and to operate the accommodated semiconductor element normally and stably over a long period of time. An object of the present invention is to provide a package for housing a semiconductor element.
[0010]
[Means for Solving the Problems]
The present invention provides a base having a mounting portion on which a semiconductor element is mounted on an upper surface, and a wiring that is attached on the base so as to surround the semiconductor element mounting portion and to which each electrode of the semiconductor element is connected A package for housing a semiconductor element, comprising: a frame-like insulator having a layer; and a lid attached on the frame-like insulator and hermetically sealing an inner side of the frame-like insulator, body relative dielectric constant of 7 or less, the thermal expansion coefficient of a glass ceramic sintered body of 4ppm / ℃ ~8ppm / ℃, the wiring layer is electrical resistivity in 2.5μΩ · cm (20 ℃) following metallic materials the substrate is a 65 to 95 wt% of silicon carbide is formed by a 5 to 35 wt% of copper, der Rukoto which silicon carbide powder is formed by dispersedly mixed in the molten copper It is a feature.
[0011]
According to the package for housing a semiconductor element of the present invention, since the frame-like insulator is formed of a glass ceramic sintered body having a relative dielectric constant of 7 or less, the propagation speed of the electric signal transmitted through the wiring layer provided on the frame-like insulator. Therefore, it is possible to accommodate a semiconductor element that requires high-speed signal propagation.
[0012]
Further, according to the package for housing a semiconductor element of the present invention, the frame-shaped insulator is formed of a glass ceramic sintered body capable of low-temperature firing (about 800 ° C. to 900 ° C.). The wiring layer can be formed of copper, silver, or gold having a specific electric resistance of 2.5 μΩ · cm (20 ° C.) or less, and as a result, when an electric signal is propagated to the wiring layer, Large attenuation does not occur, and the electric signal can be propagated accurately and reliably.
[0013]
Further, according to the package for housing a semiconductor element of the present invention, the substrate is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper, and has a high thermal conductivity of 230 W / m · K or more. Therefore, even if the semiconductor element mounted on the base generates a large amount of heat during operation, the heat spreads quickly in the plane direction of the semiconductor element mounting portion of the base and propagates well in the thickness direction of the base. Thus, the semiconductor element can be efficiently and reliably dissipated to the outside, whereby the semiconductor element always has an appropriate temperature, and the semiconductor element can be stably and normally operated over a long period of time.
[0014]
Furthermore, according to the package for housing a semiconductor element of the present invention, the substrate is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper, and the linear thermal expansion coefficient is determined from the glass ceramic sintered body. The linear thermal expansion coefficient ( 4 ppm / ° C. to 8 ppm / ° C .: room temperature to 800 ° C.) of the frame-shaped insulator is obtained. Even when heat is applied to both the base and the frame insulator during operation, a large thermal stress is generated between the base and the frame insulator due to the difference in linear thermal expansion coefficient between the two. As a result, the hermetic sealing of the space for housing the semiconductor element is always complete, and the semiconductor element can be operated stably and normally.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail based on embodiments shown in the accompanying drawings.
FIG. 1 is a cross-sectional view showing an embodiment of a package for housing a semiconductor element of the present invention. In FIG. 1, 1 is a base, 2 is a frame insulator, and 3 is a lid. The base body 1, the frame-like insulator 2, and the lid body 3 constitute a container 5 that contains the semiconductor element 4 in an airtight manner.
[0016]
The base body 1 has a mounting portion 1a on which the semiconductor element 4 is mounted, and surrounds the mounting portion 1a on which the semiconductor element 4 provided on the upper surface of the base body 1 is mounted on the outer periphery of the upper surface. Thus, the frame-like insulator 2 is attached via an adhesive such as brazing material, glass, or resin.
[0017]
The base body 1 acts as a support member for supporting the semiconductor element 4 and absorbs heat generated when the semiconductor element 4 is activated, efficiently dissipates it into the atmosphere, and makes the semiconductor element 4 always have an appropriate temperature. The semiconductor element 4 is fixed on the mounting portion 1a of the base body 1 surrounded by the frame-like insulator 2 through an adhesive such as glass, resin, or brazing material.
[0018]
Note the substrate 1 is composed of a silicon carbide and copper, are manufactured work by the fact of dispersing mixing silicon carbide powder having an average particle diameter of 5μm to copper is molten.
[0019]
The frame-like insulator 2 is made of brazing material, glass, resin or the like so as to surround the mounting portion 1a on which the semiconductor element 4 provided on the upper surface of the substrate 1 is mounted on the outer periphery of the upper surface of the substrate 1. A space for accommodating the semiconductor element 4 is formed in the base 1 and the frame-like insulator 2 by being attached via an adhesive.
[0020]
The frame-like insulator 2 attached to the substrate 1 is composed of a glass ceramic sintered body (linear thermal expansion coefficient: 4 ppm / ° C. to 8 ppm / ° C.) having a relative dielectric constant of 7 or less.
1) Glass ceramics sintered body (relative dielectric constant 5-6) manufactured from raw material powder made by adding alumina or mullite to borosilicate glass
2) Glass ceramics sintered body (relative dielectric constant 5-6) manufactured from raw material powder made by adding alumina or mullite to cordierite crystallized glass
3) Sintered glass ceramics (relative dielectric constant 5-6) manufactured from raw material powder made by adding alumina or mullite to mullite crystallized glass
Etc. are formed.
[0021]
For example, when the frame-like insulator 2 is made of a glass ceramic sintered body manufactured from a raw material powder obtained by adding alumina or mullite to borosilicate glass, the composition of the raw material powder is 72 to 76% by weight. Total amount of silica, 15-17% boron oxide, 2-4% aluminum oxide, 1.5% or less magnesium oxide, 1.1-1.4% zirconium oxide, sodium oxide, potassium oxide and lithium oxide A borosilicate glass powder composed of 2.0 to 3.0% is added with a binder, a dispersant, a plasticizer, and an organic solvent mainly composed of alumina or mullite powder and an acrylic resin to form a slurry. By adopting a doctor blade method or a calendar roll method, a green sheet (raw sheet) is formed, and then suitable for the green sheet. This laminating a plurality together subjected to blanking Chi is fabricated by firing at a temperature of about 800 ° C. to 900 ° C..
[0022]
The frame-like insulator 2 has a plurality of wiring layers 6 led out from the inner periphery to the upper portion thereof, and is attached to one end of the wiring layer 6 exposed at the inner periphery of the frame-like insulator 2. Each electrode of the element 4 is electrically connected via a bonding wire 7, and an external lead pin 8 connected to an external electric circuit is connected to an external electric circuit at a portion led out to the upper surface of the frame-like insulator 2. It is attached by brazing.
[0023]
The wiring layer 6 functions as a conductive path for connecting each electrode of the semiconductor element 4 to an external electric circuit, and is formed of a metal powder such as copper, silver, or gold.
[0024]
The wiring layer 6 is formed by adding a metal paste obtained by adding and mixing an appropriate organic binder, a solvent, etc. to a metal powder such as copper, silver, gold or the like on a green sheet to be the frame-like insulator 2 in advance. By using a printing method such as the above, a predetermined pattern is printed and applied, so that the frame-shaped insulator 2 is deposited from the inner periphery to the upper surface.
[0025]
Although the melting point of copper, silver, gold, etc. forming the wiring layer 6 is as low as about 1000 ° C., the sintering temperature of the glass-ceramic sintered body constituting the frame-shaped insulator 2 is low. It is possible to deposit and form a pattern.
[0026]
Copper, silver, gold or the like forming the wiring layer 6 has a low specific electric resistance of 2.5 μΩ · cm or less, so that the semiconductor element 4 accommodated inside the container via the wiring layer 6 and the external electric circuit Even if an electric signal is taken in and out in the meantime, the electric signal is not greatly attenuated in the wiring layer 6, and as a result, the semiconductor element 4 can be driven accurately and reliably.
[0027]
Furthermore, the wiring layer 6 has a low dielectric constant of 7 or less (room temperature, 1 MHz), preferably 5.5 to 6, since the frame-like insulator 2 to which the wiring layer 6 is applied is low. As a result, even if an electric signal is taken in and out between the semiconductor element 4 accommodated in the container and the external electric circuit via the wiring layer 6, the electric signal is propagated. Thus, an electrical signal can be input / output accurately and reliably to / from the semiconductor element 4 without causing any delay.
[0028]
When the wiring layer 6 is made of copper or silver, it is possible to effectively prevent oxidation corrosion of the wiring layer 6 by depositing a metal having excellent corrosion resistance on the exposed surface to a thickness of 1 μm to 20 μm by plating. In addition, the connection between the wiring layer 6 and the bonding wire 7 and the attachment of the external lead pin 8 to the wiring layer 6 can be strengthened. Therefore, when the wiring layer 6 is made of copper or silver, the wiring layer 6 is exposed in order to prevent oxidative corrosion of the wiring layer 6 and to firmly attach the wiring layer 6 to the bonding wire 7 and the external lead pin 8. It is preferable to deposit a metal having excellent corrosion resistance such as gold on the surface to a thickness of 1 μm to 20 μm.
[0029]
The external lead pins 8 brazed to the wiring layer 6 attached to the frame-like insulator 2 are made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy, and each electrode of the semiconductor element 4 is connected to the external electric power. Electrically connects to the circuit.
[0030]
The external lead pin 8 is formed in a predetermined shape by subjecting an ingot made of a metal such as iron-nickel-cobalt alloy to a conventionally known metal processing method such as a rolling method or a punching method.
[0031]
In the package for housing a semiconductor element of the present invention, it is important that the substrate 1 is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper.
[0032]
If the substrate 1 is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper, the substrate 1 has a high thermal conductivity of 230 W / m · K or more. Even if the semiconductor element 4 placed on 1 generates a large amount of heat during operation, the heat spreads quickly in the plane direction of the semiconductor element placement portion 1a of the base 1 and propagates in the thickness direction of the base 1 satisfactorily. Thus, the semiconductor element 4 can always be efficiently diffused to the outside efficiently, whereby the semiconductor element 4 is always at an appropriate temperature, and the semiconductor element 4 can be stably and normally operated over a long period of time.
[0033]
The substrate 1 made of the above-described 65 to 95 wt% silicon carbide and 5 to 35 wt% copper has a linear thermal expansion coefficient of the frame insulator 2 made of a glass ceramic sintered body ( 6 ppm / ° C. to 8 ppm / ° C., which approximates 4 ppm / ° C. to 8 ppm / ° C. (room temperature to 800 ° C.). As a result, the semiconductor element 4 was activated when the frame-like insulator 2 was attached on the substrate 1. Even when heat is applied to both the base 1 and the frame-like insulator 2, a large thermal stress is generated between the base 1 and the frame-like insulator 2 due to the difference in linear thermal expansion coefficient between the two. In this way, the hermetic sealing of the space for housing the semiconductor element 4 is always perfect, and the semiconductor element 4 can be operated stably and normally.
[0034]
When the amount of silicon carbide in the substrate 1 is less than 65% by weight, in other words, when the amount of copper exceeds 35% by weight, the linear thermal expansion coefficient of the substrate 1 is greatly different from the linear thermal expansion coefficient of the frame insulator 2. As a result, the frame-like insulator 2 cannot be firmly attached to the substrate 1, and when the amount of silicon carbide exceeds 95% by weight, in other words, 5% by weight of copper. If it is less than that, the thermal conductivity of the substrate 1 is greatly deteriorated, and when the semiconductor element 4 emits a large amount of heat during operation, the heat cannot be completely dissipated to the outside through the substrate 1. If the semiconductor element 4 is heated to a high temperature, the semiconductor element 4 may be thermally destroyed, or the characteristics may vary, making it impossible to operate stably. Accordingly, the substrate 1 is specified in the range of 65 to 95% by weight of silicon carbide and in the range of 5 to 35% by weight of copper.
[0035]
The substrate 1 made of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper has an oxide film such as SiO 2 on the surface of silicon carbide to a thickness of about 0.05 μm to 1 μm. If deposited, the adhesion strength between silicon carbide and copper is greatly improved, and the reliability of the substrate 1 is greatly improved. Therefore, the substrate 1 is preferably formed of silicon carbide and copper having an oxide film deposited on the surface to a thickness of 0.05 μm to 1 μm.
[0036]
As a method for depositing an oxide film on the surface of the silicon carbide, for example, silicon carbide powder is heated in the atmosphere at a temperature of about 1200 ° C.
[0037]
Further, when the base 1 is formed by dispersing and mixing silicon carbide powder in molten copper, the base 1 has a soft modulus of about 100 GPa depending on the Young's modulus of copper. Even if the semiconductor element 4 is placed on the substrate 1 and heat is applied to the base 1 and the semiconductor element 4 to generate thermal stress therebetween, the thermal stress is efficiently absorbed by slightly deforming the base 1. The semiconductor element 4 can be operated normally and stably without the semiconductor element 4 being peeled off from the base body 1 or the semiconductor element 4 being cracked or cracked.
[0038]
Thus, according to the semiconductor element storage package described above, the semiconductor element 4 is bonded and fixed onto the semiconductor element mounting portion 1a of the base 1 via an adhesive such as glass, resin, brazing material, and the like. The electrodes are connected to a predetermined wiring layer 6 via bonding wires 7, and then the lid 3 is bonded to the upper surface of the frame-like insulator 2 via a sealing material made of glass, resin, brazing material or the like. The semiconductor device 4 is hermetically accommodated in the container 5 including the base body 1, the frame-like insulator 2, and the lid body 3, thereby obtaining a semiconductor device as a product.
[0039]
In addition, this invention is not limited to the above-mentioned Example, A various change is possible if it is a range which does not deviate from the summary of this invention.
[0040]
【The invention's effect】
According to the package for housing a semiconductor element of the present invention, since the frame-like insulator is formed of a glass ceramic sintered body having a relative dielectric constant of 7 or less, the propagation speed of the electric signal transmitted through the wiring layer provided on the frame-like insulator. Therefore, it is possible to accommodate a semiconductor element that requires high-speed signal propagation.
[0041]
Further, according to the package for housing a semiconductor element of the present invention, the frame-shaped insulator is formed of a glass ceramic sintered body capable of low-temperature firing (about 800 ° C. to 900 ° C.). The wiring layer can be formed of copper, silver, or gold having a specific electric resistance of 2.5 μΩ · cm (20 ° C.) or less, and as a result, when an electric signal is propagated to the wiring layer, Large attenuation does not occur, and the electric signal can be propagated accurately and reliably.
[0042]
Further, according to the package for housing a semiconductor element of the present invention, the substrate is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper, and has a high thermal conductivity of 230 W / m · K or more. Therefore, even if the semiconductor element mounted on the base generates a large amount of heat during operation, the heat spreads quickly in the plane direction of the semiconductor element mounting portion of the base and propagates well in the thickness direction of the base. Thus, the semiconductor element can be efficiently and reliably dissipated to the outside, whereby the semiconductor element always has an appropriate temperature, and the semiconductor element can be stably and normally operated over a long period of time.
[0043]
Furthermore, according to the package for housing a semiconductor element of the present invention, the substrate is formed of 65 to 95% by weight of silicon carbide and 5 to 35% by weight of copper, and the linear thermal expansion coefficient is determined from the glass ceramic sintered body. The linear thermal expansion coefficient ( 4 ppm / ° C. to 8 ppm / ° C .: room temperature to 800 ° C.) of the frame-shaped insulator is obtained. Even when heat is applied to both the base and the frame insulator during operation, a large thermal stress is generated between the base and the frame insulator due to the difference in linear thermal expansion coefficient between the two. As a result, the hermetic sealing of the space for housing the semiconductor element is always complete, and the semiconductor element can be operated stably and normally.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a package for housing a semiconductor element of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base | substrate 1a ...... Placement part 2 ... Frame-shaped insulator 3 ... Cover body 4 ... Semiconductor element 5 ... Container 6 ... .... Wiring layer 7 ... bonding wire 8 ... external lead pin

Claims (1)

上面に半導体素子が載置される載置部を有する基体と、前記基体上に半導体素子載置部を囲繞するようにして取着され、半導体素子の各電極が接続される配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着され、枠状絶縁体の内側を気密に封止する蓋体とから成る半導体素子収納用パッケージであって、前記枠状絶縁体は比誘電率が7以下、熱膨張係数が4ppm/℃〜8ppm/℃のガラスセラミックス焼結体で、前記配線層は電気抵抗率が2.5μΩ・cm以下の金属材料で、前記基体は65乃至95重量%の炭化珪素と5乃至35重量%の銅とで形成されており、溶融した銅に炭化珪素粉末が分散混入されて形成されたものであることを特徴とする半導体素子収納用パッケージ。A frame having a base having a mounting portion on which a semiconductor element is mounted, and a wiring layer attached on the base so as to surround the semiconductor element mounting and to which each electrode of the semiconductor element is connected A semiconductor element storage package comprising: a frame-like insulator; and a lid attached on the frame-like insulator and hermetically sealing the inside of the frame-like insulator, wherein the frame-like insulator has a dielectric constant the rate is 7 or less, a glass ceramic sintered body of the thermal expansion coefficient of 4ppm / ℃ ~8ppm / ℃, the wiring layer is electrical resistivity in the following metallic material 2.5μΩ · cm, the substrate is 65 to 95 wt% of silicon carbide and is formed by a 5 to 35 wt% of copper, the semiconductor device package for housing molten copper silicon carbide powder is characterized der Rukoto those formed are dispersed and mixed.
JP2001314224A 2001-10-11 2001-10-11 Package for storing semiconductor elements Expired - Fee Related JP3748399B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001314224A JP3748399B2 (en) 2001-10-11 2001-10-11 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001314224A JP3748399B2 (en) 2001-10-11 2001-10-11 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JP2003124375A JP2003124375A (en) 2003-04-25
JP3748399B2 true JP3748399B2 (en) 2006-02-22

Family

ID=19132575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001314224A Expired - Fee Related JP3748399B2 (en) 2001-10-11 2001-10-11 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3748399B2 (en)

Also Published As

Publication number Publication date
JP2003124375A (en) 2003-04-25

Similar Documents

Publication Publication Date Title
JP2006060247A (en) Heat dissipation substrate and its manufacturing method
JP3748399B2 (en) Package for storing semiconductor elements
JP3987649B2 (en) Package for storing semiconductor elements
JP3659306B2 (en) Package for storing semiconductor elements
JP3792561B2 (en) Package for storing semiconductor elements
JP3752447B2 (en) Package for storing semiconductor elements
JP2003124376A (en) Package for housing semiconductor device
JP3638547B2 (en) Package for storing semiconductor elements
JP2740608B2 (en) Package for storing semiconductor elements
JP4562319B2 (en) Package for storing semiconductor elements
JP2003068904A (en) Package for semiconductor element storage
JP3659300B2 (en) Package for storing semiconductor elements
JPH10209336A (en) Package for storage of semiconductor element
JP2003007885A (en) Package for storing semiconductor element
JP3570852B2 (en) Package for storing semiconductor elements
JP3872391B2 (en) Package for storing semiconductor elements
JP2003110045A (en) Package for containing semiconductor element
JP3850312B2 (en) Semiconductor element storage package and semiconductor device
JP3971592B2 (en) Package for storing semiconductor elements
JP2003174109A (en) Package for storing semiconductor device
JP3752440B2 (en) Package for storing semiconductor elements
JP2003100934A (en) Package for accommodating semiconductor device
JP2003037230A (en) Package for housing semiconductor element
JP2003100935A (en) Package for accommodating semiconductor device
JP3659301B2 (en) Package for storing semiconductor elements

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040408

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050419

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050426

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050627

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20051122

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20051125

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091209

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101209

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101209

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111209

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111209

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121209

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131209

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees