JP2003031817A - Method for forming contact structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the shape of a contact hole formed on the insulating film of a thin film transistor, etc. SOLUTION: On a transparent substrate 21 on which a gate electrode 22 is arranged, a silicone nitride film 23 and a silicone oxide film 24 becoming the gate insulating films are laminated, and a polycrystal silicone film 25 as a semiconductor film becoming active area is laminated in addition. On the polycrystal silicon film 25 corresponding to the gate electrode 22, a stopper 26 is arranged, and a silicon oxide film 27, a silicon nitride film 28 and a silicon oxide film 29 are laminated as an interlayer insulating film so as to cover this stopper 26. A contact hole 30 is formed at the interlayer insulating film corresponding to a source area 25a and a drain area 25d, and a source electrode 31s and a drain electrode 31d are arranged through this contact hole 30.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact structure such as a thin film transistor which is suitable for a switching element for pixel display of an active matrix type display panel. FIG. 7 is a sectional view showing a structure of a bottom gate type thin film transistor. A gate electrode 2 made of a refractory metal such as tungsten or chromium is arranged on the surface of an insulating transparent substrate 1. The gate electrode 2 has a tapered shape in which both ends become wider on the transparent substrate 1 side. On the transparent substrate 1 on which the gate electrode 2 is arranged, a silicon oxide film 4 is laminated via a silicon nitride film 3. The silicon nitride film 3 prevents impurities contained in the transparent substrate 1 from entering an active region described later, and the silicon oxide film 4 functions as a gate insulating film. On the silicon oxide film 4, a polycrystalline silicon film 5 is stacked across the gate electrode 2. This polycrystalline silicon film 5 becomes an active region of the thin film transistor. [0004] A stopper 6 made of an insulating material such as silicon oxide is arranged on the polycrystalline silicon film 5. The polycrystalline silicon film 5 covered by the stopper 6 becomes the channel region 5c, and the other polycrystalline silicon films 5 become the source region 5s and the drain region 5d. On the polycrystalline silicon film 5 on which the stopper 6 is formed, a silicon oxide film 7 and a silicon nitride film 8 are stacked. This silicon oxide film 7
The silicon nitride film 8 serves as an interlayer insulating film for protecting the polycrystalline silicon film 5 including the source region 5s and the drain region 5d. A contact hole 9 is formed at a predetermined position in the silicon oxide film 7 and the silicon nitride film 8 on the source region 5s and the drain region 5d. In the contact hole 9 part, a source region 5s and a drain region 5d
Source electrode 10s and drain electrode 10d connected to
Is arranged. Source electrode 10s and drain electrode 10
An acrylic resin layer 11 transparent to visible light is laminated on the silicon nitride film 8 on which d is disposed. The acrylic resin layer 11 flattens the surface by filling irregularities generated by the gate electrode 2 and the stopper 6. Acrylic resin layer 11 on source electrode 10s
, A contact hole 12 is formed. Then, a transparent electrode 13 made of ITO (indium tin oxide) or the like connected to the source electrode 10s through the contact hole 12 is disposed so as to spread on the acrylic resin layer 11. The transparent electrode 13 forms a display electrode of the liquid crystal display panel. A plurality of the above thin film transistors are arranged in rows and columns on the transparent substrate 1 together with the display electrodes, and the gate electrodes 2
In response to the scanning control signal applied to the drain electrode 1
The video information supplied to Od is applied to the display electrodes. Incidentally, the polycrystalline silicon film 5 is formed with a sufficient crystal grain size so as to function as an active region of the thin film transistor. As a method for forming a large crystal grain size of the polycrystalline silicon film 5, a laser annealing method using an excimer laser is known. In this laser annealing method, amorphous silicon is stacked on a silicon oxide film 4 serving as a gate insulating film. First, hydrogen contained in the amorphous silicon film is discharged out of the film by a low-temperature heat treatment. The silicon is crystallized by irradiating the silicon with an excimer laser to once melt the silicon. If such a laser annealing method is used, since a portion where the temperature becomes high on the transparent substrate 1 is local, a glass substrate having a low melting point can be adopted as the transparent substrate 1. [0009] The polycrystalline silicon film 5 crystallized by the laser annealing method has many crystal defects, so that electrons moving in the film are easily captured and used as an active region of the transistor. Is not preferred. Therefore, an insulating film containing a large amount of hydrogen ions is formed on the once formed polycrystalline silicon film 5, and heat treatment is performed together with the insulating film to fill crystal defects with hydrogen ions. As an insulating film containing a large amount of hydrogen ions,
Silicon nitride films are known. The hydrogen ion concentration of a silicon nitride film formed by a plasma CVD method is usually about 10 ^ 22 / cm ^ 3 (^ represents a power), and the hydrogen ion concentration of a silicon oxide film formed by the same plasma CVD method is It is about two orders of magnitude higher than the concentration (10 ^ 20 / cm ^ 3). When such a silicon nitride film is formed directly on the active region, the transistor characteristics are deteriorated. Therefore, as shown in FIG. 7, a silicon oxide film is formed between the active region and the silicon nitride film. However, in the interlayer insulating film in which the silicon nitride film 8 is superposed on the silicon oxide film 7, when the contact hole 9 is formed by etching using a hydrofluoric acid-based etchant, the contact hole is formed due to a difference in etching rate. 9 becomes wider on the bottom side. That is, since the etching rate of the silicon oxide film 7 with respect to the hydrofluoric acid-based etchant is faster than that of the silicon nitride film 8, the contact hole 9 is formed at the silicon oxide film 7 portion as shown in FIG. Wider than the part. Therefore, the source electrode 10s or the drain electrode 10d formed in the contact hole 9 portion
Disconnection is likely to occur, resulting in a contact failure. Therefore, an object of the present invention is to improve the shape of a contact hole formed in an insulating film. According to a method of forming a contact structure of the present invention, a step of forming a polycrystalline silicon film on a substrate and a step of forming a nitride film on the polycrystalline silicon film via a silicon oxide film are performed. A step of forming a silicon film, a step of laminating a silicon oxide film on the silicon nitride film, and a hydrofluoric acid-based process continuously from the surface of the silicon oxide film on the silicon nitride film to the polycrystalline silicon film. A contact structure comprising: a step of forming a tapered hole extending toward the upper layer side by etching with an etchant; and a step of forming an electrode that contacts the polycrystalline silicon film through the hole. The silicon oxide film on the silicon nitride film is more etched than the silicon nitride film with respect to the hydrofluoric acid-based etchant. This is a method for forming a contact structure that is a silicon oxide film having a high chin rate. According to the present invention, during the etching for forming the contact hole, since the uppermost layer is a silicon oxide film having a higher etching rate than the silicon nitride film, the etching from the upper layer side is dominant. For this reason, the shape of the silicon nitride film itself becomes a tapered shape that spreads toward the upper layer side, and a contact hole with good step coverage is formed in forming the electrode. FIG. 1 is a sectional view showing a first embodiment in which a method for forming a contact structure according to the present invention is applied to a thin film transistor. 7, a transparent substrate 21, a gate electrode 22, a silicon nitride film 23, a silicon oxide film 24, and a polycrystalline silicon film 25 correspond to a transparent substrate 1, a gate electrode 2, a silicon nitride film 3, and a silicon oxide film of the thin film transistor shown in FIG. Film 4 and polycrystalline silicon film 5
Is the same as A gate electrode 22 is disposed on the surface of the transparent substrate 21, and a silicon nitride film 23 and a silicon oxide film 24 as a gate insulating film are laminated over the gate electrode 22. Then, on the silicon oxide film 24, a polycrystalline silicon film 25 as a semiconductor film to be an active region is laminated. A stopper 26 made of silicon oxide is arranged on polycrystalline silicon film 25. This stopper 2
6 covers the channel region 25.
and the other polycrystalline silicon film 25 becomes the source region 25s and the drain region 25d. On the polycrystalline silicon film 25 on which the stopper 26 has been formed, a silicon oxide film 27 having little adverse effect even when in contact with the polycrystalline silicon film 25 is formed.
Are laminated. Then, on the silicon oxide film 27,
A silicon nitride film 28 containing hydrogen ions in a larger amount than the silicon oxide film 27 and serving as a main supply source of hydrogen ions is stacked. Further, a silicon oxide film 29 is stacked on the silicon nitride film 28. These silicon oxide films 27,
The silicon nitride film 28 and the silicon oxide film 29 form an interlayer insulating film for protecting the polycrystalline silicon film 25. Silicon oxide film 27, silicon nitride film 28
And an interlayer insulating film composed of three layers of a silicon oxide film 29 and a contact hole 3 reaching the polycrystalline silicon film 25.
0 is provided. The source electrode 31s and the drain electrode 31d connected to the source region 25s and the drain region 25d are arranged in the contact hole 30. Further, an acrylic resin layer 32 that covers the source electrode 31s and the drain electrode 31d and that flattens the surface is laminated on the interlayer insulating film. Further, the acrylic resin layer 3
2 is provided with a contact hole 33 reaching the source electrode 31s, and a transparent electrode 34 connected to the source electrode 31s.
Are arranged to spread on the acrylic resin layer 32.
The source electrode 31s, the drain electrode 31d, and the transparent electrode 34 are the source electrode 1 of the thin film transistor shown in FIG.
0s, the same as the drain electrode 10d and the transparent electrode 13. In the above-mentioned thin film transistor, the interlayer insulating film is formed by the silicon nitride film 28 and the silicon oxide films 27 and 29 having a higher etching rate with respect to a hydrofluoric acid-based etching solution than the silicon nitride film 28. For this reason, when the contact hole 30 is formed by etching using a hydrofluoric acid-based etchant, the width of the contact hole 30 is different between the silicon oxide film 27 and the silicon nitride film 28 as shown in FIG. The difference becomes smaller. Therefore, contact failure of the source electrode 31s or the drain electrode 31d formed through the contact hole 30 can be prevented. FIG. 3 is a sectional view showing a second embodiment in which the method of forming a contact hole according to the present invention is applied to a thin film transistor. This figure shows a top gate type. On a surface of an insulating transparent substrate 41, a silicon nitride film 42 and a silicon oxide film 43 are laminated. The silicon nitride film 42 prevents precipitation of impurity ions such as sodium contained in the transparent substrate 41, and forms a silicon oxide film 43.
Allows the lamination of the polycrystalline silicon film 44 to be the active region. In a predetermined region on the silicon oxide film 43, a polycrystalline silicon film 44 as a semiconductor film to be an active region of the thin film transistor is laminated. On the silicon oxide film 43 on which the polycrystalline silicon film 44 is stacked, a silicon oxide film 45 serving as a gate insulating film is stacked. Then, on the silicon oxide film 45,
A gate electrode 46 made of a high melting point metal such as tungsten or chromium is arranged. This gate electrode 46 is arranged crossing the direction in which the polycrystalline silicon film 44 extends. The polycrystalline silicon film 44 covered by the gate electrode 46 becomes a channel region 44c, and the other polycrystalline silicon film 4
4 becomes the source region 44s and the drain region 44d. On the silicon oxide film 45 on which the gate electrode 46 is arranged, a silicon oxide film 47 is laminated. Then, a silicon nitride film 48 is stacked on the silicon oxide film 47, and a silicon oxide film 49 is further stacked on the silicon nitride film 48. The silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 form an interlayer insulating film for protecting the polycrystalline silicon film 44. In the interlayer insulating film, a contact hole 50 reaching the polycrystalline silicon film 44 is provided.
5s and source electrode 5 connected to drain region 45d
1s and the drain electrode 51d are arranged. Then, the source electrode 51s and the drain electrode 51 are formed on the interlayer insulating film.
An acrylic resin layer 52 that covers d and flattens the surface is laminated. Further, the source electrode 51 is formed on the acrylic resin layer 52.
s is provided, and a transparent electrode 54 connected to the source electrode 51 s is arranged to spread on the acrylic resin layer 52. This source electrode 51
s, the drain electrode 51d, and the transparent electrode 54 are the same as those of the bottom gate type. In the above-described thin film transistor, when the contact hole 50 is formed by etching using a hydrofluoric acid type etching solution, the contact hole 50
As in the case of the top gate type (FIG. 2), the difference between the silicon oxide film 47 and the silicon nitride film 48 becomes smaller. FIGS. 4 (a) to 4 (c) and FIGS. 5 (d) to 5 (d)
5F is a sectional view illustrating the manufacturing method of the thin film transistor in the step of forming the contact structure according to the first embodiment, which is performed by each process; FIG. In these figures, the same parts as those in FIG. 1 are shown. (A) First Step A high melting point metal film 35 is formed on the insulating transparent substrate 21 by laminating a high melting point metal such as chromium or molybdenum to a thickness of 1000 ° by a sputtering method. This high melting point metal film 3
5 is patterned into a predetermined shape to form a gate electrode 22. In this patterning process, both ends of the gate electrode 22 are formed in a tapered shape by taper etching such that the both ends become wider on the transparent substrate 21 side. (B) Second Step On the transparent substrate 21, silicon nitride is laminated to a thickness of 500 ° or more by a plasma CVD method, and silicon oxide is laminated continuously to a thickness of 1300 ° or more. This allows
A silicon nitride film 23 for preventing precipitation of impurity ions from the transparent substrate 21 and a silicon oxide film 24 serving as a gate insulating film are formed. Then, on the silicon oxide film 23,
Similarly, silicon is laminated to a thickness of 400 ° by a plasma CVD method to form an amorphous silicon film 25 ′. Then, a heat treatment is performed at about 430 ° C. for 1 hour or more to discharge hydrogen in the silicon film 25 ′ to the outside of the film, reduce the hydrogen concentration to 1% or less, and irradiate the silicon film 25 ′ with an excimer laser. Heat until the silicon in the state is melted. Thereby, silicon is crystallized, and the polycrystalline silicon film 25 is formed.
It becomes. (C) Third Step A silicon oxide film 35 is formed on the polycrystalline silicon film 25 by stacking silicon oxide to a thickness of 1000 °. Then, the silicon oxide film 35 is patterned according to the shape of the gate electrode 22 to form a stopper 26 overlapping the gate electrode 22. In forming the stopper 26, a resist layer is formed covering the silicon oxide film 35,
By exposing the resist layer from the transparent substrate side using the gate electrode 22 as a mask, mask shift can be eliminated. (D) P-type or N-type ions corresponding to the type of transistor to be formed are implanted into the polycrystalline silicon film 25 on which the fourth step stopper 26 is formed. That is, when a P-channel transistor is formed, P-type ions such as boron are implanted, and when an N-channel transistor is formed, N-type ions such as phosphorus are implanted. By this implantation, a region exhibiting P-type or N-type conductivity is formed in polycrystalline silicon film 25 except for the region covered by stopper 26. These regions become a source region 25s and a drain region 25d on both sides of the stopper 26. (E) Fifth Step The polycrystalline silicon film 25 on which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser, and heated to such an extent that silicon is not melted. Thereby, impurity ions in the source region 25s and the drain region 25d are activated. Then, the stopper 26 (gate electrode 2
The polycrystalline silicon film 25 is patterned into an island shape leaving a predetermined width on both sides of 2) to separate and insulate transistors. (F) Sixth step: A silicon oxide layer is formed on the polycrystalline silicon film 25 by a plasma CVD method to a thickness of 1000 .ANG., And a silicon nitride film of 3000 .ANG.
Are sequentially laminated. Thereby, the silicon oxide film 2
7, an interlayer insulating film composed of three layers of a silicon nitride film 28 and a silicon oxide layer 29 is formed. After forming the interlayer insulating film, the film is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 28 into the polycrystalline silicon film 25. The temperature of this heat treatment needs to be within a range where the movement of hydrogen ions is sufficient and the transparent substrate 21 is not damaged.
Is appropriate. Hydrogen ions contained in the silicon nitride film 28 are introduced into the polycrystalline silicon film 25 through the silicon oxide film 27 formed to be thin according to the thickness of the silicon nitride film 28, so that hydrogen ions necessary for the polycrystalline silicon film 25 are required. The quantity is supplied reliably. Thereby, crystal defects in polycrystalline silicon film 25 are filled with hydrogen ions. After the replenishment of the crystal defects in the polycrystalline silicon film 25 by the hydrogen ions is completed, the source region 25s
A contact hole 30 penetrating the interlayer insulating film is formed corresponding to the drain region 25d, and a source electrode 31s and a drain electrode 31d made of a metal such as aluminum are formed in the contact hole 30. The source electrode 31s and the drain electrode 31d are formed, for example, by patterning aluminum sputtered on the interlayer insulating film in which the contact holes 30 are formed. Subsequently, an acrylic resin solution is applied on the interlayer insulating film on which the source electrode 31s and the drain electrode 31d are formed and baked to form an acrylic resin layer 32. The acrylic resin layer 32 is formed on the stopper 26 and the source electrode 3.
1s, the surface is flattened by filling the unevenness due to the drain electrode 31d. Further, a contact hole 33 penetrating the acrylic resin layer 32 is formed on the source electrode 31s, and a transparent electrode 34 made of ITO or the like connected to the source electrode 31s is formed in the contact hole 33. The formation of the transparent electrode 34 is performed, for example, by using the contact hole 33.
It is formed by patterning ITO sputtered on the acrylic resin layer 32 on which is formed. Through the above first to sixth steps, a bottom gate type thin film transistor having the structure shown in FIG. 1 is formed. FIGS. 6A to 6D are cross-sectional views for explaining steps of a method of manufacturing a thin film transistor according to the second embodiment. In these figures, the same parts as those in FIG. 3 are shown. (A) First Step On a transparent insulating substrate 41, silicon nitride is laminated to a thickness of 500 ° or more by a plasma CVD method, and continuously.
Silicon oxide is laminated to a thickness of 500 °. As a result, a silicon oxide film 43 is formed, which enables lamination of the silicon nitride film 42 and the polycrystalline silicon film 44 for preventing the deposition of impurity ions from the transparent substrate 41. further,
Similarly, silicon is laminated to a thickness of 400 ° by a plasma CVD method to form an amorphous silicon film 44 ′. Then, a heat treatment is performed at about 430 ° C. for 1 hour or more to discharge hydrogen in the silicon film 44 ′ to the outside of the film and reduce the hydrogen concentration to 1% or less. Heat until the silicon in the state is melted. Thereby, silicon is crystallized, and the polycrystalline silicon film 44
It becomes. (B) Polycrystalline silicon film 4 corresponding to the formation position of the second step transistor
4 is patterned into a predetermined shape and separated for each transistor. After the polycrystalline silicon film 44 is separated, silicon oxide is deposited to a thickness of 1000 ° by a plasma CVD method to form a silicon oxide film 45 serving as a gate insulating film. Then, a metal such as chromium or molybdenum is laminated to a thickness of 1000 ° by a sputtering method to form a metal film 54. This metal film 54 is patterned into a predetermined shape crossing the polycrystalline silicon film 45 to form a gate electrode 46. (C) Third Step Using the gate electrode 46 as a mask, P-type or N-type ions corresponding to the type of the transistor to be formed are implanted into the polycrystalline silicon film 44. In this implantation, the polysilicon film 4 is removed except for the region covered by the gate electrode 46.
In 4, a region showing P-type or N-type conductivity is formed. These regions become the source region 44s and the drain region 44d. Then, an excimer laser is irradiated to the polycrystalline silicon film 44 into which impurity ions of a predetermined conductivity type have been implanted, and heated so that silicon is not melted. Thereby, impurity ions in the source region 44s and the drain region 44d are activated. (D) Fourth Step On the silicon oxide film 45 on which the gate electrode 46 is formed, silicon oxide is deposited to a thickness of 1000 by plasma CVD, and continuously, silicon nitride is deposited to a thickness of 3000 and silicon oxide is deposited to a thickness of 500. Are sequentially laminated. Thus, an interlayer insulating film composed of three layers of the silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 is formed. After the formation of the interlayer insulating film, the film is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 48 into the polycrystalline silicon film 44. This heat treatment itself is the same as the heat treatment in the sixth step of the method for manufacturing the bottom gate thin film transistor shown in FIG.
By the way, between the polycrystalline silicon film 44 and the gate electrode 46, hydrogen ions are easily diffused using the interface as a diffusion path. Therefore, in the portion of the polycrystalline silicon film 44 covered by the gate electrode 46, Hydrogen ions enter and enter. Therefore, there is no problem even if the gate electrode 46 formed of a high melting point metal does not allow passage of hydrogen ions. As a result, crystal defects in the polycrystalline silicon film 44 are filled with hydrogen ions. After hydrogen ions are introduced into the polycrystalline silicon film 4, the source region 44s and the drain region 44d
In response, a contact hole 50 penetrating through the silicon oxide film 45 and the interlayer insulating film is formed. Then, a source electrode 51s and a drain electrode 51d made of a metal such as aluminum are formed in the contact hole 50.
Subsequently, an acrylic resin solution is applied on the interlayer insulating film on which the source electrode 51s and the drain electrode 51d are formed, and is baked to form the acrylic resin layer 52. The acrylic resin layer 52 fills irregularities due to the gate electrode 46, the source electrode 51s, and the drain electrode 51d, and planarizes the surface.
Further, a contact hole 53 penetrating the acrylic resin layer 52 is formed on the source electrode 51s, and an IT connected to the source electrode 51s is formed in the contact hole 53.
A transparent electrode 53 made of O or the like is formed. Through the above-described first to fourth steps, a top-gate thin film transistor having the structure shown in FIG. 3 is formed. The film thickness of each portion exemplified in each of the above-described embodiments is an optimum value under specific conditions, and is not necessarily limited to these values. According to the present invention, it is possible to improve the shape of the contact hole that reaches the semiconductor film through the insulating film. Accordingly, it is possible to prevent the occurrence of a contact failure between the electrode and the semiconductor film and to prevent the deterioration of the operation characteristics of the transistor. As a result, it is expected that the production yield is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a first embodiment when a method for forming a contact structure according to the present invention is applied to a thin film transistor. FIG. 2 is a cross-sectional view showing the shape of a contact hole of a thin film transistor when the method for forming a contact structure of the present invention is applied to a thin film transistor. FIG. 3 is a cross-sectional view showing a second embodiment in which the method for forming a contact structure of the present invention is applied to a thin film transistor. FIG. 4 is a cross-sectional view illustrating the first half of the manufacturing method according to the first embodiment, which is performed by different processes. FIG. 5 is a cross-sectional view illustrating the second half of the manufacturing method according to the first embodiment, which is performed by different processes. FIG. 6 is a cross-sectional view illustrating another step of the manufacturing method according to the second embodiment. FIG. 7 is a cross-sectional view illustrating a structure of a conventional thin film transistor. FIG. 8 is a sectional view showing a shape of a contact hole of a conventional thin film transistor. [Description of Signs] 1, 21, 41 Transparent substrate 2, 22, 46 Gate electrode 3, 8, 23, 28, 42, 48 Silicon nitride film 4, 7, 24, 27, 29, 43, 47, 49 Silicon oxide Films 5, 25, 44 Polycrystalline silicon films 5c, 25c, 44c Channel regions 5s, 25s, 44s Source regions 5d, 25d, 44d Drain regions 6, 26 Stoppers 9, 12, 30, 33, 50, 53 Contact holes 10s, 31s, 51s Source electrode 10d, 31d, 51d Drain electrode 11, 32, 52 Acrylic resin layer 12, 34, 54 Transparent electrode

   ────────────────────────────────────────────────── ─── Continuation of front page    F term (reference) 5F033 GG04 HH08 JJ08 KK04 NN32                       QQ19 QQ20 QQ37 QQ74 RR04                       RR06 SS15 TT02 VV15 XX02                 5F110 AA26 AA30 BB01 CC02 CC08                       DD13 DD14 DD17 EE04 EE23                       EE44 FF02 FF03 FF09 FF30                       GG02 GG13 GG25 GG45 HJ01                       HJ13 HJ23 HL03 HL07 HL11                       HL14 HL23 NN03 NN04 NN12                       NN14 NN23 NN24 NN27 NN35                       NN36 PP03 PP35 QQ05 QQ09                       QQ11 QQ12 QQ19 QQ23

Claims (1)

Claims: 1. A step of forming a polycrystalline silicon film on a substrate, a step of forming a silicon nitride film on the polycrystalline silicon film via a silicon oxide film, Stacking a silicon oxide film on the film, and continuously etching with a hydrofluoric acid-based etchant from the surface of the silicon oxide film on the silicon nitride film until reaching the polycrystalline silicon film. A step of forming a tapered hole extending toward the substrate, and a step of forming an electrode in contact with the polycrystalline silicon film through the hole, wherein the silicon nitride film The upper silicon oxide film is a silicon oxide film having a higher etching rate with respect to the hydrofluoric acid-based etchant than the silicon nitride film. Method of forming a contact structure to symptoms.