JP2004363626A - Method of manufacturing thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fill a crystal defect in the semiconductor layer of a thin film transistor with hydrogen ions. <P>SOLUTION: On a transparent substrate 21 with a gate electrode 22 arranged thereon, a silicon nitride film 23 and a silicon oxide film 24 becoming a gate insulation film are deposited followed by deposition of a polysilicon film 25 as a semiconductor film becoming an active region. On the polysilicon film 25 corresponding to the gate electrode 22, a stopper 26 is arranged and then a silicon oxide film 27 and a silicon nitride film 28 becoming an interlayer insulation film are deposited to cover the stopper 26. Film thickness T1 of the superposed stopper 26 and silicon oxide film 27 is set thinner than the root of the product of the film thickness T2 of the silicon nitride film 28 and 4,000 Å. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor suitable for a pixel display switching element of an active matrix display panel.

  FIG. 9 is a cross-sectional view illustrating a structure of a bottom-gate thin film transistor.

  A gate electrode 2 made of a refractory metal such as tungsten or chromium is arranged on the surface of an insulating transparent substrate 1. The gate electrode 2 has a tapered shape in which both ends become wider on the transparent substrate 1 side. On the transparent substrate 1 on which the gate electrode 2 is arranged, a silicon oxide film 4 is laminated via a silicon nitride film 3. The silicon nitride film 3 prevents impurities contained in the transparent substrate 1 from entering an active region described later, and the silicon oxide film 4 functions as a gate insulating film. On the silicon oxide film 4, a polycrystalline silicon film 5 is stacked across the gate electrode 2. This polycrystalline silicon film 5 becomes an active region of the thin film transistor.

  On the polycrystalline silicon film 5, a stopper 6 made of an insulating material such as silicon oxide is arranged. The polycrystalline silicon film 5 covered by the stopper 6 becomes the channel region 5c, and the other polycrystalline silicon films 5 become the source region 5s and the drain region 5d. On the polycrystalline silicon film 5 on which the stopper 6 is formed, a silicon oxide film 7 and a silicon nitride film 8 are stacked. The silicon oxide film 7 and the silicon nitride film 8 become an interlayer insulating film for protecting the polycrystalline silicon film 5 including the source region 5s and the drain region 5d.

  Contact holes 9 are formed at predetermined locations in the silicon oxide film 7 and the silicon nitride film 8 on the source region 5s and the drain region 5d. In this contact hole 9, a source electrode 10s and a drain electrode 10d connected to the source region 5s and the drain region 5d are arranged. An acrylic resin layer 11 transparent to visible light is laminated on the silicon nitride film 8 on which the source electrode 10s and the drain electrode 10d are arranged. The acrylic resin layer 11 flattens the surface by filling irregularities generated by the gate electrode 2 and the stopper 6.

  A contact hole 12 is formed in the acrylic resin layer 11 on the source electrode 10s. Then, a transparent electrode 13 made of ITO (indium tin oxide) or the like connected to the source electrode 10s through the contact hole 12 is disposed so as to spread on the acrylic resin layer 11. The transparent electrode 13 forms a display electrode of the liquid crystal display panel.

  A plurality of the above thin film transistors are arranged in rows and columns on the transparent substrate 1 together with the display electrodes, and the video information supplied to the drain electrode 10d is applied to the display electrodes in response to the scanning control signal applied to the gate electrode 2. I do.

  Incidentally, the polycrystalline silicon film 5 is formed with a sufficient crystal grain size so as to function as an active region of the thin film transistor. As a method for forming a large crystal grain size of the polycrystalline silicon film 5, a laser annealing method using an excimer laser is known. In this laser annealing method, amorphous silicon is stacked on a silicon oxide film 4 serving as a gate insulating film. First, hydrogen contained in the amorphous silicon film is discharged out of the film by a low-temperature heat treatment. The silicon is crystallized by irradiating the silicon with an excimer laser to once melt the silicon. If such a laser annealing method is used, since a portion where the temperature becomes high on the transparent substrate 1 is local, a glass substrate having a low melting point can be adopted as the transparent substrate 1.

  Since the polycrystalline silicon film 5 crystallized by the laser annealing method has many crystal defects, electrons moving in the film are easily captured, which is not preferable as an active region of a transistor. Therefore, an insulating film containing a large amount of hydrogen ions is formed on the once formed polycrystalline silicon layer 5, and annealing is performed in a nitrogen atmosphere together with the insulating film to fill crystal defects with hydrogen ions.

  As an insulating film containing a large amount of hydrogen ions, a silicon nitride film is known. The hydrogen ion concentration of a silicon nitride film formed by a plasma CVD method is usually about 10 ^ 22 / cm ^ 3 (^ represents a power), and the hydrogen ion concentration of a silicon oxide film formed by the same plasma CVD method is It is about two orders of magnitude higher than the concentration (10 ^ 20 / cm ^ 3). Therefore, a silicon nitride film is used as a supply source of hydrogen ions.

Generally, when a silicon nitride film is directly formed on an active region, transistor characteristics are deteriorated. Therefore, a silicon oxide film is formed between the active region and the silicon nitride film as shown in FIG. However, when silicon oxide film 7 is interposed between polycrystalline silicon film 5 and silicon nitride film 8, sufficient hydrogen ions may not be supplied to polycrystalline silicon film 5 depending on the thickness of silicon oxide film 7. There is. Further, if impurities adhere to the interface between the silicon nitride film and the silicon oxide film, they may hinder the supply of hydrogen.
For this reason, in the manufacturing process, it is necessary to increase the temperature of the annealing treatment or to lengthen the time, thereby lowering the productivity.

  Therefore, an object of the present invention is to optimize each film thickness so that crystal defects generated in a semiconductor film can be efficiently filled with hydrogen ions.

  The method for manufacturing a thin film transistor according to the present invention includes a first step of forming a gate electrode on one main surface of a substrate, a step of stacking a gate insulating film on the substrate so as to cover the gate electrode, and forming a semiconductor on the gate insulating film. A second step of stacking a film, a third step of stacking an interlayer insulating film on the semiconductor film, and heating the semiconductor film and the interlayer insulating film to a predetermined temperature to remove hydrogen ions contained in the interlayer insulating film. And a fourth step of introducing the first silicon oxide film into a first film thickness by a plasma CVD method in contact with the semiconductor film. Stacking a silicon nitride film to a second thickness in contact with the first silicon oxide film by a plasma CVD method, wherein the first thickness is multiplied by 8000 ° to the second thickness. It should be less than or equal to the square root of the value.

  Also, the present invention is characterized in that the second step includes a step of laminating amorphous silicon on the gate insulating film, and then melting and crystallizing the amorphous silicon to form a polycrystalline silicon layer. It is a manufacturing method.

  Further, the present invention is a method for manufacturing a thin film transistor, wherein the fourth step is heat-treated at a temperature of 350 ° C. to 450 ° C.

  According to the present invention, a silicon oxide film and a silicon nitride film are stacked on a semiconductor film serving as an active region. The silicon nitride film serves as a supply source of hydrogen ions introduced to the semiconductor film, and the silicon oxide film prevents the silicon nitride film from contacting the semiconductor film. The silicon oxide film is thinly stacked in accordance with the thickness of the silicon nitride film, and does not hinder introduction of hydrogen ions from the silicon nitride film into the semiconductor film.

  According to the present invention, in a third step, a silicon oxide film and a silicon nitride film are stacked on a semiconductor film, and then heat treatment is performed in a fourth step, so that hydrogen ions contained in the silicon nitride film pass through the silicon oxide film. It is introduced into the semiconductor film. At this time, by reducing the thickness of the silicon oxide film in accordance with the thickness of the silicon nitride film, hydrogen ions contained in the silicon nitride film are not blocked by the silicon oxide film, and only a sufficient amount be introduced.

  Further, impurities can be prevented from adhering to the interface between the silicon nitride film and the silicon oxide film, and the risk that the impurities may hinder the supply of hydrogen to the semiconductor film can be eliminated. Hydrogen can be supplied.

  According to the present invention, even when a silicon nitride film is formed via a silicon oxide film on a polycrystalline silicon film that forms an active region, crystal defects of the polycrystalline silicon film cause hydrogen ions supplied from the silicon nitride film. Filled with certainty. Therefore, the annealing conditions for introducing hydrogen ions from the silicon nitride film to the polycrystalline silicon film can be relaxed, and the manufacturing process can be simplified, and as a result, the manufacturing yield can be improved.

  FIG. 1 is a sectional view showing a first embodiment of a thin film transistor of the present invention, and FIG. 2 is an enlarged view of a main part thereof. 9, the transparent substrate 21, the gate electrode 22, the silicon nitride film 23, the silicon oxide film 24, and the polycrystalline silicon film 25 are the transparent substrate 1, the gate electrode 2, the silicon nitride film 3, and the silicon oxide film of the thin film transistor shown in FIG. The same as the film 4 and the polycrystalline silicon film 5.

  A gate electrode 22 is disposed on the surface of the transparent substrate 21, and a silicon nitride film 23 and a silicon oxide film 24 as a gate insulating film are stacked over the gate electrode 22. Then, on the silicon oxide film 24, a polycrystalline silicon film 25 as a semiconductor film to be an active region is laminated.

  On polycrystalline silicon film 25, stopper 26 made of silicon oxide is arranged. The polycrystalline silicon film 25 covered by the stopper 26 becomes the channel region 25c, and the other polycrystalline silicon films 25 become the source region 25s and the drain region 25d. On the polycrystalline silicon film 25 on which the stopper 26 is formed, a silicon oxide film 27 that can be in contact with the polycrystalline silicon film 25 without affecting the polycrystalline silicon film 25 is laminated. Then, on the silicon oxide film 27, a silicon nitride film 28 containing a larger amount of hydrogen ions than the silicon oxide film 27 and serving as a main supply source of hydrogen ions is laminated. The silicon oxide film 27 and the silicon nitride film 28 form an interlayer insulating film for protecting the polycrystalline silicon film 25.

  Here, the thickness T1 of the overlapped stopper 26 and silicon oxide film 27 on the channel region 25c is set so as to satisfy Equation 1 with respect to the thickness T2 of the silicon nitride film 28 on the stopper 26.

  That is, the supply amount of hydrogen ions depends on the film thickness of the silicon nitride film 28. If the film thickness of the silicon oxide film 27 is set to be small in accordance with the supply amount, the polycrystalline silicon film 25 is An appropriate amount of hydrogen ions can be supplied. According to Equation 1, for example, when the thickness (= T2) of the silicon nitride film 28 is 2000 °, the total thickness (= T1) of the stopper 26 and the silicon oxide film 27 is set to about 4000 ° or less. There must be. In other words, when the thickness of the stopper 26 is 2000 ° and the thickness of the silicon oxide film 27 is 2000 °, the thickness of the silicon nitride film 28 needs to be 2000 ° or more.

A contact hole 29 reaching the polycrystalline silicon film 25 is provided in the silicon oxide film 27 and the silicon nitride film 28 formed to a predetermined thickness. Then, in the contact hole 29, a source electrode 30s and a drain electrode 30d connected to the source region 25s and the drain region 25d are arranged. On the silicon nitride film 28, an acrylic resin layer 31 that covers the source electrode 30s and the drain electrode 30d and flattens the surface is laminated. Further, a contact hole 32 reaching the source electrode 30 s is provided in the acrylic resin layer 31, and the transparent electrode 33 connected to the source electrode 30 s is arranged to spread on the acrylic resin layer 31. The source electrode 30s, the drain electrode 30d, and the transparent electrode 33 are the same as the source electrode 10s, the drain electrode 10d, and the transparent electrode 13 of the thin film transistor shown in FIG.

  In the above-described thin film transistor, since the thickness of the silicon oxide film 27 (including the stopper 26) on the polycrystalline silicon film 25 is formed to be thin in accordance with the thickness of the silicon nitride film 28, the thickness of the silicon nitride film 28 is large. The contained hydrogen ions are sufficiently introduced into polycrystalline silicon film 25.

  FIG. 3 shows that the threshold voltage Vt of the thin film transistor, which is a measure for knowing how much the crystal defect in the active region is filled, is two times the thickness T2 of the silicon nitride film 28 and the thickness T1 of the silicon oxide film 27. It is a figure showing how much it changes according to the ratio to the power (T1 ^ 2 / T2). This figure shows the measured values of the threshold voltage Vt of the thin film transistor at each stage by changing the composition ratio (T1 ^ 2 / T2) of the interlayer insulating film stepwise from about 2000 ° to about 10000 °. . According to the measurement results, it is understood that the threshold voltage Vt is substantially constant and stable when T1 ^ 2 / T2 is equal to or less than 4000 °. Also, it was confirmed that even when T1 ^ 2 / T2 was 6000 ° or less, the variation of the threshold voltage Vt was small, and that the threshold voltage Vt rapidly changed when T1 ^ 2 / T2 was between 8000 ° and 10000 °. . From these results, it can be determined that the minimum condition is that T1 ^ 2 / T2 is equal to or less than 8000 °, and that the optimal condition is preferably equal to or less than 4000 °.

  FIG. 4 is a cross-sectional view showing a second embodiment of the thin film transistor of the present invention, and FIG. 5 is an enlarged view of a main part thereof. This figure shows a top gate type.

  On the surface of an insulating transparent substrate 41, a silicon nitride film 42 and a silicon oxide film 43 are laminated. The silicon nitride film 42 prevents the deposition of impurity ions such as sodium contained in the transparent substrate 41, and the silicon oxide film 43 allows the polycrystalline silicon film 44 to be an active region to be stacked. In a predetermined region on the silicon oxide film 43, a polycrystalline silicon film 44 as a semiconductor film to be an active region of the thin film transistor is laminated.

  A silicon oxide film 45 serving as a gate insulating film is stacked on the silicon oxide film 43 on which the polycrystalline silicon film 44 is stacked. Then, a gate electrode 46 made of a high melting point metal such as tungsten or chromium is arranged on the silicon oxide film 45. This gate electrode 46 is arranged crossing the direction in which the polycrystalline silicon film 44 extends. The polycrystalline silicon film 44 covered by the gate electrode 46 becomes the channel region 44c, and the other polycrystalline silicon films 44 become the source region 44s and the drain region 44d. On the silicon oxide film 45 on which the gate electrode 46 is arranged, a silicon oxide film 47 and a silicon nitride film 47 are stacked. The silicon oxide film 47 and the silicon nitride film 48 form an interlayer insulating film for protecting the polycrystalline silicon film 44.

  Here, the film thickness T1 of the silicon oxide film 45 as the gate insulating film and the silicon oxide film 47 as the interlayer insulating film on the polycrystalline silicon film 44 is larger than the film thickness T2 of the silicon nitride film 48. It is set so as to satisfy Expression 1 described above. The supply of hydrogen ions to the polycrystalline silicon film 44 is the same for the bottom gate type and the top gate type. Therefore, as in the case of the bottom gate type shown in FIG. 2, if the film thickness set by the above equation 1 is satisfied, a sufficient amount of hydrogen ions can be supplied to the polycrystalline silicon film 44. .

  In the silicon oxide films 45 and 47 and the silicon nitride film 48 formed to a predetermined thickness, a contact hole 49 reaching the polycrystalline silicon film 45 is provided, and a source electrode 50s connected to the source region 45s and the drain region 45d. And a drain electrode 50d. Then, on the silicon nitride film 48, an acrylic resin layer 51 covering the source electrode 50s and the drain electrode 50d and flattening the surface is laminated. Further, a contact hole 52 reaching the source electrode 50 s is provided in the acrylic resin layer 51, and the transparent electrode 53 connected to the source electrode 50 s is arranged to spread on the acrylic resin layer 51. The source electrode 50s, the drain electrode 50d, and the transparent electrode 53 are the same as those of the bottom gate type.

  In the above-described thin film transistor, as in the case of the bottom gate type, the thickness of the silicon oxide films 45 and 46 on the polycrystalline silicon film 44 is reduced according to the thickness of the silicon nitride film 48. A sufficient amount of hydrogen ions contained in the film 48 are introduced into the polycrystalline silicon film 44 in a sufficient amount.

FIGS. 6A to 6C and FIGS. 7D to 7F are cross-sectional views for explaining steps of the method for manufacturing the thin film transistor according to the first embodiment. In these figures, the same parts as those in FIG. 1 are shown.
(A) First Step A refractory metal such as chromium or molybdenum is laminated on an insulating transparent substrate 21 to a thickness of 1000 ° by a sputtering method to form a refractory metal film 34. The refractory metal film 34 is patterned into a predetermined shape to form the gate electrode 22. In this patterning process, both ends of the gate electrode 22 are formed in a tapered shape by taper etching such that the both ends become wider on the transparent substrate 21 side.
(B) Second Step On the transparent substrate 21, silicon nitride is stacked to a thickness of 500 ° or more by a plasma CVD method, and silicon oxide is continuously stacked to a thickness of 1300 ° or more. As a result, a silicon nitride film 23 for preventing precipitation of impurity ions from the transparent substrate 21 and a silicon oxide film 24 serving as a gate insulating film are formed. Then, silicon is stacked on the silicon oxide film 23 to a thickness of 400 ° by the same plasma CVD method to form an amorphous silicon film 25 ′. Then, a heat treatment is performed at about 430 ° C. for 1 hour or more to discharge hydrogen in the silicon film 25 ′ to the outside of the film, reduce the hydrogen concentration to 1% or less, and irradiate the silicon film 25 ′ with an excimer laser. Heat until the silicon in the state is melted. As a result, silicon is crystallized to form a polycrystalline silicon film 25.
(C) Third Step A silicon oxide film 35 is formed on the polycrystalline silicon film 25 by stacking silicon oxide to a thickness of 1000 °. Then, the silicon oxide film 35 is patterned according to the shape of the gate electrode 22 to form a stopper 26 overlapping the gate electrode 22. In the formation of the stopper 26, a mask layer can be eliminated by forming a resist layer over the silicon oxide film 35 and exposing the resist layer from the transparent substrate side using the gate electrode 22 as a mask.
(D) Fourth Step P-type or N-type ions corresponding to the type of transistor to be formed are implanted into the polycrystalline silicon film 25 on which the stopper 26 has been formed. That is, when a P-channel transistor is formed, P-type ions such as boron are implanted, and when an N-channel transistor is formed, N-type ions such as phosphorus are implanted. By this implantation, a region exhibiting P-type or N-type conductivity is formed in polycrystalline silicon film 25 except for the region covered by stopper 26. These regions become a source region 25s and a drain region 25d on both sides of the stopper 26.
(E) Fifth Step The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser, and heated so that silicon does not melt. Thereby, impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned into an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), so that the transistors are separated and independent.
(F) Sixth Step Silicon oxide is deposited to a thickness of 1000 ° on the polycrystalline silicon film 25 by plasma CVD, and silicon nitride is successively deposited to a thickness of 3000 °. As a result, an interlayer insulating film composed of two layers of the silicon oxide film 27 and the silicon nitride film 28 is formed. Here, the film thickness T1 of the overlapped stopper 26 and silicon oxide film 27 is 2000 °, whereas the film thickness T2 of the silicon nitride film 28 is 3000 °, which satisfies the above equation (1). .

  After the silicon oxide film 27 and the silicon nitride film 28 are formed, the film is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 28 into the polycrystalline silicon film 25. The temperature of this heat treatment needs to be in a range in which the movement of hydrogen ions is sufficient and the transparent substrate 21 is not damaged, and a range of 350 to 450 ° C. is appropriate. Hydrogen ions contained in the silicon nitride film 28 are introduced into the polycrystalline silicon layer 25 through the silicon oxide film 27 formed to be thin according to the thickness of the silicon nitride film 28, so that hydrogen ions necessary for the polycrystalline silicon layer 25 are required. The quantity is supplied reliably. Thereby, crystal defects in polycrystalline silicon layer 25 are filled with hydrogen ions.

  After completion of the replenishment of the crystal defects in the polycrystalline silicon layer 25 by the hydrogen ions, contact holes 29 penetrating the silicon oxide film 27 and the silicon nitride film 28 are formed corresponding to the source region 25s and the drain region 25d. A source electrode 30s and a drain electrode 30d made of a metal such as aluminum are formed in the contact hole 29. The source electrode 30s and the drain electrode 30d are formed, for example, by patterning aluminum sputtered on the silicon nitride film 28 in which the contact holes 29 are formed.

  Subsequently, an acrylic resin solution is applied on the silicon nitride film 28 on which the source electrode 30s and the drain electrode 30d are formed, and is baked to form the acrylic resin layer 31. The acrylic resin layer 31 fills the unevenness due to the stopper 26, the source electrode 30s, and the drain electrode 30d and flattens the surface. Further, a contact hole 32 penetrating the acrylic resin layer 31 is formed on the source electrode 30s, and a transparent electrode 33 made of ITO or the like connected to the source electrode 30s is formed in the contact hole 32. The transparent electrode 33 is formed, for example, by patterning ITO sputtered on the acrylic resin layer 31 in which the contact hole 32 is formed.

  Through the above first to sixth steps, a bottom-gate thin film transistor having the structure shown in FIG. 1 is formed.

FIGS. 8A to 8D are cross-sectional views for respective steps illustrating a method for manufacturing a thin film transistor according to the second embodiment. In these figures, the same parts as those in FIG. 4 are shown.
(A) First Step On a transparent insulating substrate 41, silicon nitride is stacked to a thickness of 500 ° or more by a plasma CVD method, and silicon oxide is continuously stacked to a thickness of 500 °. As a result, a silicon oxide film 43 is formed, which enables lamination of the silicon nitride film 42 and the polycrystalline silicon film 44 for preventing the deposition of impurity ions from the transparent substrate 41. Further, silicon is similarly laminated to a thickness of 400 ° by the plasma CVD method to form an amorphous silicon film 44 ′. Then, a heat treatment is performed at about 430 ° C. for 1 hour or more to discharge hydrogen in the silicon film 44 ′ to the outside of the film and reduce the hydrogen concentration to 1% or less. Heat until the silicon in the state is melted. As a result, silicon is crystallized to form a polycrystalline silicon film 44.
(B) Second Step The polycrystalline silicon film 44 is patterned into a predetermined shape corresponding to the position where the transistor is formed, and is separated for each transistor. After separating the polycrystalline silicon layer 44, a silicon oxide film 45 serving as a gate insulating film is formed by stacking silicon oxide to a thickness of 1000 ° by a plasma CVD method. Then, a high melting point metal film 54 is formed by laminating a high melting point metal such as chromium or molybdenum to a thickness of 1000 ° by a sputtering method. The refractory metal film 54 is patterned into a predetermined shape crossing the polycrystalline silicon film 45 to form a gate electrode 46.
(C) Third Step Using the gate electrode 46 as a mask, P-type or N-type ions corresponding to the type of transistor to be formed are implanted into the polycrystalline silicon film 44. In this implantation, a region exhibiting P-type or N-type conductivity is formed in the polycrystalline silicon film 44 except for a region covered by the gate electrode 46. These regions become the source region 44s and the drain region 44d. Then, an excimer laser is irradiated to the polycrystalline silicon film 44 into which impurity ions of a predetermined conductivity type have been implanted, and heated so that silicon is not melted. Thereby, impurity ions in the source region 44s and the drain region 44d are activated.
(D) Fourth Step On the silicon oxide film 45 on which the gate electrode 46 has been formed, silicon oxide is deposited to a thickness of 1000 ° by plasma CVD, and silicon nitride is continuously deposited to a thickness of 3000 °. Thus, an interlayer insulating film composed of two layers of the silicon oxide film 47 and the silicon nitride film 48 is formed. Here, the film thickness T1 of the silicon oxide film 45 and the silicon oxide film 47 overlapped is 2000 °, while the film thickness T2 of the silicon nitride film 48 is 3000 °, which satisfies the above-described equation (1). ing.

  After the silicon oxide film 47 and the silicon nitride film 48 are formed, the film is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 48 into the polycrystalline silicon film 44. This heat treatment itself is the same as the heat treatment in the sixth step of the method for manufacturing the bottom gate thin film transistor shown in FIG. By the way, between the polycrystalline silicon film 44 and the gate electrode 46, hydrogen ions are very easily diffused at the respective interfaces. Therefore, in the portion of the polycrystalline silicon film 44 covered by the gate electrode 46, Hydrogen ions enter and enter. Therefore, there is no problem even if the gate electrode 46 formed of a high melting point metal does not allow passage of hydrogen ions. As a result, crystal defects in the polycrystalline silicon film 44 are filled with hydrogen ions.

  After introducing hydrogen ions into the polycrystalline silicon film 4, contact holes 49 penetrating the silicon oxide films 45 and 47 and the silicon nitride film 48 are formed corresponding to the source region 44s and the drain region 44d. Then, a source electrode 50s and a drain electrode 50d made of a metal such as aluminum are formed in the contact hole 49 portion. Subsequently, an acrylic resin solution is applied on the silicon nitride film 48 on which the source electrode 50s and the drain electrode 50d are formed, and is baked to form an acrylic resin layer 51. The acrylic resin layer 51 fills the unevenness due to the gate electrode 46, the source electrode 50s, and the drain electrode 50d, and planarizes the surface. Further, a contact hole 52 penetrating the acrylic resin layer 51 is formed on the source electrode 50s, and a transparent electrode 53 made of ITO or the like connected to the source electrode 50s is formed in the contact hole 52.

  Through the above first to fourth steps, a top-gate thin film transistor having the structure shown in FIG. 4 is formed.

  The film thickness of each portion exemplified in each of the above embodiments is an optimum value under a specific condition, and is not necessarily limited to these values. The object of the present invention can be achieved as long as the thickness of the silicon oxide film and the silicon nitride film overlapping the semiconductor film (polycrystalline silicon film) to be the active region satisfies the above equation (1).

FIG. 1 is a cross-sectional view illustrating a thin film transistor according to a first embodiment of the present invention. It is an enlarged view of the principal part of FIG. FIG. 4 is a diagram illustrating a relationship between a threshold value of a thin film transistor and a film thickness ratio of an interlayer insulating film. FIG. 4 is a cross-sectional view illustrating a thin film transistor according to a second embodiment of the present invention. FIG. 5 is an enlarged view of a main part of FIG. 4. FIG. 4 is a cross-sectional view illustrating the first half of the manufacturing method according to the first embodiment, which is performed by different processes. FIG. 7 is a sectional view illustrating the latter half of the manufacturing method according to the first embodiment, which is performed by different processes. It is sectional drawing according to process which shows the manufacturing method which concerns on 2nd Embodiment. FIG. 9 is a cross-sectional view illustrating a structure of a conventional thin film transistor.

Explanation of reference numerals

1, 21, 41 Transparent substrate 2, 22, 46 Gate electrode 3, 8, 23, 28, 42, 48 Silicon nitride film 4, 7, 24, 27, 43, 47 Silicon oxide film 5, 25, 44 Polycrystalline silicon Film 5c, 25c, 44c Channel region 5s, 25s, 44s Source region 5d, 25d, 44d Drain region 6, 26 Stopper 9, 12, 29, 32, 49, 52 Contact hole 10s, 30s, 50s Source electrode 10d, 30d, 50d Drain electrode 11, 31, 51 Acrylic resin layer 12, 33, 35 Transparent electrode

Claims (3)

A first step of forming a gate electrode on one main surface of a substrate, a second step of stacking a gate insulating film on the substrate so as to cover the gate electrode, and stacking a semiconductor film on the gate insulating film; A third step of stacking an interlayer insulating film on the semiconductor film, and a fourth step of heating the semiconductor film and the interlayer insulating film to a predetermined temperature to introduce hydrogen ions contained in the interlayer insulating film into the semiconductor film. And a third step of laminating a first silicon oxide film to a first thickness by plasma CVD in contact with the semiconductor film, and continuously forming the first silicon oxide film by plasma CVD. Stacking a silicon nitride film to a second thickness in contact with the silicon oxide film, wherein the first thickness is equal to or less than a square root of a value obtained by multiplying the second thickness by 8000 °. Of manufacturing a thin film transistor. 2. The method according to claim 1, wherein the second step includes a step of laminating amorphous silicon on the gate insulating film, and then melting and crystallizing the amorphous silicon to form a polycrystalline silicon layer. 3. The method for manufacturing a thin film transistor according to item 1. 4. The method according to claim 2, wherein in the fourth step, heat treatment is performed at a temperature in a range of 350 to 450.degree.

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