JP2003031574A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the pitch of pad array, when a connection pad using Al is to be formed on the upper face of damascene wiring, using Cu in a semiconductor device. SOLUTION: A wiring groove 12 is formed on the surface of an interlayer insulating film 11, formed on a semiconductor substrate 10 where an element, is formed. A hole for wiring connection 13, which is connected to the base being a part of the wiring groove 12 and reaches the base, is formed. The device has embedment wiring 15, embedded in the wiring groove and in the hole, through first barrier metal 14 formed in the wiring groove and the inner faces of the hole and an embed film 16, where the material of a type different from buried wiring is embedded in the partial area of buried wiring, so that a surface is positioned at the same plane as the surface of embedment wiring in the wiring groove are given.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a buried wiring structure in which a metal is buried in a wiring groove and a method of forming the same. And Al
The present invention is applied to a pad wiring layer in a memory integrated circuit having a connection pad containing as a main component.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device having a multilayer wiring structure, a wiring connection hole (a contact hole or a lower layer wiring for ensuring continuity with a device) is formed in an interlayer insulating film formed on a semiconductor substrate after the device is formed. A via hole for connection with and a wiring groove are formed, and for example, a metal containing Cu as a main component is buried to form a buried wiring.

At this time, there has been proposed a method of forming a wiring connection hole and a wiring groove by using a dual damascene process. However, in the conventional dual damascene wiring process, a damascene wiring is formed by a single filling material. ing.

Therefore, in order to form a damascene wiring using a Cu material as a pad wiring layer and use a part of the damascene wiring as a connection pad, it is necessary to newly consider the package connection process for the Cu material pad. is there.

In this case, when performing a die sort test on the chip area in a wafer state, the probe tip of the tester is brought into contact with the pad on the chip area to measure the electrical characteristics. The contact of the probe needle tip with the pad is unstable.

In order to solve this problem, a structure in which an Al material pad is formed on the Cu material damascene wiring is conceivable. However, if the Al material pad protrudes to the outside area of the Cu material damascene wiring in the in-plane direction of the substrate, the pad is formed. The pitch of the array becomes large.

An interlayer insulating film is formed on the Cu material damascene wiring to form a pad opening, an Al material pad layer is deposited on the entire surface and connected to the Cu material damascene wiring through a contact hole, and then the Al material pad is formed. A structure is conceivable in which the layer is patterned to form an Al material pad. But,
This structure has the problem of increasing the number of processes,
Design restrictions are caused by providing an inclusion margin when forming a pad opening in an interlayer insulating film on a Cu material damascene wiring by using lithography and RIE (Reactive Ion Etching).

In order to prevent the resistance from increasing due to the alloying reaction between the Cu material damascene wiring and the Al material pad,
It is desirable to deposit the barrier metal before depositing the material pad layer, but it is also necessary to consider the material and structure of this barrier metal.

[0009]

As described above, since the conventional damascene wiring is composed of a single burying material, the pitch of the pad arrangement can be reduced when the connection pads are to be formed on the upper surface of the damascene wiring. There was a problem that design restrictions such as enlargement occurred.

The present invention has been made to solve the above-mentioned problems, and has a damascene wiring composed of a plurality of embedding materials, and the pad arrangement of the pad arrangement when the connection pad is to be formed on the upper surface of the damascene wiring. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which are effective in reducing the pitch.

[0011]

A first semiconductor device of the present invention comprises: a semiconductor substrate on which elements are formed; an interlayer insulating film formed on the semiconductor substrate and having wiring grooves formed on the surface thereof; A first barrier metal formed on the inner surface of the wiring groove, an embedded wiring embedded inside the wiring groove via the first barrier metal, and an inside of the wiring groove,
It is characterized in that a material different from that of the buried wiring has a buried film buried so as to be in contact with the buried wiring at its side surface and bottom surface.

A second semiconductor device of the present invention comprises a semiconductor substrate having an element formed thereon, an interlayer insulating film having a wiring groove formed on the surface of the semiconductor substrate, and an inner surface of the wiring groove. Formed on the inner surface of the wiring groove in a state of covering the embedded first wiring and the embedded wiring embedded to the intermediate height position inside the wiring groove through the first barrier metal. And a buried film in which a conductor material of a different type from the buried wiring is buried inside the wiring groove so as to contact the second barrier metal on its side surface and bottom surface. It is characterized by including.

A method of manufacturing a semiconductor device according to the present invention is
A step of forming an interlayer insulating film on the upper surface of the semiconductor substrate after element formation, a step of forming a wiring groove on the surface portion of the interlayer insulating film, and then, on the surface of the interlayer insulating film including the inner surface of the wiring groove. A step of forming a first barrier metal on the surface of the first barrier metal, a step of depositing a metal on the surface of the first barrier metal to a height halfway inside the wiring groove, and a step of forming a second barrier on the surface of the metal. A step of forming a metal, a step of depositing a material different from the metal on the surface of the second barrier metal to a position higher than the surface of the interlayer insulating film, and a step of chemical mechanical polishing to form the wiring groove. By exposing the surfaces of the first barrier metal, the metal, the second barrier metal, and a material of a different type from the metal in the interior of the metal, the surface of the embedded wiring made of the metal is partially exposed. Different from metal Characterized by comprising the step of leaving the interconnect structure film burying made of a material of the kind is embedded inside the wiring groove.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a plan view showing an example of a pattern in the vicinity of a part of Cu-embedded wiring and an Al pad region through the surface protection film in the semiconductor device having the multilayer wiring structure according to the embodiment of FIG.

FIG. 2 is a sectional view taken along line BB 'in FIG. 1 and viewed in the direction of the arrow.

In FIG. 1 and FIG. 2, a wiring groove 12 is formed on the surface of an interlayer insulating film 11 on a semiconductor substrate 10 after element formation, and is further connected to a part of the bottom surface of the wiring groove 12. Thus, a wiring connecting hole (a contact hole reaching the substrate surface or a via hole reaching the lower layer wiring surface) 13 reaching the bottom surface of the interlayer insulating film is formed. The hole 13 and the wiring groove 12 can be formed by, for example, a dual damascene process.

Then, the wiring groove is formed through the first barrier metal 14 formed on each inner surface of the wiring groove 12 and the hole 13.
Embedded wirings 15 made of Cu or a metal containing Cu as a main component are embedded in the holes 12 and the holes 13. The first barrier metal 14 is, for example, a metal film containing a refractory metal in order to prevent Cu from diffusing into the interlayer insulating film 11.

Further, a buried film 16 made of a material different from that of the buried wiring 15 is buried inside the wiring groove 12 so that the side surface and the bottom surface of the buried film 16 are in contact with the buried wiring 15. In this case, the embedded film 16 is embedded so that the surface thereof is on the same or substantially the same plane as the surface of the embedded wiring 15, and is formed so as not to protrude to the outer region of the embedded wiring 15 in the in-plane direction of the substrate. There is.

In this example, the buried film 16 is a buried wiring.
Al or a metal containing Al as a main component embedded in a partial region of 15 through a second barrier metal 17 (for example, Al
-Cu).

Then, the embedded wiring 15 and the embedded film
A surface protective film 18 is formed on the interlayer insulating film including 16 and a pad opening 19 is formed in the surface protective film 18 on a part of the embedded film 16, and a part of the embedded film 16 is a pad for connection. It is a region PAD.

Further, the second barrier metal 17 has a role of preventing a resistance increase due to an alloying reaction between the embedded wiring 15 made of a metal containing Cu as a main component and the embedded film 16 made of Al--Cu. For example, TiN or Ta
N is used.

In the semiconductor device having the above structure, damascene wiring is composed of two kinds of wiring materials. That is, a part of the surface of the embedded wiring 15 in which Cu or a metal containing Cu as a main component is embedded in the wiring groove 12 is made of a metal whose main component is Al, which is a material different from that of the embedded wiring 15. The burying film 16 is buried, and a part of the burying film 16 serves as a pad area PAD. In this case, Cu or the embedded wiring 15 mainly composed of Cu has a role of reducing the electric resistance, and the characteristic of the Cu wiring having a low resistance can be fully utilized. Also,
The pad region PAD made of Al—Cu has a role of enabling stable connection with a bonding wire or a metal bump electrode or contact with a probe tip of a tester.

Further, since the embedded film 16 is formed so as not to extend to the outer region of the embedded wiring 15 in the in-plane direction of the substrate, the arrangement pitch of a plurality of pads arranged in the in-plane direction of the substrate should be made small. Therefore, the pattern margin at the time of forming the pad opening portion 19 in the surface protection film 18 can be reduced, and the restriction on the design does not occur.

FIGS. 3A to 3C are sectional views showing the substrate structure in a part of the process of forming the embedded wiring 15, the embedded film 16 and the pad region PAD of the semiconductor device of FIG.

As shown in FIG. 3A, S after element formation is performed.
A TEOS-based SiO ₂ film 11 formed on the i-substrate 10 and kept flat by CMP (Chemical Mechanical Polishing)
Then, a wiring connection hole 13 and a wiring groove 12 corresponding to the embedded wiring pattern continuous with the wiring connection hole 13 are formed.

Next, as shown in FIG. 3B, a first barrier metal 14 is formed on the entire surface by a sputtering method, and a Cu film 15a for a buried wiring is formed in a hole 13 and a wiring groove 12.
Embed in At this time, the Cu film formed in the wiring groove 12
At least a part of the upper surface of 15a needs to be lower than the upper surface of the SiO ₂ film 11. In other words, it is necessary to form the Cu film 15a so that a buried film formed after the Cu film 15a is also formed in the wiring groove 12 as described later.

The Cu film 15a can be embedded by a sputtering method, a CVD (vapor phase growth) method, or a plating method. In the case of adopting the electrolytic plating method, first, a thin Cu film to be a seed (SEED) layer is formed on the entire surface by a sputtering method, plating is performed by using this seed layer (Cu film) as one electrode, and then embedded. C for wiring
The u film 15a is formed on the entire surface. At this time, the film formation is stopped at the stage where the film is formed to a height midway in the wiring groove 12.

Next, as shown in FIG. 3C, a second barrier metal 17 is formed on the entire surface by a sputtering method, and an Al--Cu film 16a is further deposited on the entire surface. At this time, any of the sputtering method, the CVD method, the vapor deposition method and the like may be used, but at present, the sputtering method is preferable in terms of cost.

Next, polishing is performed by the CMP method, and as shown in FIG. 2, the first barrier metal 14, the Cu film 15, the second barrier metal 17 and the Al--Cu film 16a are formed on the respective surfaces with wiring trenches. 12
While remaining in the wiring trench 12 in a state where it is exposed to the same plane inside, unnecessary portions deposited on the interlayer insulating film 11 are removed. As a result, the Cu film 15a becomes the Cu embedded wiring 15, and the Al—Cu film 16a becomes the embedded film 16 in a state in which it does not protrude to the outer region of the embedded wiring 15 in the in-plane direction of the substrate.

After that, a surface protection film 18 is formed on the entire surface of the interlayer insulating film including the Cu embedded wiring 15 and the embedded film 16, and a pad opening 19 is formed corresponding to a part of the embedded film 16. Part of the embedded film 16
PAD.

The Cu film 15 is buried in the wiring groove 12 by the first barrier metal 14 and the second barrier metal 14 formed by the sputtering method.
The Cu film 15 is melted by the laser irradiation method after the Cu film 15 is formed on the entire surface by the sputtering method, placing importance on the compatibility with the step of forming the barrier metal 17 and the Al—Cu film 16 of FIG. It is also possible.

In the above-described semiconductor device manufacturing method, the semiconductor device shown in FIGS. 1 and 2 can be realized by a simple process by changing the type of wiring material to be embedded in the dual damascene wiring process. .

The dual damascene process in the above-described first embodiment is known, but in the embodiment, it is necessary to doubly fill the buried wiring 15 and the buried film 16 in the wiring groove 12 as described above. It is desirable that the depth of the wiring groove 12 can be accurately set independently of the depth of the via hole 13. For that purpose, the manufacturing process proposed by the "manufacturing method of a semiconductor device" of Japanese Patent Application No. 10-286732 (Japanese Patent Laid-Open No. 2000-114373) relating to the present applicant can be adopted.

<Second Embodiment> In the first embodiment,
The case where the barrier metal 17 and the metal 16 are embedded in the concave portion existing in a part of the surface portion of the embedded wiring 15 inside the wiring groove 12 is shown.

On the other hand, the second embodiment is different in that a metal other than a metal (for example, an insulating film) is buried as a buried film after the metal is buried halfway inside the wiring groove 12. Are the same. In this case,
A buried insulating film having a small arrangement pitch can be realized, and this buried insulating film can have a desired role.

<Third Embodiment> In the first embodiment,
The case where the barrier metal 17 and the metal 16 are embedded in the concave portion existing in a part of the surface portion of the embedded wiring 15 inside the wiring groove 12 is shown.

On the other hand, in the third embodiment, as shown in FIG.
As shown in (c), the first barrier metal 14 is formed on the inner surface of the wiring groove 12 to a position lower than the intermediate height position of the side surface, and the inside of the wiring groove 12 is interposed via the first barrier metal 14. Embedded wiring (eg Cu film) 15 to the middle height position
Is embedded. Then, a second layer is formed on the inner surface of the wiring groove 12 so as to cover the first barrier metal 14 and the embedded wiring 15.
Barrier metal 17 is formed, and a conductor material of a type different from that of the buried wiring 15 (for example, Al--Cu
A buried film 16 made of a film) is buried inside the wiring groove 12 so as to contact the second barrier metal 17 on its side surface and bottom surface.

In FIG. 4C, the parts corresponding to those in FIG. 2 are designated by the same reference numerals as those in FIG.

According to the third embodiment, basically the first
In addition to the same effect as in the embodiment of FIG.
It is convenient because the area of the upper surface of the pad can be made large, and the pad area can be made large when a part of the embedded film 16 is used as a pad region.

Here, with reference to FIGS. 4A to 4C, the embedded wiring 1 of the semiconductor device according to the third embodiment.
5, an example of a process of forming the buried film 16 and the pad region PAD will be briefly described.

As shown in FIG. 4A, S after element formation is performed.
A wiring connection hole 13 and a wiring groove 12 corresponding to an embedded wiring pattern continuous with the wiring connection hole 13 are formed in the SiO ₂ film 11 formed on the i substrate 10 and kept flat by CMP. Next, a first barrier metal 14 is deposited on the entire surface by a sputtering method to a thickness that does not fill the wiring groove 12, and subsequently, a Cu film 15a for a buried wiring is deposited on the entire surface and a Cu film 15a is formed as a hole. 13. The wiring groove 12 is completely embedded.

Next, as shown in FIG. 4B, the Cu film 15a and the first barrier metal 14 are ground by CMP until the SiO ₂ film 11 is exposed, and the surface is flattened. Then, the Cu film 15a is selectively etched by using the RIE method to form a step in the wiring groove 12. At this time, at least a part of the upper surface of the embedded wiring 15 made of the Cu film 15a remaining in the wiring groove 12 needs to be lower than the upper surface of the SiO ₂ film 11.

Next, as shown in FIG. 4C, a second barrier metal 17 is formed on the entire surface by a sputtering method, and an Al--Cu film 16a is further deposited on the entire surface to form the inside of the wiring groove 12. Fill the step. Next, the wiring groove 12 is polished by the CMP method.
The Al-Cu film 16a and the second barrier metal 17 are left exposed in the inside, and unnecessary portions deposited on the interlayer insulating film 11 are removed to planarize the surface. Thus, the Al--Cu film 16a remaining in the wiring groove 12
Becomes the embedded film 16 in a state where the embedded film 16 does not protrude to the region outside the wiring groove 12 in the in-plane direction of the substrate.

After that, a surface protection film 18 is formed on the entire surface of the interlayer insulating film including the second barrier metal 17 and the burying film 16, and a pad opening 19 is formed corresponding to a part of the burying film 16.
Are formed to form a part of the buried film 16 as a pad area PAD.

<Fourth Embodiment> As described in the first embodiment, when Cu or a metal containing Cu as a main component is embedded in the hole 13 and the wiring groove 12 of the interlayer insulating film 11, Cu A barrier metal 14 is formed in order to prevent diffusion into the substrate 10 and the interlayer insulating film 11. As the material of the barrier metal 14, a refractory metal or a nitride thereof (for example, a WSiN film) can be used, but these materials have a relatively high resistivity (several hundred μΩc).
m), the contact resistance with the embedded wiring becomes high, and there is a possibility that the characteristic of the Cu wiring, which has a low resistance, cannot be fully utilized.

In order to solve such a problem, Japanese Patent Application No. 10-286733 (Japanese Patent Application Laid-Open No. 2000-114374) filed by the present applicant.
No.), "semiconductor device and manufacturing method thereof", a metal silicide is formed on the substrate surface at the bottom of the hole before embedding a metal containing Cu as a main component, and a low resistance aluminum-silicide alloy film is formed on the metal silicide. And forming an alumina alloy film as a barrier metal having a Cu diffusion preventing function on the side surface of the wiring connection hole and the inner surface of the wiring groove. As the material of the metal silicide, any one of Ti, Zr, Hf, Mo, W and Ta can be used.

In the fourth embodiment, the above-mentioned Japanese Patent Application No. 10-2867 is used.
By applying the proposal of No. 33 to any of the first to third embodiments, the hole bottom portion is formed before the metal having Cu as the main component is embedded in the hole 13 and the wiring groove 12 to form the embedded wiring 15. The barrier metal of the contact portion is formed of silicide and an Al alloy, and has a lower resistance than the refractory metal or its nitride, and the contact resistance of the embedded wiring 15 can be reduced.

<Fifth Embodiment> As described in the first embodiment, when the metal containing Cu as a main component is embedded in the hole 13 and the wiring groove 12, normally, during Cu film formation or It heats after film-forming. At this time, in the heating step,
When water is released (degas) from the side walls of the holes 13 and the wiring grooves 12, the Cu wiring is damaged and voids are generated. When CMP is performed on the Cu film in a later step, wiring defects (notches) occur. It may occur.

In order to solve such a problem, Japanese Patent Application No. 10-260113 filed by the present applicant (Japanese Patent Laid-Open No. 2000-91429).
No.) “method for manufacturing a semiconductor device”, a side wall (SiN film) having a high blocking property against degas from the side wall of the hole or the wiring groove before forming the embedded wiring by burying Cu in the hole or the wiring groove. Alternatively, it was proposed that a SiO film) be formed on the side wall. Moreover, not only is the sidewall highly blocking against degas,
It also has a function as a Cu diffusion prevention film that prevents Cu in the hole and the wiring embedded with Cu in the wiring groove from diffusing from the side wall of the hole and the wiring groove into the interlayer insulating film. On this occasion,
For example, a SiN film may be formed as a sidewall by a P-CVD (plasma vapor deposition) method, and a WSiN film may be formed as a barrier metal layer. Further, as the material of the sidewall, a SiO film may be used when the SiN film is not preferable. Further, the barrier metal layer is not limited to the WSiN film, but is a refractory metal such as W,
A material containing at least one of Ta and Ti may be used.

In the fifth embodiment, the above-mentioned Japanese Patent Application No. 10-2601 is used.
By applying the proposal of No. 13 to any of the first to third embodiments, it is possible to prevent degassing from the sidewalls of holes and wiring trenches during the heating process during or after Cu film formation, and to fill them. It becomes possible to suppress the occurrence of defects (voids). As a result, when the Cu film is subjected to CMP in a later step, it is possible to suppress the occurrence of wiring loss and realize a good buried wiring.

In each of the above embodiments, the case where the via hole and the wiring groove are formed in the interlayer insulating film has been described.
Generally, when forming a wiring groove in the interlayer insulating film, such as when forming a contact hole and a wiring groove in the interlayer insulating film, and when forming a contact hole, a via hole, and a wiring groove in the interlayer insulating film at the same time. The invention can be applied.

[0053]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, when the damascene wiring made of a plurality of embedding materials is provided and the connection pad is to be formed on the upper surface of the damascene wiring. The effect that the pitch of the pad array can be reduced can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a pattern in the vicinity of a part of a Cu-embedded wiring and an Al pad region through a surface protection film in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view as seen in the direction of the arrow along the line BB ′ in FIG.

FIG. 3 is a diagram illustrating a Cu embedded wiring and A of the semiconductor device of FIG.
Sectional drawing which shows the board | substrate structure in an example of the formation process of l pad.

FIG. 4 is a cross-sectional view showing, in the order of steps, a substrate structure near a part of a Cu-embedded wiring and an Al pad region in a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

10 ... Semiconductor substrate, 11 ... Interlayer insulating film, 12 ... Wiring groove, 13 ... hole for wiring connection, 14 ... the first barrier metal, 15… Embedded wiring, 16 ... Embedded film, PAD ... Pad area, 17 ... second barrier metal, 18 ... Surface protective film, 19 ... Pad opening.

Continued front page    F term (reference) 5F033 HH09 HH11 HH32 HH33 JJ01                       JJ11 JJ25 JJ26 JJ32 JJ33                       KK01 MM02 MM03 MM12 MM13                       MM21 NN06 NN07 PP06 PP15                       PP27 QQ09 QQ37 QQ48 QQ73                       QQ75 QQ83 RR04 SS04 TT07                       VV07 XX00 XX03 XX09 XX10                       XX28 XX33

Claims (12)

[Claims] 1. A semiconductor substrate having an element formed thereon, an interlayer insulating film formed on the semiconductor substrate and having a wiring groove formed on the surface thereof, and a first barrier metal formed on an inner surface of the wiring groove. Embedded wiring embedded in the wiring groove through the first barrier metal, and a material different from the embedded wiring in the wiring groove inside the wiring groove And a buried film buried so as to be in contact with the semiconductor device. 2. The semiconductor device according to claim 1, wherein the embedded film is embedded so that the surface thereof is located in the same plane as the surface of the embedded wiring inside the wiring groove. 3. The semiconductor device according to claim 1, wherein the buried film is a metal, and a second barrier metal is present between the buried film and the buried wiring. 4. A semiconductor substrate having an element formed thereon, an interlayer insulating film formed on the semiconductor substrate and having a wiring groove formed on a surface thereof, and a first barrier metal formed on an inner surface of the wiring groove. An embedded wiring embedded to the intermediate height position inside the wiring groove through the first barrier metal, and a second barrier metal formed on the inner surface of the wiring groove so as to cover the embedded wiring. And a buried film in which a conductor material different from that of the buried wiring is buried inside the wiring groove so as to contact the second barrier metal on the side surface and the bottom surface thereof. Semiconductor device. 5. The embedded wiring is Cu or a metal containing Cu as a main component, the embedded film is a metal containing Al as a main component, and surface protection is performed on an interlayer insulating film including the embedded wiring and the embedded film. 5. A film is formed, a pad opening is formed in the surface protection film on a part of the burying film, and a part of the burying film is used as a pad region. The semiconductor device described. 6. The semiconductor device according to claim 5, wherein TiN or TaN is used for the second barrier metal. 7. The interlayer insulating film has a hole for wiring connection which is continuous with a bottom surface of a part of the wiring groove and reaches the bottom surface, and the first barrier metal is also formed on an inner surface of the hole. 7. The semiconductor device according to claim 1, wherein the semiconductor device is formed, and the embedded wiring is also embedded in the hole through the first barrier metal. 8. A step of forming an interlayer insulating film on an upper surface of a semiconductor substrate after element formation, a step of forming a wiring groove on a surface portion of the interlayer insulating film, and a step of forming an interlayer including an inner surface of the wiring groove. Forming a first barrier metal on the surface of the insulating film, depositing a metal on the surface of the first barrier metal to a height halfway inside the wiring groove, and forming a metal on the surface of the metal Forming a second barrier metal on the surface of the second barrier metal, depositing a material different from the metal on the surface of the second barrier metal to a position higher than the surface of the interlayer insulating film, and chemical mechanical polishing. By exposing the respective surfaces of the first barrier metal, the metal, the second barrier metal, and a material of a different type from the metal inside the wiring groove, the surface of the embedded wiring made of the metal Before part of And a step of leaving a wiring structure in which a buried film made of a material different from that of the metal is buried inside the wiring groove. 9. The metal forming the embedded wiring is Cu.
Alternatively, a metal containing Cu as a main component and a material forming the embedded film is a metal containing Al as a main component, and a surface protective film is deposited on the interlayer insulating film after the chemical mechanical polishing, 9. The method of manufacturing a semiconductor device according to claim 8, further comprising the step of forming a pad opening corresponding to a part of the embedded film. 10. The second barrier metal and the A
10. The method of manufacturing a semiconductor device according to claim 9, wherein the metal containing 1 as a main component is formed by a sputtering method. 11. The step of forming Cu comprises forming a thin Cu film to be a seed layer on the entire surface by a sputtering method and forming a Cu film by an electrolytic plating method using the seed layer as one electrode. Claim 9 characterized by
Alternatively, the manufacturing method of the semiconductor device according to the tenth item. 12. The step of forming the first barrier metal by a sputtering method and forming the metal containing Cu as a main component is performed by forming a metal containing Cu as a main component on the entire surface by a sputtering method and then performing laser irradiation. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the metal is melted by a method.