WO2018163020A1 - Conductor, method for manufacturing conductor, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Conductor, method for manufacturing conductor, semiconductor device, and method for manufacturing semiconductor device Download PDF

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Publication number
WO2018163020A1
WO2018163020A1 PCT/IB2018/051251 IB2018051251W WO2018163020A1 WO 2018163020 A1 WO2018163020 A1 WO 2018163020A1 IB 2018051251 W IB2018051251 W IB 2018051251W WO 2018163020 A1 WO2018163020 A1 WO 2018163020A1
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Prior art keywords
conductor
insulator
oxide
transistor
region
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PCT/IB2018/051251
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French (fr)
Japanese (ja)
Inventor
木村俊介
森若智昭
山崎舜平
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株式会社半導体エネルギー研究所
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Publication of WO2018163020A1 publication Critical patent/WO2018163020A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Definitions

  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Integrated Circuit Integrated Circuit: IC
  • LSI and VLSI technologies that have higher integration ICs are used.
  • Such an IC is mounted on a circuit board, for example, a printed wiring board, and is used as one of components of various electronic devices constituting a computer, an information terminal, a display device, an automobile, and the like. Research is also underway to use these in artificial intelligence (AI) systems.
  • AI artificial intelligence
  • desktop computers As computers and information terminals, desktop computers, laptop computers, tablet computers, smartphones, mobile phones and the like are known.
  • Silicon-based semiconductor materials are widely known as semiconductor materials used for semiconductor elements, but oxide semiconductors have attracted attention as other materials.
  • a transistor using an oxide semiconductor has extremely small leakage current in a non-conduction state.
  • a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
  • An electrode, a wiring, or a plug formed by a damascene method is used for connecting a semiconductor element or an integrated circuit (see Patent Document 2).
  • An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics and a manufacturing method thereof.
  • An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof.
  • An object of one embodiment of the present invention is to provide a highly productive semiconductor device and a manufacturing method thereof.
  • Another object of one embodiment of the present invention is to provide a semiconductor device in which a surface of an electrode, a wiring, or a plug formed by a damascene method is planarized and a manufacturing method thereof.
  • Another object of one embodiment of the present invention is to prevent impurities from entering an oxide through an electrode, a wiring, or a plug formed by a damascene method in a semiconductor device using an oxide.
  • One embodiment of the present invention includes an insulator having an opening, a first conductor provided inside the opening and having a first recess, a second conductor in contact with the bottom surface of the first recess, A semiconductor device having a third conductor in contact with the side surface of the first recess and the upper surface of the second conductor and having the second recess, and a fourth conductor provided in the second recess It is.
  • the insulator is a first insulator, and the second insulator on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor. And an oxide which overlaps with the first conductor with the body and the second insulator interposed therebetween.
  • the insulator is provided over the fifth conductor, and the first conductor, the second conductor, the third conductor, and the fourth conductor are electrically connected to the fifth conductor. May be connected.
  • the first conductor includes the first material and the second material, the first material is in contact with the side surface and the bottom surface of the opening, and the second material is the second conductor and the third material. May be in contact with the conductor.
  • the first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the second material is preferably a material different from the first material.
  • One embodiment of the present invention includes an oxide, an insulator that covers the oxide and has an opening, a first conductor that is in contact with a side surface and a bottom surface of the opening and has a first recess, and a first recess
  • a first conductor, a second conductor, a third conductor, and a fourth conductor are semiconductor devices that are electrically connected to the oxide.
  • the insulator may be a laminated body made of a plurality of insulating materials.
  • the first insulator includes any one of oxides including one or both of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum, and hafnium
  • the second insulator includes It is preferable to include an oxide containing one or both of aluminum and hafnium.
  • the first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride. It is preferable.
  • the second conductor includes any one of tungsten, copper, and aluminum
  • the fourth conductor includes any one of tungsten, copper, and aluminum
  • the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • an opening is formed in an insulator, a first conductor is formed over the insulator and in the opening, a second conductor is formed over the first conductor, and the insulator
  • the first conductor and the second conductor located above are removed, a part of the second conductor located inside the opening is removed, and the first conductor is formed on the insulator and inside the opening.
  • a third conductor is formed to be in contact with the body and the second conductor, a fourth conductor is formed on the third conductor, and the third conductor and the second conductor located above the insulator 4 is a method for manufacturing a semiconductor device in which the conductor 4 is removed.
  • the insulator is a first insulator
  • the second insulator is formed on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor.
  • An insulator may be formed, and an oxide may be formed over the second insulator so as to overlap with the fourth conductor.
  • the first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride. It is preferable.
  • the first conductor includes the first material and the second material, the first material is in contact with the side surface and the bottom surface of the opening, and the second material is the second conductor and the third material. It is preferable to contact the conductor.
  • the first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride
  • the second material is preferably a material different from the first material.
  • the second conductor includes any one of tungsten, copper, and aluminum
  • the fourth conductor includes any one of tungsten, copper, and aluminum
  • the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • a semiconductor device having favorable electrical characteristics and a manufacturing method thereof can be provided.
  • a highly reliable semiconductor device and a manufacturing method thereof can be provided.
  • a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof can be provided.
  • a highly productive semiconductor device and a manufacturing method thereof can be provided.
  • a semiconductor device in which a surface of an electrode, a wiring, or a plug formed by a damascene method is planarized and a manufacturing method thereof can be provided.
  • impurities can be prevented from entering the semiconductor device from the outside through the electrode, wiring, or plug formed by the damascene method.
  • a novel semiconductor device can be provided.
  • a module including the semiconductor device can be provided.
  • an electronic device including the semiconductor device or the module can be provided.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • 4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device.
  • FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device.
  • 1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention.
  • FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • a top view also referred to as a “plan view”
  • a perspective view a perspective view, and the like
  • some components may be omitted in order to facilitate understanding of the invention.
  • description of some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows between the source and drain via the channel region.
  • a channel region refers to a region through which a current mainly flows.
  • the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor).
  • channel width Sometimes referred to as “channel width”).
  • the effective channel width may be larger than the apparent channel width, and the influence may not be negligible.
  • the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
  • the apparent channel width may be referred to as “surrounded channel width (SCW)”.
  • SCW surrounded channel width
  • channel width in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity.
  • the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease.
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • water may also function as an impurity.
  • oxygen vacancies may be formed, for example, by mixing impurities.
  • impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • a silicon oxynitride film has a higher oxygen content than nitrogen as its composition.
  • oxygen is 55 atomic% to 65 atomic%
  • nitrogen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • the silicon nitride oxide film has a nitrogen content higher than that of oxygen.
  • nitrogen is 55 atomic% to 65 atomic%
  • oxygen is 1 atomic% to 20 atomic%
  • silicon is 25 atomic% to 35 atomic%
  • hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
  • film and “layer” can be interchanged.
  • conductive layer may be changed to the term “conductive film”.
  • insulating film may be changed to the term “insulating layer” in some cases.
  • the term “insulator” can be referred to as an insulating film or an insulating layer.
  • the term “conductor” can be restated as a conductive film or a conductive layer.
  • the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
  • the transistors described in this specification and the like are field-effect transistors unless otherwise specified.
  • the transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • a crystal when a crystal is a trigonal crystal or a rhombohedral crystal, it is included in a hexagonal crystal system.
  • a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.
  • a metal oxide is a metal oxide in a broad expression.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as OS FET, it can be translated into a transistor including an oxide or an oxide semiconductor.
  • 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention, and the periphery of the transistor 200.
  • FIG. 1A is a top view of the transistor 200.
  • 1B, 1C, and 1D are cross-sectional views of the transistor 200.
  • FIG. 1B is a cross-sectional view taken along dashed-dotted line AB in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view taken along dashed-dotted line CD in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view taken along the dashed line EF in FIG. 1A and is a cross-sectional view illustrating a connection portion between the oxide 230 and the conductor 2522. In the top view of FIG. 1A, some elements are omitted for clarity.
  • the transistor 200 includes an insulator 208, an insulator 210, and an insulator 212 disposed on a substrate (not shown), and a conductor disposed so as to be embedded in the insulator 212.
  • an insulator 274 which is disposed in contact with each other.
  • the conductor 205 provided to be embedded in the insulator 216 can be formed by a damascene method. Although details will be described later, the conductor 205 including the conductor 205a, the conductor 205b, the conductor 205c, the conductor 205d, and the conductor 205e has excellent surface flatness, and is formed of a film formed thereon. Shape defects such as coverage failures can be suppressed. In addition, an element provided over the conductor 205 has favorable characteristics.
  • the conductor 205 includes a plurality of conductive barrier films, impurities such as hydrogen and water are introduced to the transistor 200 side through the conductor 205 from the substrate side of the insulator 212 or the insulator 210. Diffusion can be suppressed. Further, diffusion of oxygen from the transistor 200 side to the substrate side through the conductor 205 can be suppressed.
  • the transistor 200 has a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are stacked as illustrated in FIG. 1, but the present invention is not limited thereto.
  • a two-layer structure of the oxide 230a and the oxide 230b or a stacked structure of four or more layers may be used.
  • a single layer including only the oxide 230b or only the oxide 230b and the oxide 230c may be provided.
  • the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this.
  • a single layer or a stacked structure of three or more layers may be used.
  • FIG. 2 shows an enlarged view of a region 239 in the vicinity of the channel, which is surrounded by a one-dot chain line in FIG.
  • the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200, and a region 231 (region 231 a and region 231 b) functioning as a source region or a drain region.
  • the bonding region 232 (the bonding region 232a and the bonding region 232b) is provided.
  • the region 231 functioning as a source region or a drain region is a region with high carrier density and low resistance.
  • the region 234 functioning as a channel formation region is a region having a lower carrier density than the region 231 functioning as a source region or a drain region.
  • a high resistance region is not formed between the region 231 functioning as a source region or a drain region and the region 234 functioning as a channel formation region, so that the on-state current of the transistor can be increased.
  • the junction region 232 includes a region overlapping with the conductor 260 functioning as a gate electrode.
  • a region overlapping with the conductor 260 functioning as a gate electrode in the junction region 232 may function as a so-called overlap region (also referred to as a Lov region).
  • the region 231 is preferably in contact with the insulator 274.
  • the region 231 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the junction region 232 and the region 234.
  • the bonding region 232 has a region overlapping with the insulator 272.
  • the junction region 232 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 234.
  • a metal element such as indium and an impurity element such as hydrogen and nitrogen
  • the region 234 overlaps with the conductor 260.
  • the region 234 is disposed between the junction region 232 a and the junction region 232 b, and the region 231 has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen, and the junction region 232. More preferably, it is smaller.
  • the boundary between the region 231, the junction region 232, and the region 234 may not be clearly detected in some cases.
  • Concentrations of metal elements such as indium and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). You may do it. That is, the closer to the region 234 from the region 231 to the junction region 232, the lower the concentration of the metal element such as indium and the impurity element such as hydrogen and nitrogen.
  • the region 234, the region 231, and the junction region 232 are formed in the oxide 230 b, but the present invention is not limited to this.
  • these regions include the oxide 230 a, Alternatively, the oxide 230c may be formed.
  • the boundary of each region is displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this.
  • the junction region 232 may protrude to the conductor 260 side near the surface of the oxide 230b and recede to the conductor 2521 side or the conductor 2522 side near the lower surface of the oxide 230b.
  • the oxide 230 is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • a transistor including an oxide semiconductor its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including an oxide semiconductor in which an oxygen vacancy is included in a channel formation region is likely to be normally on. For this reason, it is preferable that oxygen vacancies in the channel formation region be reduced as much as possible.
  • the insulator 250 overlapping with the region 234 of the oxide 230 preferably contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. That is, excess oxygen in the insulator 250 diffuses into the region 234, so that oxygen vacancies in the region 234 can be reduced.
  • the insulator 272 is preferably provided in contact with the insulator 250.
  • the insulator 272 preferably has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits). Since the insulator 272 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.
  • oxygen for example, oxygen atoms and oxygen molecules
  • the transistor 200 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen.
  • An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. Insulators using an insulating material that has (which is difficult to transmit the above impurities).
  • the conductor 205 functioning as the second gate electrode is provided so as to overlap with the oxide 230 and the conductor 260.
  • the conductor 205 is preferably provided larger than the region 234 in the oxide 230 so that the length in the channel width direction is larger.
  • the conductor 205 preferably extends in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.
  • the conductor 260 may function as the first gate electrode.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked.
  • the threshold voltage of the transistor 200 can be made higher than 0 V and the off-state current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260 is 0 V can be reduced.
  • a conductor 205a is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b is formed further inside.
  • a conductor 205c is formed inside the conductor 205b.
  • a conductor 205d is formed so as to be in contact with the inner wall of the conductor 205b and in contact with the upper surface of the conductor 205c, and a conductor 205e is formed inside the conductor 205d.
  • the heights of the upper surfaces of the conductor 205a, the conductor 205b, the conductor 205d, and the conductor 205e can be substantially the same as the height of the upper surface of the insulator 216.
  • the conductor 205a, the conductor 205b, and the conductor 205d include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like), a copper atom, and the like. It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities (it is difficult for the impurities to pass through). Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit).
  • oxygen for example, oxygen atoms and oxygen molecules
  • the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen.
  • a conductor having such a function may be referred to as a conductive barrier film.
  • the conductivity can be prevented from being reduced due to oxidation of the conductor 205c and the conductor 205e.
  • titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion. Therefore, the conductive material may be a single layer or a stacked layer as the conductor 205a, the conductor 205b, and the conductor 205d.
  • tantalum nitride is used as the conductor 205a
  • titanium nitride is used as the conductor 205b and the conductor 205d.
  • the conductor 205c and the conductor 205e are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In this embodiment mode, tungsten is used as the conductor 205c and the conductor 205e.
  • a conductor 203 that is electrically connected to the conductor 205 may be provided.
  • the conductor 203 is formed so as to be embedded in an insulator 212 provided on the insulator 210.
  • the conductor 203 can function as a wiring.
  • the conductor 205 functions as the second gate electrode of the transistor 200, part of the conductor 203 can function as a gate wiring.
  • a first conductor 203a is formed in contact with the inner wall of the opening of the insulator 212, and a conductor 203b is formed further inside.
  • the heights of the upper surfaces of the conductors 203a and 203b and the height of the upper surface of the insulator 212 can be approximately the same.
  • the transistor 200 has a structure in which the conductor 203a and the conductor 203b are stacked, the present invention is not limited to this. For example, only the conductor 203b may be provided.
  • the insulator 210 preferably functions as an insulating barrier film which prevents impurities such as water or hydrogen from entering the transistor from the substrate side. Therefore, the insulator 210 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, and the like) and copper atoms. It is preferable to use an insulating material (which is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).
  • oxygen for example, oxygen atoms and oxygen molecules
  • the insulator 210 is preferably formed using aluminum oxide, silicon nitride, or the like.
  • impurities such as hydrogen and water can be prevented from diffusing from the insulator 210 to the transistor side.
  • oxygen contained in the insulator 224 or the like can be prevented from diffusing from the insulator 210 to the substrate side.
  • the insulator 208, the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films preferably have a lower dielectric constant than the insulator 210.
  • parasitic capacitance generated between the wirings can be reduced.
  • the insulator 208, the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and titanic acid.
  • An insulator such as lead zirconate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST) can be used in a single layer or a stacked layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220, the insulator 222, and the insulator 224 function as gate insulators.
  • an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used as the insulator 224 in contact with the oxide 230. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis.
  • the oxide film has a thickness of 0.0 ⁇ 10 20 atoms / cm 3 or more.
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Is preferred.
  • the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side.
  • the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, hafnium aluminate, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST).
  • An insulator including a so-called high-k material such as a single layer or a stacked layer is preferably used. By using a high-k material for the insulator that functions as a gate insulator, transistors can be miniaturized and highly integrated.
  • an insulating material such as aluminum oxide, hafnium oxide, and hafnium aluminate that has a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits).
  • an insulating material such as aluminum oxide, hafnium oxide, and hafnium aluminate that has a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits).
  • it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 220 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining with an insulator of a high-k material.
  • the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient. Further, although the structure in which the insulator 220, the insulator 222, and the insulator 224 function as gate insulators in the transistor 200 is described, this embodiment is not limited thereto. For example, any two layers or one layer of the insulator 220, the insulator 222, and the insulator 224 may be provided as the gate insulator.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230 includes a region 231, a bonding region 232, and a region 234.
  • at least part of the region 231 is preferably in contact with the insulator 274.
  • at least part of the region 231 preferably has a concentration of at least one of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.
  • the region 231a or the region 231b functions as a source region or a drain region.
  • at least part of the region 234 functions as a region where a channel is formed.
  • the oxide 230 preferably includes a junction region 232.
  • the on-state current can be increased and the leakage current (off-state current) at the time of non-conduction can be reduced.
  • the oxide 230b over the oxide 230a, diffusion of impurities into the oxide 230b can be suppressed from a structure formed below the oxide 230a. In addition, by including the oxide 230b below the oxide 230c, diffusion of impurities into the oxide 230b can be suppressed from a structure formed above the oxide 230c.
  • the oxide 230 has a curved surface between the side surface and the upper surface. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used as the metal oxide to be the region 234. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
  • the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • the region 234 preferably has a stacked structure with oxides having different atomic ratios of metal atoms.
  • the metal oxide used for the oxide 230b has an atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. Is larger than the atomic ratio of the element M in the constituent elements.
  • the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the oxide 230c a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • An oxide can be used.
  • the said composition shows the atomic ratio in the oxide formed on the board
  • Ga: Zn 1: 3: 4 as the oxide 230a
  • In: Ga: Zn 4: 2: 3 as the oxide 230b
  • In: Ga: Zn 1: 3: 4 as the oxide 230c.
  • the oxide 230b can be sandwiched between the oxide 230a and the oxide 230c having a wider energy gap, which is preferable.
  • the oxides 230a and 230c having a wide energy gap may be referred to as a wide gap
  • the oxide 230b having a relatively narrow energy gap may be referred to as a narrow gap.
  • the wide gap and the narrow gap will be described in [Configuration of metal oxide].
  • the region 231 and the junction region 232 are regions in which a metal atom provided as the oxide 230 is added with a metal atom such as indium or an impurity to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234. Note that in order to add impurities to the region 231 and the junction region 232, for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, and an ionized source gas without mass separation. A dopant which is at least one of a metal element such as indium and an impurity may be added by an ion doping method, a plasma immersion ion implantation method, or the like.
  • the insulator 274 containing an element serving as an impurity can be formed in contact with the oxide 230, whereby the impurity can be added to the region 231 and the junction region 232.
  • the resistance of the region 231 and the junction region 232 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies.
  • elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 and the bonding region 232 may have a structure including one or more of the above elements.
  • a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used as the insulator 274.
  • oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232.
  • hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
  • the junction region 232 since the junction region 232 is provided, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; And mobility can be increased. In addition, since the junction region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, since the junction region 232 is provided, leakage current at the time of non-conduction can be reduced.
  • the insulator 250 functions as a gate insulating film.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • the amount of desorbed oxygen converted to oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3.0 ⁇ 10 20.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • the conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a.
  • the conductor 260a titanium nitride or the like is preferably used.
  • a metal having high conductivity such as tungsten can be used.
  • a conductor made of a conductive oxide may be provided between the insulator 250 and the conductor 260a.
  • a metal oxide that can be used as the oxide 230a or the oxide 230b can be used.
  • oxygen can be added to the insulator 250 and oxygen can be supplied to the oxide 230b. Accordingly, oxygen vacancies in the region 234 of the oxide 230 can be reduced.
  • the insulator 270 functioning as a barrier film may be provided over the conductor 260b.
  • an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used.
  • an insulator including one or both of aluminum and hafnium can be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Thereby, oxidation of the conductor 260 can be prevented.
  • impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
  • the insulator 271 functioning as a hard mask is preferably provided over the insulator 270.
  • the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, it can be set to 80 degrees or more and 95 degrees or less.
  • the insulator 272 to be formed next can be formed into a desired shape.
  • An insulator 272 functioning as a barrier film is provided in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270.
  • the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • an insulator including one or both of aluminum and hafnium can be used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • oxygen in the insulator 250 can be prevented from diffusing outside.
  • entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed.
  • an upper surface and a side surface of the conductor 260 and a side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. it can.
  • impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.
  • the impurity element contained in the structure provided around the transistor 200 is diffused, so that the region 231a and the region 231b or the junction is formed. There is a possibility that the region 232a and the bonding region 232b are electrically connected.
  • the insulator 272 by forming the insulator 272, impurities such as hydrogen and water can be prevented from entering the insulator 250 and the conductor 260, and oxygen in the insulator 250 can be reduced. Can be prevented from spreading outside. Therefore, when the first gate voltage is 0 V, the source region and the drain region can be prevented from being electrically connected directly or via the junction region 232 or the like.
  • the insulator 274 is provided to cover the insulator 271, the insulator 272, the oxide 230, the insulator 224, and the like.
  • the insulator 274 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen.
  • the insulator 274 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.
  • oxygen can be prevented from being transmitted through the insulator 274 and supplying oxygen to oxygen vacancies in the regions 231 a and 231 b, thereby reducing the carrier density.
  • the insulator 274 is trapped by an element that forms an oxygen vacancy in the oxide 230 or an oxygen vacancy in the oxide 230. It is preferable to have an element to be used. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.
  • a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used as the insulator 274.
  • oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232.
  • hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
  • An insulator 280 that functions as an interlayer film is preferably provided over the insulator 274.
  • the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the insulator 280 may have a stacked structure including similar insulators.
  • a conductor 252 (a conductor 2521, a conductor 2522, a conductor 2523, and a conductor 2524) that is electrically connected to the transistor 200 is provided.
  • a conductor 2521 and a conductor 2522 that are electrically connected to the oxide 230 are provided in openings formed in the insulator 280 and the insulator 274, and the insulator 280, the insulator 274, the insulator 271, and the insulator
  • a conductor 2523 electrically connected to the conductor 260 functioning as the first gate is provided in the opening formed in the 270, and the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator A conductor 2524 electrically connected to the conductor 205 functioning as the second gate is disposed in the opening formed in 220.
  • the top surfaces of the conductor 2521, the conductor 2522, the conductor 2523, and the conductor 2524 may be flush with the top surface of the insulator
  • the conductor 252 can be formed by a damascene method.
  • the conductor 2521 is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200
  • the conductor 2522 is in contact with the region 231b functioning as the other of the source region and the drain region of the transistor 200. Since the region 231a and the region 231b have low resistance, the contact resistance between the conductor 2521 and the region 231a and the contact resistance between the conductor 2522 region 231b can be reduced and the on-state current of the transistor 200 can be increased.
  • the conductor 2522 is preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230.
  • the conductor 2522 is preferably in contact with both or one of the side surface on the C side and the side surface on the D side on the side surface intersecting the channel width direction of the oxide 230.
  • the conductor 2522 may be in contact with the side surface on the A side (B side) on the side surface intersecting the channel length direction of the oxide 230.
  • the conductor 2522 (conductor 2521) is in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact portion between the conductor 2522 (conductor 2521) and the oxide 230 is formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductor 2522 (conductor 2521) and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • a conductor 252 a is formed in contact with the inner wall of each opening, and a conductor 252 b is formed further inside.
  • a conductor 252c is formed so as to be in contact with an inner wall of the conductor 252a and in contact with an upper surface of the conductor 252b, and a conductor 252d is formed inside the conductor 252c.
  • the heights of the top surfaces of the conductor 252a, the conductor 252c, and the conductor 205d can be approximately the same as the height of the top surface of the insulator 280.
  • the conductor 252 is provided with a conductor 252a and a conductor 252c inside each opening. That is, two conductors functioning as a conductive barrier are provided. With the conductive barrier having a two-layer structure, it is possible to more effectively suppress impurities in the insulator 280 or impurities generated in the subsequent steps from entering the transistor 200 through the conductor 252. Can do.
  • the conductor 252c is provided such that the outer side surface is in contact with the inner side surface of the conductor 252a, so that the effect of suppressing impurity contamination is improved.
  • an insulator having a function of suppressing transmission of impurities such as water or hydrogen may be provided in contact with the inner walls of the openings of the insulator 274 and the insulator 280 in which the conductor 252 is embedded.
  • an insulator that can be used for the insulator 270 and the insulator 272, for example, aluminum oxide is preferably used. Accordingly, impurities such as hydrogen and water from the insulator 280 and the like can be prevented from entering the oxide 230 through the conductor 252.
  • the insulator can be formed with good coverage by forming the insulator using, for example, an ALD method or a CVD method.
  • the conductor 256 functioning as a wiring may be provided in contact with the upper surface of the conductor 252.
  • the conductor 256 functioning as a wiring is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • a plurality of conductive barrier films may be provided in at least one of the conductor 205 and the conductor 252 in accordance with characteristics and specifications required for the semiconductor device.
  • a substrate over which the transistor 200 is formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate may be used as the substrate.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • the substrate may have elasticity.
  • the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, more preferably 15 ⁇ m to 300 ⁇ m.
  • a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate which is a flexible substrate for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used.
  • a substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • the substrate which is a flexible substrate for example, a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
  • Insulator examples include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
  • a high-k material having a high relative dielectric constant is used for the insulator that functions as a gate insulator, so that transistors can be miniaturized and highly integrated. Become.
  • an insulator functioning as an interlayer film a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
  • Insulators having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium-containing oxides, aluminum and hafnium-containing oxynitrides, silicon and hafnium-containing oxides, silicon And oxynitride having hafnium or nitride having silicon and hafnium.
  • Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.
  • silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.
  • a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
  • Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used as the insulator 222 and the insulator 210.
  • the insulator 222 and the insulator 210 can be formed using an insulator containing one or both of aluminum and hafnium.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • Examples of the insulator 220, the insulator 224, the insulator 250, and the insulator 271 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium,
  • An insulator containing zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • silicon oxide, silicon oxynitride, or silicon nitride is preferably included.
  • the insulator 224 and the insulator 250 that function as gate insulators have a structure in which aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide is in contact with the oxide 230, so that silicon oxide or silicon oxynitride is included. It is possible to prevent silicon to be mixed into the oxide 230.
  • the insulator 224 and the insulator 250 by using silicon oxide or silicon oxynitride in contact with the oxide 230, aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide, and silicon oxide or silicon oxynitride In some cases, a trap center is formed at the interface. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.
  • the insulator 208, the insulator 212, the insulator 216, and the insulator 280 preferably include an insulator with a low relative dielectric constant.
  • the insulator 208, the insulator 212, the insulator 216, and the insulator 280 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and It is preferable to include silicon oxide to which nitrogen is added, silicon oxide having holes, or a resin.
  • the insulator 208, the insulator 212, the insulator 216, and the insulator 280 are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and the like. It is preferable to have a stacked structure of silicon oxide to which nitrogen is added or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.
  • the insulator 270 and the insulator 272 include metal oxides such as aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide. Silicon nitride oxide, silicon nitride, or the like may be used.
  • Conductor a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc.
  • a material containing one or more elements can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed using the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
  • the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode.
  • the above-described conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260, the conductor 205, the conductor 203, the conductor 252, and the conductor 256 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium
  • a material containing one or more metal elements selected from manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used.
  • an oxide semiconductor a metal oxide functioning as an oxide semiconductor
  • the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
  • the oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
  • the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • composition of metal oxide A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.
  • CAAC c-axis aligned crystal
  • CAC Cloud-aligned Composite
  • CAC-OS or CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material has a function as a semiconductor.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is an electron serving as carriers. It is a function that does not flow.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily.
  • CAC-OS or CAC-metal oxide by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor).
  • OS amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain.
  • the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons.
  • a lattice arrangement such as a pentagon and a heptagon in the distortion.
  • a clear crystal grain boundary also referred to as a grain boundary
  • the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
  • the CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked.
  • In layer a layer containing indium and oxygen
  • M, Zn elements M, zinc, and oxygen
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
  • the CAAC-OS is an oxide semiconductor with high crystallinity.
  • CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs.
  • the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and different properties.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
  • an oxide semiconductor with low carrier density is preferably used.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the oxide semiconductor has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / What is necessary is just to be cm 3 or more.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.
  • the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen in the oxide semiconductor is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less in SIMS. Preferably, it is 5 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • an oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • FIG. 3A is a top view of the transistor 201.
  • 3B, 3C, and 3D are cross-sectional views of the transistor 201.
  • FIG. 3B is a cross-sectional view taken along dashed-dotted line AB in FIG. 3A and a cross-sectional view in the channel length direction of the transistor 200.
  • FIG. 3C is a cross-sectional view taken along dashed-dotted line CD in FIG. 3A and also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 3D is a cross-sectional view taken along the dashed line EF in FIG. 3A, and is also a cross-sectional view illustrating a connection portion between the oxide 230 and the conductor 2522.
  • FIG. 3A some elements are omitted for clarity.
  • the structure of the transistor 201 will be described with reference to FIGS. Note that in this item as well, the material described in detail in ⁇ Structure Example 1 of Semiconductor Device> can be used as the constituent material of the transistor 201.
  • a conductor 285 functioning as a source electrode or a drain electrode is provided over the oxide 230b.
  • An insulator 286 is provided over the conductor 285.
  • a material similar to that of the conductor 205 can be used.
  • tantalum nitride or tungsten is preferably used.
  • the insulator 286 can be formed using a material similar to that of the insulator 270 or the insulator 272.
  • the channel length of the transistor 201 is determined depending on the length between the conductors 285, the channel length of the transistor 201 is unintentionally increased due to oxidation of the ends of the opposing conductors 285. May occur.
  • the insulator 286 is preferably provided.
  • a region in contact with the conductor 285 surrounded by a dotted line in the oxide 230b is n-type and becomes a low resistance region. This is considered to be because the conductor 285 extracts oxygen from the oxide 230b and causes oxygen vacancies in the oxide 230b. Impurities existing inside or outside the oxide 230b are captured by oxygen vacancies in the oxide 230b, and the resistance of the region is reduced.
  • An oxide 230c, an oxide 230d, an insulator 250, a conductor 260, and an insulator 270 are provided so as to cover the oxide 230b, the conductor 285, and part of the insulator 286.
  • the conductor 260 has the width in the AB direction and the length in the CD direction as shown in FIGS. 3A, 3B, and 3C, and has an oxide 230c. It is smaller than the object 230d, the insulator 250, and the insulator 270. Therefore, the insulator 270 covers the top surface and the side surface of the conductor 260 and is in contact with the insulator 250 outside the conductor 260. Since the insulator 270 is formed using a material that suppresses permeation of oxygen, the insulator 270 thus provided can suppress the oxidation of the conductor 260 and suppress an increase in electrical resistance.
  • a material similar to that of the oxide 230b can be used for the oxide 230c.
  • the oxide 230d can be formed using the same material as the oxide 230a. Note that the oxide 230c is not necessarily formed.
  • a channel is formed in a region between the pair of conductors 285 or the pair of low resistance regions in the oxides 230b and 230c.
  • An insulator 287 and an insulator 288 are formed over the insulator 280.
  • an oxide insulator formed by a sputtering method is preferably used.
  • aluminum oxide, hafnium oxide, or hafnium aluminate is preferably used.
  • oxygen can be added to the insulator 280 through a surface where the insulator 280 and the insulator 287 are in contact with each other, so that the insulator 280 can be in an oxygen-excess state.
  • Oxygen supplied to the insulator 280 is supplied to the oxide 230.
  • oxygen added to the insulator 224 and the insulator 280 can move upward during film formation. Diffusion can be suppressed. Thereby, oxygen can be added to the insulator 280 more efficiently.
  • the insulator 288 can be formed using a material similar to that of the insulator 208, the insulator 212, the insulator 216, and the insulator 280.
  • an opening is provided in an insulator such as the insulator 280, the insulator 287, and the insulator 288, and the opening is provided inside the opening.
  • a conductor 252 (a conductor 2521, a conductor 2522, a conductor 2523, and a conductor 2524) is provided.
  • An insulator 289 is provided between the conductor 252 and the insulator such as the insulator 280, the insulator 287, and the insulator 288.
  • the insulator 289 can be formed using a material similar to that of the insulator 270 and suppresses entry of impurities into the oxide 230 from the insulator 280 and an upper insulator or conductor.
  • the conductor 2522 (conductor 2521) is in contact with the side surface of the oxide 230 in addition to the conductor 285, so that the contact portion between the conductor 2522 (conductor 2521) and the oxide 230 is formed.
  • the contact area of the contact portion can be increased, and the contact resistance between the conductor 2522 (conductor 2521) and the oxide 230 can be reduced.
  • the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
  • FIG. 4A is a schematic cross-sectional view showing a state where the conductor 203, the insulator 216 on the conductor 203, and the hard mask 101 and the resist mask 103 on the insulator 216 are formed.
  • the shape of the resist mask 103 when viewed from the direction perpendicular to the insulator 216 is formed to be the reverse of the shapes of wirings, electrodes, and plugs formed in a later step.
  • the insulator 216 is processed by etching to form an opening.
  • etching dry etching or wet etching can be used, but for fine processing, dry etching capable of performing anisotropic etching is preferably used.
  • the conductor 203 preferably functions as an etching stopper. Specifically, in forming the opening, the etching rate of the conductor 203 is preferably lower than the etching rate of the insulator 216.
  • both the resist mask 103 and the hard mask 101 may be used as a mask in the etching treatment, or only the hard mask 101 may be used.
  • the resist mask 103 may disappear when the hard mask 101 is formed, or may be removed using a chemical solution or plasma after the hard mask 101 is formed.
  • a conductor 205A is formed over the insulator 216 so as to cover the opening.
  • the hard mask 101 is not removed, and the conductor 205A is formed so that the hard mask 101 exists between the insulator 216 and the conductor 205A.
  • the conductor 205A is formed by stacking a plurality of conductors.
  • the conductors 205aA and 205bA preferably function as a conductive barrier.
  • a conductive barrier is a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. Is the body.
  • the conductive barrier titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. By using such a conductive barrier, impurities can be prevented from entering the transistor 200.
  • tantalum nitride is used as the conductor 205aA, and impurities such as copper atoms are prevented from diffusing upward from the conductor 205aA from the conductor 203 side.
  • titanium nitride is used as the conductor 205bA, and impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N 2 O, NO, NO 2, etc.) Diffusion above the conductor 205bA is suppressed.
  • Titanium nitride also functions as a tungsten seed layer formed by a metal CVD method in a later step.
  • a low-resistance conductive material is preferably used.
  • the low resistance conductive material tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used as the conductor 205cA and is formed by a metal CVD method.
  • FIG. 4C is a diagram for explaining a state in the middle of forming the conductor 205cA made of tungsten by a metal CVD method.
  • the conductor 205cA is formed to grow in a direction perpendicular to each of the surface of the insulator 216, the bottom surface of the opening, and the side surface using the conductor 205bA made of titanium nitride as a seed layer. That is, in the opening, the formation of the conductor 205cA proceeds in the vertical direction from the side surface of the opening (that is, in the horizontal direction in FIG. 4C).
  • the conductors 205cA that have been formed from the side surfaces of the openings collide with each other at substantially the center of the opening, and the inside of the opening is filled with the conductor 205cA.
  • FIG. 5A is a diagram showing the state after the conductor 205cA is formed.
  • a region where tungsten having different formation directions collide with each other is formed from the center of the opening toward the surface of the conductor 205cA. This area is called a seam 105. It is considered that a gap exists along the seam 105 in the conductor 205cA. Further, it is considered that the density of the conductor 205cA is sparse around the seam 105.
  • optical end point detection For removing the conductor using the CMP method, it is preferable to use optical end point detection or motor current detection type (torque type) end point detection.
  • a change in the reflection of the laser or white light on the surface to be polished can be detected by a sensor provided in the end point detector to determine the polishing end time.
  • the end point detector can detect a change in resistance due to friction generated between the polishing cloth and the surface to be polished, and determine the polishing end time.
  • the reflectivity with respect to the laser and white light and the resistance due to friction generated with respect to the polishing cloth be different between the conductor 205cA, the conductor 205bA, the conductor 205aA, the hard mask 101, and the insulator 216. .
  • the conductor 205cB after the polishing process by the CMP method may be formed with a concave portion around the portion where the seam 105 is formed in the conductor 205cA.
  • This recess is called a keyhole 107.
  • the chemical contained in the slurry is infiltrated into the seam 105 or the gap existing along the seam 105, and the conductor 205cA around the seam 105 becomes brittle due to a reaction with the chemical such as oxidation. This is considered to be caused by excessive polishing by a polishing pad.
  • the chemical 205 is easily soaked in because the density of the conductor 205cA around the seam 105 is sparse, or is easily polished by abrasive grains or a polishing pad.
  • FIG. 5C illustrates an example in which an insulator or an oxide is stacked over the conductor 205 ⁇ / b> B having the keyhole 107.
  • An insulator 220, an insulator 222, an insulator 224, an oxide 230a, and an oxide 230b are formed over the insulator 216 and the conductor 205B.
  • the keyhole 107 causes a defective shape such as a recess 109 formed in the insulator or oxide.
  • the shape defect affects the operation of the transistor and the circuit, and causes a characteristic defect.
  • the crystallinity of the oxide 230 may be deteriorated.
  • the keyhole 107 formed in the conductor 205cB is removed.
  • the conductor 205cB is half-etched to form the conductor 205cC from which the keyhole 107 is removed.
  • dry etching or wet etching can be used for removing the conductor 205cB.
  • the polishing by the CMP method may be finished while leaving the hard mask 101. Since the hard mask 101 remains, etching and contamination of the insulator 216 can be reduced without exposing the insulator 216 during etching of the conductor 205cB. In the case where the hard mask 101 and the conductor 205cB are made of the same material, the hard mask 101 can be removed during the etching of the conductor 205cB. Even when the hard mask 101 disappears during the etching of the conductor 205cB, the time for the insulator 216 to be exposed can be reduced; therefore, it is preferable to leave the hard mask 101 after polishing by the CMP method. On the other hand, in the half etching of the conductor 205cB in the next process, the hard mask 101 may be removed if the etching amount of the insulator 216 does not affect the subsequent process.
  • FIG. 6B shows a state after the conductor 205cB is half-etched.
  • the hard mask 101 is removed by etching the conductor 205cB.
  • the etching rates of the conductor 205aB and the conductor 205bB are lower than the etching rate of the conductor 205cB, the conductor 205aB and the conductor 205bB remain unetched and protrude above the insulator 216. Yes.
  • the present embodiment is not limited to this.
  • the hard mask 101 may remain after the conductor 205cB is etched, or the conductor 205aB and the conductor 205bB may be etched, and the upper surface thereof may substantially coincide with the upper surface of the insulator 216 or the upper surface of the conductor 205cC.
  • a conductor 205dA and a conductor 205eA are sequentially formed so as to cover the insulator 216, the conductor 205aB, the conductor 205bB, and the conductor 205cC.
  • the conductor 205dA is preferably a conductor that functions as a conductive barrier, and titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. More preferably, the same material as that of the conductor 205bA is used.
  • titanium nitride is used as the conductor 205dA, and from the conductor 203 side, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, etc.), etc. Are prevented from diffusing above the conductor 205dA.
  • a low-resistance conductive material is preferably used.
  • the low resistance conductive material tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used as the conductor 205eA and is formed by a metal CVD method.
  • the conductors 205dA and 205eA located above the insulator 216 are removed.
  • a CMP method can be used to remove the conductor 205dA and the conductor 205eA.
  • the conductor 205aB and the conductor 205bB protrude above the insulator 216
  • the conductor 205aB and the conductor 205bB located above the insulator 216 are removed in the step of removing the conductor 205dA and the conductor 205eA.
  • the conductor 205 including the conductor 205a, the conductor 205b, the conductor 205c, the conductor 205d, and the conductor 205e is formed. Note that since the seam 111 in the conductor 205eA is removed by polishing by the CMP method, the keyhole as shown in FIG. 6A is not formed.
  • the conductor 205 is provided with a conductor 205b and a conductor 205d inside an opening formed in the insulator 216. That is, two conductors functioning as a conductive barrier are provided. By making the conductive barrier into a two-layer structure, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. from the conductor 203 side Can be prevented from diffusing above the conductor 205.
  • the conductor 205d is provided so that the outer side surface is in contact with the inner side surface of the conductor 205b, and the effect of suppressing impurity diffusion is improved. Further, the conductor 205a is provided outside the conductor 205b so as to be in contact with the conductor 205b, and the effect of suppressing impurity diffusion is further improved.
  • the conductor 205 formed in this manner can be used as an electrode such as a gate electrode in a semiconductor device, or a wiring connecting a transistor or a circuit.
  • the plug is formed in a contact hole provided in an insulator between the first element and the second element provided on the first element and at least partially overlapping the first element;
  • the first element and the second element are electrically connected. That is, it can be used for connection between wirings in a semiconductor device, connection between wirings and elements such as transistors and capacitors, connection between elements, and the like. More specifically, it is used for connection between a wiring and a source, drain or gate of a transistor, connection between a wiring and a capacitor electrode, connection between a source, drain or gate of a transistor and a capacitor electrode, or the like. Can do.
  • FIG. 7A illustrates a structure in which an insulator 274 and an insulator 280 are sequentially stacked over the oxide 230, the hard mask 113 is provided over the insulator 280, and the resist mask 115 is provided over the hard mask 113.
  • the oxide 230 functions as one of a source and a drain of the transistor.
  • a conductor functioning as a source electrode or a drain electrode may be provided over the oxide 230.
  • the number of insulators provided over the oxide 230 is two layers; however, this embodiment is not limited to this.
  • the insulator provided over the oxide 230 may be a single layer or a stacked structure including three or more layers.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, oxide containing hafnium and aluminum (hafnium aluminate), or the like can be used as the insulator 274 and the insulator 280.
  • silicon nitride is used as the insulator 274 and silicon oxynitride is used as the insulator 280.
  • insulators include a three-layer structure in which hafnium aluminate, silicon nitride, and silicon oxynitride are sequentially stacked, a three-layer structure in which aluminum oxide, silicon nitride, and silicon oxynitride are sequentially stacked, or aluminum oxide and oxide
  • a four-layer structure in which silicon nitride, aluminum oxide, and silicon oxynitride are sequentially stacked may be employed.
  • the insulator 280 and the insulator 274 are processed by etching to form openings.
  • etching dry etching or wet etching can be used, but for fine processing, dry etching capable of performing anisotropic etching is preferably used.
  • both the resist mask 115 and the hard mask 113 may be used as a mask in the etching treatment, or only the hard mask 113 may be used.
  • the resist mask 115 may disappear when the hard mask 113 is formed, or may be removed using a chemical solution or plasma after the hard mask 113 is formed.
  • a conductor 252A is formed over the insulator 280 so as to cover the opening.
  • this embodiment shows an example in which the conductor 252A is formed so that the hard mask 113 exists between the insulator 280 and the conductor 252A without removing the hard mask 113, the invention is not limited to this.
  • the conductor 252A may be formed after the hard mask 113 is removed after the opening is formed.
  • the conductor 252A is formed by stacking a plurality of conductors.
  • the conductor 252aA preferably functions as a conductive barrier.
  • the conductive barrier preferably has a function similar to that described above, and titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. By using such a conductive barrier, impurities in the insulator 280 or impurities generated in a subsequent process can be prevented from being mixed into the transistor 200.
  • titanium nitride is used as the conductor 252aA. Titanium nitride can be used as a seed layer when tungsten is formed by metal CVD in a later step.
  • a low-resistance conductive material is preferably used.
  • the low resistance conductive material tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used for the conductor 252bA and is formed by a metal CVD method. A seam 117 is formed by the material and the formation method of the conductor 252bA (see FIG. 7C).
  • a CMP method can be used to remove the conductor 252A.
  • FIG. 8A illustrates a state where the conductor 252bA located above the insulator 280 and above the conductor 252aA is removed, and a conductor 252B including the conductor 252aA and the conductor 252bB is formed. .
  • a part of the conductor 252aA is exposed outside the conductor 252bB.
  • the conductor 252bB may be formed with a recess, that is, a keyhole 119.
  • the conductor 252bA and the conductor 252aA located above the hard mask 113 provided over the insulator 280 are removed, and the conductor 252C including the conductor 252aC and the conductor 252bC is formed. It shows a state.
  • the hard mask 113 is exposed outside the conductor 252C.
  • the conductor 252bC may be formed with a recess, that is, a keyhole 119.
  • FIG. 8C illustrates a state where the conductor 252bA, the conductor 252aA, and the hard mask 113 located above the insulator 280 are removed, and a conductor 252D including the conductor 252aD and the conductor 252bD is formed. ing. An insulator 280 is exposed outside the conductor 252C. In addition, a recess, that is, a keyhole 119 may be formed in the conductor 252bD.
  • optical end point detection For removing the conductor using the CMP method, it is preferable to use optical end point detection or motor current detection type (torque type) end point detection.
  • a change in the reflection of the laser or white light on the surface to be polished can be detected by a sensor provided in the end point detector to determine the polishing end time.
  • the end point detector can detect a change in resistance due to friction generated between the polishing cloth and the surface to be polished, and determine the polishing end time.
  • the reflectance with respect to a laser and white light, and the resistance by friction which arise with respect to polishing cloth differ between the conductor 252bA, the conductor 252aA, the hard mask 113, and the insulator 280.
  • the state after removing the conductor using the CMP method may be any of those shown in FIGS. 8A to 8C, and may be determined in consideration of the ease of detecting the end point. .
  • FIG. 9A illustrates a conductor 252bE in which the conductor 252bB illustrated in FIG. 8A is half-etched and part of the conductor 252bB including the keyhole 119 is removed.
  • dry etching or wet etching can be used for the removal of the conductor 252bB.
  • the conductor 252aA may be etched during the etching of the conductor 252bB.
  • the conductor 252bB and the hard mask 113 are made of the same material or can be etched under the same etching conditions, the hard mask 113 may be etched during the etching of the conductor 252bB.
  • FIG. 9B illustrates a conductor 252bE in which the conductor 252bC illustrated in FIG. 8B is half-etched and part of the conductor 252bC including the keyhole 119 is removed.
  • dry etching or wet etching can be used for removing the conductor 252bC.
  • the conductor 252bC and the hard mask 113 are made of the same material or can be etched under the same etching conditions, the hard mask 113 may be etched during the etching of the conductor 252bC.
  • FIG. 9C illustrates a conductor 252bE in which the conductor 252bD illustrated in FIG. 8C is half-etched and part of the conductor 252bD including the keyhole 119 is removed. Dry etching or wet etching can be used to remove the conductor 252bD.
  • the seam 121 may remain on the conductor 252bE.
  • the upper surface of the conductor 252bE is lower than the upper surface of the insulator 280, and a recess is formed.
  • a conductor is formed over the conductor 252bE and the insulator 280.
  • FIG. 10A illustrates the case where the conductor 252cA is formed over the conductor 252bE and the conductor 252aA illustrated in FIG. 9A and the conductor 252dA is formed over the conductor 252cA.
  • the conductor 252cA and the conductor 252dA fill the upper surface of the conductor 252bE and the recess formed on the upper surface of the conductor 252aA. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam.
  • a seam 123 may be formed at 252 dA.
  • conductor 252cA As the conductor 252cA, a conductor similar to the conductor 252aA can be used.
  • conductor 252dA a conductor similar to the conductor 252bA can be used.
  • FIG. 10B illustrates the case where the conductor 252cB is formed over the conductor 252bE and the insulator 280 illustrated in FIG. 9B and the conductor 252dB is formed over the conductor 252cB.
  • the conductor 252cB and the conductor 252dB fill the recess formed on the upper surface of the conductor 252bE and the upper surface of the insulator 280. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam.
  • a seam 123 may be formed at 252 dB.
  • conductor 252cB a conductor similar to the conductor 252aA can be used.
  • conductor 252dB a conductor similar to the conductor 252bA can be used.
  • FIG. 10C illustrates the case where the conductor 252cC is formed over the conductor 252bE and the insulator 280 illustrated in FIG. 9C and the conductor 252dC is formed over the conductor 252cC.
  • the conductors 252cC and 252dC fill the upper surface of the conductor 252bE and the recess formed on the upper surface of the insulator 280. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam.
  • a seam 123 may be formed at 252 dC.
  • conductor 252cC a conductor similar to the conductor 252aA can be used.
  • conductor 252dC a conductor similar to the conductor 252bA can be used.
  • the conductor located above the insulator 280 is removed by a CMP method, and a conductor including the conductor 252a, the conductor 252b, the conductor 252c, and the conductor 252d is formed.
  • a body 252 is formed.
  • a conductor 256 that functions as a wiring and includes a conductor 256a, a conductor 256b, and a conductor 256c may be formed over the conductor 252 as needed.
  • the oxide 230 and the conductor 256 are electrically connected through the conductor 252.
  • a conductor 252a and a conductor 252c are provided inside the openings formed in the insulator 280 and the insulator 274. That is, two conductors functioning as a conductive barrier are provided. With the conductive barrier having a two-layer structure, it is possible to more effectively suppress impurities in the insulator 280 or impurities generated in the subsequent steps from entering the transistor 200 through the conductor 252. Can do.
  • the conductor 252c is provided such that the outer side surface is in contact with the inner side surface of the conductor 252a, so that the effect of suppressing impurity contamination is improved.
  • FIGS. 12 to 23 a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. 12 to 23,
  • (B) of each figure is sectional drawing corresponding to the site
  • (C) of each figure is sectional drawing corresponding to the site
  • (D) of each figure is sectional drawing corresponding to the site
  • a substrate (not shown) is prepared, and an insulator 208 is formed over the substrate.
  • the insulator 208 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD (ALD) method. (Atomic Layer Deposition) method or the like can be used.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed.
  • the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • a silicon oxide film is formed as the insulator 208 by a CVD method.
  • the insulator 210 is formed over the insulator 208.
  • an aluminum oxide film is formed as the insulator 210 by a sputtering method.
  • the insulator 210 may have a multilayer structure.
  • an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method.
  • a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.
  • the insulator 212 is formed over the insulator 210.
  • the insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 216 by a CVD method.
  • an opening is formed in the insulator 212.
  • the opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • the insulator 210 may be used as an etching stopper film when the insulator 212 is etched to form a groove.
  • a silicon oxide film is used for the insulator 212 forming the groove
  • a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 210 as an insulating film functioning as an etching stopper film.
  • a conductive film to be the conductor 203a is formed.
  • the conductive film preferably includes a conductor having a function of suppressing permeation of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductor to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 203a tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method.
  • a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out of the conductor 203a even when a metal that easily diffuses such as copper is used in the conductor 203b described later.
  • a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a.
  • the conductive film can be formed by using one method selected from a sputtering method, a CVD method, an MBE method, a plating method, a PLD method, an ALD method, or a combination of a plurality of methods.
  • a low-resistance conductive material such as tungsten or copper is formed as the conductive film to be the conductor 203b.
  • the conductive film to be the conductor 203a and part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed.
  • the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 12). Note that part of the insulator 212 may be removed by the CMP treatment.
  • the insulator 216 is formed over the insulator 212 and the conductor 203.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed as the insulator 216 by a CVD method.
  • an opening is formed in the insulator 216.
  • Wet etching may be used to form the opening, but dry etching is preferable for fine processing.
  • the conductor 203 may be used as an etching stopper film when the insulator 216 is etched to form a groove.
  • the conductor 205 described in ⁇ Conductor manufacturing method 1> is formed (see FIG. 12).
  • the insulator 220 is formed over the insulator 216 and the conductor 205.
  • the insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 is formed over the insulator 220.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator including one or both of aluminum and hafnium is preferably used.
  • the insulator containing one or both of aluminum and hafnium aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
  • the insulator 222 is preferably formed by an ALD method.
  • the insulator 222 formed by the ALD method has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 13).
  • heat treatment is preferably performed.
  • the heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.
  • the first heat treatment may be performed in a reduced pressure state.
  • heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be.
  • impurities such as hydrogen and water contained in the insulator 224 can be removed.
  • plasma treatment containing oxygen in a reduced pressure state may be performed as the heat treatment.
  • the plasma treatment including oxygen it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • a power source for applying RF (Radio Frequency) may be provided on the substrate side.
  • High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side.
  • plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.
  • the heat treatment can also be performed after the insulator 220 is formed and after the insulator 222 is formed. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.
  • treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed.
  • an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 13).
  • the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
  • the oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed.
  • the ratio of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.
  • an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed.
  • a transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.
  • the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 14).
  • the insulator 224 may be processed into an island shape. Further, half etching may be performed on the insulator 224. By performing half etching on the insulator 224, the insulator 224 is formed in a state where the insulator 224 remains also under the oxide 230c formed in a later step. Note that the insulator 224 can be processed into an island shape when the insulating film 272A, which is a subsequent step, is processed. In that case, the insulator 222 may be used as an etching stopper film.
  • the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially.
  • the side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased.
  • the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.
  • a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape).
  • the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, for example, at the ends of the oxide 230a and the oxide 230b.
  • membrane coverage in a subsequent film-forming process improves by not having a corner
  • the oxide film may be processed by a lithography method.
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultra violet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do.
  • the etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after the oxide film is etched.
  • the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a, the oxide 230b, or the like.
  • impurities include fluorine and chlorine.
  • Cleaning is performed in order to remove the impurities and the like.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning using pure water or carbonated water may be performed.
  • ultrasonic cleaning using pure water or carbonated water is performed.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • the oxide film 230C, the insulating film 250A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b (FIG. 15).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c.
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film 250A is exposed to the oxygen plasma, so that oxygen is supplied to the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.
  • heat treatment may be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
  • the conductive film 260A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • titanium nitride is formed as the conductive film 260A by a sputtering method.
  • the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a transistor with a low driving voltage can be provided.
  • tungsten is formed as the conductive film 260B by a sputtering method.
  • a conductor may be further provided between the insulating film 250A and the conductive film 260A.
  • the conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an oxide semiconductor that can be used as the oxide 230 becomes a conductive oxide by performing resistance reduction treatment.
  • an oxide that can be used as the oxide 230 may be formed, and the resistance of the oxide may be reduced in a later step.
  • oxygen can be added to the insulating film 250A by forming an oxide that can be used as the oxide 230 over the insulating film 250A by a sputtering method in an atmosphere containing oxygen. By adding oxygen to the insulating film 250A, the added oxygen can supply oxygen to the oxide 230 through the insulating film 250A.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed.
  • treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.
  • the insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, it is preferable to use aluminum oxide, hafnium oxide, hafnium aluminate, or the like. Thereby, oxidation of the conductor 260 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
  • the insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.
  • the insulator 271 functions as a hard mask.
  • the side surface of the insulator 250, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.
  • the insulating film 271A is etched to form the insulator 271. Subsequently, using the insulator 271 as a mask, the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form the insulator 250, the conductor 260 (conductor 260a, conductor 260b), and the insulating film. A body 270 is formed (see FIG. 16). Note that a post-process may be performed without removing the insulator 271 even after the processing. The insulator 271 can function as a hard mask even when a dopant is added in a later step.
  • the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably in the same plane.
  • the same surface shared by the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 is preferably substantially perpendicular to the substrate. That is, in the cross-sectional shape, the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably as acute and large as possible with respect to the top surface of the oxide 230.
  • a cross-sectional shape of the side surface of the insulator 250, the side surface of the conductor 260, the side surface of the insulator 270, and the top surface of the oxide 230 in contact with the insulator 250 may be an acute angle.
  • the angle formed by the side surface of the insulator 250, the side surface of the conductor 260, the side surface of the insulator 270, and the top surface of the oxide 230 in contact with the insulator 250 is preferably as large as possible.
  • the insulator 250, the conductor 260, and the insulator 270 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
  • the etching may etch the upper portion of the region of the oxide film 230C that does not overlap with the insulator 250.
  • the thickness of the region of the oxide film 230C that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
  • an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 17).
  • the insulating film 272A is preferably formed by an ALD method with excellent coverage. By using the ALD method, an insulating film having a uniform thickness with respect to the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 even in the step portion formed by the conductor 260 and the like. 272A can be formed.
  • anisotropic etching is performed on the insulating film 272A, so that the insulator 272 is formed in contact with the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 (see FIG. 18).
  • anisotropic etching process it is preferable to perform a dry etching process.
  • the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.
  • the insulator 271 can serve as a mask and the insulator 270 can remain. Further, the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is set higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C, thereby oxidizing the oxide.
  • the insulating film 272A on the side surfaces of the oxide 230a and the oxide 230b through the film 230C can be removed.
  • the oxide film 230C is etched, and part of the oxide film 230C is removed to form the oxide 230c. (See FIG. 19.) Note that in this step, part of the top surface and side surfaces of the oxide 230b and part of side surfaces of the oxide 230a may be removed.
  • a region 231, a junction region 232, and a region 234 may be formed.
  • the region 231 and the junction region 232 are regions in which a metal atom such as indium or an impurity is added to a metal oxide provided as the oxide 230a, the oxide 230b, and the oxide 230c to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234.
  • a metal element such as indium and a dopant that is at least one of impurities may be added.
  • the dopant is added by an ion implantation method in which ionized source gas is added by mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like. Can be used.
  • mass separation the ionic species to be added and the concentration thereof can be strictly controlled.
  • mass separation is not performed, high-concentration ions can be added in a short time.
  • an ion doping method in which atomic or molecular clusters are generated and ionized may be used.
  • the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
  • the dopant may be added by plasma treatment.
  • plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, or an ashing apparatus, and the dopant can be added to the oxides 230a, 230b, and 230c.
  • a film containing the dopant may be formed so as to be in contact with the region 231.
  • an insulator 274 containing hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, or the like as a dopant is formed so as to be in contact with the region 231 of the oxide 230 (see FIG. 20).
  • the resistance of the region 231 is reduced and the bonding region 232 is formed. It is considered that the dopant contained in the insulator 274 diffuses into the region 231 and the junction region 232 and the region has a low resistance.
  • the oxide 230a, the oxide 230b, and the oxide 230c can have high carrier density and low resistance by increasing the content of indium. Therefore, a metal element such as indium that improves the carrier density of the oxide 230a, the oxide 230b, and the oxide 230c can be used as the dopant.
  • the content of metal atoms such as indium in the oxide 230a, the oxide 230b, and the oxide 230c is increased, so that the electron mobility is increased and the resistance is reduced. be able to.
  • At least the ratio of the number of indium atoms to the element M in the region 231 is larger than the ratio of the number of indium atoms to the element M in the region 234.
  • the above-described element that forms oxygen vacancies or an element that is trapped by oxygen vacancies may be used.
  • examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases.
  • Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.
  • the junction region 232 since the junction region 232 is provided, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; And mobility can be increased. In addition, since the junction region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, since the junction region 232 is provided, leakage current at the time of non-conduction can be reduced.
  • the insulator 274 is formed to cover the insulator 224, the oxide 230, the insulator 271, and the insulator 272 (see FIG. 20).
  • silicon nitride, silicon nitride oxide, or silicon oxynitride formed by a CVD method can be used as the insulator 274.
  • silicon nitride oxide is used as the insulator 274.
  • the region 231a and the region 231b can be formed in a film formation atmosphere of the insulator 274 such as hydrogen or nitrogen.
  • Impurity elements are added. Oxygen vacancies are formed by the added impurity element around the region in contact with the insulator 274 of the oxide 230, and the impurity element enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. At that time, the impurity diffuses also in the junction region 232 that is not in contact with the insulator 274, so that the resistance is reduced.
  • the concentration of at least one of hydrogen and nitrogen be higher in the region 231a and the region 231b than in the region 234.
  • the concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like.
  • SIMS secondary ion mass spectrometry
  • the concentration of hydrogen or nitrogen in the region 234 the distance from the vicinity of the center of the region overlapping the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the insulator 250 in the oxide 230b) is approximately. What is necessary is just to measure the density
  • a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used as the insulator 274.
  • oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232.
  • hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
  • the insulator 274 is formed as an insulator including an element serving as an impurity or an insulator from which oxygen is extracted from the oxide 230
  • the insulator 274 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD. This can be done using methods.
  • the insulator 274 including the element serving as an impurity is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. By performing deposition in such an atmosphere, oxygen vacancies are formed around the oxide 230b and the oxide 250c that do not overlap with the insulator 250, and the oxygen vacancies are bonded to an impurity element such as nitrogen or hydrogen. Thus, the carrier density can be increased. In this manner, the region 231a and the region 231b with reduced resistance can be formed.
  • silicon nitride, silicon nitride oxide, or silicon oxynitride can be used by, for example, a CVD method. In this embodiment, silicon nitride oxide is used as the insulator 274.
  • the source region and the drain region can be formed in a self-aligned manner by forming the insulator 274. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.
  • an impurity element such as nitrogen or hydrogen is transferred to the conductor 260 and the insulator 250.
  • Mixing can be prevented.
  • an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260 and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
  • the region 231, the junction region 232, and the region 234 are formed by reducing the resistance of the oxide 230 by forming the insulator 274, but this embodiment is not limited to this. .
  • a dopant addition treatment or plasma treatment may be used, or a plurality of these may be combined to form the region 231, the junction region 232, and the region 234.
  • heat treatment can be performed.
  • the heat treatment conditions described above can be used for the heat treatment.
  • the added dopant diffuses into the junction region 232 of the oxide 230, so that the on-state current can be increased.
  • the insulator 280 is preferably formed so that an upper surface thereof has flatness.
  • the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280.
  • the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process.
  • the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process.
  • the top surface of the insulator 280 is not necessarily flat.
  • An opening reaching the conductor 205 is formed in the insulator 274, the insulator 224, the insulator 222, and the insulator 220.
  • the opening may be formed using a lithography method.
  • the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 2521 and the conductor 2522 are provided in contact with the side surface of the oxide 230.
  • the conductor 252 (the conductor 2521, the conductor 2522, the conductor 2523, and the conductor 2524) described in ⁇ Conductor manufacturing method 2> is formed (see FIG. 23). Further, a conductor 256 that is electrically connected to the conductor 252 may be formed as needed (see FIG. 1).
  • a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 12 to 22, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
  • a keyhole is formed on the surfaces of the conductor 205 and the conductor 252. It is possible to suppress shape defects due to unevenness.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device with low off-state current can be provided.
  • a transistor with high on-state current can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with reduced power consumption can be provided.
  • a highly productive semiconductor device can be provided.
  • the memory device illustrated in FIG. 23 includes the transistor 200, the capacitor 100, and the transistor 300.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
  • the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300.
  • the wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 23 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing).
  • predetermined charge is given to the gate of the transistor 300 (writing).
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
  • the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V th_H when the gate of the transistor 300 is supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present.
  • the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”.
  • the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
  • the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V 0 (> V th_H ).
  • the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
  • a memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
  • HEMT High Electron Mobility Transistor
  • the low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
  • the conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron.
  • a conductive material such as a material or a metal oxide material can be used.
  • the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
  • transistor 300 illustrated in FIGS. 23A and 23B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
  • the insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • the insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by a CVD method can be used.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • the amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS).
  • TDS temperature programmed desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is 10 ⁇ 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like.
  • the conductor 328 and the conductor 330 function as plugs or wirings.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer.
  • a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324.
  • the conductor 356 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen.
  • tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 354 and the conductor 356.
  • an insulator 360, an insulator 362, and an insulator 364 are provided in this order.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 364 and the conductor 366.
  • an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked.
  • a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 370.
  • the conductor 376 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided over the insulator 374 and the conductor 376.
  • an insulator 380, an insulator 382, and an insulator 384 are stacked in this order.
  • a conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
  • an insulator having a barrier property against hydrogen is preferably used as the insulator 380.
  • the conductor 386 preferably includes a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen.
  • An insulator 210 and an insulator 212 are sequentially stacked over the insulator 384 and the conductor 386. Any of the insulator 210 and the insulator 212 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
  • a conductor 218 is formed on the insulator 210 and the insulator 212.
  • the conductor 218 can be formed at the same time as the conductor 203.
  • a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.
  • silicon nitride formed by a CVD method can be used as an example of a film having a barrier property against hydrogen.
  • silicon nitride formed by a CVD method when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300.
  • the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
  • a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210.
  • aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.
  • the insulator 212 can be formed using the same material as the insulator 320.
  • a material having a relatively low dielectric constant as an interlayer film parasitic capacitance generated between wirings can be reduced.
  • a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212.
  • An insulator 216 is provided over the insulator 212, the conductor 203, and the conductor 218.
  • a conductor 219, a conductor included in the transistor 200 (conductor 205), and the like are embedded in the insulator 216.
  • the conductor 219 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300.
  • the conductor 219 can be formed at the same time as the conductor 205.
  • the conductor 219 in a region in contact with the insulator 210 is preferably a conductor having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 200 can be separated from each other by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.
  • a transistor 200 is provided above the insulator 212. Note that the transistor 200 described in the above embodiment may be used as the structure of the transistor 200. Further, the transistor 200 illustrated in FIGS. 23A and 23B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
  • a capacitor 100 is provided above the transistor 200.
  • a conductor 256 that is electrically connected to the other of the source and the drain of the transistor 200 is used.
  • the conductor 256 is electrically connected to the gate of the transistor 300.
  • An insulator 120 that functions as a dielectric of the capacitor 100 is provided over the conductor 256.
  • the conductor 130 is provided so as to overlap with the conductor 256 with the insulator 120 interposed therebetween.
  • the conductor 130 functions as the other electrode of the capacitor 100 and is electrically connected to the wiring 3005.
  • the insulator 120 may be provided so as to cover the side surface of the conductor 256.
  • the conductor 130 may be provided on the side surface of the conductor 256 with the insulator 120 interposed therebetween.
  • the capacitor element 100 can be formed using not only the upper surface of the conductor 256 and the conductor 130 facing it, but also the side surface of the conductor 256 and the conductor 130 facing it.
  • the capacitance value can be increased without increasing the upper surface area, which is preferable.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • 2T type, 3T type a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor such as NOSRAM
  • OS memory a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied.
  • the OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
  • FIG. 24 shows a configuration example of NOSRAM.
  • a NOSRAM 1600 illustrated in FIG. 24 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670.
  • the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
  • the memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL.
  • the word line WWL is a write word line
  • the word line RWL is a read word line.
  • one memory cell 1611 stores 3-bit (eight values) data.
  • the controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0].
  • the controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
  • the row driver 1650 has a function of selecting a row to be accessed.
  • the row driver 1650 includes a row decoder 1651 and a word line driver 1652.
  • the column driver 1660 drives the source line SL and the bit line BL.
  • the column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
  • the DAC 1663 converts 3-bit digital data into an analog voltage.
  • the DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
  • the write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL.
  • the output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673.
  • the selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672.
  • the ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
  • FIG. 25A is a circuit diagram illustrating a structural example of the memory cell 1611.
  • the memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL.
  • the memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61.
  • the OS transistor MO61 is a write transistor.
  • the transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor.
  • the capacitive element C61 is a holding capacitor for holding the voltage of the node SN.
  • the node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
  • the NOSRAM 1600 can hold data for a long time.
  • the bit line is a common bit line for writing and reading.
  • a writing bit line WBL and a reading bit line RBL may be provided. Good.
  • FIGS. 25C to 25E show other configuration examples of the memory cell.
  • FIGS. 25C to 25E show an example in which a write bit line and a read bit line are provided. Although shown, a bit line shared by writing and reading may be provided as shown in FIG.
  • a memory cell 1612 illustrated in FIG. 25C is a modification example of the memory cell 1611 in which the reading transistor is changed to an n-channel transistor (MN61).
  • the transistor MN61 may be an OS transistor or a Si transistor.
  • the OS transistor MO61 may be an OS transistor without a back gate.
  • a memory cell 1613 illustrated in FIG. 25D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL.
  • the memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62.
  • the OS transistor MO62 is a write transistor.
  • the transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
  • a memory cell 1614 shown in FIG. 25E is a modification example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (MN62 and MN63).
  • the transistors MN62 and MN63 may be OS transistors or Si transistors.
  • the OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.
  • the NOSRAM 1600 Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
  • the transistor 200 is used as the OS transistors MO61 and MO62
  • the capacitor 100 is used as the capacitors C61 and C62
  • the transistors MP61 and MN62 are used.
  • the transistor 300 can be used. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS.
  • DOSRAM registered trademark
  • amic Oxide Semiconductor RAM refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells.
  • OS memory is applied to DOSRAM as well as NOSRAM.
  • FIG. 26 shows a configuration example of the DOSRAM.
  • the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
  • MC-SA array 1420 a sense amplifier array 1420
  • the row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414.
  • the column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417.
  • the global sense amplifier array 1416 has a plurality of global sense amplifiers 1447.
  • the MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
  • the MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423.
  • Global bit lines GBLL and GBLR are stacked on the memory cell array 1422.
  • a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
  • the memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 ⁇ 0> -1425 ⁇ N-1>.
  • FIG. 27A illustrates a configuration example of the local memory cell array 1425.
  • the local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR.
  • the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
  • FIG. 27B illustrates a circuit configuration example of the memory cell 1445.
  • the memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2.
  • the transistor MW1 has a function of controlling charging / discharging of the capacitor CS1.
  • the gate of the transistor MW1 is electrically connected to the word line WL, the first terminal is electrically connected to the bit line (BLL or BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1.
  • BLL or BLR bit line
  • the second terminal of the capacitive element CS1 is electrically connected to the terminal B2.
  • a constant voltage (for example, a low power supply voltage) is input to the terminal B2.
  • the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1.
  • the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated.
  • the storage capacity per unit area of the storage device according to this embodiment can be increased.
  • the transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1.
  • the voltage at the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B1 may be changed according to the operation of the DOSRAM 1400.
  • the back gate of the transistor MW1 may be electrically connected to the gate, the first terminal, or the second terminal of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.
  • the sense amplifier array 1423 includes N local sense amplifier arrays 1426 ⁇ 0> -1426 ⁇ N-1>.
  • the local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446.
  • a bit line pair is electrically connected to the sense amplifier 1446.
  • the sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference.
  • the switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
  • bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier.
  • a global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier.
  • a bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines.
  • bit line BLL and the bit line BLR form one bit line pair.
  • Global bit line GBLL and global bit line GBLR form a pair of global bit lines.
  • bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
  • the controller 1405 has a function of controlling the overall operation of the DOSRAM 1400.
  • the controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
  • the row circuit 1410 has a function of driving the MC-SA array 1420.
  • the decoder 1411 has a function of decoding an address signal.
  • the word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
  • a column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423.
  • the column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column.
  • the switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413.
  • the plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
  • the column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0].
  • the data signal WDA [31: 0] is a write data signal
  • the data signal RDA [31: 0] is a read data signal.
  • the global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR).
  • the global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference.
  • Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.
  • Data is written to the global bit line pair by the input / output circuit 1417.
  • Data of the global bit line pair is held by the global sense amplifier array 1416.
  • the data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal.
  • the local sense amplifier array 1426 amplifies and holds the written data.
  • the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
  • One row of the local memory cell array 1425 is designated by the address signal.
  • the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line.
  • the local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data.
  • the switch array 1444 writes the data in the column specified by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair.
  • the global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
  • the DOSRAM 1400 Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
  • the transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.
  • the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.
  • an FPGA field programmable gate array
  • OS-FPGA field programmable gate array
  • FIG. 28A shows a configuration example of the OS-FPGA.
  • the OS-FPGA 3110 shown in FIG. 28A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE.
  • the OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
  • the programmable area 3115 includes two input / output blocks (IOB) 3117 and a core (Core) 3119.
  • the IOB 3117 has a plurality of programmable input / output circuits.
  • the core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130.
  • the LAB 3120 includes a plurality of PLE 3121s.
  • FIG. 28B shows an example in which the LAB 3120 is composed of five PLE 3121s.
  • the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array.
  • the LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
  • the SB 3131 will be described with reference to FIGS. 29 (A) to 29 (C).
  • Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship.
  • the number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal.
  • the signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
  • the SB 3131 includes PRSs (programmable routing switches) 3133 [0] and 3133 [1].
  • the PRSs 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
  • FIG. 29B illustrates a circuit configuration example of the PRS 3133 [0].
  • PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration.
  • PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal.
  • the signals context [0] and word [0] are input to the PRS 3133 [0]
  • the signals context [1] and word [1] are input to the PRS 3133 [1].
  • the signal context [0] becomes “H”
  • the PRS 3133 [0] becomes active.
  • the PRS 3133 [0] includes a CM 3135 and a Si transistor M31.
  • the Si transistor M31 is a pass transistor controlled by the CM 3135.
  • the CM 3135 includes memory circuits 3137 and 3137B.
  • the memory circuits 3137 and 3137B have the same circuit configuration.
  • the memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32.
  • the memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.
  • the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitor 100 can be used as the capacitors C31 and CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.
  • the gate of the Si transistor M31 is the node N31
  • the gate of the OS transistor MO32 is the node N32
  • the gate of the OS transistor MOB32 is the node NB32.
  • Nodes N32 and NB32 are charge holding nodes of the CM 3135.
  • the OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0].
  • the OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.
  • the logic of data held in the memory circuits 3137 and 3137B has a complementary relationship. Therefore, either one of the OS transistors MO32 or MOB32 becomes conductive.
  • the PRS 3133 [0] While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
  • the PRS 3133 [0] is active.
  • the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
  • the OS transistor MO32 of the memory circuit 3137 is a source follower, so that the gate voltage of the Si transistor M31 increases due to boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
  • the CM 3135 also has a multiplexer function.
  • FIG. 30 shows a configuration example of the PLE 3121.
  • the PLE 3121 includes an LUT (Look Up Table) block (LUT block) 3123, a register block 3124, a selector 3125, and a CM 3126.
  • the LUT block 3123 is configured to select and output data according to the inputs inA-inD.
  • the selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
  • the PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
  • the register block 3124 is configured by a nonvolatile register.
  • the nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.
  • the register block 3124 includes OS-FFs 3140 [1] and 3140 [2]. Signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2].
  • the clock signal CLK1 is input to the OS-FF 3140 [1]
  • the clock signal CLK2 is input to the OS-FF 3140 [2].
  • FIG. 31A illustrates a configuration example of the OS-FF 3140.
  • the OS-FF 3140 includes an FF 3141 and a shadow register 3142.
  • the FF 3141 includes nodes CK, R, D, Q, and QB.
  • a clock signal is input to the node CK.
  • a signal user_res is input to the node R.
  • the signal user_res is a reset signal.
  • Node D is a data input node
  • node Q is a data output node.
  • Nodes Q and QB have a complementary logic relationship.
  • the shadow register 3142 functions as a backup circuit for the FF 3141.
  • the shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
  • the shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B.
  • the memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133.
  • the memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36.
  • the memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36.
  • Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes.
  • Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.
  • the transistor 200 can be used as the OS transistors MO35 and MOB35, and the capacitor 100 can be used as the capacitors C36 and CB36. Since the occupation area in the top view can be reduced, the semiconductor device according to this embodiment can be highly integrated.
  • the OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.
  • the shadow register 3142 backs up the data in the FF 3141.
  • the node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 holds the backed up data even when the power is turned off.
  • the power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
  • the power consumption of the OS-FPGA 3110 can be effectively reduced.
  • An error that may occur in the memory circuit is a soft error due to the incidence of radiation.
  • a soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair.
  • An OS memory using an OS transistor has high soft error resistance. Therefore, by installing the OS memory, a highly reliable OS-FPGA 3110 can be provided.
  • FIG. 32 is a block diagram illustrating a configuration example of the AI system 4041.
  • the AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.
  • the arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014.
  • DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.
  • the control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access MemoryPROM 40 Memory, Memory Memory 4024).
  • the input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.
  • the arithmetic unit 4010 can execute learning or inference using a neural network.
  • the analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
  • the analog arithmetic circuit 4011 is preferably formed using an OS transistor.
  • An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.
  • the DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021.
  • the DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
  • the input data may exceed 1000.
  • the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions.
  • the DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.
  • a NOSRAM 4013 is a non-volatile memory using an OS transistor.
  • the NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.
  • the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data.
  • the NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.
  • the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit.
  • analog data refers to data having a resolution of 3 bits (8 values) or more. The multi-value data described above may be included in the analog data.
  • Data and parameters used for calculation of the neural network can be temporarily stored in the NOSRAM 4013.
  • the data and parameters may be stored in the memory provided outside the AI system 4041 via the CPU 4021.
  • the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.
  • the FPGA 4014 is an FPGA using an OS transistor.
  • the AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM).
  • a neural network connection such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.
  • the FPGA 4014 is an FPGA having an OS transistor.
  • the OS-FPGA can reduce the area of the memory compared to the FPGA configured with the SRAM. Therefore, even if a context switching function is added, the area increase is small.
  • the OS-FPGA can transmit data and parameters at high speed by boosting.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption.
  • the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
  • the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014.
  • One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.
  • the AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed.
  • the PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.
  • the AI system 4041 preferably includes a GPU 4022.
  • the AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.
  • the power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog calculation.
  • the power supply circuit 4027 may use an OS memory.
  • the power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
  • the PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.
  • the CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.
  • the PLL 4023 has a function of generating a clock.
  • the AI system 4041 operates based on the clock generated by the PLL 4023.
  • the PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.
  • the AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM.
  • the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.
  • Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.
  • the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
  • the AI system 4041 includes an audio codec 4032 and a video codec 4033.
  • the audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data
  • the video codec 4033 encodes and decodes video data.
  • the AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034.
  • the general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).
  • the AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.
  • the analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory.
  • the flash memory has a limited number of rewritable times.
  • it is very difficult to form a multi-level flash memory in an embedded manner an arithmetic circuit and a memory are formed on the same die.
  • the analog arithmetic circuit 4011 may use ReRAM as an analog memory.
  • ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy.
  • circuit design for separating data writing and reading becomes complicated.
  • the analog arithmetic circuit 4011 may use MRAM as an analog memory.
  • MRAM has a low resistance change rate and has a problem in terms of storage accuracy.
  • the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.
  • FIG. 33A shows an AI system 4041A in which the AI systems 4041 described in FIG. 32 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.
  • An AI system 4041A illustrated in FIG. 33A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number).
  • the AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.
  • An AI system 4041B illustrated in FIG. 33B includes a plurality of AI systems 4041_1 to 4041_n.
  • the AI systems 4041_1 to 4041_n are connected to each other via a network 4099.
  • the network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
  • the communication module can communicate via an antenna.
  • the Internet Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (Campure Area Network, MAN (MetropoliAwareNetwork), MAN (MetropoliAureNetwork), which are the foundations of the World Wide Web (WWW).
  • Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication.
  • LTE Long Term Evolution
  • GSM Global System for Mobile Communication: registered trademark
  • EDGE Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Emulsion
  • Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.
  • analog signals obtained by an external sensor or the like can be processed by separate AI systems.
  • information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information
  • various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor
  • analog signals can be processed by separate AI systems. it can.
  • the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.
  • the AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.
  • FIG. 34 shows an example of an IC incorporating an AI system.
  • An AI system IC 7000 shown in FIG. 34 includes a lead 7001 and a circuit portion 7003.
  • the AI system IC 7000 is mounted on a printed circuit board 7002, for example.
  • a plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004).
  • the circuit portion 7003 is provided with the various circuits described in the above embodiment in one die.
  • the circuit portion 7003 has a stacked structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.
  • QFP Quad Flat Package
  • a digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and OS memories such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.
  • the semiconductor device according to one embodiment of the present invention can be used for various electronic devices.
  • FIG. 35 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
  • FIG. 35A shows the monitor 830.
  • the monitor 830 includes a display portion 831, a housing 832, a speaker 833, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
  • the monitor 830 can be operated with a remote controller 834.
  • the monitor 830 can function as a television device by receiving broadcast radio waves.
  • Broadcast radio waves that can be received by the monitor 830 include terrestrial waves or radio waves transmitted from satellites.
  • broadcast radio waves there are analog broadcasts, digital broadcasts, etc., and video and audio, or audio-only broadcasts.
  • broadcast radio waves transmitted in a specific frequency band in the UHF band (300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received.
  • the transfer rate can be increased and more information can be obtained.
  • an image having a resolution exceeding full high-definition can be displayed on the display unit 831. For example, an image having a resolution of 4K-2K, 8K-4K, 16K-8K, or higher can be displayed.
  • the monitor 830 may not have a tuner.
  • the monitor 830 can be connected to a computer and used as a computer monitor.
  • a monitor 830 connected to a computer can be viewed by a plurality of people at the same time, and can be used for a conference system. Further, the monitor 830 can be used in a video conference system by displaying computer information via the network or connecting the monitor 830 itself to the network.
  • the monitor 830 can also be used as digital signage.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • image processing such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing is performed. Can do. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • HDR high dynamic range
  • a video camera 2940 illustrated in FIG. 35B includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like.
  • the operation switch 2944 and the lens 2945 are provided on the housing 2941
  • the display portion 2944 is provided on the housing 2942.
  • the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941.
  • the housing 2941 and the housing 2942 are connected to each other by a connection portion 2946.
  • the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946.
  • the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • an AI system including the semiconductor device of one embodiment of the present invention for the image processing portion of the video camera 2940, shooting according to the environment around the video camera 2940 can be realized. Specifically, shooting can be performed with an optimal exposure according to the ambient brightness. In addition, when shooting under different lighting conditions, such as shooting in backlight or indoor and outdoor, high dynamic range (HDR) shooting can be performed.
  • HDR high dynamic range
  • the AI system can learn a photographer's habit and can assist in photographing. Specifically, by learning the camera shake of the photographer and correcting the camera shake during shooting, it is possible to minimize the image disturbance caused by the camera shake. Further, when using the zoom function during shooting, the direction of the lens and the like can be controlled so that the subject is always shot at the center of the image.
  • An information terminal 2910 illustrated in FIG. 35C includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
  • the display portion 2912 includes a display panel using a flexible substrate and a touch screen.
  • the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
  • the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold the control information of the above-described information terminal 2910, the control program, and the like for a long period.
  • image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed.
  • image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed.
  • inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased.
  • a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • the AI system can learn the user's habit and assist the operation of the information terminal 2910.
  • An information terminal 2910 equipped with an AI system can predict a touch input from the movement of a user's finger, the line of sight, and the like.
  • a laptop personal computer 2920 illustrated in FIG. 35D includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
  • the laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the laptop personal computer 2920 for a long period.
  • images such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing can be used. Processing can be performed. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed.
  • the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • HDR high dynamic range
  • the AI system can learn a user's habit and assist the operation of the laptop personal computer 2920.
  • a laptop personal computer 2920 equipped with an AI system can predict a touch input to the display unit 2922 from the movement of a user's finger, a line of sight, or the like.
  • input prediction is performed based on past text input information and figures such as preceding and following texts and photographs, and conversion is assisted. Thereby, input mistakes and conversion mistakes can be reduced as much as possible.
  • FIG. 35E illustrates an external view of an example of an automobile
  • FIG. 35F illustrates a navigation device 860.
  • the automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.
  • the automobile 2980 includes an antenna, a battery, and the like.
  • the navigation device 860 includes a display unit 861, operation buttons 862, and an external input terminal 863.
  • the automobile 2980 and the navigation device 860 may be independent of each other, but it is preferable that the navigation device 860 is incorporated in the automobile 2980 and functions in conjunction with the automobile 2980.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the automobile 2980 and the navigation device 860 for a long period.
  • the AI system learns driving skills and habits of the driver, assists in safe driving, and uses gasoline or batteries. It is possible to assist driving that efficiently uses such fuel. Assisting safe driving not only learns the driver's driving skills and habits, but also learns driving behavior such as the speed and movement method of the car 2980, road information stored in the navigation device 860, etc.
  • the navigation device 860 can transmit the road information to the automobile 2980 to control the speed of the automobile 2980 and assist the steering operation.
  • FIGS. examples of a conductor created based on ⁇ Conductor manufacturing method 1> are shown in FIGS.
  • a scanning transmission electron microscope STEM: Scanning Transmission Electron Microscope
  • model number: HD-2300 manufactured by Hitachi High-Technologies Corporation was used to obtain the cross-sectional photographs of the samples shown in FIGS.
  • the sample observation conditions were an acceleration voltage of 200 kV and a beam diameter of about 0.5 nm ⁇ .
  • a thermal oxide film (SiOx) was formed on a substrate, and aluminum oxide (AlOx) was deposited on the thermal oxide film by sputtering to a thickness of 40 nm, and silicon oxynitride (SiON) was deposited in a thickness of 200 nm by a plasma CVD method.
  • SiOx silicon oxide film
  • SiON silicon oxynitride
  • silicon oxynitride was opened by etching using the mask to form a conductor formation groove.
  • silicon oxynitride was etched using a hard mask (HM) obtained by forming a tungsten film with a thickness of 35 nm on silicon oxynitride and performing etching using a resist mask. Thereafter, the resist mask was removed.
  • HM hard mask
  • tungsten is used as the hard mask, but the material of the hard mask is not limited to this.
  • silicon oxynitride may be etched using only a resist mask without using a hard mask.
  • the silicon oxide oxynitride was etched without removing the resist mask after the hard mask was formed.
  • the silicon oxynitride was formed using only the hard mask as a mask after removing the resist mask after the hard mask was formed. Etching may be performed.
  • a conductor is formed inside the trench so as to cover the silicon oxide and the hard mask.
  • tantalum nitride (TaN) is 40 nm by sputtering as a first conductive barrier
  • titanium nitride (TiN) is 5 nm by ALD as a second conductive barrier
  • CVD is also used as a conductor.
  • Tungsten (W) was deposited in the order of 250 nm by the method.
  • FIG. 36A, FIG. 36B, and FIG. 36C are cross-sectional photographs after conductor formation.
  • 36A, 36B, and 36C correspond to the cross-sectional view of FIG.
  • FIG. 36B is a cross-sectional photograph in which FIG. 36A is further enlarged.
  • FIG. 36C is a dark field image of FIG. In tungsten located at the center of the groove, a seam was confirmed at a portion surrounded by a broken line.
  • polishing cloth used is IC1000 / SUBA400 XY-P manufactured by Nitta Haas
  • the slurry is an acidic slurry containing colloidal silica diluted to 2 times diluted W7300-B21 manufactured by Cabot.
  • the first polishing was performed using a solution to which hydrogen peroxide water (H 2 O 2 ) was added.
  • IC1000 / SUBA400 XY-P is used for the polishing cloth, and the slurry is a two-fold dilution of Semi-Sperse 25 (SS25) manufactured by Cabot, which is an alkaline slurry containing fumed silica. A second polishing was performed.
  • SS25 Semi-Sperse 25
  • FIG. 36D and 36E are cross-sectional photographs after polishing tungsten, titanium nitride, tantalum nitride, and a hard mask by a CMP method.
  • FIG. 36E is the dark field image of FIG. 36D and 36E correspond to the cross-sectional view of FIG. There are irregularities on the surface of tungsten, and a keyhole was confirmed in a portion surrounded by a broken line in tungsten located at the center of the groove.
  • the tungsten inside the groove is half-etched to remove the keyhole. Dry etching was used for half etching of tungsten.
  • dry etching a mixed gas of CF 4 , O 2 , and Cl 2 was used.
  • FIGS. 37A and 37B are cross-sectional photographs after half etching of tungsten.
  • FIGS. 37A and 37B correspond to the cross-sectional view of FIG.
  • FIG. 37B is a dark field image of FIG.
  • tungsten is etched by about 70 nm, and about 100 nm of tungsten remains inside the groove. Further, tantalum nitride and titanium nitride protrude above the upper surface of the silicon oxynitride film.
  • a silicon oxynitride, tungsten, titanium nitride, and tantalum nitride are covered, and a conductor is formed inside the groove.
  • titanium nitride (TiN) was deposited in a thickness of 5 nm by an ALD method as a third conductive barrier
  • tungsten (W) was deposited in a thickness of 150 nm by a CVD method as a conductor.
  • FIG. 37C and FIG. 37D are cross-sectional photographs after the conductor is formed.
  • FIGS. 37C and 37D correspond to the cross-sectional view of FIG.
  • FIG. 37D is a dark field image of FIG. In tungsten, a seam was confirmed in a portion surrounded by a broken line, but no seam was confirmed in the groove.
  • polishing was performed in two steps. First, IC1000 / SUBA400 XY-P is used for the polishing cloth, and a slurry obtained by diluting W7300-B21 twice and adding 2% aqueous hydrogen peroxide (H 2 O 2 ) is used for the slurry. The first polishing was performed. Next, IC1000 / SUBA400 XY-P was used for the polishing cloth, and the second polishing was performed using a slurry obtained by diluting SS25 twice.
  • FIG. 37E and FIG. 37F are cross-sectional photographs after polishing tungsten, titanium nitride, and the like by a CMP method.
  • FIG. 37F is the dark field image of FIG.
  • FIGS. 37E and 37F correspond to the cross-sectional view of FIG. The unevenness of the tungsten surface was reduced as compared with FIGS. 36D and 36E, and no keyhole was observed in tungsten.
  • a conductor having improved flatness can be formed.

Abstract

In order to provide a semiconductor device with high reliability and favorable electrical characteristics, this semiconductor device has: a first insulator having an opening; a first conductor provided inside the opening and having a first recessed part; a second conductor contacting the bottom surface of the first recessed part; a third conductor contacting a side surface of the first recessed part and the upper surface of the second conductor, and having a second recessed part; a fourth conductor provided in the second recessed part; a second insulator over the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor; and an oxide that overlaps the fourth conductor with the second insulator disposed therebetween.

Description

導電体、導電体の作製方法、半導体装置、および半導体装置の作製方法Conductor, method for manufacturing conductor, semiconductor device, and method for manufacturing semiconductor device
　本発明の一態様は、半導体装置、ならびに半導体装置の作製方法に関する。または、本発明の一態様は、半導体ウエハ、モジュールおよび電子機器に関する。 One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. One embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
　なお、本明細書等において半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。トランジスタなどの半導体素子をはじめ、半導体回路、演算装置、記憶装置は、半導体装置の一態様である。表示装置（液晶表示装置、発光表示装置など）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置および電子機器などは、半導体装置を有すると言える場合がある。 Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.
　なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様は、物、方法、または、製造方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
半導体素子を用いた集積回路（Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ：ＩＣ）の開発が進められている。ＣＰＵやメモリの開発および製造には、より高い集積度のＩＣからなるＬＳＩや超ＬＳＩの技術が用いられている。このようなＩＣは、回路基板、例えばプリント配線板に実装され、コンピュータ、情報端末、表示装置、自動車などを構成する、様々な電子機器の部品の一つとして用いられる。また、これらを人工知能（ＡＩ）システムに用いる研究も進められている。 Development of an integrated circuit (Integrated Circuit: IC) using a semiconductor element is in progress. In the development and manufacture of CPUs and memories, LSI and VLSI technologies that have higher integration ICs are used. Such an IC is mounted on a circuit board, for example, a printed wiring board, and is used as one of components of various electronic devices constituting a computer, an information terminal, a display device, an automobile, and the like. Research is also underway to use these in artificial intelligence (AI) systems.
コンピュータや情報端末として、デスクトップ型コンピュータ、ラップトップ型コンピュータ、タブレット型コンピュータ、スマートフォン、携帯電話などが知られている。 As computers and information terminals, desktop computers, laptop computers, tablet computers, smartphones, mobile phones and the like are known.
半導体素子に用いられる半導体材料としてシリコン系半導体材料が広く知られているが、その他の材料として酸化物半導体が注目されている。 Silicon-based semiconductor materials are widely known as semiconductor materials used for semiconductor elements, but oxide semiconductors have attracted attention as other materials.
　また、酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいことが知られている。例えば、酸化物半導体を用いたトランジスタのリーク電流が低いという特性を応用した低消費電力のＣＰＵなどが開示されている（特許文献１参照。）。 Further, it is known that a transistor using an oxide semiconductor has extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic that a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
　また、近年では電子機器の小型化、軽量化に伴い、集積回路のさらなる高密度化への要求が高まっている。また、集積回路を含む半導体装置の生産性の向上が求められている。 In recent years, with the downsizing and weight reduction of electronic devices, there is an increasing demand for higher density integrated circuits. There is also a need for improved productivity of semiconductor devices including integrated circuits.
半導体素子の接続、あるいは集積回路の接続には、ダマシン法にて形成された電極、配線、あるいはプラグが用いられる（特許文献２参照。）。 An electrode, a wiring, or a plug formed by a damascene method is used for connecting a semiconductor element or an integrated circuit (see Patent Document 2).
特開２０１２−２５７１８７号公報JP 2012-257187 A 特表２００３−５２８４４２号公報Special table 2003-528442 gazette
　本発明の一態様は、良好な電気特性を有する半導体装置およびその作製方法を提供することを課題の一つとする。本発明の一態様は、信頼性の高い半導体装置およびその作製方法を提供することを課題の一つとする。本発明の一態様は、微細化または高集積化が可能な半導体装置およびその作製方法を提供することを課題の一つとする。本発明の一態様は、生産性の高い半導体装置およびその作製方法を提供することを課題の一つとする。 An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof. An object of one embodiment of the present invention is to provide a highly productive semiconductor device and a manufacturing method thereof.
また、本発明の一態様は、ダマシン法で形成された電極、配線、あるいはプラグの表面が平坦化された半導体装置およびその作製方法を提供することを課題の一つとする。 Another object of one embodiment of the present invention is to provide a semiconductor device in which a surface of an electrode, a wiring, or a plug formed by a damascene method is planarized and a manufacturing method thereof.
また、本発明の一態様は、酸化物を用いた半導体装置において、ダマシン法で形成された電極、配線、あるいはプラグを介した酸化物への不純物の混入を防ぐことを課題の一つとする。 Another object of one embodiment of the present invention is to prevent impurities from entering an oxide through an electrode, a wiring, or a plug formed by a damascene method in a semiconductor device using an oxide.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these issues does not disturb the existence of other issues. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様は、開口を有する絶縁体と、開口の内部に設けられ、且つ第１の凹部を有する第１の導電体と、第１の凹部の底面に接する第２の導電体と、第１の凹部の側面と第２の導電体の上面に接し、且つ第２の凹部を有する第３の導電体と、第２の凹部に設けられた第４の導電体と、を有する半導体装置である。 One embodiment of the present invention includes an insulator having an opening, a first conductor provided inside the opening and having a first recess, a second conductor in contact with the bottom surface of the first recess, A semiconductor device having a third conductor in contact with the side surface of the first recess and the upper surface of the second conductor and having the second recess, and a fourth conductor provided in the second recess It is.
上記において、絶縁体は第１の絶縁体であり、第１の絶縁体、第１の導電体、第２の導電体、第３の導電体、および第４の導電体上の第２の絶縁体と、第２の絶縁体を間に挟み、第１の導電体と重なる酸化物を有してもよい。 In the above, the insulator is a first insulator, and the second insulator on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor. And an oxide which overlaps with the first conductor with the body and the second insulator interposed therebetween.
上記において、絶縁体は、第５の導電体上に設けられ、第１の導電体、第２の導電体、第３の導電体、および第４の導電体は、第５の導電体と電気的に接続してもよい。 In the above, the insulator is provided over the fifth conductor, and the first conductor, the second conductor, the third conductor, and the fourth conductor are electrically connected to the fifth conductor. May be connected.
上記において、第１の導電体は、第１の材料および第２の材料を含み、第１の材料は、開口の側面と底面に接し、第２の材料は、第２の導電体および第３の導電体と接していてもよい。 In the above, the first conductor includes the first material and the second material, the first material is in contact with the side surface and the bottom surface of the opening, and the second material is the second conductor and the third material. May be in contact with the conductor.
上記において、第１の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第２の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第２の材料は、第１の材料と異なる材料であることが好ましい。 In the above, the first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, and the second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, The second material is preferably a material different from the first material.
本発明の一態様は、酸化物と、酸化物を覆い、且つ開口を有する絶縁体と、開口の側面と底面に接し、且つ第１の凹部を有する第１の導電体と、第１の凹部の底面に接する第２の導電体と、第１の凹部の側面と第２の導電体の上面に接し、且つ第２の凹部を有する第３の導電体と、第２の凹部に設けられた第４の導電体と、を有し、第１の導電体、第２の導電体、第３の導電体、および第４の導電体は、酸化物と電気的に接続する半導体装置である。 One embodiment of the present invention includes an oxide, an insulator that covers the oxide and has an opening, a first conductor that is in contact with a side surface and a bottom surface of the opening and has a first recess, and a first recess A second conductor in contact with the bottom surface, a third conductor in contact with the side surface of the first recess and the upper surface of the second conductor and having the second recess, and the second recess. A first conductor, a second conductor, a third conductor, and a fourth conductor are semiconductor devices that are electrically connected to the oxide.
上記において、絶縁体は、複数の絶縁材料からなる積層体でもよい。 In the above, the insulator may be a laminated body made of a plurality of insulating materials.
上記において、絶縁体は第１の絶縁体であり、開口の側面には、第２の絶縁体が設けられ、第１の導電体は、第２の絶縁体を介して、第１の絶縁体と接することが好ましい。 In the above, the insulator is a first insulator, a second insulator is provided on a side surface of the opening, and the first conductor is connected to the first insulator via the second insulator. It is preferable to contact with.
上記において、第１の絶縁体は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、アルミニウム、およびハフニウムの一方あるいは両方を含む酸化物のいずれか一を含み、第２の絶縁体は、アルミニウムおよびハフニウムの一方または両方を含む酸化物を含むことが好ましい。 In the above, the first insulator includes any one of oxides including one or both of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum, and hafnium, and the second insulator includes It is preferable to include an oxide containing one or both of aluminum and hafnium.
上記において、第１の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第３の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含むことが好ましい。 In the above, the first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, and the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride. It is preferable.
上記において、第２の導電体は、タングステン、銅およびアルミニウムのいずれか一を含み、第４の導電体は、タングステン、銅およびアルミニウムのいずれか一を含むことが好ましい。 In the above, it is preferable that the second conductor includes any one of tungsten, copper, and aluminum, and the fourth conductor includes any one of tungsten, copper, and aluminum.
上記において、酸化物は、Ｉｎと、元素Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎ）と、Ｚｎと、を含むことが好ましい。 In the above, the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
本発明の一態様は、絶縁体に開口を形成し、絶縁体上、および開口内部に第１の導電体を形成し、第１の導電体上に第２の導電体を形成し、絶縁体の上方に位置する第１の導電体および第２の導電体を除去し、開口内部に位置する第２の導電体の一部を除去し、絶縁体上、および開口内部に、第１の導電体および第２の導電体と接するように第３の導電体を形成し、第３の導電体上に第４の導電体を形成し、絶縁体の上方に位置する第３の導電体および第４の導電体を除去する半導体装置の作製方法である。 According to one embodiment of the present invention, an opening is formed in an insulator, a first conductor is formed over the insulator and in the opening, a second conductor is formed over the first conductor, and the insulator The first conductor and the second conductor located above are removed, a part of the second conductor located inside the opening is removed, and the first conductor is formed on the insulator and inside the opening. A third conductor is formed to be in contact with the body and the second conductor, a fourth conductor is formed on the third conductor, and the third conductor and the second conductor located above the insulator 4 is a method for manufacturing a semiconductor device in which the conductor 4 is removed.
上記において、絶縁体は、第１の絶縁体であり、第１の絶縁体、第１の導電体、第２の導電体、第３の導電体、および第４の導電体上に第２の絶縁体を形成し、第２の絶縁体上に、第４の導電体と重なるように酸化物を形成してもよい。 In the above, the insulator is a first insulator, and the second insulator is formed on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor. An insulator may be formed, and an oxide may be formed over the second insulator so as to overlap with the fourth conductor.
上記において、第１の導電体および第２の導電体の除去、および第３の導電体および第４の導電体の除去に、ＣＭＰ法を用いることが好ましい。 In the above, it is preferable to use the CMP method for removing the first conductor and the second conductor and for removing the third conductor and the fourth conductor.
上記において、第１の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第３の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含むことが好ましい。 In the above, the first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, and the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride. It is preferable.
上記において、第１の導電体は、第１の材料および第２の材料を含み、第１の材料は、開口の側面と底面に接し、第２の材料は、第２の導電体および第３の導電体と接することが好ましい。 In the above, the first conductor includes the first material and the second material, the first material is in contact with the side surface and the bottom surface of the opening, and the second material is the second conductor and the third material. It is preferable to contact the conductor.
上記において、第１の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第２の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、第２の材料は、第１の材料と異なる材料であることが好ましい。 In the above, the first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, and the second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride, The second material is preferably a material different from the first material.
上記において、第２の導電体は、タングステン、銅およびアルミニウムのいずれか一を含み、第４の導電体は、タングステン、銅およびアルミニウムのいずれか一を含むことが好ましい。 In the above, it is preferable that the second conductor includes any one of tungsten, copper, and aluminum, and the fourth conductor includes any one of tungsten, copper, and aluminum.
上記において、酸化物は、Ｉｎと、元素Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎ）と、Ｚｎと、を含むことが好ましい。 In the above, the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
本発明の一態様により、良好な電気特性を有する半導体装置およびその作製方法を提供することができる。本発明の一態様により、信頼性の高い半導体装置およびその作製方法を提供することができる。本発明の一態様により、微細化または高集積化が可能な半導体装置およびその作製方法を提供することができる。本発明の一態様により、生産性の高い半導体装置およびその作製方法を提供することができる。 According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly productive semiconductor device and a manufacturing method thereof can be provided.
また、本発明の一態様により、ダマシン法で形成された電極、配線、あるいはプラグの表面が平坦化された半導体装置およびその作製方法を提供することができる。 Further, according to one embodiment of the present invention, a semiconductor device in which a surface of an electrode, a wiring, or a plug formed by a damascene method is planarized and a manufacturing method thereof can be provided.
また、本発明の一態様により、ダマシン法で形成された電極、配線、あるいはプラグを介した、半導体装置外部から半導体装置内部への不純物の混入を防ぐことができる。 According to one embodiment of the present invention, impurities can be prevented from entering the semiconductor device from the outside through the electrode, wiring, or plug formed by the damascene method.
酸化物半導体を有するトランジスタを用いた半導体装置において、電気特性の変動を抑制すると共に、信頼性を向上させることができる。または、オン電流が大きい酸化物半導体を有するトランジスタを提供することができる。または、オフ電流が小さい酸化物半導体を有するトランジスタを提供することができる。または、消費電力が低減された半導体装置を提供することができる。または、動作周波数が向上した半導体装置を提供することができる。 In a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a semiconductor device with improved operating frequency can be provided.
または、新規な半導体装置を提供することができる。または、該半導体装置を有するモジュールを提供することができる。または、該半導体装置、または該モジュールを有する電子機器を提供することができる。 Alternatively, a novel semiconductor device can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.
　なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.
本発明の一態様に係る半導体装置を示す上面図および断面図。4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す断面図。FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置を示す上面図および断面図。4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す断面図。9A to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の作製方法を示す上面図および断面図。4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成を示す断面図。FIG. 10 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図。FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示す回路図。FIG. 10 is a circuit diagram illustrating a structural example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図。FIG. 10 is a block diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る記憶装置の構成例を示すブロック図、および回路図。4A and 4B are a block diagram and a circuit diagram illustrating a structure example of a memory device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の構成例を示すブロック図。FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の構成例を示すブロック図、回路図、および半導体装置の動作例を示すタイミングチャート。10A and 10B are a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a timing chart illustrating an operation example of the semiconductor device. 本発明の一態様に係る半導体装置の構成例を示すブロック図。FIG. 10 is a block diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention. 本発明の一態様に係る半導体装置の構成例を示す回路図、および半導体装置の動作例を示すタイミングチャート。4A and 4B are a circuit diagram illustrating a structure example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. 本発明の一態様に係るＡＩシステムの構成例を示すブロック図。1 is a block diagram illustrating a configuration example of an AI system according to one embodiment of the present invention. 本発明の一態様に係るＡＩシステムの応用例を説明するブロック図。FIG. 10 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. 本発明の一態様に係るＡＩシステムを組み込んだＩＣの構成例を示す斜視模式図。FIG. 10 is a schematic perspective view illustrating a configuration example of an IC incorporating an AI system according to one embodiment of the present invention. 本発明の一態様に係る電子機器を示す図。FIG. 14 illustrates an electronic device according to one embodiment of the present invention. 本発明の一実施例に係る断面写真。The cross-sectional photograph which concerns on one Example of this invention. 本発明の一実施例に係る断面写真。The cross-sectional photograph which concerns on one Example of this invention.
　以下、実施の形態について図面を参照しながら説明する。但し、実施の形態は多くの異なる態様で実施することが可能であり、趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.
　また、図面において、大きさ、層の厚さ、又は領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお図面は、理想的な例を模式的に示したものであり、図面に示す形状又は値などに限定されない。例えば、実際の製造工程において、エッチングなどの処理により層やレジストマスクなどが意図せずに目減りすることがあるが、理解を容易とするために省略して示すことがある。また、図面において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.
　また、特に上面図（「平面図」ともいう。）や斜視図などにおいて、発明の理解を容易とするため、一部の構成要素の記載を省略する場合がある。また、一部の隠れ線などの記載を省略する場合がある。 In particular, in a top view (also referred to as a “plan view”), a perspective view, and the like, some components may be omitted in order to facilitate understanding of the invention. Moreover, description of some hidden lines may be omitted.
　また、本明細書などにおいて、第１、第２等として付される序数詞は便宜上用いるものであり、工程順又は積層順を示すものではない。そのため、例えば、「第１の」を「第２の」又は「第３の」などと適宜置き換えて説明することができる。また、本明細書等に記載されている序数詞と、本発明の一態様を特定するために用いられる序数詞は一致しない場合がある。 In the present specification and the like, the ordinal numbers attached as the first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.
　また、本明細書において、「上に」、「下に」などの配置を示す語句は、構成同士の位置関係を、図面を参照して説明するために、便宜上用いている。また、構成同士の位置関係は、各構成を描写する方向に応じて適宜変化するものである。従って、明細書で説明した語句に限定されず、状況に応じて適切に言い換えることができる。 Further, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience in order to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.
　例えば、本明細書等において、ＸとＹとが接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが機能的に接続されている場合と、ＸとＹとが直接接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図または文章に示された接続関係に限定されず、図または文章に示された接続関係以外のものも、図または文章に記載されているものとする。 For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.
　ここで、Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など）であるとする。 Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
　ＸとＹとが直接的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）が、ＸとＹとの間に接続されていない場合であり、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）を介さずに、ＸとＹとが、接続されている場合である。 As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.
　ＸとＹとが電気的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）が、ＸとＹとの間に１個以上接続されることが可能である。なお、スイッチは、オンオフが制御される機能を有している。つまり、スイッチは、導通状態（オン状態）、または、非導通状態（オフ状態）になり、電流を流すか流さないかを制御する機能を有している。または、スイッチは、電流を流す経路を選択して切り替える機能を有している。なお、ＸとＹとが電気的に接続されている場合は、ＸとＹとが直接的に接続されている場合を含むものとする。 As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
　ＸとＹとが機能的に接続されている場合の一例としては、ＸとＹとの機能的な接続を可能とする回路（例えば、論理回路（インバータ、ＮＡＮＤ回路、ＮＯＲ回路など）、信号変換回路（ＤＡ変換回路、ＡＤ変換回路、ガンマ補正回路など）、電位レベル変換回路（電源回路（昇圧回路、降圧回路など）、信号の電位レベルを変えるレベルシフタ回路など）、電圧源、電流源、切り替え回路、増幅回路（信号振幅または電流量などを大きく出来る回路、オペアンプ、差動増幅回路、ソースフォロワ回路、バッファ回路など）、信号生成回路、記憶回路、制御回路など）が、ＸとＹとの間に１個以上接続されることが可能である。なお、一例として、ＸとＹとの間に別の回路を挟んでいても、Ｘから出力された信号がＹへ伝達される場合は、ＸとＹとは機能的に接続されているものとする。なお、ＸとＹとが機能的に接続されている場合は、ＸとＹとが直接的に接続されている場合と、ＸとＹとが電気的に接続されている場合とを含むものとする。 As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
　また、本明細書等において、トランジスタとは、ゲートと、ドレインと、ソースとを含む少なくとも三つの端子を有する素子である。そして、ドレイン（ドレイン端子、ドレイン領域またはドレイン電極）とソース（ソース端子、ソース領域またはソース電極）の間にチャネル領域を有しており、チャネル領域を介して、ソースとドレインとの間に電流を流すことができるものである。なお、本明細書等において、チャネル領域とは、電流が主として流れる領域をいう。 In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows between the source and drain via the channel region. Can be used. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.
　また、ソースやドレインの機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書等においては、ソースやドレインの用語は、入れ替えて用いることができる場合がある。 Also, the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” may be used interchangeably.
　なお、チャネル長とは、例えば、トランジスタの上面図において、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソース（ソース領域またはソース電極）とドレイン（ドレイン領域またはドレイン電極）との間の距離をいう。なお、一つのトランジスタにおいて、チャネル長が全ての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル長は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル長は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
　チャネル幅とは、例えば、半導体（またはトランジスタがオン状態のときに半導体の中で電流の流れる部分）とゲート電極とが互いに重なる領域、またはチャネルが形成される領域における、ソースとドレインとが向かい合っている部分の長さをいう。なお、一つのトランジスタにおいて、チャネル幅がすべての領域で同じ値をとるとは限らない。即ち、一つのトランジスタのチャネル幅は、一つの値に定まらない場合がある。そのため、本明細書では、チャネル幅は、チャネルの形成される領域における、いずれか一の値、最大値、最小値または平均値とする。 The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
　なお、トランジスタの構造によっては、実際にチャネルの形成される領域におけるチャネル幅（以下、「実効的なチャネル幅」ともいう。）と、トランジスタの上面図において示されるチャネル幅（以下、「見かけ上のチャネル幅」ともいう。）と、が異なる場合がある。例えば、ゲート電極が半導体の側面を覆う場合、実効的なチャネル幅が、見かけ上のチャネル幅よりも大きくなり、その影響が無視できなくなる場合がある。例えば、微細かつゲート電極が半導体の側面を覆うトランジスタでは、半導体の側面に形成されるチャネル形成領域の割合が大きくなる場合がある。その場合は、見かけ上のチャネル幅よりも、実効的なチャネル幅の方が大きくなる。 Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as “effective channel width”) and the channel width (hereinafter “apparently” shown in the top view of the transistor). Sometimes referred to as “channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers a side surface of a semiconductor, the ratio of a channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.
　このような場合、実効的なチャネル幅の、実測による見積もりが困難となる場合がある。例えば、設計値から実効的なチャネル幅を見積もるためには、半導体の形状が既知という仮定が必要である。したがって、半導体の形状が正確にわからない場合には、実効的なチャネル幅を正確に測定することは困難である。 In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.
　そこで、本明細書では、見かけ上のチャネル幅を、「囲い込みチャネル幅（ＳＣＷ：Ｓｕｒｒｏｕｎｄｅｄ　Ｃｈａｎｎｅｌ　Ｗｉｄｔｈ）」と呼ぶ場合がある。また、本明細書では、単にチャネル幅と記載した場合には、囲い込みチャネル幅または見かけ上のチャネル幅を指す場合がある。または、本明細書では、単にチャネル幅と記載した場合には、実効的なチャネル幅を指す場合がある。なお、チャネル長、チャネル幅、実効的なチャネル幅、見かけ上のチャネル幅、囲い込みチャネル幅などは、断面ＴＥＭ像などを解析することなどによって、値を決定することができる。 Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
　なお、半導体の不純物とは、例えば、半導体を構成する主成分以外をいう。例えば、濃度が０．１原子％未満の元素は不純物と言える。不純物が含まれることにより、例えば、半導体のＤＯＳ（Ｄｅｎｓｉｔｙ　ｏｆ　Ｓｔａｔｅｓ）が高くなることや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第１族元素、第２族元素、第１３族元素、第１４族元素、第１５族元素、および酸化物半導体の主成分以外の遷移金属などがあり、例えば、水素、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。酸化物半導体の場合、水も不純物として機能する場合がある。また、酸化物半導体の場合、例えば不純物の混入によって酸素欠損を形成する場合がある。また、半導体がシリコンである場合、半導体の特性を変化させる不純物としては、例えば、酸素、水素を除く第１族元素、第２族元素、第１３族元素、第１５族元素などがある。 In addition, the impurity of a semiconductor means the thing other than the main component which comprises a semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. When the impurities are included, for example, DOS (Density of States) of the semiconductor may increase or crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by mixing impurities. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
　なお、本明細書等において、酸化窒化シリコン膜とは、その組成として、窒素よりも酸素の含有量が多いものである。例えば、好ましくは酸素が５５原子％以上６５原子％以下、窒素が１原子％以上２０原子％以下、シリコンが２５原子％以上３５原子％以下、水素が０．１原子％以上１０原子％以下の濃度範囲で含まれるものをいう。また、窒化酸化シリコン膜とは、その組成として、酸素よりも窒素の含有量が多いものである。例えば、好ましくは窒素が５５原子％以上６５原子％以下、酸素が１原子％以上２０原子％以下、シリコンが２５原子％以上３５原子％以下、水素が０．１原子％以上１０原子％以下の濃度範囲で含まれるものをいう。 Note that in this specification and the like, a silicon oxynitride film has a higher oxygen content than nitrogen as its composition. For example, preferably oxygen is 55 atomic% to 65 atomic%, nitrogen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range. The silicon nitride oxide film has a nitrogen content higher than that of oxygen. For example, preferably, nitrogen is 55 atomic% to 65 atomic%, oxygen is 1 atomic% to 20 atomic%, silicon is 25 atomic% to 35 atomic%, and hydrogen is 0.1 atomic% to 10 atomic%. It is included in the concentration range.
　また、本明細書等において、「膜」という用語と、「層」という用語とは、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能な場合がある。または、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能な場合がある。 In addition, in this specification and the like, the terms “film” and “layer” can be interchanged. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.
　また、本明細書等において、「絶縁体」という用語を、絶縁膜または絶縁層と言い換えることができる。また、「導電体」という用語を、導電膜または導電層と言い換えることができる。また、「半導体」という用語を、半導体膜または半導体層と言い換えることができる。 Further, in this specification and the like, the term “insulator” can be referred to as an insulating film or an insulating layer. In addition, the term “conductor” can be restated as a conductive film or a conductive layer. In addition, the term “semiconductor” can be restated as a semiconductor film or a semiconductor layer.
　また、本明細書等に示すトランジスタは、明示されている場合を除き、電界効果トランジスタとする。また、本明細書等に示すトランジスタは、明示されている場合を除き、ｎチャネル型のトランジスタとする。よって、そのしきい値電圧（「Ｖｔｈ」ともいう。）は、明示されている場合を除き、０Ｖよりも大きいものとする。 Further, the transistors described in this specification and the like are field-effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is assumed to be greater than 0 V unless otherwise specified.
　また、本明細書等において、「平行」とは、二つの直線が−１０°以上１０°以下の角度で配置されている状態をいう。したがって、−５°以上５°以下の場合も含まれる。また、「略平行」とは、二つの直線が−３０°以上３０°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０°以上１００°以下の角度で配置されている状態をいう。したがって、８５°以上９５°以下の場合も含まれる。また、「略垂直」とは、二つの直線が６０°以上１２０°以下の角度で配置されている状態をいう。 In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
　また、本明細書において、結晶が三方晶または菱面体晶である場合、六方晶系に含まれるものとする。 Further, in this specification, when a crystal is a trigonal crystal or a rhombohedral crystal, it is included in a hexagonal crystal system.
　なお、本明細書において、バリア膜とは、水素などの不純物および酸素の透過を抑制する機能を有する膜のことであり、該バリア膜に導電性を有する場合は、導電性バリア膜と呼ぶことがある。 Note that in this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. There is.
　本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い表現での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む）、酸化物半導体（Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒまたは単にＯＳともいう）などに分類される。例えば、トランジスタの活性層に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、ＯＳ　ＦＥＴと記載する場合においては、酸化物または酸化物半導体を有するトランジスタと換言することができる。 In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing as OS FET, it can be translated into a transistor including an oxide or an oxide semiconductor.
（実施の形態１）
＜半導体装置の構成例１＞
以下では、本発明の一態様に係るトランジスタ２００を有する半導体装置の一例について説明する。 (Embodiment 1)
<Configuration Example 1 of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.
図１（Ａ）、図１（Ｂ）、図１（Ｃ）、および図１（Ｄ）は、本発明の一態様に係るトランジスタ２００、およびトランジスタ２００周辺の上面図、および断面図である。 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention, and the periphery of the transistor 200.
図１（Ａ）は、トランジスタ２００の上面図である。また、図１（Ｂ）、図１（Ｃ）、および図１（Ｄ）はトランジスタ２００の断面図である。ここで、図１（Ｂ）は、図１（Ａ）にＡ−Ｂの一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、図１（Ｃ）は、図１（Ａ）にＣ−Ｄの一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、図１（Ｄ）は、図１（Ａ）にＥ−Ｆの一点鎖線で示す部位の断面図であり、酸化物２３０と導電体２５２２の接続部を示す断面図でもある。図１（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。 FIG. 1A is a top view of the transistor 200. 1B, 1C, and 1D are cross-sectional views of the transistor 200. FIG. Here, FIG. 1B is a cross-sectional view taken along dashed-dotted line AB in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view taken along dashed-dotted line CD in FIG. 1A and also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view taken along the dashed line EF in FIG. 1A and is a cross-sectional view illustrating a connection portion between the oxide 230 and the conductor 2522. In the top view of FIG. 1A, some elements are omitted for clarity.
図１に示すように、トランジスタ２００は、基板（図示せず）の上に配置された絶縁体２０８、絶縁体２１０、および絶縁体２１２と、絶縁体２１２に埋め込まれるように配置された導電体２０３と、絶縁体２１２と導電体２０３の上に配置された絶縁体２１６と、絶縁体２１６に埋め込まれるように配置された導電体２０５と、絶縁体２１６と導電体２０５の上に配置された絶縁体２２０と、絶縁体２２０の上に配置された絶縁体２２２と、絶縁体２２２の上に配置された絶縁体２２４と、絶縁体２２４の上に配置された酸化物２３０（酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃ）と、酸化物２３０の上に配置された絶縁体２５０と、絶縁体２５０の上に配置された導電体２６０（導電体２６０ａ、および導電体２６０ｂ）と、導電体２６０の上に配置された絶縁体２７０、および絶縁体２７１と、少なくとも絶縁体２５０、および導電体２６０の側面に接して配置された絶縁体２７２と、酸化物２３０、および絶縁体２７２と接して配置された絶縁体２７４と、を有する。 As shown in FIG. 1, the transistor 200 includes an insulator 208, an insulator 210, and an insulator 212 disposed on a substrate (not shown), and a conductor disposed so as to be embedded in the insulator 212. 203, the insulator 212 and the insulator 216 disposed on the conductor 203, the conductor 205 disposed to be embedded in the insulator 216, and the insulator 216 and the conductor 205. An insulator 220, an insulator 222 disposed on the insulator 220, an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a, Oxide 230b and oxide 230c), insulator 250 disposed on oxide 230, and conductor 260 (conductor 260a and conductor 260b) disposed on insulator 250 , The insulator 270 disposed on the conductor 260, and the insulator 271, at least the insulator 250, the insulator 272 disposed on the side surface of the conductor 260, the oxide 230, and the insulator 272 And an insulator 274 which is disposed in contact with each other.
なお、絶縁体２１６に埋め込まれるように配置された導電体２０５は、ダマシン法を用いて形成することができる。また、詳細は後述するが、導電体２０５ａ、導電体２０５ｂ、導電体２０５ｃ、導電体２０５ｄ、および導電体２０５ｅからなる導電体２０５は、表面の平坦性に優れ、その上に形成される膜のカバレッジ不良といった形状不良を抑制することができる。また、導電体２０５上に設けられる素子は、良好な特性を有する。 Note that the conductor 205 provided to be embedded in the insulator 216 can be formed by a damascene method. Although details will be described later, the conductor 205 including the conductor 205a, the conductor 205b, the conductor 205c, the conductor 205d, and the conductor 205e has excellent surface flatness, and is formed of a film formed thereon. Shape defects such as coverage failures can be suppressed. In addition, an element provided over the conductor 205 has favorable characteristics.
また、導電体２０５は複数の導電性バリア膜を有していることから、絶縁体２１２、あるいは絶縁体２１０より基板側から、水素、水などの不純物が、導電体２０５を通じて、トランジスタ２００側に拡散するのを抑制することができる。また、トランジスタ２００側から、酸素が導電体２０５を通じて、基板側に拡散するのを抑制することができる。 In addition, since the conductor 205 includes a plurality of conductive barrier films, impurities such as hydrogen and water are introduced to the transistor 200 side through the conductor 205 from the substrate side of the insulator 212 or the insulator 210. Diffusion can be suppressed. Further, diffusion of oxygen from the transistor 200 side to the substrate side through the conductor 205 can be suppressed.
なお、トランジスタ２００では、図１に示すように、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃを積層する構成について示しているが、本発明はこれに限られるものではない。例えば、酸化物２３０ａ、酸化物２３０ｂの２層構造、または４層以上の積層構造としてもよい。また、酸化物２３０ｂのみの単層、または酸化物２３０ｂと酸化物２３０ｃのみを設ける構成にしてもよい。また、トランジスタ２００では、導電体２６０ａ、および導電体２６０ｂを積層する構成について示しているが、本発明はこれに限られるものではない。例えば、単層、または３層以上の積層構造としてもよい。 Note that the transistor 200 has a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are stacked as illustrated in FIG. 1, but the present invention is not limited thereto. For example, a two-layer structure of the oxide 230a and the oxide 230b or a stacked structure of four or more layers may be used. Alternatively, a single layer including only the oxide 230b or only the oxide 230b and the oxide 230c may be provided. In the transistor 200, the structure in which the conductors 260a and 260b are stacked is described; however, the present invention is not limited to this. For example, a single layer or a stacked structure of three or more layers may be used.
ここで、図１（Ｂ）における一点鎖線で囲む、チャネル近傍の領域２３９の拡大図を図２に示す。 Here, FIG. 2 shows an enlarged view of a region 239 in the vicinity of the channel, which is surrounded by a one-dot chain line in FIG.
図１（Ｂ）および図２に示すように、酸化物２３０は、トランジスタ２００のチャネル形成領域として機能する領域２３４と、ソース領域またはドレイン領域として機能する領域２３１（領域２３１ａ、および領域２３１ｂ）との間に、接合領域２３２（接合領域２３２ａ、および接合領域２３２ｂ）を有する。ソース領域またはドレイン領域として機能する領域２３１は、キャリア密度が高い、低抵抗化した領域である。また、チャネル形成領域として機能する領域２３４は、ソース領域またはドレイン領域として機能する領域２３１よりも、キャリア密度が低い領域である。また、接合領域２３２は、ソース領域またはドレイン領域として機能する領域２３１よりもキャリア密度が低く、チャネル形成領域として機能する領域２３４よりもキャリア密度が高い領域である。すなわち接合領域２３２は、チャネル形成領域と、ソース領域またはドレイン領域との間の接合領域（ｊｕｎｃｔｉｏｎ　ｒｅｇｉｏｎ）としての機能を有する。 As illustrated in FIGS. 1B and 2, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200, and a region 231 (region 231 a and region 231 b) functioning as a source region or a drain region. In the meantime, the bonding region 232 (the bonding region 232a and the bonding region 232b) is provided. The region 231 functioning as a source region or a drain region is a region with high carrier density and low resistance. The region 234 functioning as a channel formation region is a region having a lower carrier density than the region 231 functioning as a source region or a drain region. The junction region 232 has a lower carrier density than the region 231 that functions as a source region or a drain region and a higher carrier density than the region 234 that functions as a channel formation region. In other words, the junction region 232 functions as a junction region between the channel formation region and the source region or the drain region.
接合領域を設けることで、ソース領域またはドレイン領域として機能する領域２３１と、チャネル形成領域として機能する領域２３４との間に高抵抗領域が形成されず、トランジスタのオン電流を大きくすることができる。 By providing the junction region, a high resistance region is not formed between the region 231 functioning as a source region or a drain region and the region 234 functioning as a channel formation region, so that the on-state current of the transistor can be increased.
また、接合領域２３２は、ゲート電極として機能する導電体２６０と重なる領域を有する。特に、接合領域２３２においてゲート電極として機能する導電体２６０と重なる領域は、いわゆるオーバーラップ領域（Ｌｏｖ領域ともいう）として機能する場合がある。 The junction region 232 includes a region overlapping with the conductor 260 functioning as a gate electrode. In particular, a region overlapping with the conductor 260 functioning as a gate electrode in the junction region 232 may function as a so-called overlap region (also referred to as a Lov region).
領域２３１は、絶縁体２７４と接することが好ましい。また、領域２３１は、インジウムなどの金属元素、並びに水素、および窒素などの不純物元素、の少なくとも一の濃度が接合領域２３２、および領域２３４よりも大きいことが好ましい。 The region 231 is preferably in contact with the insulator 274. The region 231 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the junction region 232 and the region 234.
接合領域２３２は、絶縁体２７２と重畳する領域を有する。接合領域２３２は、インジウムなどの金属元素、並びに水素、および窒素などの不純物元素、の少なくとも一の濃度が領域２３４よりも大きいことが好ましい。一方、インジウムなどの金属元素、並びに水素、および窒素などの不純物元素、の少なくとも一の濃度が領域２３１よりも、小さいことが好ましい。 The bonding region 232 has a region overlapping with the insulator 272. The junction region 232 preferably has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen higher than that of the region 234. On the other hand, it is preferable that at least one concentration of a metal element such as indium and an impurity element such as hydrogen and nitrogen be smaller than that of the region 231.
領域２３４は、導電体２６０と重畳する。領域２３４は、接合領域２３２ａ、および接合領域２３２ｂとの間に配置しており、インジウムなどの金属元素、並びに水素、および窒素などの不純物元素、の少なくとも一の濃度が領域２３１、および接合領域２３２より、小さいことが好ましい。 The region 234 overlaps with the conductor 260. The region 234 is disposed between the junction region 232 a and the junction region 232 b, and the region 231 has a concentration of at least one of a metal element such as indium and an impurity element such as hydrogen and nitrogen, and the junction region 232. More preferably, it is smaller.
また、酸化物２３０において、領域２３１、接合領域２３２、および領域２３４の境界は明確に検出できない場合がある。各領域内で検出されるインジウムなどの金属元素、並びに水素、および窒素などの不純物元素の濃度は、領域ごとの段階的な変化に限らず、各領域内でも連続的に変化（グラデーションともいう）していてもよい。つまり、領域２３１から接合領域２３２へ、領域２３４に近い領域であるほど、インジウムなどの金属元素、並びに水素、および窒素などの不純物元素の濃度が減少していればよい。 In the oxide 230, the boundary between the region 231, the junction region 232, and the region 234 may not be clearly detected in some cases. Concentrations of metal elements such as indium and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes in each region, but also continuously change in each region (also referred to as gradation). You may do it. That is, the closer to the region 234 from the region 231 to the junction region 232, the lower the concentration of the metal element such as indium and the impurity element such as hydrogen and nitrogen.
また、図１（Ｂ）および図２では、領域２３４、領域２３１、および接合領域２３２が、酸化物２３０ｂに形成されているが、これに限られることなく、例えばこれらの領域は酸化物２３０ａ、または酸化物２３０ｃにも形成されていてもよい。また、図では、各領域の境界を、酸化物２３０の上面に対して略垂直に表示しているが、本実施の形態はこれに限られるものではない。例えば、接合領域２３２が酸化物２３０ｂの表面近傍では導電体２６０側に張り出し、酸化物２３０ｂの下面近傍では、導電体２５２１側または導電体２５２２側に後退する形状になる場合がある。 In FIGS. 1B and 2, the region 234, the region 231, and the junction region 232 are formed in the oxide 230 b, but the present invention is not limited to this. For example, these regions include the oxide 230 a, Alternatively, the oxide 230c may be formed. Further, in the figure, the boundary of each region is displayed substantially perpendicular to the upper surface of the oxide 230, but this embodiment is not limited to this. For example, the junction region 232 may protrude to the conductor 260 side near the surface of the oxide 230b and recede to the conductor 2521 side or the conductor 2522 side near the lower surface of the oxide 230b.
なお、トランジスタ２００において、酸化物２３０は、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう）を用いることが好ましい。酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流（オフ電流）が小さいため、低消費電力の半導体装置が提供できる。また、酸化物半導体は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。 Note that in the transistor 200, the oxide 230 is preferably a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Since a transistor including an oxide semiconductor has extremely small leakage current (off-state current) in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
一方で、酸化物半導体を用いたトランジスタは、酸化物半導体中の不純物及び酸素欠損によって、その電気特性が変動しやすく、信頼性が悪くなる場合がある。また、酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。従って、チャネル形成領域に酸素欠損が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、チャネル形成領域中の酸素欠損はできる限り低減されていることが好ましい。 On the other hand, in a transistor including an oxide semiconductor, its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the oxide semiconductor, and reliability may deteriorate. In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including an oxide semiconductor in which an oxygen vacancy is included in a channel formation region is likely to be normally on. For this reason, it is preferable that oxygen vacancies in the channel formation region be reduced as much as possible.
特に、酸化物２３０におけるチャネルが形成される領域２３４と、ゲート絶縁膜として機能する絶縁体２５０との界面に、酸素欠損が存在すると、電気特性の変動が生じやすく、また信頼性が悪くなる場合がある。 In particular, when oxygen vacancies exist at the interface between the region 234 where the channel is formed in the oxide 230 and the insulator 250 functioning as a gate insulating film, electrical characteristics are likely to fluctuate and reliability is deteriorated. There is.
そこで、酸化物２３０の領域２３４と重畳する絶縁体２５０が化学量論的組成を満たす酸素よりも多くの酸素（過剰酸素ともいう）を含むことが好ましい。つまり、絶縁体２５０が有する過剰酸素が、領域２３４へと拡散することで、領域２３４中の酸素欠損を低減することができる。 Therefore, the insulator 250 overlapping with the region 234 of the oxide 230 preferably contains more oxygen (also referred to as excess oxygen) than oxygen that satisfies the stoichiometric composition. That is, excess oxygen in the insulator 250 diffuses into the region 234, so that oxygen vacancies in the region 234 can be reduced.
また、絶縁体２５０と接して、絶縁体２７２を設けることが好ましい。例えば、絶縁体２７２は、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい）ことが好ましい。絶縁体２７２が、酸素の拡散を抑制する機能を有することで、過剰酸素領域の酸素は絶縁体２７４側へ拡散することなく、効率よく領域２３４へ供給される。従って、酸化物２３０と、絶縁体２５０との界面における酸素欠損の形成が抑制され、トランジスタ２００の信頼性を向上させることができる。 Further, the insulator 272 is preferably provided in contact with the insulator 250. For example, the insulator 272 preferably has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits). Since the insulator 272 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region is efficiently supplied to the region 234 without diffusing to the insulator 274 side. Accordingly, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200 can be improved.
さらに、トランジスタ２００は、水または水素などの不純物の混入を防ぐバリア性を有する絶縁体で覆われていることが好ましい。バリア性を有する絶縁体とは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい）絶縁性材料を用いた絶縁体である。また、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい）絶縁性材料を用いることが好ましい。 Further, the transistor 200 is preferably covered with an insulator having a barrier property to prevent entry of impurities such as water or hydrogen. An insulator having a barrier property is a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. Insulators using an insulating material that has (which is difficult to transmit the above impurities). In addition, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen hardly transmits).
以下では、本発明の一態様に係るトランジスタ２００を有する半導体装置の詳細な構成について説明する。 Hereinafter, a detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.
第２のゲート電極として機能する導電体２０５は、酸化物２３０および導電体２６０と重なるように配置する。 The conductor 205 functioning as the second gate electrode is provided so as to overlap with the oxide 230 and the conductor 260.
ここで、導電体２０５は、酸化物２３０における領域２３４よりも、チャネル幅方向の長さが大きくなるように大きく設けるとよい。特に、導電体２０５は、酸化物２３０の領域２３４がチャネル幅方向と交わる端部よりも外側の領域においても、延伸していることが好ましい。つまり、酸化物２３０のチャネル幅方向における側面において、導電体２０５と、導電体２６０とは、絶縁体を介して重畳していることが好ましい。 Here, the conductor 205 is preferably provided larger than the region 234 in the oxide 230 so that the length in the channel width direction is larger. In particular, the conductor 205 preferably extends in a region outside the end where the region 234 of the oxide 230 intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other through the insulator on the side surface of the oxide 230 in the channel width direction.
ここで、導電体２６０は、第１のゲート電極として機能する場合がある。また、導電体２０５は、第２のゲート電極として機能する場合がある。その場合、導電体２０５に印加する電位を、導電体２６０に印加する電位と、連動させず、独立して変化させることで、トランジスタ２００のしきい値電圧を制御することができる。特に、導電体２０５に負の電位を印加することにより、トランジスタ２００のしきい値電圧を０Ｖより大きくし、オフ電流を低減することが可能となる。従って、導電体２６０に印加する電圧が０Ｖのときのドレイン電流を小さくすることができる。 Here, the conductor 260 may function as the first gate electrode. In addition, the conductor 205 may function as a second gate electrode. In that case, the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without being linked. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made higher than 0 V and the off-state current can be reduced. Therefore, the drain current when the voltage applied to the conductor 260 is 0 V can be reduced.
導電体２０５は、絶縁体２１６の開口の内壁に接して導電体２０５ａが形成され、さらに内側に導電体２０５ｂが形成されている。また、導電体２０５ｂの内側に導電体２０５ｃが形成されている。さらに、導電体２０５ｂの内壁に接し、かつ導電体２０５ｃの上面に接するように導電体２０５ｄが形成され、導電体２０５ｄの内側に導電体２０５ｅが形成されている。ここで、導電体２０５ａ、導電体２０５ｂ、導電体２０５ｄ、および導電体２０５ｅの上面の高さと、絶縁体２１６の上面の高さは同程度にできる。 In the conductor 205, a conductor 205a is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205b is formed further inside. A conductor 205c is formed inside the conductor 205b. Further, a conductor 205d is formed so as to be in contact with the inner wall of the conductor 205b and in contact with the upper surface of the conductor 205c, and a conductor 205e is formed inside the conductor 205d. Here, the heights of the upper surfaces of the conductor 205a, the conductor 205b, the conductor 205d, and the conductor 205e can be substantially the same as the height of the upper surface of the insulator 216.
ここで、導電体２０５ａ、導電体２０５ｂ、および導電体２０５ｄは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい）導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい）導電性材料を用いることが好ましい。なお、本明細書において、不純物、または酸素の拡散を抑制する機能とは、上記不純物、または上記酸素のいずれか一または、すべての拡散を抑制する機能とする。本明細書中、このような機能を有する導電体を、導電性バリア膜と呼ぶことがある。 Here, the conductor 205a, the conductor 205b, and the conductor 205d include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, and the like), a copper atom, and the like. It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities (it is difficult for the impurities to pass through). Alternatively, it is preferable to use a conductive material that has a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Note that in this specification, the function of suppressing diffusion of impurities or oxygen is a function of suppressing diffusion of any one or all of the impurities and oxygen. In this specification, a conductor having such a function may be referred to as a conductive barrier film.
導電体２０５ａ、導電体２０５ｂ、および導電体２０５ｄが酸素の拡散を抑制する機能を持つことにより、導電体２０５ｃ、および導電体２０５ｅが酸化して導電率が低下することを防ぐことができる。酸素の拡散を抑制する機能を有する導電性材料としては、例えば、チタン、窒化チタン、タンタル、窒化タンタル、ルテニウムまたは酸化ルテニウムなどを用いることが好ましい。従って、導電体２０５ａ、導電体２０５ｂ、および導電体２０５ｄとしては、上記導電性材料を単層または積層とすればよい。これにより、絶縁体２１２、あるいは絶縁体２１０より基板側から、水素、水などの不純物が、導電体２０５を通じて、トランジスタ２００側に拡散するのを抑制することができる。本実施の形態では、導電体２０５ａとして、窒化タンタルを用い、導電体２０５ｂ、および導電体２０５ｄとして、窒化チタンを用いた。 When the conductor 205a, the conductor 205b, and the conductor 205d have a function of suppressing diffusion of oxygen, the conductivity can be prevented from being reduced due to oxidation of the conductor 205c and the conductor 205e. For example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used as the conductive material having a function of suppressing oxygen diffusion. Therefore, the conductive material may be a single layer or a stacked layer as the conductor 205a, the conductor 205b, and the conductor 205d. Accordingly, diffusion of impurities such as hydrogen and water from the insulator 212 or the substrate 210 to the transistor 200 side through the conductor 205 can be suppressed. In this embodiment, tantalum nitride is used as the conductor 205a, and titanium nitride is used as the conductor 205b and the conductor 205d.
また、導電体２０５ｃ、および導電体２０５ｅは、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。本実施の形態では、導電体２０５ｃ、および導電体２０５ｅとして、タングステンを用いた。 The conductor 205c and the conductor 205e are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In this embodiment mode, tungsten is used as the conductor 205c and the conductor 205e.
また、導電体２０５と電気的に接続する導電体２０３を設けてもよい。導電体２０３は、絶縁体２１０の上に設けられた絶縁体２１２に埋め込まれるように形成される。導電体２０３は、配線として機能することができ、導電体２０５がトランジスタ２００の第２のゲート電極として機能する場合、導電体２０３の一部は、ゲート配線として機能することができる。 Further, a conductor 203 that is electrically connected to the conductor 205 may be provided. The conductor 203 is formed so as to be embedded in an insulator 212 provided on the insulator 210. The conductor 203 can function as a wiring. When the conductor 205 functions as the second gate electrode of the transistor 200, part of the conductor 203 can function as a gate wiring.
導電体２０３は、絶縁体２１２の開口の内壁に接して第１の導電体２０３ａが形成され、さらに内側に導電体２０３ｂが形成されている。ここで、導電体２０３ａ、および導電体２０３ｂの上面の高さと、絶縁体２１２の上面の高さは同程度にできる。なお、トランジスタ２００では、導電体２０３ａおよび導電体２０３ｂを積層する構成について示しているが、本発明はこれに限られるものではない。例えば、導電体２０３ｂのみを設ける構成にしてもよい。 In the conductor 203, a first conductor 203a is formed in contact with the inner wall of the opening of the insulator 212, and a conductor 203b is formed further inside. Here, the heights of the upper surfaces of the conductors 203a and 203b and the height of the upper surface of the insulator 212 can be approximately the same. Note that although the transistor 200 has a structure in which the conductor 203a and the conductor 203b are stacked, the present invention is not limited to this. For example, only the conductor 203b may be provided.
導電体２０３ａとしては、導電体２０５ａ、導電体２０５ｂ、および導電体２０５ｄと同様の材料を用いることが好ましい。すなわち、導電性バリア膜を用いることが好ましい。また、導電体２０３ｂとしては、導電体２０５ｃ、および導電体２０５ｅと同様の材料を用いることができる。 As the conductor 203a, a material similar to that of the conductor 205a, the conductor 205b, and the conductor 205d is preferably used. That is, it is preferable to use a conductive barrier film. For the conductor 203b, a material similar to that of the conductor 205c and the conductor 205e can be used.
絶縁体２１０は、水または水素などの不純物が、基板側からトランジスタに混入するのを防ぐ絶縁性バリア膜として機能することが好ましい。従って、絶縁体２１０は、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい）絶縁性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい）絶縁性材料を用いることが好ましい。 The insulator 210 preferably functions as an insulating barrier film which prevents impurities such as water or hydrogen from entering the transistor from the substrate side. Therefore, the insulator 210 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, and the like) and copper atoms. It is preferable to use an insulating material (which is difficult for the impurities to pass through). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of at least one of oxygen (for example, oxygen atoms and oxygen molecules) (the above-described oxygen hardly transmits).
例えば、絶縁体２１０として、酸化アルミニウムや窒化シリコンなどを用いることが好ましい。これにより、水素、水などの不純物が絶縁体２１０よりトランジスタ側に拡散するのを抑制することができる。または、絶縁体２２４などに含まれる酸素が、絶縁体２１０より基板側に、拡散するのを抑制することができる。 For example, the insulator 210 is preferably formed using aluminum oxide, silicon nitride, or the like. Thus, impurities such as hydrogen and water can be prevented from diffusing from the insulator 210 to the transistor side. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing from the insulator 210 to the substrate side.
また、層間膜として機能する絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０は、絶縁体２１０よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。 The insulator 208, the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films preferably have a lower dielectric constant than the insulator 210. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.
例えば、層間膜として機能する絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０として、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、酸化アルミニウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）または（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などの絶縁体を単層または積層で用いることができる。またはこれらの絶縁体に例えば酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。またはこれらの絶縁体を窒化処理しても良い。上記の絶縁体に酸化シリコン、酸化窒化シリコンまたは窒化シリコンを積層して用いてもよい。 For example, the insulator 208, the insulator 212, the insulator 216, and the insulator 280 that function as interlayer films include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, and titanic acid. An insulator such as lead zirconate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST) can be used in a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
絶縁体２２０、絶縁体２２２、および絶縁体２２４は、ゲート絶縁体としての機能を有する。 The insulator 220, the insulator 222, and the insulator 224 function as gate insulators.
ここで、酸化物２３０と接する絶縁体２２４は、化学量論的組成を満たす酸素よりも多くの酸素を含む酸化物絶縁体を用いることが好ましい。つまり、絶縁体２２４には、過剰酸素領域が形成されていることが好ましい。このような過剰酸素を含む絶縁体を酸化物２３０に接して設けることにより、酸化物２３０中の酸素欠損を低減し、信頼性を向上させることができる。 Here, as the insulator 224 in contact with the oxide 230, an oxide insulator containing more oxygen than oxygen that satisfies the stoichiometric composition is preferably used. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.
過剰酸素領域を有する絶縁体として、具体的には、加熱により一部の酸素が脱離する酸化物材料を用いることが好ましい。加熱により酸素を脱離する酸化物とは、ＴＤＳ（Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）分析にて、酸素原子に換算しての酸素の脱離量が１．０×１０１８ａｔｏｍｓ／ｃｍ３以上、好ましくは３．０×１０２０ａｔｏｍｓ／ｃｍ３以上である酸化物膜である。なお、上記ＴＤＳ分析時における膜の表面温度としては１００℃以上７００℃以下、または１００℃以上４００℃以下の範囲が好ましい。 Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen in terms of oxygen atom is 1.0 × 10 18 atoms / cm 3 or more, preferably 3 in TDS (Thermal Desorption Spectroscopy) analysis. The oxide film has a thickness of 0.0 × 10 20 atoms / cm 3 or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
また、絶縁体２２４が、過剰酸素領域を有する場合、絶縁体２２２は、酸素（例えば、酸素原子、酸素分子など）の少なくとも一の拡散を抑制する機能を有する（上記酸素が透過しにくい）ことが好ましい。 In the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms and oxygen molecules) (the oxygen is difficult to transmit). Is preferred.
絶縁体２２２が、酸素の拡散を抑制する機能を有することで、過剰酸素領域の酸素は、絶縁体２２０側へ拡散することなく、効率よく酸化物２３０へ供給することができる。また、導電体２０５が、絶縁体２２４が有する過剰酸素領域の酸素と反応することを抑制することができる。 Since the insulator 222 has a function of suppressing oxygen diffusion, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224.
絶縁体２２２は、例えば、酸化アルミニウム、酸化ハフニウム、ハフニウムアルミネート、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）または（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などのいわゆるｈｉｇｈ−ｋ材料を含む絶縁体を単層または積層で用いることが好ましい。ゲート絶縁体として機能する絶縁体に、ｈｉｇｈ−ｋ材料を用いることで、トランジスタの微細化、および高集積化が可能となる。特に、酸化アルミニウム、酸化ハフニウム、およびハフニウムアルミネート、などの、不純物、および酸素などの拡散を抑制する機能を有する（上記酸素が透過しにくい）絶縁性材料を用いることが好ましい。このような材料を用いて形成した場合、酸化物２３０からの酸素の放出や、トランジスタ２００の周辺部からの水素等の不純物の混入を防ぐ層として機能する。 The insulator 222 is made of, for example, aluminum oxide, hafnium oxide, hafnium aluminate, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba, Sr) TiO 3 (BST). An insulator including a so-called high-k material such as a single layer or a stacked layer is preferably used. By using a high-k material for the insulator that functions as a gate insulator, transistors can be miniaturized and highly integrated. In particular, it is preferable to use an insulating material such as aluminum oxide, hafnium oxide, and hafnium aluminate that has a function of suppressing diffusion of impurities and oxygen (the oxygen hardly transmits). In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200.
または、これらの絶縁体に、例えば、酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。またはこれらの絶縁体を窒化処理しても良い。上記の絶縁体に酸化シリコン、酸化窒化シリコンまたは窒化シリコンを積層して用いてもよい。 Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
また、絶縁体２２０は、熱的に安定していることが好ましい。例えば、酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため、ｈｉｇｈ−ｋ材料の絶縁体と組み合わせることで、熱的に安定かつ比誘電率の高い積層構造とすることができる。 The insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a high thermal stability and a high dielectric constant can be obtained by combining with an insulator of a high-k material.
なお、絶縁体２２０、絶縁体２２２、および絶縁体２２４が、２層以上の積層構造を有していてもよい。その場合、同じ材料からなる積層構造に限定されず、異なる材料からなる積層構造でもよい。また、トランジスタ２００で絶縁体２２０、絶縁体２２２、および絶縁体２２４がゲート絶縁体として機能する構成を示したが、本実施の形態はこれに限られるものではない。例えば、ゲート絶縁体として、絶縁体２２０、絶縁体２２２、および絶縁体２２４のいずれか２層または１層を設ける構成にしてもよい。 Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient. Further, although the structure in which the insulator 220, the insulator 222, and the insulator 224 function as gate insulators in the transistor 200 is described, this embodiment is not limited thereto. For example, any two layers or one layer of the insulator 220, the insulator 222, and the insulator 224 may be provided as the gate insulator.
酸化物２３０は、酸化物２３０ａと、酸化物２３０ａ上の酸化物２３０ｂと、酸化物２３０ｂ上の酸化物２３０ｃと、を有する。また、酸化物２３０は、領域２３１、接合領域２３２、および領域２３４を有する。なお、領域２３１の少なくとも一部は、絶縁体２７４と接することが好ましい。また、領域２３１の少なくとも一部は、インジウムなどの金属元素、水素、および窒素の少なくとも一の濃度が領域２３４よりも大きいことが好ましい。 The oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. In addition, the oxide 230 includes a region 231, a bonding region 232, and a region 234. Note that at least part of the region 231 is preferably in contact with the insulator 274. In addition, at least part of the region 231 preferably has a concentration of at least one of a metal element such as indium, hydrogen, and nitrogen higher than that of the region 234.
トランジスタ２００をオンさせると、領域２３１ａ、または領域２３１ｂは、ソース領域、またはドレイン領域として機能する。一方、領域２３４の少なくとも一部は、チャネルが形成される領域として機能する。 When the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least part of the region 234 functions as a region where a channel is formed.
ここで、図２に示すように、酸化物２３０は、接合領域２３２を有することが好ましい。当該構成とすることで、トランジスタ２００において、オン電流を大きくし、かつ、非導通時のリーク電流（オフ電流）を小さくすることができる。 Here, as illustrated in FIG. 2, the oxide 230 preferably includes a junction region 232. With such a structure, in the transistor 200, the on-state current can be increased and the leakage current (off-state current) at the time of non-conduction can be reduced.
また、酸化物２３０ａ上に、酸化物２３０ｂを有することで、酸化物２３０ａよりも下方に形成された構造物から、酸化物２３０ｂに対する不純物の拡散を抑制することができる。また、酸化物２３０ｃ下に、酸化物２３０ｂを有することで、酸化物２３０ｃよりも上方に形成された構造物から、酸化物２３０ｂに対する不純物の拡散を抑制することができる。 Further, by including the oxide 230b over the oxide 230a, diffusion of impurities into the oxide 230b can be suppressed from a structure formed below the oxide 230a. In addition, by including the oxide 230b below the oxide 230c, diffusion of impurities into the oxide 230b can be suppressed from a structure formed above the oxide 230c.
また、酸化物２３０は、その側面と、上面との間に、湾曲面を有する。つまり、側面の端部と上面の端部は、湾曲していることが好ましい（以下、ラウンド状ともいう）。湾曲面は、例えば、酸化物２３０ｂの端部において、曲率半径が、３ｎｍ以上１０ｎｍ以下、好ましくは、５ｎｍ以上６ｎｍ以下とすることが好ましい。 The oxide 230 has a curved surface between the side surface and the upper surface. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm at the end of the oxide 230b.
酸化物２３０は、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう）を用いることが好ましい。例えば、領域２３４となる金属酸化物としては、エネルギーギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上のものを用いることが好ましい。このように、エネルギーギャップの広い金属酸化物を用いることで、トランジスタのオフ電流を低減することができる。 As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, as the metal oxide to be the region 234, an oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.
酸化物半導体を用いたトランジスタは、非導通状態において極めてリーク電流が小さいため、低消費電力の半導体装置が提供できる。また、酸化物半導体は、スパッタリング法などを用いて成膜できるため、高集積型の半導体装置を構成するトランジスタに用いることができる。 Since a transistor including an oxide semiconductor has extremely low leakage current in a non-conduction state, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a transistor included in a highly integrated semiconductor device.
例えば、酸化物２３０として、Ｉｎ−Ｍ−Ｚｎ酸化物（元素Ｍは、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種）等の金属酸化物を用いるとよい。また、酸化物２３０として、Ｉｎ−Ｇａ酸化物、Ｉｎ−Ｚｎ酸化物を用いてもよい。 For example, the oxide 230 includes an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium) It is preferable to use a metal oxide such as neodymium, hafnium, tantalum, tungsten, or magnesium. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.
ここで、酸化物２３０の領域２３４について説明する。 Here, the region 234 of the oxide 230 is described.
領域２３４は、各金属原子の原子数比が異なる酸化物により、積層構造を有することが好ましい。具体的には、酸化物２３０ａ、および酸化物２３０ｂの積層構造を有する場合、酸化物２３０ａに用いる金属酸化物において、構成元素中の元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、構成元素中の元素Ｍの原子数比より、大きいことが好ましい。また、酸化物２３０ａに用いる金属酸化物において、Ｉｎに対する元素Ｍの原子数比が、酸化物２３０ｂに用いる金属酸化物における、Ｉｎに対する元素Ｍの原子数比より大きいことが好ましい。また、酸化物２３０ｂに用いる金属酸化物において、元素Ｍに対するＩｎの原子数比が、酸化物２３０ａに用いる金属酸化物における、元素Ｍに対するＩｎの原子数比より大きいことが好ましい。また、酸化物２３０ｃは、酸化物２３０ａまたは酸化物２３０ｂに用いることができる金属酸化物を、用いることができる。 The region 234 preferably has a stacked structure with oxides having different atomic ratios of metal atoms. Specifically, in the case where the oxide 230a and the oxide 230b have a stacked structure, the metal oxide used for the oxide 230b has an atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. Is larger than the atomic ratio of the element M in the constituent elements. In the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
酸化物２３０ａには、例えばＩｎ：Ｇａ：Ｚｎ＝１：３：４、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２、またはＩｎ：Ｇａ：Ｚｎ＝１：１：１の組成を有する金属酸化物を用いることができる。また、酸化物２３０ｂには、例えばＩｎ：Ｇａ：Ｚｎ＝４：２：３、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、またはＩｎ：Ｇａ：Ｚｎ＝５：１：６の組成を有する金属酸化物を用いることができる。酸化物２３０ｃには、例えばＩｎ：Ｇａ：Ｚｎ＝１：３：４、Ｉｎ：Ｇａ：Ｚｎ＝１：３：２、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３、またはＩｎ：Ｇａ：Ｚｎ＝１：１：１の組成を有する金属酸化物を用いることができる。なお、上記組成は、基板上に形成された酸化物中の原子数比、またはスパッタターゲットにおける原子数比を示す。 The oxide 230a includes, for example, a metal oxide having a composition of In: Ga: Zn = 1: 3: 4, In: Ga: Zn = 1: 3: 2, or In: Ga: Zn = 1: 1: 1. Can be used. The oxide 230b includes a metal having a composition of, for example, In: Ga: Zn = 4: 2: 3, In: Ga: Zn = 1: 1: 1, or In: Ga: Zn = 5: 1: 6. An oxide can be used. For the oxide 230c, for example, In: Ga: Zn = 1: 3: 4, In: Ga: Zn = 1: 3: 2, In: Ga: Zn = 4: 2: 3, or In: Ga: Zn = Metal oxides having a 1: 1: 1 composition can be used. In addition, the said composition shows the atomic ratio in the oxide formed on the board | substrate, or the atomic ratio in a sputtering target.
特に、酸化物２３０ａとしてＩｎ：Ｇａ：Ｚｎ＝１：３：４、酸化物２３０ｂとしてＩｎ：Ｇａ：Ｚｎ＝４：２：３、酸化物２３０ｃとしてＩｎ：Ｇａ：Ｚｎ＝１：３：４の組成を有する金属酸化物を組み合わせると、酸化物２３０ｂを、よりエネルギーギャップの広い酸化物２３０ａと酸化物２３０ｃで挟むことができ、好ましい。この時、エネルギーギャップの広い酸化物２３０ａと酸化物２３０ｃをワイドギャップ、相対的にエネルギーギャップが狭い酸化物２３０ｂをナローギャップと呼ぶことがある。ワイドギャップ、およびナローギャップについては、［金属酸化物の構成］にて説明する。 In particular, In: Ga: Zn = 1: 3: 4 as the oxide 230a, In: Ga: Zn = 4: 2: 3 as the oxide 230b, and In: Ga: Zn = 1: 3: 4 as the oxide 230c. When a metal oxide having a composition is combined, the oxide 230b can be sandwiched between the oxide 230a and the oxide 230c having a wider energy gap, which is preferable. At this time, the oxides 230a and 230c having a wide energy gap may be referred to as a wide gap, and the oxide 230b having a relatively narrow energy gap may be referred to as a narrow gap. The wide gap and the narrow gap will be described in [Configuration of metal oxide].
続いて、酸化物２３０の領域２３１、および接合領域２３２について説明する。 Subsequently, the region 231 of the oxide 230 and the bonding region 232 will be described.
領域２３１、および接合領域２３２は、酸化物２３０として設けられた金属酸化物に、インジウムなどの金属原子、または不純物を添加し、低抵抗化した領域である。なお、各領域は、少なくとも、領域２３４における酸化物２３０ｂよりも、導電性が高い。なお、領域２３１、および接合領域２３２に、不純物を添加するために、例えば、プラズマ処理、イオン化された原料ガスを質量分離して添加するイオン注入法、イオン化された原料ガスを質量分離せずに添加するイオンドーピング法、プラズマイマージョンイオンインプランテーション法などを用いて、インジウムなどの金属元素、および不純物の少なくとも一であるドーパントを添加すればよい。 The region 231 and the junction region 232 are regions in which a metal atom provided as the oxide 230 is added with a metal atom such as indium or an impurity to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234. Note that in order to add impurities to the region 231 and the junction region 232, for example, plasma treatment, an ion implantation method in which an ionized source gas is added by mass separation, and an ionized source gas without mass separation. A dopant which is at least one of a metal element such as indium and an impurity may be added by an ion doping method, a plasma immersion ion implantation method, or the like.
つまり、領域２３１、および接合領域２３２において、酸化物２３０のインジウムなどの金属原子の含有率を高くすることで、電子移動度を高くし、低抵抗化を図ることができる。 That is, in the region 231 and the junction region 232, by increasing the content of metal atoms such as indium in the oxide 230, electron mobility can be increased and resistance can be reduced.
または、酸化物２３０に接して、不純物となる元素を含む絶縁体２７４を成膜することで、領域２３１、および接合領域２３２に、不純物を添加することができる。 Alternatively, the insulator 274 containing an element serving as an impurity can be formed in contact with the oxide 230, whereby the impurity can be added to the region 231 and the junction region 232.
つまり、領域２３１、および接合領域２３２は、酸素欠損を形成する元素、または酸素欠損に捕獲される元素を添加されることで低抵抗化される。このような元素としては、代表的には水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が挙げられる。また、希ガス元素の代表例としては、ヘリウム、ネオン、アルゴン、クリプトン、及びキセノン等がある。よって、領域２３１、および接合領域２３２は、上記元素の一つまたは複数を含む構成にすればよい。 That is, the resistance of the region 231 and the junction region 232 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 and the bonding region 232 may have a structure including one or more of the above elements.
または、絶縁体２７４として、領域２３１、および接合領域２３２に含まれる酸素を引き抜き、吸収する膜を用いてもよい。酸素が引き抜かれると、領域２３１、および接合領域２３２には酸素欠損が生じる。酸素欠損に水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が捕獲されることにより、領域２３１、および接合領域２３２は低抵抗化する。 Alternatively, as the insulator 274, a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used. When oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232. When hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
また、トランジスタ２００において、接合領域２３２を設けることで、ソース領域およびドレイン領域として機能する領域２３１と、チャネルが形成される領域２３４との間に高抵抗領域が形成されないため、トランジスタのオン電流、および移動度を大きくすることができる。また、接合領域２３２を有することで、チャネル長方向において、ソース領域およびドレイン領域と、ゲートとが重ならないため、不要な容量が形成されるのを抑制することができる。また、接合領域２３２有することで、非導通時のリーク電流を小さくすることができる。 In the transistor 200, since the junction region 232 is provided, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; And mobility can be increased. In addition, since the junction region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, since the junction region 232 is provided, leakage current at the time of non-conduction can be reduced.
従って、接合領域２３２の範囲を適宜選択することにより、回路設計に合わせて、要求に見合う電気特性を有するトランジスタを容易に提供することができる。 Therefore, by appropriately selecting the range of the junction region 232, a transistor having electrical characteristics that meet requirements can be easily provided in accordance with circuit design.
絶縁体２５０は、ゲート絶縁膜として機能する。絶縁体２５０は、酸化物２３０ｃの上面に接して配置することが好ましい。絶縁体２５０は、加熱により酸素が放出される絶縁体を用いて形成することが好ましい。例えば、昇温脱離ガス分光法分析（ＴＤＳ分析）にて、酸素原子に換算しての酸素の脱離量が１．０×１０１８ａｔｏｍｓ／ｃｍ３以上、好ましくは３．０×１０２０ａｔｏｍｓ／ｃｍ３以上である酸化物膜である。なお、上記ＴＤＳ分析時における膜の表面温度としては１００℃以上７００℃以下、または１００℃以上５００℃以下の範囲が好ましい。 The insulator 250 functions as a gate insulating film. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in the temperature-programmed desorption gas spectroscopy analysis (TDS analysis), the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 18 atoms / cm 3 or more, preferably 3.0 × 10 20. An oxide film having atoms / cm 3 or more. The surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
加熱により酸素が放出される絶縁体を、絶縁体２５０として、酸化物２３０ｃの上面に接して設けることにより、酸化物２３０ｂの領域２３４に効果的に酸素を供給することができる。また、絶縁体２２４と同様に、絶縁体２５０中の水または水素などの不純物濃度が低減されていることが好ましい。絶縁体２５０の膜厚は、１ｎｍ以上２０ｎｍ以下とするのが好ましい。 By providing the insulator from which oxygen is released by heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
第１のゲート電極として機能する導電体２６０は、導電体２６０ａ、および導電体２６０ａ上の導電体２６０ｂを有する。 The conductor 260 functioning as the first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a.
導電体２６０ａは、窒化チタンなどを用いることが好ましい。また、導電体２６０ｂとして、例えばタングステンなどの、導電性が高い金属を用いることができる。 As the conductor 260a, titanium nitride or the like is preferably used. In addition, as the conductor 260b, a metal having high conductivity such as tungsten can be used.
また、絶縁体２５０と導電体２６０ａの間に、導電性酸化物からなる導電体を設けてもよい。例えば、酸化物２３０ａまたは酸化物２３０ｂとして用いることができる金属酸化物を用いることができる。特に、Ｉｎ−Ｇａ−Ｚｎ系酸化物のうち、導電性が高い、金属の原子数比が［Ｉｎ］：［Ｇａ］：［Ｚｎ］＝４：２：３から４．１、およびその近傍値のものを用いることが好ましい。このような導電体を絶縁体２５０上に設けることで、導電体２６０ａへの酸素の透過を抑制し、酸化によって導電体２６０ａの電気抵抗値が増加することを防ぐことができる。 Further, a conductor made of a conductive oxide may be provided between the insulator 250 and the conductor 260a. For example, a metal oxide that can be used as the oxide 230a or the oxide 230b can be used. In particular, among In—Ga—Zn-based oxides, the metal atomic ratio is high from [In]: [Ga]: [Zn] = 4: 2: 3 to 4.1, and the vicinity thereof. It is preferable to use those. By providing such a conductor over the insulator 250, transmission of oxygen to the conductor 260a can be suppressed, and an increase in the electrical resistance value of the conductor 260a due to oxidation can be prevented.
また、上記導電性酸化物を、スパッタリング法を用いて成膜することで、絶縁体２５０に酸素を添加し、酸化物２３０ｂに酸素を供給することが可能となる。これにより、酸化物２３０の領域２３４の酸素欠損を低減することができる。 Further, when the conductive oxide is formed by a sputtering method, oxygen can be added to the insulator 250 and oxygen can be supplied to the oxide 230b. Accordingly, oxygen vacancies in the region 234 of the oxide 230 can be reduced.
また、導電体２６０ｂの上に、バリア膜として機能する絶縁体２７０を配置してもよい。絶縁体２７０は、水または水素などの不純物、および酸素の透過を抑制する機能を有する絶縁性材料を用いるとよい。例えば、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体を用いることができる。アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。これにより、導電体２６０の酸化を防ぐことができる。また、導電体２６０および絶縁体２５０を介して、水または水素などの不純物が酸化物２３０に混入することを防ぐことができる。 Further, the insulator 270 functioning as a barrier film may be provided over the conductor 260b. As the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, an insulator including one or both of aluminum and hafnium can be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Thereby, oxidation of the conductor 260 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
また、絶縁体２７０上に、ハードマスクとして機能する絶縁体２７１を配置することが好ましい。絶縁体２７１を設けることで、導電体２６０の加工の際、導電体２６０の側面が概略垂直、具体的には、導電体２６０の側面と基板表面のなす角を、７５度以上１００度以下、好ましくは８０度以上９５度以下とすることができる。導電体をこのような形状に加工することで、次に形成する絶縁体２７２を所望の形状に形成することができる。 Further, the insulator 271 functioning as a hard mask is preferably provided over the insulator 270. By providing the insulator 271, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, it can be set to 80 degrees or more and 95 degrees or less. By processing the conductor into such a shape, the insulator 272 to be formed next can be formed into a desired shape.
また、バリア膜として機能する絶縁体２７２を、絶縁体２５０、導電体２６０、および絶縁体２７０の側面に接して設ける。 An insulator 272 functioning as a barrier film is provided in contact with the side surfaces of the insulator 250, the conductor 260, and the insulator 270.
ここで、絶縁体２７２は、水または水素などの不純物、および酸素の透過を抑制する機能を有する絶縁性材料を用いるとよい。例えば、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体を用いることができる。アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。これにより、絶縁体２５０中の酸素が外部に拡散することを防ぐことができる。また、絶縁体２５０の端部などから酸化物２３０に水素、水などの不純物が混入するのを抑制することができる。 Here, the insulator 272 may be formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, an insulator including one or both of aluminum and hafnium can be used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Thereby, oxygen in the insulator 250 can be prevented from diffusing outside. Further, entry of impurities such as hydrogen and water into the oxide 230 from an end portion of the insulator 250 or the like can be suppressed.
絶縁体２７０、および絶縁体２７２を設けることで、水または水素などの不純物、および酸素の透過を抑制する機能を有する絶縁体で導電体２６０の上面と側面および絶縁体２５０の側面を覆うことができる。これにより、導電体２６０および絶縁体２５０を介して、水または水素などの不純物が酸化物２３０に混入することを防ぐことができる。従って、絶縁体２７２は、ゲート電極およびゲート絶縁膜の側面を保護するサイドバリアとしての機能を有する。 By providing the insulator 270 and the insulator 272, an upper surface and a side surface of the conductor 260 and a side surface of the insulator 250 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. it can. Thus, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250. Therefore, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.
また、トランジスタが微細化され、チャネル長が１０ｎｍ以上３０ｎｍ以下程度に形成されている場合、トランジスタ２００の周辺に設けられる構造体に含まれる不純物元素が拡散し、領域２３１ａと領域２３１ｂ、あるいは、接合領域２３２ａと接合領域２３２ｂと、が電気的に導通する恐れがある。 In the case where the transistor is miniaturized and the channel length is 10 nm or more and 30 nm or less, the impurity element contained in the structure provided around the transistor 200 is diffused, so that the region 231a and the region 231b or the junction is formed. There is a possibility that the region 232a and the bonding region 232b are electrically connected.
そこで、本実施の形態に示すように、絶縁体２７２を形成することにより、絶縁体２５０および導電体２６０に水素、水などの不純物が混入するのを抑制し、かつ、絶縁体２５０中の酸素が外部に拡散することを防ぐことができる。従って、第１のゲート電圧が０Ｖのときに、ソース領域とドレイン領域が直接、あるいは接合領域２３２などを介して電気的に導通することを防ぐことができる。 Thus, as shown in this embodiment, by forming the insulator 272, impurities such as hydrogen and water can be prevented from entering the insulator 250 and the conductor 260, and oxygen in the insulator 250 can be reduced. Can be prevented from spreading outside. Therefore, when the first gate voltage is 0 V, the source region and the drain region can be prevented from being electrically connected directly or via the junction region 232 or the like.
絶縁体２７４は、絶縁体２７１、絶縁体２７２、酸化物２３０および絶縁体２２４などを覆って設ける。 The insulator 274 is provided to cover the insulator 271, the insulator 272, the oxide 230, the insulator 224, and the like.
また、絶縁体２７４は、水または水素などの不純物、および酸素の透過を抑制する機能を有する絶縁性材料を用いることが好ましい。例えば、絶縁体２７４として、窒化シリコン、窒化酸化シリコン、酸化窒化シリコン、窒化アルミニウム、窒化酸化アルミニウムなどを用いることが好ましい。このような絶縁体２７４を形成することで、絶縁体２７４を透過して酸素が混入し、領域２３１ａおよび領域２３１ｂの酸素欠損に酸素を供給して、キャリア密度が低下するのを防ぐことができる。また、絶縁体２７４を透過して水または水素などの不純物が混入し、領域２３１ａおよび領域２３１ｂが過剰に領域２３４側に拡張するのを防ぐことができる。 The insulator 274 is preferably formed using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, the insulator 274 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like. By forming such an insulator 274, oxygen can be prevented from being transmitted through the insulator 274 and supplying oxygen to oxygen vacancies in the regions 231 a and 231 b, thereby reducing the carrier density. . Further, it is possible to prevent the region 231a and the region 231b from being excessively expanded to the region 234 side by being mixed with impurities such as water or hydrogen through the insulator 274.
なお、絶縁体２７４を成膜することにより、領域２３１、および接合領域２３２を設ける場合、絶縁体２７４は、酸化物２３０内に酸素欠損を形成する元素、または酸化物２３０中の酸素欠損に捕獲される元素を有することが好ましい。このような元素としては、代表的には水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が挙げられる。また、希ガス元素の代表例としては、ヘリウム、ネオン、アルゴン、クリプトン、及びキセノン等がある。このような元素を有する絶縁体を絶縁体２７４に用いることで、当該元素を酸化物２３０に添加して、酸化物２３０において、領域２３１、および接合領域２３２を形成することができる。 Note that in the case where the region 231 and the junction region 232 are provided by forming the insulator 274, the insulator 274 is trapped by an element that forms an oxygen vacancy in the oxide 230 or an oxygen vacancy in the oxide 230. It is preferable to have an element to be used. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. By using an insulator including such an element for the insulator 274, the element 231 and the bonding region 232 can be formed in the oxide 230 by adding the element to the oxide 230.
または、絶縁体２７４として、領域２３１、および接合領域２３２に含まれる酸素を引き抜き、吸収する膜を用いてもよい。酸素が引き抜かれると、領域２３１、および接合領域２３２には酸素欠損が生じる。酸素欠損に水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が捕獲されることにより、領域２３１、および接合領域２３２は低抵抗化する。 Alternatively, as the insulator 274, a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used. When oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232. When hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
絶縁体２７４の上に、層間膜として機能する絶縁体２８０を設けることが好ましい。絶縁体２８０は、絶縁体２２４などと同様に、膜中の水または水素などの不純物濃度が低減されていることが好ましい。なお、絶縁体２８０は、同様の絶縁体からなる積層構造としてもよい。 An insulator 280 that functions as an interlayer film is preferably provided over the insulator 274. As in the case of the insulator 224, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that the insulator 280 may have a stacked structure including similar insulators.
次に、トランジスタ２００と電気的に接続する導電体２５２（導電体２５２１、導電体２５２２、導電体２５２３、および導電体２５２４）を設ける。絶縁体２８０および絶縁体２７４に形成された開口に、酸化物２３０と電気的に接続する導電体２５２１、および導電体２５２２を配置し、絶縁体２８０、絶縁体２７４、絶縁体２７１、および絶縁体２７０に形成された開口に、第１のゲートとして機能する導電体２６０と電気的に接続する導電体２５２３を配置し、絶縁体２８０、絶縁体２７４、絶縁体２２４、絶縁体２２２、および絶縁体２２０に形成された開口に、第２のゲートとして機能する導電体２０５と電気的に接続する導電体２５２４を配置する。なお、導電体２５２１、導電体２５２２、導電体２５２３、および導電体２５２４の上面の高さは、絶縁体２８０の上面と、同一平面上としてもよい。 Next, a conductor 252 (a conductor 2521, a conductor 2522, a conductor 2523, and a conductor 2524) that is electrically connected to the transistor 200 is provided. A conductor 2521 and a conductor 2522 that are electrically connected to the oxide 230 are provided in openings formed in the insulator 280 and the insulator 274, and the insulator 280, the insulator 274, the insulator 271, and the insulator A conductor 2523 electrically connected to the conductor 260 functioning as the first gate is provided in the opening formed in the 270, and the insulator 280, the insulator 274, the insulator 224, the insulator 222, and the insulator A conductor 2524 electrically connected to the conductor 205 functioning as the second gate is disposed in the opening formed in 220. Note that the top surfaces of the conductor 2521, the conductor 2522, the conductor 2523, and the conductor 2524 may be flush with the top surface of the insulator 280.
なお、導電体２５２は、ダマシン法を用いて形成することができる。 Note that the conductor 252 can be formed by a damascene method.
また、導電体２５２１は、トランジスタ２００のソース領域およびドレイン領域の一方として機能する領域２３１ａと接しており、導電体２５２２はトランジスタ２００のソース領域およびドレイン領域の他方として機能する領域２３１ｂと接している。領域２３１ａおよび領域２３１ｂは低抵抗化されているので、導電体２５２１と領域２３１ａの接触抵抗、および導電体２５２２領域２３１ｂの接触抵抗を低減し、トランジスタ２００のオン電流を大きくすることができる。 The conductor 2521 is in contact with the region 231a functioning as one of the source region and the drain region of the transistor 200, and the conductor 2522 is in contact with the region 231b functioning as the other of the source region and the drain region of the transistor 200. . Since the region 231a and the region 231b have low resistance, the contact resistance between the conductor 2521 and the region 231a and the contact resistance between the conductor 2522 region 231b can be reduced and the on-state current of the transistor 200 can be increased.
ここで、図１（Ｄ）に示すように、導電体２５２２（導電体２５２１）は、少なくとも酸化物２３０の上面と接し、さらに酸化物２３０の側面と接することが好ましい。特に、導電体２５２２（導電体２５２１）は、酸化物２３０のチャネル幅方向と交わる側面において、Ｃ側の側面、およびＤ側の側面の双方または一方と接することが好ましい。また、導電体２５２２（導電体２５２１）が、酸化物２３０のチャネル長方向と交わる側面において、Ａ側（Ｂ側）の側面と接する構成にしてもよい。このように、導電体２５２２（導電体２５２１）が酸化物２３０の上面に加えて、酸化物２３０の側面と接する構成にすることにより、導電体２５２２（導電体２５２１）と酸化物２３０のコンタクト部の上面積を増やすことなく、コンタクト部の接触面積を増加させ、導電体２５２２（導電体２５２１）と酸化物２３０の接触抵抗を低減することができる。これにより、トランジスタのソース電極およびドレイン電極の微細化を図りつつ、オン電流を大きくすることができる。 Here, as illustrated in FIG. 1D, the conductor 2522 (conductor 2521) is preferably in contact with at least the upper surface of the oxide 230 and further in contact with the side surface of the oxide 230. In particular, the conductor 2522 (the conductor 2521) is preferably in contact with both or one of the side surface on the C side and the side surface on the D side on the side surface intersecting the channel width direction of the oxide 230. Alternatively, the conductor 2522 (conductor 2521) may be in contact with the side surface on the A side (B side) on the side surface intersecting the channel length direction of the oxide 230. In this manner, the conductor 2522 (conductor 2521) is in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230, whereby the contact portion between the conductor 2522 (conductor 2521) and the oxide 230 is formed. Without increasing the upper area, the contact area of the contact portion can be increased, and the contact resistance between the conductor 2522 (conductor 2521) and the oxide 230 can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
導電体２５２は、それぞれの開口の内壁に接して導電体２５２ａが形成され、さらに内側に導電体２５２ｂが形成されている。また、導電体２５２ａの内壁に接し、かつ導電体２５２ｂの上面に接するように導電体２５２ｃが形成され、導電体２５２ｃの内側に導電体２５２ｄが形成されている。ここで、導電体２５２ａ、導電体２５２ｃ、および導電体２０５ｄの上面の高さと、絶縁体２８０の上面の高さは同程度にできる。 In the conductor 252, a conductor 252 a is formed in contact with the inner wall of each opening, and a conductor 252 b is formed further inside. In addition, a conductor 252c is formed so as to be in contact with an inner wall of the conductor 252a and in contact with an upper surface of the conductor 252b, and a conductor 252d is formed inside the conductor 252c. Here, the heights of the top surfaces of the conductor 252a, the conductor 252c, and the conductor 205d can be approximately the same as the height of the top surface of the insulator 280.
導電体２５２ａ、および導電体２５２ｃとしては、導電体２０５ａ、導電体２０５ｂ、および導電体２０５ｄと同様の材料を用いることが好ましい。すなわち、導電性バリア膜を用いることが好ましい。また、導電体２５２ｂ、および導電体２５２ｄとしては、導電体２０５ｃ、および導電体２０５ｅと同様の材料を用いることができる。 As the conductor 252a and the conductor 252c, the same material as the conductor 205a, the conductor 205b, and the conductor 205d is preferably used. That is, it is preferable to use a conductive barrier film. For the conductor 252b and the conductor 252d, the same material as the conductor 205c and the conductor 205e can be used.
導電体２５２は、それぞれの開口内部において、導電体２５２ａおよび導電体２５２ｃが設けられている。すなわち、導電性バリアとして機能する導電体が２層設けられている。導電性バリアを２層構造とすることで、絶縁体２８０中の不純物、あるいは以降の工程により生じる不純物が導電体２５２中を通って、トランジスタ２００へ混入することを、より効果的に抑制することができる。また、導電体２５２ｃは、外側の側面が導電体２５２ａの内側の側面と接するように設けられており、不純物混入の抑制効果が向上する。 The conductor 252 is provided with a conductor 252a and a conductor 252c inside each opening. That is, two conductors functioning as a conductive barrier are provided. With the conductive barrier having a two-layer structure, it is possible to more effectively suppress impurities in the insulator 280 or impurities generated in the subsequent steps from entering the transistor 200 through the conductor 252. Can do. In addition, the conductor 252c is provided such that the outer side surface is in contact with the inner side surface of the conductor 252a, so that the effect of suppressing impurity contamination is improved.
また、導電体２５２が埋め込まれた絶縁体２７４および絶縁体２８０の開口の内壁に接して、水または水素などの不純物の透過を抑制する機能を有する絶縁体が設けられる構成にしてもよい。このような絶縁体としては、絶縁体２７０や絶縁体２７２に用いることができる絶縁体、例えば、酸化アルミニウムなどを用いることが好ましい。これにより、絶縁体２８０などから水素、水などの不純物が、導電体２５２を通じて酸化物２３０に混入するのを抑制することができる。また、当該絶縁体は、例えばＡＬＤ法またはＣＶＤ法などを用いて成膜することで被覆性良く成膜することができる。 Alternatively, an insulator having a function of suppressing transmission of impurities such as water or hydrogen may be provided in contact with the inner walls of the openings of the insulator 274 and the insulator 280 in which the conductor 252 is embedded. As such an insulator, an insulator that can be used for the insulator 270 and the insulator 272, for example, aluminum oxide is preferably used. Accordingly, impurities such as hydrogen and water from the insulator 280 and the like can be prevented from entering the oxide 230 through the conductor 252. Further, the insulator can be formed with good coverage by forming the insulator using, for example, an ALD method or a CVD method.
また、導電体２５２の上面に接して配線として機能する導電体２５６を配置してもよい。配線として機能する導電体２５６は、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。 Alternatively, the conductor 256 functioning as a wiring may be provided in contact with the upper surface of the conductor 252. The conductor 256 functioning as a wiring is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
なお、本実施の形態では、導電体２０５および導電体２５２において、導電性バリア膜を複数設ける構成について説明したが、これに限らない。半導体装置において必要とされる特性や仕様に応じて、導電体２０５および導電体２５２の少なくとも一方において、導電性バリア膜を複数設ける構成とすればよい。 Note that although a structure in which a plurality of conductive barrier films are provided in the conductor 205 and the conductor 252 has been described in this embodiment, the present invention is not limited thereto. A plurality of conductive barrier films may be provided in at least one of the conductor 205 and the conductor 252 in accordance with characteristics and specifications required for the semiconductor device.
＜半導体装置の構成材料＞
以下では、半導体装置に用いることができる構成材料について説明する。 <Constituent materials for semiconductor devices>
Hereinafter, constituent materials that can be used for the semiconductor device will be described.
＜＜基板＞＞
トランジスタ２００を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 << Board >>
As a substrate over which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
また、基板として、可とう性基板を用いてもよい。なお、可とう性基板上にトランジスタを設ける方法としては、非可とう性の基板上にトランジスタを作製した後、トランジスタを剥離し、可とう性基板である基板に転置する方法もある。その場合には、非可とう性基板とトランジスタとの間に剥離層を設けるとよい。また、基板が伸縮性を有してもよい。また、基板は、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有してもよい。または、元の形状に戻らない性質を有してもよい。基板は、例えば、５μｍ以上７００μｍ以下、好ましくは１０μｍ以上５００μｍ以下、さらに好ましくは１５μｍ以上３００μｍ以下の厚さとなる領域を有する。基板を薄くすると、トランジスタを有する半導体装置を軽量化することができる。また、基板を薄くすることで、ガラスなどを用いた場合にも伸縮性を有する場合や、折り曲げや引っ張りをやめた際に、元の形状に戻る性質を有する場合がある。そのため、落下などによって基板上の半導体装置に加わる衝撃などを緩和することができる。即ち、丈夫な半導体装置を提供することができる。 A flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.
可とう性基板である基板としては、例えば、金属、合金、樹脂もしくはガラス、またはそれらの繊維などを用いることができる。また、基板として、繊維を編みこんだシート、フィルムまたは箔などを用いてもよい。可とう性基板である基板は、線膨張率が低いほど環境による変形が抑制されて好ましい。可とう性基板である基板としては、例えば、線膨張率が１×１０−３／Ｋ以下、５×１０−５／Ｋ以下、または１×１０−５／Ｋ以下である材質を用いればよい。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネート、アクリルなどがある。特に、アラミドは、線膨張率が低いため、可とう性基板である基板として好適である。 As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. Further, as the substrate, a sheet woven with fibers, a film, a foil, or the like may be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 −3 / K or less, 5 × 10 −5 / K or less, or 1 × 10 −5 / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.
＜＜絶縁体＞＞
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。 << Insulator >>
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.
ここで、ゲート絶縁体として機能する絶縁体には、ゲート絶縁体として機能する絶縁体に、比誘電率の高いｈｉｇｈ−ｋ材料を用いることで、トランジスタの微細化、および高集積化が可能となる。一方、層間膜として機能する絶縁体には、比誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。従って、絶縁体の機能に応じて、材料を選択するとよい。 Here, for the insulator that functions as a gate insulator, a high-k material having a high relative dielectric constant is used for the insulator that functions as a gate insulator, so that transistors can be miniaturized and highly integrated. Become. On the other hand, for an insulator functioning as an interlayer film, a parasitic capacitance generated between wirings can be reduced by using a material having a low relative dielectric constant as an interlayer film. Therefore, the material may be selected according to the function of the insulator.
また、比誘電率の高い絶縁体としては、酸化アルミニウム、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物またはシリコンおよびハフニウムを有する窒化物などがある。 Insulators having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium-containing oxides, aluminum and hafnium-containing oxynitrides, silicon and hafnium-containing oxides, silicon And oxynitride having hafnium or nitride having silicon and hafnium.
また、比誘電率が低い絶縁体としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンまたは樹脂などがある。 Insulators having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, Examples include silicon oxide or resin having holes.
また、特に、酸化シリコンおよび酸化窒化シリコンは、熱的に安定である。そのため、例えば、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネートまたはアクリルなどがある。また、例えば、酸化シリコン、および酸化窒化シリコンは、比誘電率の高い絶縁体と組み合わせることで、熱的に安定かつ比誘電率の高い積層構造とすることができる。 In particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, a laminated structure having a thermally stable and low relative dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high relative dielectric constant to provide a thermally stable and high stacked dielectric structure.
また、酸化物半導体を用いたトランジスタは、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体で囲うことによって、トランジスタの電気特性を安定にすることができる。 In addition, a transistor including an oxide semiconductor can be stabilized in electrical characteristics of the transistor by being surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen.
水素などの不純物および酸素の透過を抑制する機能を有する絶縁体としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体として、酸化アルミニウム、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いることができる。 Examples of the insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
例えば、絶縁体２２２、および絶縁体２１０として、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体を用いればよい。なお、絶縁体２２２、および絶縁体２１０は、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体を用いることができる。アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。 For example, as the insulator 222 and the insulator 210, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Note that the insulator 222 and the insulator 210 can be formed using an insulator containing one or both of aluminum and hafnium. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.
絶縁体２２０、絶縁体２２４、絶縁体２５０、および絶縁体２７１、としては、例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁体を、単層で、または積層で用いればよい。具体的には、酸化シリコン、酸化窒化シリコンまたは、窒化シリコンを有することが好ましい。 Examples of the insulator 220, the insulator 224, the insulator 250, and the insulator 271 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, An insulator containing zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. Specifically, silicon oxide, silicon oxynitride, or silicon nitride is preferably included.
例えば、ゲート絶縁体として機能する絶縁体２２４および絶縁体２５０において、酸化アルミニウム、酸化ガリウム、ハフニウムアルミネート、または酸化ハフニウムを酸化物２３０と接する構造とすることで、酸化シリコンまたは酸化窒化シリコンに含まれるシリコンが、酸化物２３０に混入することを抑制することができる。一方、絶縁体２２４および絶縁体２５０において、酸化シリコンまたは酸化窒化シリコンを酸化物２３０と接する構造とすることで、酸化アルミニウム、酸化ガリウム、ハフニウムアルミネート、または酸化ハフニウムと、酸化シリコンまたは酸化窒化シリコンと、の界面にトラップセンターが形成される場合がある。該トラップセンターは、電子を捕獲することでトランジスタのしきい値電圧をプラス方向に変動させることができる場合がある。 For example, the insulator 224 and the insulator 250 that function as gate insulators have a structure in which aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide is in contact with the oxide 230, so that silicon oxide or silicon oxynitride is included. It is possible to prevent silicon to be mixed into the oxide 230. On the other hand, in the insulator 224 and the insulator 250, by using silicon oxide or silicon oxynitride in contact with the oxide 230, aluminum oxide, gallium oxide, hafnium aluminate, or hafnium oxide, and silicon oxide or silicon oxynitride In some cases, a trap center is formed at the interface. In some cases, the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.
絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０は、比誘電率の低い絶縁体を有することが好ましい。例えば、絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコンまたは樹脂などを有することが好ましい。または、絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコンまたは空孔を有する酸化シリコンと、樹脂と、の積層構造を有することが好ましい。酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため、樹脂と組み合わせることで、熱的に安定かつ比誘電率の低い積層構造とすることができる。樹脂としては、例えば、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミドなど）、ポリイミド、ポリカーボネートまたはアクリルなどがある。 The insulator 208, the insulator 212, the insulator 216, and the insulator 280 preferably include an insulator with a low relative dielectric constant. For example, the insulator 208, the insulator 212, the insulator 216, and the insulator 280 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon, and It is preferable to include silicon oxide to which nitrogen is added, silicon oxide having holes, or a resin. Alternatively, the insulator 208, the insulator 212, the insulator 216, and the insulator 280 are formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon, and the like. It is preferable to have a stacked structure of silicon oxide to which nitrogen is added or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
絶縁体２７０、および絶縁体２７２としては、水素などの不純物および酸素の透過を抑制する機能を有する絶縁体を用いればよい。絶縁体２７０および絶縁体２７２としては、例えば、酸化アルミニウム、酸化ハフニウム、ハフニウムアルミネート、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いればよい。 As the insulator 270 and the insulator 272, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulator 270 and the insulator 272 include metal oxides such as aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide. Silicon nitride oxide, silicon nitride, or the like may be used.
＜＜導電体＞＞
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 << Conductor >>
As the conductor, a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
また、上記の材料で形成される導電層を複数積層して用いてもよい。例えば、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、酸素を含む導電性材料と、窒素を含む導電性材料と、を組み合わせた積層構造としてもよい。 A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.
なお、トランジスタのチャネル形成領域に酸化物を用いる場合において、ゲート電極として機能する導電体には、前述した金属元素を含む材料と、酸素を含む導電性材料と、を組み合わせた積層構造を用いることが好ましい。この場合は、酸素を含む導電性材料をチャネル形成領域側に設けるとよい。酸素を含む導電性材料をチャネル形成領域側に設けることで、当該導電性材料から離脱した酸素がチャネル形成領域に供給されやすくなる。 Note that in the case where an oxide is used for a channel formation region of the transistor, the conductor functioning as the gate electrode has a stacked structure in which the above-described material containing a metal element and the conductive material containing oxygen are combined. Is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.
特に、ゲート電極として機能する導電体として、チャネルが形成される金属酸化物に含まれる金属元素および酸素を含む導電性材料を用いることが好ましい。また、前述した金属元素および窒素を含む導電性材料を用いてもよい。例えば、窒化チタン、窒化タンタルなどの窒素を含む導電性材料を用いてもよい。また、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、シリコンを添加したインジウム錫酸化物を用いてもよい。また、窒素を含むインジウムガリウム亜鉛酸化物を用いてもよい。このような材料を用いることで、チャネルが形成される金属酸化物に含まれる水素を捕獲することができる場合がある。または、外方の絶縁体などから混入する水素を捕獲することができる場合がある。 In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as the conductor functioning as a gate electrode. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen mixed from an external insulator or the like may be captured.
導電体２６０、導電体２０５、導電体２０３、導電体２５２、および導電体２５６としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を１種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。 As the conductor 260, the conductor 205, the conductor 203, the conductor 252, and the conductor 256, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium A material containing one or more metal elements selected from manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
＜＜金属酸化物＞＞
酸化物２３０として、酸化物半導体として機能する金属酸化物（以下、酸化物半導体ともいう）を用いることが好ましい。以下では、本発明に係る酸化物２３０に適用可能な金属酸化物について説明する。 << Metal oxide >>
As the oxide 230, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. Below, the metal oxide applicable to the oxide 230 which concerns on this invention is demonstrated.
酸化物半導体は、少なくともインジウムまたは亜鉛を含むことが好ましい。特にインジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウムまたはスズなどが含まれていることが好ましい。また、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。 The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.
ここでは、酸化物半導体が、インジウム、元素Ｍおよび亜鉛を有するＩｎ‐Ｍ‐Ｚｎ酸化物である場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウムまたはスズなどとする。そのほかの元素Ｍに適用可能な元素としては、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.
なお、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 Note that in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.
［金属酸化物の構成］
以下では、本発明の一態様で開示されるトランジスタに用いることができるＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ）−ＯＳの構成について説明する。 [Composition of metal oxide]
A structure of a CAC (Cloud-Aligned Composite) -OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.
なお、本明細書等において、ＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌ）、及びＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ）と記載する場合がある。なお、ＣＡＡＣは結晶構造の一例を表し、ＣＡＣは機能、または材料の構成の一例を表す。 In addition, in this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.
ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅとは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。なお、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅを、トランジスタの活性層に用いる場合、導電性の機能は、キャリアとなる電子（またはホール）を流す機能であり、絶縁性の機能は、キャリアとなる電子を流さない機能である。導電性の機能と、絶縁性の機能とを、それぞれ相補的に作用させることで、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅに付与することができる。ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、それぞれの機能を分離させることで、双方の機能を最大限に高めることができる。 CAC-OS or CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material has a function as a semiconductor. Note that in the case where CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、導電性領域、及び絶縁性領域を有する。導電性領域は、上述の導電性の機能を有し、絶縁性領域は、上述の絶縁性の機能を有する。また、材料中において、導電性領域と、絶縁性領域とは、ナノ粒子レベルで分離している場合がある。また、導電性領域と、絶縁性領域とは、それぞれ材料中に偏在する場合がある。また、導電性領域は、周辺がぼけてクラウド状に連結して観察される場合がある。 In addition, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、導電性領域と、絶縁性領域とは、それぞれ０．５ｎｍ以上１０ｎｍ以下、好ましくは０．５ｎｍ以上３ｎｍ以下のサイズで材料中に分散している場合がある。 In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、異なるバンドギャップを有する成分により構成される。例えば、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、絶縁性領域に起因するワイドギャップを有する成分と、導電性領域に起因するナローギャップを有する成分と、により構成される。当該構成の場合、キャリアを流す際に、ナローギャップを有する成分において、主にキャリアが流れる。また、ナローギャップを有する成分が、ワイドギャップを有する成分に相補的に作用し、ナローギャップを有する成分に連動してワイドギャップを有する成分にもキャリアが流れる。このため、上記ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅをトランジスタのチャネル領域に用いる場合、トランジスタのオン状態において高い電流駆動力、つまり大きなオン電流、及び高い電界効果移動度を得ることができる。 Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
すなわち、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、マトリックス複合材（ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）、または金属マトリックス複合材（ｍｅｔａｌ　ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）と呼称することもできる。 That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
［金属酸化物の構造］
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、ＣＡＡＣ−ＯＳ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶酸化物半導体、ｎｃ−ＯＳ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）および非晶質酸化物半導体などがある。 [Structure of metal oxide]
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), and a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor). OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
ＣＡＡＣ−ＯＳは、ｃ軸配向性を有し、かつａ−ｂ面方向において複数のナノ結晶が連結し、歪みを有した結晶構造となっている。なお、歪みとは、複数のナノ結晶が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。 The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.
ナノ結晶は、六角形を基本とするが、正六角形状とは限らず、非正六角形状である場合がある。また、歪みにおいて、五角形、および七角形などの格子配列を有する場合がある。なお、ＣＡＡＣ−ＯＳにおいて、歪み近傍においても、明確な結晶粒界（グレインバウンダリーともいう）を確認することはできない。即ち、格子配列の歪みによって、結晶粒界の形成が抑制されていることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において酸素原子の配列が稠密でないことや、金属元素が置換することで原子間の結合距離が変化することなどによって、歪みを許容することができるためと考えられる。 Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.
また、ＣＡＡＣ−ＯＳは、インジウム、および酸素を有する層（以下、Ｉｎ層）と、元素Ｍ、亜鉛、および酸素を有する層（以下、（Ｍ，Ｚｎ）層）とが積層した、層状の結晶構造（層状構造ともいう）を有する傾向がある。なお、インジウムと元素Ｍは、互いに置換可能であり、（Ｍ，Ｚｎ）層の元素Ｍがインジウムと置換した場合、（Ｉｎ，Ｍ，Ｚｎ）層と表すこともできる。また、Ｉｎ層のインジウムが元素Ｍと置換した場合、（Ｉｎ，Ｍ）層と表すこともできる。 The CAAC-OS includes a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer including elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. There is a tendency to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.
ＣＡＡＣ−ＯＳは結晶性の高い酸化物半導体である。一方、ＣＡＡＣ−ＯＳは、明確な結晶粒界を確認することはできないため、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、酸化物半導体の結晶性は不純物の混入や欠陥の生成などによって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物や欠陥（酸素欠損など）の少ない酸化物半導体ともいえる。従って、ＣＡＡＣ−ＯＳを有する酸化物半導体は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する酸化物半導体は熱に強く、信頼性が高い。 The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of an oxide semiconductor may be deteriorated due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including a CAAC-OS are stable. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.
ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。また、ｎｃ−ＯＳは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳや非晶質酸化物半導体と区別が付かない場合がある。 The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する酸化物半導体である。ａ−ｌｉｋｅ　ＯＳは、鬆または低密度領域を有する。即ち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、結晶性が低い。 The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.
酸化物半導体は、多様な構造をとり、それぞれが異なる特性を有する。本発明の一態様の酸化物半導体は、非晶質酸化物半導体、多結晶酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有していてもよい。 Oxide semiconductors have various structures and different properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
［酸化物半導体を有するトランジスタ］
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。 [Transistor having oxide semiconductor]
Next, the case where the above oxide semiconductor is used for a transistor is described.
なお、上記酸化物半導体をトランジスタに用いることで、高い電界効果移動度のトランジスタを実現することができる。また、信頼性の高いトランジスタを実現することができる。 Note that by using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.
また、トランジスタには、キャリア密度の低い酸化物半導体を用いることが好ましい。酸化物半導体膜のキャリア密度を低くする場合においては、酸化物半導体膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性と言う。例えば、酸化物半導体は、キャリア密度が８×１０１１／ｃｍ３未満、好ましくは１×１０１１／ｃｍ３未満、さらに好ましくは１×１０１０／ｃｍ３未満であり、１×１０−９／ｃｍ３以上とすればよい。 For the transistor, an oxide semiconductor with low carrier density is preferably used. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 11 / cm 3 , preferably less than 1 × 10 11 / cm 3 , more preferably less than 1 × 10 10 / cm 3 , and 1 × 10 −9 / What is necessary is just to be cm 3 or more.
また、高純度真性または実質的に高純度真性である酸化物半導体膜は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。 In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states.
また、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル領域が形成されるトランジスタは、電気特性が不安定となる場合がある。 In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.
従って、トランジスタの電気特性を安定にするためには、酸化物半導体中の不純物濃度を低減することが有効である。また、酸化物半導体中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。 Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in an adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
［不純物］
ここで、酸化物半導体中における各不純物の影響について説明する。 [impurities]
Here, the influence of each impurity in the oxide semiconductor is described.
酸化物半導体において、第１４族元素の一つであるシリコンや炭素が含まれると、酸化物半導体において欠陥準位が形成される。このため、酸化物半導体におけるシリコンや炭素の濃度と、酸化物半導体との界面近傍のシリコンや炭素の濃度（二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 In the oxide semiconductor, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.
また、酸化物半導体にアルカリ金属またはアルカリ土類金属が含まれると、欠陥準位を形成し、キャリアを生成する場合がある。従って、アルカリ金属またはアルカリ土類金属が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体中のアルカリ金属またはアルカリ土類金属の濃度を低減することが好ましい。具体的には、ＳＩＭＳにより得られる酸化物半導体中のアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed and carriers may be generated in some cases. Therefore, a transistor including an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less.
また、酸化物半導体において、窒素が含まれると、キャリアである電子が生じ、キャリア密度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体を半導体に用いたトランジスタはノーマリーオン特性となりやすい。従って、該酸化物半導体において、窒素はできる限り低減されていることが好ましい。例えば、酸化物半導体中の窒素濃度は、ＳＩＭＳにおいて、５×１０１９ａｔｏｍｓ／ｃｍ３未満、好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 In addition, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier density is increased, and the oxide semiconductor is likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Therefore, nitrogen in the oxide semiconductor is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 19 atoms / cm 3 , preferably 5 × 10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 or less in SIMS. Preferably, it is 5 × 10 17 atoms / cm 3 or less.
また、酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。従って、水素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体中の水素はできる限り低減されていることが好ましい。具体的には、酸化物半導体において、ＳＩＭＳにより得られる水素濃度を、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とする。 In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 20 atoms / cm 3 , preferably less than 1 × 10 19 atoms / cm 3 , more preferably 5 × 10 18 atoms / cm 3. Less than 3 , more preferably less than 1 × 10 18 atoms / cm 3 .
不純物が十分に低減された酸化物半導体をトランジスタのチャネル領域に用いることで、安定した電気特性を付与することができる。 By using an oxide semiconductor in which impurities are sufficiently reduced for the channel region of the transistor, stable electrical characteristics can be imparted.
＜半導体装置の構成例２＞
以下では、図３を用いて、本発明の一態様に係る半導体装置の一例について説明する。 <Configuration Example 2 of Semiconductor Device>
An example of a semiconductor device according to one embodiment of the present invention is described below with reference to FIGS.
図３（Ａ）は、トランジスタ２０１の上面図である。また、図３（Ｂ）、図３（Ｃ）、および図３（Ｄ）はトランジスタ２０１の断面図である。ここで、図３（Ｂ）は、図３（Ａ）にＡ−Ｂの一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル長方向の断面図でもある。また、図３（Ｃ）は、図３（Ａ）にＣ−Ｄの一点鎖線で示す部位の断面図であり、トランジスタ２００のチャネル幅方向の断面図でもある。また、図３（Ｄ）は、図３（Ａ）にＥ−Ｆの一点鎖線で示す部位の断面図であり、酸化物２３０と導電体２５２２の接続部を示す断面図でもある。図３（Ａ）の上面図では、図の明瞭化のために一部の要素を省いて図示している。 FIG. 3A is a top view of the transistor 201. 3B, 3C, and 3D are cross-sectional views of the transistor 201. FIG. Here, FIG. 3B is a cross-sectional view taken along dashed-dotted line AB in FIG. 3A and a cross-sectional view in the channel length direction of the transistor 200. FIG. 3C is a cross-sectional view taken along dashed-dotted line CD in FIG. 3A and also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 3D is a cross-sectional view taken along the dashed line EF in FIG. 3A, and is also a cross-sectional view illustrating a connection portion between the oxide 230 and the conductor 2522. In the top view of FIG. 3A, some elements are omitted for clarity.
なお、図３に示す半導体装置において、＜半導体装置の構成例１＞に示した半導体装置を構成する構造と同機能を有する構造には、同符号を付記する。 Note that in the semiconductor device illustrated in FIG. 3, the structure having the same function as the structure of the semiconductor device illustrated in <Structure Example 1 of Semiconductor Device> is denoted by the same reference numeral.
以下、トランジスタ２０１の構成についてそれぞれ図３を用いて説明する。なお、本項目においても、トランジスタ２０１の構成材料については＜半導体装置の構成例１＞で詳細に説明した材料を用いることができる。 Hereinafter, the structure of the transistor 201 will be described with reference to FIGS. Note that in this item as well, the material described in detail in <Structure Example 1 of Semiconductor Device> can be used as the constituent material of the transistor 201.
トランジスタ２０１において、酸化物２３０ｂ上には、ソース電極またはドレイン電極として機能する導電体２８５が設けられている。また、導電体２８５の上には絶縁体２８６が設けられている。導電体２８５は、導電体２０５と同様の材料を用いることができる。特に、窒化タンタルやタングステンを用いることが好ましい。また、絶縁体２８６は、絶縁体２７０や絶縁体２７２と同様の材料を用いることができる。絶縁体２８６を設けることで、導電体２８５の酸化を抑制し、導電体２８５の電気抵抗の増加を抑制することができる。また、トランジスタ２０１のチャネル長は導電体２８５間の長さに依存して決まるが、向かい合う導電体２８５の端部が酸化することで、トランジスタ２０１のチャネル長は意図せずに長くなるという不具合が生じる恐れがある。このような不具合を軽減するためにも、絶縁体２８６を設けることは好ましい。 In the transistor 201, a conductor 285 functioning as a source electrode or a drain electrode is provided over the oxide 230b. An insulator 286 is provided over the conductor 285. For the conductor 285, a material similar to that of the conductor 205 can be used. In particular, tantalum nitride or tungsten is preferably used. The insulator 286 can be formed using a material similar to that of the insulator 270 or the insulator 272. By providing the insulator 286, oxidation of the conductor 285 can be suppressed and an increase in electrical resistance of the conductor 285 can be suppressed. Although the channel length of the transistor 201 is determined depending on the length between the conductors 285, the channel length of the transistor 201 is unintentionally increased due to oxidation of the ends of the opposing conductors 285. May occur. In order to reduce such a problem, the insulator 286 is preferably provided.
図３（Ｂ）に示すように、酸化物２３０ｂにおいて点線で囲われた、導電体２８５と接する領域はｎ型化し、低抵抗領域となる。これは、導電体２８５が酸化物２３０ｂの酸素を引き抜き、酸化物２３０ｂに酸素欠損を生じさせていることに起因していると考えられる。酸化物２３０ｂ中の酸素欠損に、酸化物２３０ｂ内部あるいは外部に存在する不純物が捕獲され、当該領域は低抵抗化する。 As shown in FIG. 3B, a region in contact with the conductor 285 surrounded by a dotted line in the oxide 230b is n-type and becomes a low resistance region. This is considered to be because the conductor 285 extracts oxygen from the oxide 230b and causes oxygen vacancies in the oxide 230b. Impurities existing inside or outside the oxide 230b are captured by oxygen vacancies in the oxide 230b, and the resistance of the region is reduced.
酸化物２３０ｂ、導電体２８５、および絶縁体２８６の一部を覆うように、酸化物２３０ｃ、酸化物２３０ｄ、絶縁体２５０、導電体２６０、および絶縁体２７０が設けられる。なお、導電体２６０は、図３（Ａ）、図３（Ｂ）、および図３（Ｃ）に示すようにＡ−Ｂ方向における幅、およびＣ−Ｄ方向における長さが酸化物２３０ｃ、酸化物２３０ｄ、絶縁体２５０、および絶縁体２７０に比べて小さい。よって、絶縁体２７０は導電体２６０の上面および側面を覆い、導電体２６０の外側で絶縁体２５０と接する構造となる。絶縁体２７０には酸素の透過を抑制する材料を用いていることから、このように設けられた絶縁体２７０により、導電体２６０の酸化は抑制され、電気抵抗の増加を抑制することができる。 An oxide 230c, an oxide 230d, an insulator 250, a conductor 260, and an insulator 270 are provided so as to cover the oxide 230b, the conductor 285, and part of the insulator 286. Note that the conductor 260 has the width in the AB direction and the length in the CD direction as shown in FIGS. 3A, 3B, and 3C, and has an oxide 230c. It is smaller than the object 230d, the insulator 250, and the insulator 270. Therefore, the insulator 270 covers the top surface and the side surface of the conductor 260 and is in contact with the insulator 250 outside the conductor 260. Since the insulator 270 is formed using a material that suppresses permeation of oxygen, the insulator 270 thus provided can suppress the oxidation of the conductor 260 and suppress an increase in electrical resistance.
酸化物２３０ｃには、酸化物２３０ｂと同様の材料を用いることができる。また、酸化物２３０ｄには、酸化物２３０ａと同様の材料を用いることができる。なお、酸化物２３０ｃは形成しなくてもよい。 A material similar to that of the oxide 230b can be used for the oxide 230c. The oxide 230d can be formed using the same material as the oxide 230a. Note that the oxide 230c is not necessarily formed.
トランジスタ２０１では、チャネルは、酸化物２３０ｂおよび酸化物２３０ｃ内において一対の導電体２８５、または一対の低抵抗領域に挟まれた領域に形成される。 In the transistor 201, a channel is formed in a region between the pair of conductors 285 or the pair of low resistance regions in the oxides 230b and 230c.
絶縁体２８０上には、絶縁体２８７および絶縁体２８８が形成される。絶縁体２８７は、スパッタリング法を用いて成膜された酸化物絶縁体を用いることが好ましく、例えば酸化アルミニウム、酸化ハフニウム、またはハフニウムアルミネートを用いることが好ましい。このような絶縁体２８７を用いることにより、絶縁体２８０と絶縁体２８７が接する面を介して絶縁体２８０に酸素を添加して、絶縁体２８０を酸素過剰な状態にできる。絶縁体２８０に供給された酸素は、酸化物２３０に供給される。 An insulator 287 and an insulator 288 are formed over the insulator 280. As the insulator 287, an oxide insulator formed by a sputtering method is preferably used. For example, aluminum oxide, hafnium oxide, or hafnium aluminate is preferably used. By using such an insulator 287, oxygen can be added to the insulator 280 through a surface where the insulator 280 and the insulator 287 are in contact with each other, so that the insulator 280 can be in an oxygen-excess state. Oxygen supplied to the insulator 280 is supplied to the oxide 230.
さらに、絶縁体２８７として、酸化アルミニウム、酸化ハフニウム、またはハフニウムアルミネートなどの酸素が透過しにくい絶縁性材料を用いることにより、絶縁体２２４及び絶縁体２８０に添加した酸素が、成膜中に上方拡散するのを抑制することができる。これにより、さらに効率よく絶縁体２８０に酸素を添加することができる。 Further, by using an insulating material that does not easily transmit oxygen, such as aluminum oxide, hafnium oxide, or hafnium aluminate, as the insulator 287, oxygen added to the insulator 224 and the insulator 280 can move upward during film formation. Diffusion can be suppressed. Thereby, oxygen can be added to the insulator 280 more efficiently.
絶縁体２８８は、絶縁体２０８、絶縁体２１２、絶縁体２１６、および絶縁体２８０と同様の材料を用いることができる。 The insulator 288 can be formed using a material similar to that of the insulator 208, the insulator 212, the insulator 216, and the insulator 280.
図３（Ｂ）、図３（Ｃ）、および図３（Ｄ）に示すように、絶縁体２８０、絶縁体２８７、および絶縁体２８８などの絶縁体には開口が設けられ、開口内部には、導電体２５２（導電体２５２１、導電体２５２２、導電体２５２３、および導電体２５２４）が設けられる。絶縁体２８０、絶縁体２８７、および絶縁体２８８などの絶縁体と、導電体２５２の間には、絶縁体２８９が設けられる。絶縁体２８９は、絶縁体２７０と同様の材料を用いることができ、絶縁体２８０および上方の絶縁体や導電体から酸化物２３０への不純物の混入を抑制する。 As shown in FIGS. 3B, 3C, and 3D, an opening is provided in an insulator such as the insulator 280, the insulator 287, and the insulator 288, and the opening is provided inside the opening. , A conductor 252 (a conductor 2521, a conductor 2522, a conductor 2523, and a conductor 2524) is provided. An insulator 289 is provided between the conductor 252 and the insulator such as the insulator 280, the insulator 287, and the insulator 288. The insulator 289 can be formed using a material similar to that of the insulator 270 and suppresses entry of impurities into the oxide 230 from the insulator 280 and an upper insulator or conductor.
図３（Ｄ）に示すように、導電体２５２２（導電体２５２１）は酸化物２３０上の導電体２８５と接するだけでなく、酸化物２３０の側面とも接することで、酸化物２３０と電気的に接続することが好ましい。特に、導電体２５２２（導電体２５２１）は、酸化物２３０のチャネル幅方向と交わる側面において、Ｃ側の側面、およびＤ側の側面の双方または一方と接することが好ましい。また、導電体２５２２（導電体２５２１）が、酸化物２３０のチャネル長方向と交わる側面において、Ａ側（Ｂ側）の側面と接する構成にしてもよい。このように、導電体２５２２（導電体２５２１）が導電体２８５に加えて、酸化物２３０の側面と接する構成にすることにより、導電体２５２２（導電体２５２１）と酸化物２３０のコンタクト部の上面積を増やすことなく、コンタクト部の接触面積を増加させ、導電体２５２２（導電体２５２１）と酸化物２３０の接触抵抗を低減することができる。これにより、トランジスタのソース電極およびドレイン電極の微細化を図りつつ、オン電流を大きくすることができる。 As shown in FIG. 3D, the conductor 2522 (conductor 2521) not only contacts the conductor 285 over the oxide 230 but also contacts the side surface of the oxide 230, so that the conductor is electrically connected to the oxide 230. It is preferable to connect. In particular, the conductor 2522 (the conductor 2521) is preferably in contact with both or one of the side surface on the C side and the side surface on the D side on the side surface intersecting the channel width direction of the oxide 230. Alternatively, the conductor 2522 (conductor 2521) may be in contact with the side surface on the A side (B side) on the side surface intersecting the channel length direction of the oxide 230. In this manner, the conductor 2522 (conductor 2521) is in contact with the side surface of the oxide 230 in addition to the conductor 285, so that the contact portion between the conductor 2522 (conductor 2521) and the oxide 230 is formed. Without increasing the area, the contact area of the contact portion can be increased, and the contact resistance between the conductor 2522 (conductor 2521) and the oxide 230 can be reduced. Thus, the on-current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.
＜導電体の作製方法１＞
　以下では、本発明の一態様に係る半導体装置が有する配線の作製方法の一例について図４乃至図６を用いて説明する。 <Conductor manufacturing method 1>
Hereinafter, an example of a method for manufacturing a wiring included in a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.
　図４（Ａ）は、導電体２０３と、導電体２０３上の絶縁体２１６と、絶縁体２１６上のハードマスク１０１およびレジストマスク１０３が形成されている様子を示す断面模式図である。レジストマスク１０３を絶縁体２１６に対して垂直方向から見たときの形状は、後工程により形成される配線、電極、およびプラグの形状と反転した形で形成されている。 FIG. 4A is a schematic cross-sectional view showing a state where the conductor 203, the insulator 216 on the conductor 203, and the hard mask 101 and the resist mask 103 on the insulator 216 are formed. The shape of the resist mask 103 when viewed from the direction perpendicular to the insulator 216 is formed to be the reverse of the shapes of wirings, electrodes, and plugs formed in a later step.
次に、図４（Ｂ）に示すように、絶縁体２１６をエッチングにより加工し、開口を形成する。エッチングには、ドライエッチングやウェットエッチングを用いることができるが、微細加工には異方性エッチングを行うことが可能なドライエッチングを用いることが好ましい。 Next, as illustrated in FIG. 4B, the insulator 216 is processed by etching to form an opening. For etching, dry etching or wet etching can be used, but for fine processing, dry etching capable of performing anisotropic etching is preferably used.
当該エッチング処理において、導電体２０３はエッチングストッパとして機能することが好ましい。具体的には、該開口の形成において、絶縁体２１６のエッチングレートに比べ、導電体２０３のエッチングレートは低いことが好ましい。 In the etching process, the conductor 203 preferably functions as an etching stopper. Specifically, in forming the opening, the etching rate of the conductor 203 is preferably lower than the etching rate of the insulator 216.
なお、当該エッチング処理におけるマスクは、レジストマスク１０３とハードマスク１０１の両方を用いてもよいし、ハードマスク１０１のみを用いてもよい。レジストマスク１０３は、ハードマスク１０１形成時に消失する場合もあるし、ハードマスク１０１形成後に薬液やプラズマを用いて除去してもよい。 Note that both the resist mask 103 and the hard mask 101 may be used as a mask in the etching treatment, or only the hard mask 101 may be used. The resist mask 103 may disappear when the hard mask 101 is formed, or may be removed using a chemical solution or plasma after the hard mask 101 is formed.
次に開口を覆うように絶縁体２１６上に導電体２０５Ａを形成する。この時、ハードマスク１０１は除去せず、絶縁体２１６と導電体２０５Ａの間にハードマスク１０１が存在するように導電体２０５Ａを形成する。本実施の形態では、導電体２０５Ａを複数の導電体を積層して形成した。導電体２０５ａＡおよび導電体２０５ｂＡは導電性バリアとして機能することが好ましい。導電性バリアとは、水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物の拡散を抑制する機能を有する導電体である。また、チャネルが形成される金属酸化物に含まれる金属元素および酸素の拡散を抑制する機能を有していることが好ましい。導電性バリアとして、チタン、窒化チタン、タンタル、および窒化タンタルなどを用いることができる。このような導電性バリアを用いることで、不純物がトランジスタ２００に混入することを抑制することができる。 Next, a conductor 205A is formed over the insulator 216 so as to cover the opening. At this time, the hard mask 101 is not removed, and the conductor 205A is formed so that the hard mask 101 exists between the insulator 216 and the conductor 205A. In this embodiment, the conductor 205A is formed by stacking a plurality of conductors. The conductors 205aA and 205bA preferably function as a conductive barrier. A conductive barrier is a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N 2 O, NO, NO 2, etc.), copper atoms, and the like. Is the body. Further, it preferably has a function of suppressing diffusion of a metal element and oxygen contained in a metal oxide in which a channel is formed. As the conductive barrier, titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. By using such a conductive barrier, impurities can be prevented from entering the transistor 200.
本実施の形態では、導電体２０５ａＡとして窒化タンタルを用い、導電体２０３側から銅原子などの不純物が、導電体２０５ａＡより上方に拡散することを抑制している。また、導電体２０５ｂＡとして窒化チタンを用い、導電体２０３側から水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）などの不純物が、導電体２０５ｂＡより上方に拡散することを抑制している。 In this embodiment, tantalum nitride is used as the conductor 205aA, and impurities such as copper atoms are prevented from diffusing upward from the conductor 205aA from the conductor 203 side. Further, titanium nitride is used as the conductor 205bA, and impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N 2 O, NO, NO 2, etc.) Diffusion above the conductor 205bA is suppressed.
また、窒化チタンは、後工程でメタルＣＶＤ法にて形成するタングステンのシード層としても機能する。 Titanium nitride also functions as a tungsten seed layer formed by a metal CVD method in a later step.
導電体２０５ｃＡとしては、低抵抗な導電性材料を用いることが好ましい。低抵抗な導電性材料としては、タングステン、銅、アルミニウムなどを用いることができる。本実施の形態では、導電体２０５ｃＡとしてタングステンを用い、メタルＣＶＤ法にて形成した。 As the conductor 205cA, a low-resistance conductive material is preferably used. As the low resistance conductive material, tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used as the conductor 205cA and is formed by a metal CVD method.
図４（Ｃ）は、メタルＣＶＤ法にてタングステンからなる導電体２０５ｃＡを形成している途中の様子を説明する図である。導電体２０５ｃＡは、窒化チタンからなる導電体２０５ｂＡをシード層として、絶縁体２１６の表面、開口の底面および側面のそれぞれに対して垂直な方向に成長するように形成される。つまり、開口内部では、開口の側面から垂直方向に（すなわち、図４（Ｃ）の水平方向に）導電体２０５ｃＡの形成が進む。開口の側面から形成が進んだ導電体２０５ｃＡは、開口のほぼ中央でお互いに衝突し、開口内部は導電体２０５ｃＡで充填される。 FIG. 4C is a diagram for explaining a state in the middle of forming the conductor 205cA made of tungsten by a metal CVD method. The conductor 205cA is formed to grow in a direction perpendicular to each of the surface of the insulator 216, the bottom surface of the opening, and the side surface using the conductor 205bA made of titanium nitride as a seed layer. That is, in the opening, the formation of the conductor 205cA proceeds in the vertical direction from the side surface of the opening (that is, in the horizontal direction in FIG. 4C). The conductors 205cA that have been formed from the side surfaces of the openings collide with each other at substantially the center of the opening, and the inside of the opening is filled with the conductor 205cA.
図５（Ａ）は、導電体２０５ｃＡ形成後を示す図である。開口中央部から導電体２０５ｃＡの表面に向かって、形成方向の異なるタングステン同士が衝突した領域が形成されている。この領域は、シーム１０５と呼ばれる。導電体２０５ｃＡ内には、シーム１０５に沿って隙間が存在していると考えられている。また、シーム１０５周辺では、導電体２０５ｃＡの密度が疎になっていると考えられている。 FIG. 5A is a diagram showing the state after the conductor 205cA is formed. A region where tungsten having different formation directions collide with each other is formed from the center of the opening toward the surface of the conductor 205cA. This area is called a seam 105. It is considered that a gap exists along the seam 105 in the conductor 205cA. Further, it is considered that the density of the conductor 205cA is sparse around the seam 105.
次に、絶縁体２１６の上方に位置するハードマスク１０１および導電体２０５Ａを除去し、導電体２０５ａＢ、導電体２０５ｂＢ、および導電体２０５ｃＢからなる導電体２０５Ｂを形成する。ハードマスク１０１および導電体２０５Ａの除去には、化学機械研磨（ＣＭＰ）法を用いることができる。 Next, the hard mask 101 and the conductor 205A located above the insulator 216 are removed, and a conductor 205B including the conductor 205aB, the conductor 205bB, and the conductor 205cB is formed. A chemical mechanical polishing (CMP) method can be used to remove the hard mask 101 and the conductor 205A.
ＣＭＰ法は、被研磨剤をスラリーに含まれる化学薬品と反応させ、この反応物をスラリーに含まれる粒子と、研磨パッドを使って削り取る方法である。化学反応と機械的研磨を組み合わせた手法であることが特徴の一つである。スラリーとは、液体中に砥粒などの粒子と、酸化剤などの化学薬品を混合したもので、コロイド溶液、あるいは懸濁液と呼ぶことができる。ＣＭＰ法で処理された基板や膜は、その表面の平坦性が高く、ダマシンプロセスを用いた配線、電極、プラグ形成に用いられる。ＣＭＰ法を用いたダマシンプロセスは、多層配線技術にとって有効な技術である。 The CMP method is a method in which a polishing agent is reacted with a chemical contained in a slurry, and the reaction product is scraped off using particles contained in the slurry and a polishing pad. One of the features is that it is a method combining chemical reaction and mechanical polishing. A slurry is a mixture of particles such as abrasive grains and a chemical such as an oxidizer in a liquid, and can be called a colloidal solution or a suspension. A substrate or a film processed by the CMP method has high surface flatness, and is used for wiring, electrodes, and plug formation using a damascene process. The damascene process using the CMP method is an effective technique for the multilayer wiring technique.
ＣＭＰ法を用いた導電体の除去には、光学式の終点検出、あるいはモーター電流検知式（トルク式）の終点検出を用いるのが好ましい。光学式の終点検出を用いる場合、被研磨面におけるレーザあるいは白色光の反射の変化を終点検出器に設けられたセンサにて検知し、研磨の終了時間を決定することができる。また、モーター電流検知式の終点検出を用いる場合、終点検出器は、研磨布と被研磨面の間に生じる摩擦による抵抗の変化を検知し、研磨の終了時間を決定することができる。 For removing the conductor using the CMP method, it is preferable to use optical end point detection or motor current detection type (torque type) end point detection. When optical end point detection is used, a change in the reflection of the laser or white light on the surface to be polished can be detected by a sensor provided in the end point detector to determine the polishing end time. Further, when the motor current detection type end point detection is used, the end point detector can detect a change in resistance due to friction generated between the polishing cloth and the surface to be polished, and determine the polishing end time.
よって、導電体２０５ｃＡ、導電体２０５ｂＡ、導電体２０５ａＡ、ハードマスク１０１、および絶縁体２１６の間で、レーザや白色光に対する反射率や、研磨布に対して生じる、摩擦による抵抗が異なることが好ましい。 Therefore, it is preferable that the reflectivity with respect to the laser and white light and the resistance due to friction generated with respect to the polishing cloth be different between the conductor 205cA, the conductor 205bA, the conductor 205aA, the hard mask 101, and the insulator 216. .
図５（Ｂ）に示すようにＣＭＰ法による研磨処理後の導電体２０５ｃＢには、導電体２０５ｃＡにおいてシーム１０５が形成されていた部分を中心に凹部が形成されることがある。この凹部は、キーホール１０７と呼ばれる。キーホール１０７は、シーム１０５、またはシーム１０５に沿って存在する隙間に、スラリーに含まれる化学薬品がしみこみ、シーム１０５周辺の導電体２０５ｃＡが酸化など、化学薬品との反応によりもろくなり、砥粒や研磨パッドにより過剰に研磨されることが原因と考えられている。また、シーム１０５周辺の導電体２０５ｃＡの密度が疎であることから化学薬品がしみこみやすい、あるいは、砥粒や研磨パッドにより研磨されやすいことが原因と考えられている。 As shown in FIG. 5B, the conductor 205cB after the polishing process by the CMP method may be formed with a concave portion around the portion where the seam 105 is formed in the conductor 205cA. This recess is called a keyhole 107. In the keyhole 107, the chemical contained in the slurry is infiltrated into the seam 105 or the gap existing along the seam 105, and the conductor 205cA around the seam 105 becomes brittle due to a reaction with the chemical such as oxidation. This is considered to be caused by excessive polishing by a polishing pad. In addition, it is considered that the chemical 205 is easily soaked in because the density of the conductor 205cA around the seam 105 is sparse, or is easily polished by abrasive grains or a polishing pad.
導電体２０５ｃＢにキーホール１０７が形成されると、その上に形成される膜にも凹部は転写され、カバレッジ不良などの形状不良を引き起こすことがある。図５（Ｃ）は、キーホール１０７を有する導電体２０５Ｂ上に絶縁体や酸化物を積層して形成した例を示している。絶縁体２１６および導電体２０５Ｂ上には、絶縁体２２０、絶縁体２２２、絶縁体２２４、酸化物２３０ａ、および酸化物２３０ｂが形成されている。キーホール１０７により、絶縁体や酸化物にも凹部１０９が形成されるなど、形状不良が発生していることがわかる。形状不良は、トランジスタや、回路の動作に影響を与え、特性不良の原因となる。また、酸化物２３０の結晶性を悪化させる場合がある。 When the keyhole 107 is formed in the conductor 205cB, the concave portion is also transferred to the film formed thereon, which may cause a shape defect such as a coverage defect. FIG. 5C illustrates an example in which an insulator or an oxide is stacked over the conductor 205 </ b> B having the keyhole 107. An insulator 220, an insulator 222, an insulator 224, an oxide 230a, and an oxide 230b are formed over the insulator 216 and the conductor 205B. It can be seen that the keyhole 107 causes a defective shape such as a recess 109 formed in the insulator or oxide. The shape defect affects the operation of the transistor and the circuit, and causes a characteristic defect. In addition, the crystallinity of the oxide 230 may be deteriorated.
そこで、導電体２０５ｃＢに形成されたキーホール１０７を除去する。具体的には、導電体２０５ｃＢをハーフエッチングして、キーホール１０７が除去された導電体２０５ｃＣを形成する。導電体２０５ｃＢの除去には、ドライエッチングやウェットエッチングを用いることができる。 Therefore, the keyhole 107 formed in the conductor 205cB is removed. Specifically, the conductor 205cB is half-etched to form the conductor 205cC from which the keyhole 107 is removed. For removing the conductor 205cB, dry etching or wet etching can be used.
導電体２０５ｃＢの除去の際、図６（Ａ）に示すように、ハードマスク１０１を残してＣＭＰ法による研磨を終了させてもよい。ハードマスク１０１が残っていることで、導電体２０５ｃＢのエッチング中に絶縁体２１６が露出することなく、絶縁体２１６のエッチングや汚染を低減させることができる。また、ハードマスク１０１と導電体２０５ｃＢが同様な材料の場合、導電体２０５ｃＢのエッチング中にハードマスク１０１を除去することができる。導電体２０５ｃＢのエッチング中にハードマスク１０１が消失する場合でも、絶縁体２１６が露出する時間を低減できるため、ＣＭＰ法による研磨後にハードマスク１０１を残しておくことは好ましい。一方、次工程の導電体２０５ｃＢのハーフエッチングにおいて、絶縁体２１６のエッチング量が後工程に影響を及ぼさない場合は、ハードマスク１０１まで除去してもよい。 When the conductor 205cB is removed, as shown in FIG. 6A, the polishing by the CMP method may be finished while leaving the hard mask 101. Since the hard mask 101 remains, etching and contamination of the insulator 216 can be reduced without exposing the insulator 216 during etching of the conductor 205cB. In the case where the hard mask 101 and the conductor 205cB are made of the same material, the hard mask 101 can be removed during the etching of the conductor 205cB. Even when the hard mask 101 disappears during the etching of the conductor 205cB, the time for the insulator 216 to be exposed can be reduced; therefore, it is preferable to leave the hard mask 101 after polishing by the CMP method. On the other hand, in the half etching of the conductor 205cB in the next process, the hard mask 101 may be removed if the etching amount of the insulator 216 does not affect the subsequent process.
図６（Ｂ）は導電体２０５ｃＢのハーフエッチング後を示す図である。導電体２０５ｃＢのエッチングによりハードマスク１０１が除去される例を示している。また、導電体２０５ｃＢのエッチングレートに比べ、導電体２０５ａＢおよび導電体２０５ｂＢのエッチングレートが低い場合、導電体２０５ａＢおよび導電体２０５ｂＢはエッチングされずに残り、絶縁体２１６の上方に突き出す形状となっている。しかしながら、本実施の形態はこれに限らない。導電体２０５ｃＢのエッチング後にハードマスク１０１が残っていてもよい、また導電体２０５ａＢおよび導電体２０５ｂＢはエッチングされ、上面が絶縁体２１６の上面や導電体２０５ｃＣの上面と概略一致していてもよい。 FIG. 6B shows a state after the conductor 205cB is half-etched. In the example, the hard mask 101 is removed by etching the conductor 205cB. Further, when the etching rates of the conductor 205aB and the conductor 205bB are lower than the etching rate of the conductor 205cB, the conductor 205aB and the conductor 205bB remain unetched and protrude above the insulator 216. Yes. However, the present embodiment is not limited to this. The hard mask 101 may remain after the conductor 205cB is etched, or the conductor 205aB and the conductor 205bB may be etched, and the upper surface thereof may substantially coincide with the upper surface of the insulator 216 or the upper surface of the conductor 205cC.
次に、図６（Ｃ）に示すように、絶縁体２１６、導電体２０５ａＢ、導電体２０５ｂＢ、および導電体２０５ｃＣ、を覆うように導電体２０５ｄＡおよび導電体２０５ｅＡを順に形成する。 Next, as illustrated in FIG. 6C, a conductor 205dA and a conductor 205eA are sequentially formed so as to cover the insulator 216, the conductor 205aB, the conductor 205bB, and the conductor 205cC.
導電体２０５ｄＡは、導電性バリアとして機能する導電体が好ましく、チタン、窒化チタン、タンタル、および窒化タンタルなどを用いることができる。より好ましくは、導電体２０５ｂＡと同じ材料を用いる。本実施の形態では、導電体２０５ｄＡとして窒化チタンを用い、導電体２０３側から水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）などの不純物が、導電体２０５ｄＡより上方に拡散することを防いでいる。 The conductor 205dA is preferably a conductor that functions as a conductive barrier, and titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. More preferably, the same material as that of the conductor 205bA is used. In this embodiment, titanium nitride is used as the conductor 205dA, and from the conductor 203 side, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2, etc.), etc. Are prevented from diffusing above the conductor 205dA.
導電体２０５ｅＡとしては、低抵抗な導電性材料を用いることが好ましい。低抵抗な導電性材料としては、タングステン、銅、アルミニウムなどを用いることができる。本実施の形態では、導電体２０５ｅＡとしてタングステンを用い、メタルＣＶＤ法にて形成した。 As the conductor 205eA, a low-resistance conductive material is preferably used. As the low resistance conductive material, tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used as the conductor 205eA and is formed by a metal CVD method.
図６（Ｃ）において、導電体２０５ｅＡは、導電体２０５ｃＣの上面に形成された導電体２０５ｄＡ、および導電体２０５ｂＢの側面に形成された導電体２０５ｄＡから垂直方向に成長するように形成される。よって、導電体２０５ｅＡにもシーム１１１が形成されている。一方、絶縁体２１６に形成された開口の一部は、導電体２０５ｃＣにより充填されているため、導電体２０５ｅＡが充填すべき開口の深さは、導電体２０５ｃＡ形成時の充填すべき開口の深さより浅い。よって、導電体２０５ｅＡ内のシーム１１１は、絶縁体２１６の上方に形成される。 In FIG. 6C, the conductor 205eA is formed to grow vertically from the conductor 205dA formed on the upper surface of the conductor 205cC and the conductor 205dA formed on the side surface of the conductor 205bB. Therefore, the seam 111 is also formed on the conductor 205eA. On the other hand, since a part of the opening formed in the insulator 216 is filled with the conductor 205cC, the depth of the opening to be filled with the conductor 205eA is the depth of the opening to be filled when the conductor 205cA is formed. Shallower. Therefore, the seam 111 in the conductor 205eA is formed above the insulator 216.
次に、図６（Ｄ）に示すように、絶縁体２１６の上方に位置する導電体２０５ｄＡおよび導電体２０５ｅＡを除去する。導電体２０５ｄＡおよび導電体２０５ｅＡの除去には、ＣＭＰ法を用いることができる。導電体２０５ａＢおよび導電体２０５ｂＢが絶縁体２１６の上方に突き出す形状となっている場合、導電体２０５ｄＡおよび導電体２０５ｅＡの除去工程にて絶縁体２１６の上方に位置する導電体２０５ａＢおよび導電体２０５ｂＢを除去することができる。以上の工程により、導電体２０５ａ、導電体２０５ｂ、導電体２０５ｃ、導電体２０５ｄ、および導電体２０５ｅからなる導電体２０５が形成される。なお、導電体２０５ｅＡ内のシーム１１１はＣＭＰ法による研磨にて除去されるため、図６（Ａ）に示したようなキーホールは形成されない。 Next, as illustrated in FIG. 6D, the conductors 205dA and 205eA located above the insulator 216 are removed. A CMP method can be used to remove the conductor 205dA and the conductor 205eA. In the case where the conductor 205aB and the conductor 205bB protrude above the insulator 216, the conductor 205aB and the conductor 205bB located above the insulator 216 are removed in the step of removing the conductor 205dA and the conductor 205eA. Can be removed. Through the above steps, the conductor 205 including the conductor 205a, the conductor 205b, the conductor 205c, the conductor 205d, and the conductor 205e is formed. Note that since the seam 111 in the conductor 205eA is removed by polishing by the CMP method, the keyhole as shown in FIG. 6A is not formed.
導電体２０５は、絶縁体２１６に形成された開口内部において、導電体２０５ｂ、および導電体２０５ｄが設けられている。すなわち、導電性バリアとして機能する導電体が２層設けられている。導電性バリアを２層構造とすることで、導電体２０３側から水素原子、水素分子、水分子、窒素原子、窒素分子、酸化窒素分子（Ｎ２Ｏ、ＮＯ、ＮＯ２など）、銅原子などの不純物が導電体２０５より上方に拡散することを抑制することができる。また、導電体２０５ｄは、外側の側面が導電体２０５ｂの内側の側面と接するように設けられており、不純物拡散の抑制効果が向上する。さらに、導電体２０５ｂの外側に、導電体２０５ａが導電体２０５ｂと接するように設けられており、不純物拡散の抑制効果はさらに向上する。 The conductor 205 is provided with a conductor 205b and a conductor 205d inside an opening formed in the insulator 216. That is, two conductors functioning as a conductive barrier are provided. By making the conductive barrier into a two-layer structure, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atoms, etc. from the conductor 203 side Can be prevented from diffusing above the conductor 205. In addition, the conductor 205d is provided so that the outer side surface is in contact with the inner side surface of the conductor 205b, and the effect of suppressing impurity diffusion is improved. Further, the conductor 205a is provided outside the conductor 205b so as to be in contact with the conductor 205b, and the effect of suppressing impurity diffusion is further improved.
このようにして形成された導電体２０５は、半導体装置におけるゲート電極などの電極や、トランジスタや回路を接続する配線として用いることができる。 The conductor 205 formed in this manner can be used as an electrode such as a gate electrode in a semiconductor device, or a wiring connecting a transistor or a circuit.
＜導電体の作製方法２＞
上述したような電極や配線として機能する導電体２０５の形成方法は、プラグの形成にも適用することができる。以下、図７乃至図１１を用いて説明する。 <Conductor manufacturing method 2>
The above-described method for forming the conductor 205 functioning as an electrode or wiring can also be applied to the formation of a plug. This will be described below with reference to FIGS.
プラグは、第１の要素と、第１の要素の上に設けられ、少なくとも一部が第１の要素と重なる第２の要素との間の絶縁体に設けられたコンタクトホール内に形成され、第１の要素と第２の要素を電気的に接続する。すなわち、半導体装置における配線間の接続、配線とトランジスタや容量などの素子の接続、素子間の接続などに用いることができる。より具体的には、配線と、トランジスタのソース、ドレイン、またはゲートとの接続、配線と容量の電極との接続、トランジスタのソース、ドレイン、またはゲートと、容量の電極との接続などに用いることができる。 The plug is formed in a contact hole provided in an insulator between the first element and the second element provided on the first element and at least partially overlapping the first element; The first element and the second element are electrically connected. That is, it can be used for connection between wirings in a semiconductor device, connection between wirings and elements such as transistors and capacitors, connection between elements, and the like. More specifically, it is used for connection between a wiring and a source, drain or gate of a transistor, connection between a wiring and a capacitor electrode, connection between a source, drain or gate of a transistor and a capacitor electrode, or the like. Can do.
本実施の形態では、トランジスタ上に絶縁体が設けられ、絶縁体上に配線が設けられ、当該配線と当該トランジスタを絶縁体中に設けられたプラグを用いて電気的に接続する例を示す。 In this embodiment, an example is described in which an insulator is provided over a transistor, a wiring is provided over the insulator, and the wiring and the transistor are electrically connected using a plug provided in the insulator.
図７（Ａ）は、酸化物２３０上に絶縁体２７４および絶縁体２８０が順に積層され、絶縁体２８０上にハードマスク１１３が設けられ、ハードマスク１１３上にレジストマスク１１５が設けられている構造を示している。後述するが、酸化物２３０は、トランジスタのソースおよびドレインの一方として機能する。また、酸化物２３０上に、ソース電極またはドレイン電極として機能する導電体が設けられていてもよい。また、本実施の形態では、酸化物２３０上に設けられる絶縁体は２層としたが、本実施の形態はこれに限らない。酸化物２３０上に設けられる絶縁体は単層でもよいし、３層以上の積層構造としてもよい。 FIG. 7A illustrates a structure in which an insulator 274 and an insulator 280 are sequentially stacked over the oxide 230, the hard mask 113 is provided over the insulator 280, and the resist mask 115 is provided over the hard mask 113. Is shown. Although described later, the oxide 230 functions as one of a source and a drain of the transistor. Further, a conductor functioning as a source electrode or a drain electrode may be provided over the oxide 230. In this embodiment, the number of insulators provided over the oxide 230 is two layers; however, this embodiment is not limited to this. The insulator provided over the oxide 230 may be a single layer or a stacked structure including three or more layers.
絶縁体２７４および絶縁体２８０としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化ハフニウム、ハフニウムおよびアルミニウムを含む酸化物（ハフニウムアルミネート）などを用いることができる。本実施の形態では、絶縁体２７４として窒化シリコンを用い、絶縁体２８０として酸化窒化シリコンを用いた。その他の絶縁体の組み合わせとして、ハフニウムアルミネート、窒化シリコン、および酸化窒化シリコンを順に積層した３層構造、酸化アルミニウム、窒化シリコン、および酸化窒化シリコンを順に積層した３層構造、あるいは酸化アルミニウム、酸化窒化シリコン、酸化アルミニウム、および酸化窒化シリコンを順に積層した４層構造としてもよい。 As the insulator 274 and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, oxide containing hafnium and aluminum (hafnium aluminate), or the like can be used. In this embodiment, silicon nitride is used as the insulator 274 and silicon oxynitride is used as the insulator 280. Other combinations of insulators include a three-layer structure in which hafnium aluminate, silicon nitride, and silicon oxynitride are sequentially stacked, a three-layer structure in which aluminum oxide, silicon nitride, and silicon oxynitride are sequentially stacked, or aluminum oxide and oxide A four-layer structure in which silicon nitride, aluminum oxide, and silicon oxynitride are sequentially stacked may be employed.
次に、図７（Ｂ）に示すように、絶縁体２８０および絶縁体２７４をエッチングにより加工し、開口を形成する。エッチングには、ドライエッチングやウェットエッチングを用いることができるが、微細加工には異方性エッチングを行うことが可能なドライエッチングを用いることが好ましい。 Next, as illustrated in FIG. 7B, the insulator 280 and the insulator 274 are processed by etching to form openings. For etching, dry etching or wet etching can be used, but for fine processing, dry etching capable of performing anisotropic etching is preferably used.
なお、当該エッチング処理におけるマスクは、レジストマスク１１５とハードマスク１１３の両方を用いてもよいし、ハードマスク１１３のみを用いてもよい。レジストマスク１１５は、ハードマスク１１３形成時に消失する場合もあるし、ハードマスク１１３形成後に薬液やプラズマを用いて除去してもよい。 Note that both the resist mask 115 and the hard mask 113 may be used as a mask in the etching treatment, or only the hard mask 113 may be used. The resist mask 115 may disappear when the hard mask 113 is formed, or may be removed using a chemical solution or plasma after the hard mask 113 is formed.
次に開口を覆うように絶縁体２８０上に導電体２５２Ａを形成する。本実施の形態では、ハードマスク１１３は除去せず、絶縁体２８０と導電体２５２Ａの間にハードマスク１１３が存在するように導電体２５２Ａを形成する例を示すが、これに限らない。開口形成後にハードマスク１１３を除去してから導電体２５２Ａを形成してもよい。 Next, a conductor 252A is formed over the insulator 280 so as to cover the opening. Although this embodiment shows an example in which the conductor 252A is formed so that the hard mask 113 exists between the insulator 280 and the conductor 252A without removing the hard mask 113, the invention is not limited to this. The conductor 252A may be formed after the hard mask 113 is removed after the opening is formed.
本実施の形態では、導電体２５２Ａを複数の導電体を積層して形成した。導電体２５２ａＡは導電性バリアとして機能することが好ましい。導電性バリアとして、前述した機能と同様の機能を有することが好ましく、チタン、窒化チタン、タンタル、および窒化タンタルなどを用いることができる。このような導電性バリアを用いることで、絶縁体２８０中の不純物、あるいは以降の工程により生じる不純物のトランジスタ２００への混入を抑制することができる。 In this embodiment, the conductor 252A is formed by stacking a plurality of conductors. The conductor 252aA preferably functions as a conductive barrier. The conductive barrier preferably has a function similar to that described above, and titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used. By using such a conductive barrier, impurities in the insulator 280 or impurities generated in a subsequent process can be prevented from being mixed into the transistor 200.
本実施の形態では、導電体２５２ａＡとして窒化チタンを用いた。また、窒化チタンは、後工程でメタルＣＶＤ法にてタングステンを形成する場合、シード層として用いることができる。 In this embodiment, titanium nitride is used as the conductor 252aA. Titanium nitride can be used as a seed layer when tungsten is formed by metal CVD in a later step.
導電体２５２ｂＡとしては、低抵抗な導電性材料を用いることが好ましい。低抵抗な導電性材料としては、タングステン、銅、アルミニウムなどを用いることができる。本実施の形態では、導電体２５２ｂＡとしてタングステンを用い、メタルＣＶＤ法にて形成した。導電体２５２ｂＡの材質や形成方法により、シーム１１７が形成される（図７（Ｃ）参照。）。 As the conductor 252bA, a low-resistance conductive material is preferably used. As the low resistance conductive material, tungsten, copper, aluminum, or the like can be used. In this embodiment mode, tungsten is used for the conductor 252bA and is formed by a metal CVD method. A seam 117 is formed by the material and the formation method of the conductor 252bA (see FIG. 7C).
次に、絶縁体２８０の上方に位置する導電体２５２Ａを除去する。導電体２５２Ａの除去には、ＣＭＰ法を用いることができる。 Next, the conductor 252A located above the insulator 280 is removed. A CMP method can be used to remove the conductor 252A.
図８（Ａ）は、絶縁体２８０の上方、かつ導電体２５２ａＡの上方に位置する導電体２５２ｂＡを除去し、導電体２５２ａＡおよび導電体２５２ｂＢからなる導電体２５２Ｂが形成された様子を示している。導電体２５２Ｂにおいて、導電体２５２ｂＢの外側に、導電体２５２ａＡの一部が露出している。また、導電体２５２ｂＢには、凹部、すなわちキーホール１１９が形成される場合がある。 FIG. 8A illustrates a state where the conductor 252bA located above the insulator 280 and above the conductor 252aA is removed, and a conductor 252B including the conductor 252aA and the conductor 252bB is formed. . In the conductor 252B, a part of the conductor 252aA is exposed outside the conductor 252bB. The conductor 252bB may be formed with a recess, that is, a keyhole 119.
図８（Ｂ）は、絶縁体２８０上に設けられたハードマスク１１３の上方に位置する導電体２５２ｂＡおよび導電体２５２ａＡを除去し、導電体２５２ａＣおよび導電体２５２ｂＣからなる導電体２５２Ｃが形成された様子を示している。導電体２５２Ｃの外側には、ハードマスク１１３が露出している。また、導電体２５２ｂＣには、凹部、すなわちキーホール１１９が形成される場合がある。 In FIG. 8B, the conductor 252bA and the conductor 252aA located above the hard mask 113 provided over the insulator 280 are removed, and the conductor 252C including the conductor 252aC and the conductor 252bC is formed. It shows a state. The hard mask 113 is exposed outside the conductor 252C. The conductor 252bC may be formed with a recess, that is, a keyhole 119.
図８（Ｃ）は、絶縁体２８０の上方に位置する導電体２５２ｂＡ、導電体２５２ａＡ、およびハードマスク１１３を除去し、導電体２５２ａＤおよび導電体２５２ｂＤからなる導電体２５２Ｄが形成された様子を示している。導電体２５２Ｃの外側には、絶縁体２８０が露出している。また、導電体２５２ｂＤには、凹部、すなわちキーホール１１９が形成される場合がある。 FIG. 8C illustrates a state where the conductor 252bA, the conductor 252aA, and the hard mask 113 located above the insulator 280 are removed, and a conductor 252D including the conductor 252aD and the conductor 252bD is formed. ing. An insulator 280 is exposed outside the conductor 252C. In addition, a recess, that is, a keyhole 119 may be formed in the conductor 252bD.
ＣＭＰ法を用いた導電体の除去には、光学式の終点検出、あるいはモーター電流検知式（トルク式）の終点検出を用いるのが好ましい。光学式の終点検出を用いる場合、被研磨面におけるレーザあるいは白色光の反射の変化を終点検出器に設けられたセンサにて検知し、研磨の終了時間を決定することができる。また、モーター電流検知式の終点検出を用いる場合、終点検出器は、研磨布と被研磨面の間に生じる摩擦による抵抗の変化を検知し、研磨の終了時間を決定することができる。 For removing the conductor using the CMP method, it is preferable to use optical end point detection or motor current detection type (torque type) end point detection. When optical end point detection is used, a change in the reflection of the laser or white light on the surface to be polished can be detected by a sensor provided in the end point detector to determine the polishing end time. Further, when the motor current detection type end point detection is used, the end point detector can detect a change in resistance due to friction generated between the polishing cloth and the surface to be polished, and determine the polishing end time.
よって、導電体２５２ｂＡ、導電体２５２ａＡ、ハードマスク１１３、および絶縁体２８０の間で、レーザや白色光に対する反射率や、研磨布に対して生じる、摩擦による抵抗が異なることが好ましい。 Therefore, it is preferable that the reflectance with respect to a laser and white light, and the resistance by friction which arise with respect to polishing cloth differ between the conductor 252bA, the conductor 252aA, the hard mask 113, and the insulator 280.
ＣＭＰ法を用いた導電体の除去後の状態は、図８（Ａ）乃至図８（Ｃ）に示したいずれのものでもよく、終点検出のしやすさなどを考慮して決定してもよい。 The state after removing the conductor using the CMP method may be any of those shown in FIGS. 8A to 8C, and may be determined in consideration of the ease of detecting the end point. .
次に、キーホール１１９を除去する。図９（Ａ）は、図８（Ａ）に示す導電体２５２ｂＢをハーフエッチングして、キーホール１１９を含む導電体２５２ｂＢの一部が除去された導電体２５２ｂＥを示す。導電体２５２ｂＢの除去には、ドライエッチングやウェットエッチングを用いることができる。この時、導電体２５２ｂＢと導電体２５２ａＡが同じエッチング条件にてエッチングされ得る材質の場合、導電体２５２ｂＢのエッチング中に導電体２５２ａＡもエッチングされる場合がある。さらに、導電体２５２ｂＢとハードマスク１１３が同じ材質、あるいは同じエッチング条件にてエッチングされ得る材質の場合、導電体２５２ｂＢのエッチング中にハードマスク１１３もエッチングされる場合がある。 Next, the keyhole 119 is removed. FIG. 9A illustrates a conductor 252bE in which the conductor 252bB illustrated in FIG. 8A is half-etched and part of the conductor 252bB including the keyhole 119 is removed. For the removal of the conductor 252bB, dry etching or wet etching can be used. At this time, in the case where the conductor 252bB and the conductor 252aA can be etched under the same etching conditions, the conductor 252aA may be etched during the etching of the conductor 252bB. Further, when the conductor 252bB and the hard mask 113 are made of the same material or can be etched under the same etching conditions, the hard mask 113 may be etched during the etching of the conductor 252bB.
図９（Ｂ）は、図８（Ｂ）に示す導電体２５２ｂＣをハーフエッチングして、キーホール１１９を含む導電体２５２ｂＣの一部が除去された導電体２５２ｂＥを示す。導電体２５２ｂＣの除去には、ドライエッチングやウェットエッチングを用いることができる。この時、導電体２５２ｂＣとハードマスク１１３が同じ材質、あるいは同じエッチング条件にてエッチングされ得る材質の場合、導電体２５２ｂＣのエッチング中にハードマスク１１３もエッチングされる場合がある。 FIG. 9B illustrates a conductor 252bE in which the conductor 252bC illustrated in FIG. 8B is half-etched and part of the conductor 252bC including the keyhole 119 is removed. For removing the conductor 252bC, dry etching or wet etching can be used. At this time, if the conductor 252bC and the hard mask 113 are made of the same material or can be etched under the same etching conditions, the hard mask 113 may be etched during the etching of the conductor 252bC.
図９（Ｃ）は、図８（Ｃ）に示す導電体２５２ｂＤをハーフエッチングして、キーホール１１９を含む導電体２５２ｂＤの一部が除去された導電体２５２ｂＥを示す。導電体２５２ｂＤの除去には、ドライエッチングやウェットエッチングを用いることができる。 FIG. 9C illustrates a conductor 252bE in which the conductor 252bD illustrated in FIG. 8C is half-etched and part of the conductor 252bD including the keyhole 119 is removed. Dry etching or wet etching can be used to remove the conductor 252bD.
図９（Ａ）乃至図９（Ｃ）において、導電体２５２ｂＥには、シーム１２１が残存している場合がある。 9A to 9C, the seam 121 may remain on the conductor 252bE.
図９（Ａ）乃至図９（Ｃ）において、導電体２５２ｂＥの上表面は、絶縁体２８０の上表面よりも低く、凹部が形成される。 9A to 9C, the upper surface of the conductor 252bE is lower than the upper surface of the insulator 280, and a recess is formed.
次に、導電体２５２ｂＥおよび絶縁体２８０上方に導電体を形成する。 Next, a conductor is formed over the conductor 252bE and the insulator 280.
図１０（Ａ）は、図９（Ａ）に示す導電体２５２ｂＥおよび導電体２５２ａＡ上に導電体２５２ｃＡを形成し、導電体２５２ｃＡ上に導電体２５２ｄＡを形成する場合を示している。導電体２５２ｃＡおよび導電体２５２ｄＡにより、導電体２５２ｂＥの上表面と、導電体２５２ａＡの上表面で形成された凹部は充填される。絶縁体２８０および絶縁体２４０に形成された開口の底部は導電体２５２ｂＥにより充填されているため、当該凹部の深さは開口の深さに比べて浅いため、シームは形成されにくいが、導電体２５２ｄＡにはシーム１２３が形成される場合がある。 FIG. 10A illustrates the case where the conductor 252cA is formed over the conductor 252bE and the conductor 252aA illustrated in FIG. 9A and the conductor 252dA is formed over the conductor 252cA. The conductor 252cA and the conductor 252dA fill the upper surface of the conductor 252bE and the recess formed on the upper surface of the conductor 252aA. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam. A seam 123 may be formed at 252 dA.
導電体２５２ｃＡには、導電体２５２ａＡと同様の導電体を用いることができる。また、導電体２５２ｄＡには、導電体２５２ｂＡと同様の導電体を用いることができる。 As the conductor 252cA, a conductor similar to the conductor 252aA can be used. For the conductor 252dA, a conductor similar to the conductor 252bA can be used.
図１０（Ｂ）は、図９（Ｂ）に示す導電体２５２ｂＥおよび絶縁体２８０上に導電体２５２ｃＢを形成し、導電体２５２ｃＢ上に導電体２５２ｄＢを形成する場合を示している。導電体２５２ｃＢおよび導電体２５２ｄＢにより、導電体２５２ｂＥの上表面と、絶縁体２８０の上表面で形成された凹部は充填される。絶縁体２８０および絶縁体２４０に形成された開口の底部は導電体２５２ｂＥにより充填されているため、当該凹部の深さは開口の深さに比べて浅いため、シームは形成されにくいが、導電体２５２ｄＢにはシーム１２３が形成される場合がある。 FIG. 10B illustrates the case where the conductor 252cB is formed over the conductor 252bE and the insulator 280 illustrated in FIG. 9B and the conductor 252dB is formed over the conductor 252cB. The conductor 252cB and the conductor 252dB fill the recess formed on the upper surface of the conductor 252bE and the upper surface of the insulator 280. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam. A seam 123 may be formed at 252 dB.
導電体２５２ｃＢには、導電体２５２ａＡと同様の導電体を用いることができる。また、導電体２５２ｄＢには、導電体２５２ｂＡと同様の導電体を用いることができる。 For the conductor 252cB, a conductor similar to the conductor 252aA can be used. For the conductor 252dB, a conductor similar to the conductor 252bA can be used.
図１０（Ｃ）は、図９（Ｃ）に示す導電体２５２ｂＥおよび絶縁体２８０上に導電体２５２ｃＣを形成し、導電体２５２ｃＣ上に導電体２５２ｄＣを形成する場合を示している。導電体２５２ｃＣおよび導電体２５２ｄＣにより、導電体２５２ｂＥの上表面と、絶縁体２８０の上表面で形成された凹部は充填される。絶縁体２８０および絶縁体２４０に形成された開口の底部は導電体２５２ｂＥにより充填されているため、当該凹部の深さは開口の深さに比べて浅いため、シームは形成されにくいが、導電体２５２ｄＣにはシーム１２３が形成される場合がある。 FIG. 10C illustrates the case where the conductor 252cC is formed over the conductor 252bE and the insulator 280 illustrated in FIG. 9C and the conductor 252dC is formed over the conductor 252cC. The conductors 252cC and 252dC fill the upper surface of the conductor 252bE and the recess formed on the upper surface of the insulator 280. Since the bottoms of the openings formed in the insulator 280 and the insulator 240 are filled with the conductor 252bE, the depth of the concave portion is shallower than the depth of the opening, and thus it is difficult to form a seam. A seam 123 may be formed at 252 dC.
導電体２５２ｃＣには、導電体２５２ａＡと同様の導電体を用いることができる。また、導電体２５２ｄＣには、導電体２５２ｂＡと同様の導電体を用いることができる。 For the conductor 252cC, a conductor similar to the conductor 252aA can be used. For the conductor 252dC, a conductor similar to the conductor 252bA can be used.
次に、図１１（Ａ）に示すように、絶縁体２８０上方に位置する導電体をＣＭＰ法を用いて除去し、導電体２５２ａ、導電体２５２ｂ、導電体２５２ｃ、および導電体２５２ｄからなる導電体２５２を形成する。 Next, as illustrated in FIG. 11A, the conductor located above the insulator 280 is removed by a CMP method, and a conductor including the conductor 252a, the conductor 252b, the conductor 252c, and the conductor 252d is formed. A body 252 is formed.
また、図１１（Ｂ）に示すように、必要に応じて導電体２５２上に導電体２５６ａ、導電体２５６ｂ、および導電体２５６ｃからなり、配線として機能する導電体２５６を形成してもよい。酸化物２３０と導電体２５６は、導電体２５２を介して電気的に接続される。 In addition, as illustrated in FIG. 11B, a conductor 256 that functions as a wiring and includes a conductor 256a, a conductor 256b, and a conductor 256c may be formed over the conductor 252 as needed. The oxide 230 and the conductor 256 are electrically connected through the conductor 252.
絶縁体２８０および絶縁体２７４に形成された開口の内部には、導電体２５２ａおよび導電体２５２ｃが設けられている。すなわち、導電性バリアとして機能する導電体が２層設けられている。導電性バリアを２層構造とすることで、絶縁体２８０中の不純物、あるいは以降の工程により生じる不純物が導電体２５２中を通って、トランジスタ２００へ混入することを、より効果的に抑制することができる。また、導電体２５２ｃは、外側の側面が導電体２５２ａの内側の側面と接するように設けられており、不純物混入の抑制効果が向上する。 Inside the openings formed in the insulator 280 and the insulator 274, a conductor 252a and a conductor 252c are provided. That is, two conductors functioning as a conductive barrier are provided. With the conductive barrier having a two-layer structure, it is possible to more effectively suppress impurities in the insulator 280 or impurities generated in the subsequent steps from entering the transistor 200 through the conductor 252. Can do. In addition, the conductor 252c is provided such that the outer side surface is in contact with the inner side surface of the conductor 252a, so that the effect of suppressing impurity contamination is improved.
＜トランジスタの作製方法＞
次に、本発明に係るトランジスタ２００を有する半導体装置について、作製方法を図１２乃至図２２を用いて説明する。また、図１２乃至図２３において、各図の（Ａ）は上面図を示す。また、各図の（Ｂ）は（Ａ）に示すＡ−Ｂの一点鎖線で示す部位に対応する断面図である。また、各図の（Ｃ）は、（Ａ）にＣ−Ｄの一点鎖線で示す部位に対応する断面図である。また、各図の（Ｄ）は、（Ａ）にＥ−Ｆの一点鎖線で示す部位に対応する断面図である。 <Method for Manufacturing Transistor>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. 12 to 23, (A) in each drawing shows a top view. Moreover, (B) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of AB shown to (A). Moreover, (C) of each figure is sectional drawing corresponding to the site | part shown by the dashed-dotted line of CD in (A). Moreover, (D) of each figure is sectional drawing corresponding to the site | part shown with the dashed-dotted line of EF in (A).
まず、基板（図示しない）を準備し、当該基板上に絶縁体２０８を成膜する。絶縁体２０８の成膜は、スパッタリング法、化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、分子線エピタキシー（ＭＢＥ：Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法、パルスレーザ堆積（ＰＬＤ：Ｐｕｌｓｅｄ　Ｌａｓｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法またはＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などを用いて行うことができる。 First, a substrate (not shown) is prepared, and an insulator 208 is formed over the substrate. The insulator 208 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an ALD (ALD) method. (Atomic Layer Deposition) method or the like can be used.
なお、ＣＶＤ法は、プラズマを利用するプラズマＣＶＤ（ＰＥＣＶＤ：Ｐｌａｓｍａ　Ｅｎｈａｎｃｅｄ　ＣＶＤ）法、熱を利用する熱ＣＶＤ（ＴＣＶＤ：Ｔｈｅｒｍａｌ　ＣＶＤ）法、光を利用する光ＣＶＤ（Ｐｈｏｔｏ　ＣＶＤ）法などに分類できる。さらに用いる原料ガスによって金属ＣＶＤ（ＭＣＶＤ：Ｍｅｔａｌ　ＣＶＤ）法、有機金属ＣＶＤ（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　ＣＶＤ）法に分けることができる。 In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.
プラズマＣＶＤ法は、比較的低温で高品質の膜が得られる。また、熱ＣＶＤ法は、プラズマを用いないため、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。例えば、半導体装置に含まれる配線、電極、素子（トランジスタ、容量素子など）などは、プラズマから電荷を受け取ることでチャージアップする場合がある。このとき、蓄積した電荷によって、半導体装置に含まれる配線、電極、素子などが破壊される場合がある。一方、プラズマを用いない熱ＣＶＤ法の場合、こういったプラズマダメージが生じないため、半導体装置の歩留まりを高くすることができる。また、熱ＣＶＤ法では、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.
また、ＡＬＤ法も、被処理物へのプラズマダメージを小さくすることが可能な成膜方法である。また、ＡＬＤ法も、成膜中のプラズマダメージが生じないため、欠陥の少ない膜が得られる。 The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
ＣＶＤ法およびＡＬＤ法は、ターゲットなどから放出される粒子が堆積する成膜方法とは異なり、被処理物の表面における反応により膜が形成される成膜方法である。したがって、被処理物の形状の影響を受けにくく、良好な段差被覆性を有する成膜方法である。特に、ＡＬＤ法は、優れた段差被覆性と、優れた厚さの均一性を有するため、アスペクト比の高い開口部の表面を被覆する場合などに好適である。ただし、ＡＬＤ法は、比較的成膜速度が遅いため、成膜速度の速いＣＶＤ法などの他の成膜方法と組み合わせて用いることが好ましい場合もある。 The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
ＣＶＤ法およびＡＬＤ法は、原料ガスの流量比によって、得られる膜の組成を制御することができる。例えば、ＣＶＤ法およびＡＬＤ法では、原料ガスの流量比によって、任意の組成の膜を成膜することができる。また、例えば、ＣＶＤ法およびＡＬＤ法では、成膜しながら原料ガスの流量比を変化させることによって、組成が連続的に変化した膜を成膜することができる。原料ガスの流量比を変化させながら成膜する場合、複数の成膜室を用いて成膜する場合と比べて、搬送や圧力調整に掛かる時間の分、成膜に掛かる時間を短くすることができる。したがって、半導体装置の生産性を高めることができる場合がある。 In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.
本実施の形態では、絶縁体２０８として、ＣＶＤ法によって酸化シリコンを成膜する。 In this embodiment, a silicon oxide film is formed as the insulator 208 by a CVD method.
次に、絶縁体２０８上に絶縁体２１０を形成する。本実施の形態では、絶縁体２１０として、スパッタリング法によって酸化アルミニウムを成膜する。また、絶縁体２１０は、多層構造としてもよい。例えばスパッタリング法によって酸化アルミニウムを成膜し、該酸化アルミニウム上にＡＬＤ法によって酸化アルミニウムを成膜する構造としてもよい。または、ＡＬＤ法によって酸化アルミニウムを成膜し、該酸化アルミニウム上に、スパッタリング法によって酸化アルミニウムを成膜する構造としてもよい。 Next, the insulator 210 is formed over the insulator 208. In this embodiment, an aluminum oxide film is formed as the insulator 210 by a sputtering method. The insulator 210 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, a structure in which an aluminum oxide film is formed by an ALD method and an aluminum oxide film is formed on the aluminum oxide by a sputtering method may be employed.
次に絶縁体２１０上に絶縁体２１２を成膜する。絶縁体２１２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２１６として、ＣＶＤ法によって酸化シリコンを成膜する。 Next, the insulator 212 is formed over the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.
次に、絶縁体２１２に開口を形成する。開口とは、例えば、溝やスリットなども含まれる。また、開口が形成された領域を指して開口部とする場合がある。開口の形成はウェットエッチングを用いてもよいが、ドライエッチングを用いるほうが微細加工には好ましい。また、絶縁体２１２に開口を形成する場合、絶縁体２１０は、絶縁体２１２をエッチングして溝を形成する際のエッチングストッパ膜として用いてもよい。例えば、溝を形成する絶縁体２１２に酸化シリコン膜を用いた場合は、エッチングストッパ膜として機能する絶縁膜として、絶縁体２１０は窒化シリコン膜、酸化アルミニウム膜、酸化ハフニウム膜を用いるとよい。 Next, an opening is formed in the insulator 212. The opening includes, for example, a groove and a slit. In some cases, the opening is pointed to a region where the opening is formed. Wet etching may be used to form the opening, but dry etching is preferable for fine processing. In the case where an opening is formed in the insulator 212, the insulator 210 may be used as an etching stopper film when the insulator 212 is etched to form a groove. For example, in the case where a silicon oxide film is used for the insulator 212 forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 210 as an insulating film functioning as an etching stopper film.
開口の形成後に、導電体２０３ａとなる導電膜を成膜する。該導電膜は、酸素の透過を抑制する機能を有する導電体を含むことが望ましい。たとえば、窒化タンタル、窒化タングステン、窒化チタンなどを用いることができる。またはタンタル、タングステン、チタン、モリブデン、アルミニウム、銅、モリブデンタングステン合金との積層膜とすることができる。導電体２０３ａとなる導電体の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 After the opening is formed, a conductive film to be the conductor 203a is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductor to be the conductor 203a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
本実施の形態では、導電体２０３ａとなる導電膜として、スパッタリング法によって窒化タンタルまたは、窒化タンタルの上に窒化チタンを積層した膜を成膜する。導電体２０３ａとしてこのような金属窒化物を用いることにより、後述する導電体２０３ｂで銅など拡散しやすい金属を用いても、当該金属が導電体２０３ａから外に拡散するのを防ぐことができる。 In this embodiment, as the conductive film to be the conductor 203a, tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the conductor 203a, it is possible to prevent the metal from diffusing out of the conductor 203a even when a metal that easily diffuses such as copper is used in the conductor 203b described later.
次に、導電体２０３ａとなる導電膜上に、導電体２０３ｂとなる導電膜を成膜する。該導電膜の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、メッキ法、ＰＬＤ法、およびＡＬＤ法などから選ばれた一つの方法または複数の方法を組み合わせて用いて行うことができる。本実施の形態では、導電体２０３ｂとなる導電膜として、タングステンや、銅などの低抵抗導電性材料を成膜する。 Next, a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a. The conductive film can be formed by using one method selected from a sputtering method, a CVD method, an MBE method, a plating method, a PLD method, an ALD method, or a combination of a plurality of methods. In this embodiment, a low-resistance conductive material such as tungsten or copper is formed as the conductive film to be the conductor 203b.
次に、ＣＭＰ処理を行うことで、導電体２０３ａとなる導電膜、ならびに導電体２０３ｂとなる導電膜の一部を除去し、絶縁体２１２を露出する。その結果、開口部のみに、導電体２０３ａとなる導電膜、ならびに導電体２０３ｂとなる導電膜が残存する。これにより、上面が平坦な、導電体２０３ａおよび導電体２０３ｂを含む導電体２０３を形成することができる（図１２参照。）。なお、当該ＣＭＰ処理により、絶縁体２１２の一部が除去される場合がある。 Next, by performing CMP treatment, the conductive film to be the conductor 203a and part of the conductive film to be the conductor 203b are removed, and the insulator 212 is exposed. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b having a flat upper surface can be formed (see FIG. 12). Note that part of the insulator 212 may be removed by the CMP treatment.
次に絶縁体２１２および導電体２０３上に絶縁体２１６を成膜する。絶縁体２１６の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。本実施の形態では、絶縁体２１６として、ＣＶＤ法によって酸化シリコンを成膜する。 Next, the insulator 216 is formed over the insulator 212 and the conductor 203. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.
次に、絶縁体２１６に開口を形成する。開口の形成はウェットエッチングを用いてもよいが、ドライエッチングを用いるほうが微細加工には好ましい。また、絶縁体２１６に開口を形成する場合、導電体２０３は、絶縁体２１６をエッチングして溝を形成する際のエッチングストッパ膜として用いてもよい。 Next, an opening is formed in the insulator 216. Wet etching may be used to form the opening, but dry etching is preferable for fine processing. In the case where an opening is formed in the insulator 216, the conductor 203 may be used as an etching stopper film when the insulator 216 is etched to form a groove.
開口の形成後に、＜導電体の作製方法１＞で説明した導電体２０５を形成する（図１２参照。）。 After the opening is formed, the conductor 205 described in <Conductor manufacturing method 1> is formed (see FIG. 12).
次に、絶縁体２１６、および導電体２０５上に絶縁体２２０を成膜する。絶縁体２２０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
次に、絶縁体２２０上に絶縁体２２２を成膜する。絶縁体２２２の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 Next, the insulator 222 is formed over the insulator 220. The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
特に、絶縁体２２２として、アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体を用いることが好ましい。アルミニウム及びハフニウムの一方または双方の酸化物を含む絶縁体として、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）などを用いることが好ましい。絶縁体２２２は、ＡＬＤ法により形成されることが好ましい。ＡＬＤ法により成膜された絶縁体２２２は、酸素、水素、および水に対するバリア性を有する。絶縁体２２２が、水素および水に対するバリア性を有することで、トランジスタ２００の周辺に設けられた構造体に含まれる水素、および水は、トランジスタ２００の内側へ拡散することなく、酸化物２３０中の酸素欠損の生成を抑制することができる。 In particular, as the insulator 222, an insulator including one or both of aluminum and hafnium is preferably used. As the insulator containing one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator 222 is preferably formed by an ALD method. The insulator 222 formed by the ALD method has a barrier property against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor 200 do not diffuse inside the transistor 200 and are contained in the oxide 230. Generation of oxygen vacancies can be suppressed.
次に、絶縁体２２２上に絶縁体２２４を成膜する。絶縁体２２４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる（図１３参照。）。 Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 13).
続いて、加熱処理を行うと好ましい。加熱処理は、２５０℃以上６５０℃以下、好ましくは３００℃以上５００℃以下、さらに好ましくは３２０℃以上４５０℃以下で行えばよい。第１の加熱処理は、窒素または不活性ガス雰囲気、または酸化性ガスを１０ｐｐｍ以上、１％以上もしくは１０％以上含む雰囲気で行う。第１の加熱処理は減圧状態で行ってもよい。または、第１の加熱処理は、窒素または不活性ガス雰囲気で加熱処理した後に、脱離した酸素を補うために酸化性ガスを１０ｐｐｍ以上、１％以上または１０％以上含む雰囲気で加熱処理を行ってもよい。 Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. The first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed in a reduced pressure state. Alternatively, in the first heat treatment, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. May be.
上記加熱処理によって、絶縁体２２４に含まれる水素や水などの不純物を除去することなどができる。 By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.
または、加熱処理として、減圧状態で酸素を含むプラズマ処理を行ってもよい。酸素を含むプラズマ処理は、例えばマイクロ波を用いた高密度プラズマを発生させる電源を有する装置を用いることが好ましい。または、基板側にＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）を印加する電源を有してもよい。高密度プラズマを用いることより高密度の酸素ラジカルを生成することができ、基板側にＲＦを印加することで高密度プラズマによって生成された酸素ラジカルを効率よく絶縁体２２４内に導くことができる。または、この装置を用いて不活性ガスを含むプラズマ処理を行った後に脱離した酸素を補うために酸素を含むプラズマ処理を行ってもよい。尚、第１の加熱処理は行わなくても良い場合がある。 Alternatively, plasma treatment containing oxygen in a reduced pressure state may be performed as the heat treatment. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224 by applying RF to the substrate side. Alternatively, plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.
また、加熱処理は、絶縁体２２０成膜後、および絶縁体２２２の成膜後のそれぞれに行うこともできる。該加熱処理は、上述した加熱処理条件を用いることができるが、絶縁体２２０成膜後の加熱処理は、窒素を含む雰囲気中で行うことが好ましい。 The heat treatment can also be performed after the insulator 220 is formed and after the insulator 222 is formed. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.
本実施の形態では、加熱処理として、絶縁体２２４成膜後に窒素雰囲気にて４００℃の温度で１時間の処理を行なう。 In this embodiment, as the heat treatment, treatment is performed for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere after the insulator 224 is formed.
次に、絶縁体２２４上に、酸化物２３０ａとなる酸化膜２３０Ａと、酸化物２３０ｂとなる酸化膜２３０Ｂを順に成膜する（図１３参照。）。なお、上記酸化膜は、大気環境にさらさずに連続して成膜することが好ましい。大気開放せずに成膜することで、酸化膜２３０Ａ、および酸化膜２３０Ｂ上に大気環境からの不純物または水分が付着することを防ぐことができ、酸化膜２３０Ａと酸化膜２３０Ｂとの界面近傍を清浄に保つことができる。 Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed over the insulator 224 (see FIG. 13). Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without opening to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be prevented. Can be kept clean.
酸化膜２３０Ａ、および酸化膜２３０Ｂの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
例えば、酸化膜２３０Ａ、および酸化膜２３０Ｂの成膜をスパッタリング法によって成膜する場合は、スパッタリングガスとして酸素、または、酸素と希ガスの混合ガスを用いる。スパッタリングガスに含まれる酸素の割合を高めることで、成膜される酸化膜中の過剰酸素を増やすことができる。また、上記の酸化膜の成膜をスパッタリング法によって成膜する場合は、上記のＩｎ−Ｍ−Ｚｎ酸化物ターゲットを用いることができる。 For example, in the case where the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the oxide film is formed by a sputtering method, the In-M-Zn oxide target can be used.
特に、酸化膜２３０Ａの成膜時に、スパッタリングガスに含まれる酸素の一部が絶縁体２２４に供給される場合がある。なお、酸化膜２３０Ａのスパッタリングガスに含まれる酸素の割合は７０％以上、好ましくは８０％以上、より好ましくは１００％とすればよい。 In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when the oxide film 230A is formed. Note that the ratio of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.
また、酸化膜２３０Ｂをスパッタリング法で形成する場合、スパッタリングガスに含まれる酸素の割合を１％以上３０％以下、好ましくは５％以上２０％以下として成膜すると、酸素欠乏型の酸化物半導体が形成される。酸素欠乏型の酸化物半導体を用いたトランジスタは、比較的高い電界効果移動度が得られる。 In the case where the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%. It is formed. A transistor including an oxygen-deficient oxide semiconductor can have a relatively high field-effect mobility.
本実施の形態では、酸化膜２３０Ａとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜する。また、酸化膜２３０Ｂとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］のターゲットを用いて成膜する。なお、各酸化膜は、成膜条件、および原子数比を適宜選択することで、酸化物２３０に求める特性に合わせて形成するとよい。 In this embodiment, the oxide film 230A is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. The oxide film 230B is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Note that each oxide film is preferably formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.
次に、加熱処理を行ってもよい。加熱処理は、上述した加熱処理条件を用いることができる。加熱処理によって、酸化膜２３０Ａ、および酸化膜２３０Ｂ中の水素や水などの不純物を除去することなどができる。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行なった後に、連続して酸素雰囲気にて４００℃の温度で１時間の処理を行う。 Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.
次に、酸化膜２３０Ａ、および酸化膜２３０Ｂを島状に加工して、酸化物２３０ａ、および酸化物２３０ｂを形成する（図１４参照。）。 Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 14).
なお、上記工程において、絶縁体２２４を島状に加工してもよい。また、絶縁体２２４に対しては、ハーフエッチングを行ってもよい。絶縁体２２４に対してハーフエッチングを行うことで、後の工程で形成する酸化物２３０ｃの下にも絶縁体２２４が残った状態で形成される。なお、絶縁体２２４は、後の工程である絶縁膜２７２Ａを加工する際に、島状に加工することができる。その場合、絶縁体２２２をエッチングストッパ膜として用いてもよい。 Note that in the above step, the insulator 224 may be processed into an island shape. Further, half etching may be performed on the insulator 224. By performing half etching on the insulator 224, the insulator 224 is formed in a state where the insulator 224 remains also under the oxide 230c formed in a later step. Note that the insulator 224 can be processed into an island shape when the insulating film 272A, which is a subsequent step, is processed. In that case, the insulator 222 may be used as an etching stopper film.
ここで、酸化物２３０ａ、および酸化物２３０ｂは、少なくとも一部が導電体２０５と重なるように形成する。また、酸化物２３０ａ、および酸化物２３０ｂの側面は、絶縁体２２２に対し、概略垂直であることが好ましい。酸化物２３０ａ、および酸化物２３０ｂの側面が、絶縁体２２２に対し、概略垂直であることで、複数のトランジスタ２００を設ける際に、小面積化、高密度化が可能となる。なお、酸化物２３０ａ、および酸化物２３０ｂの側面と絶縁体２２２の上面のなす角が鋭角になる構成にしてもよい。その場合、酸化物２３０ａ、および酸化物２３０ｂの側面と絶縁体２２２の上面のなす角は大きいほど好ましい。 Here, the oxide 230 a and the oxide 230 b are formed so as to overlap with the conductor 205 at least partially. The side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the insulator 222. Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the insulator 222, when the plurality of transistors 200 are provided, the area can be reduced and the density can be increased. Note that the angle formed between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.
また、酸化物２３０ａ、および酸化物２３０ｂの側面と、酸化物２３０ｂの上面との間に、湾曲面を有する。つまり、側面の端部と上面の端部は、湾曲していることが好ましい（以下、ラウンド状ともいう）。湾曲面は、例えば、酸化物２３０ａ、および酸化物２３０ｂの端部において、曲率半径が、３ｎｍ以上１０ｎｍ以下、好ましくは、５ｎｍ以上６ｎｍ以下とすることが好ましい。 In addition, a curved surface is provided between the side surfaces of the oxides 230a and 230b and the upper surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the upper surface are curved (hereinafter also referred to as a round shape). The curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, for example, at the ends of the oxide 230a and the oxide 230b.
なお、端部に角を有さないことで、以降の成膜工程における膜の被覆性が向上する。 In addition, the film | membrane coverage in a subsequent film-forming process improves by not having a corner | angular part in an edge part.
なお、当該酸化膜の加工はリソグラフィー法を用いて行えばよい。また、該加工はドライエッチング法やウェットエッチング法を用いることができる。ドライエッチング法による加工は微細加工に適している。 Note that the oxide film may be processed by a lithography method. In addition, a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.
なお、リソグラフィー法では、まず、マスクを介してレジストを露光する。次に、露光された領域を、現像液を用いて除去または残存させてレジストマスクを形成する。次に、当該レジストマスクを介してエッチング処理することで導電体、半導体または絶縁体などを所望の形状に加工することができる。例えば、ＫｒＦエキシマレーザ光、ＡｒＦエキシマレーザ光、ＥＵＶ（Ｅｘｔｒｅｍｅ　Ｕｌｔｒａ　ｖｉｏｌｅｔ）光などを用いて、レジストを露光することでレジストマスクを形成すればよい。また、基板と投影レンズとの間に液体（例えば水）を満たして露光する、液浸技術を用いてもよい。また、前述した光に代えて、電子ビームやイオンビームを用いてもよい。なお、電子ビームやイオンビームを用いる場合には、マスクは不要となる。なお、レジストマスクの除去には、アッシングなどのドライエッチング処理を行う、ウェットエッチング処理を行う、ドライエッチング処理後にウェットエッチング処理を行う、またはウェットエッチング処理後にドライエッチング処理を行うことができる。 In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultra violet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that a mask is not necessary when an electron beam or an ion beam is used. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
また、レジストマスクの代わりに絶縁体や導電体からなるハードマスクを用いてもよい。ハードマスクを用いる場合、酸化膜２３０Ｂ上にハードマスク材料となる絶縁膜や導電膜を形成し、その上にレジストマスクを形成し、ハードマスク材料をエッチングすることで所望の形状のハードマスクを形成することができる。酸化膜２３０Ａ、および酸化膜２３０Ｂのエッチングは、レジストマスクを除去してから行っても良いし、レジストマスクを残したまま行っても良い。後者の場合、エッチング中にレジストマスクが消失することがある。上記酸化膜のエッチング後にハードマスクをエッチングにより除去しても良い。一方、ハードマスクの材料が後工程に影響が無い、あるいは後工程で利用できる場合、必ずしもハードマスクを除去する必要は無い。 Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film to be a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the oxide film is etched. On the other hand, when the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.
ドライエッチング装置としては、平行平板型電極を有する容量結合型プラズマ（ＣＣＰ：Ｃａｐａｃｉｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置を用いることができる。平行平板型電極を有する容量結合型プラズマエッチング装置は、平行平板型電極の一方の電極に高周波電源を印加する構成でもよい。または平行平板型電極の一方の電極に複数の異なった高周波電源を印加する構成でもよい。または平行平板型電極それぞれに同じ周波数の高周波電源を印加する構成でもよい。または平行平板型電極それぞれに周波数の異なる高周波電源を印加する構成でもよい。または高密度プラズマ源を有するドライエッチング装置を用いることができる。高密度プラズマ源を有するドライエッチング装置は、例えば、誘導結合型プラズマ（ＩＣＰ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）エッチング装置などを用いることができる。 As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one electrode of the parallel plate electrode may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.
また、上記ドライエッチングなどの処理を行うことによって、エッチングガスなどに起因した不純物が酸化物２３０ａ、および酸化物２３０ｂなどの表面または内部に付着または拡散することがある。不純物としては、例えば、フッ素または塩素などがある。 In addition, by performing the treatment such as dry etching, impurities due to an etching gas or the like may adhere or diffuse on the surface or inside of the oxide 230a, the oxide 230b, or the like. Examples of impurities include fluorine and chlorine.
上記の不純物などを除去するために、洗浄を行う。洗浄方法としては、洗浄液など用いたウェット洗浄、プラズマを用いたプラズマ処理または、熱処理による洗浄などがあり、上記洗浄を適宜組み合わせて行ってもよい。 Cleaning is performed in order to remove the impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.
ウェット洗浄としては、シュウ酸、リン酸またはフッ化水素酸などを炭酸水または純水で希釈した水溶液を用いて洗浄処理を行ってもよい。または、純水または炭酸水を用いた超音波洗浄を行ってもよい。本実施の形態では、純水または炭酸水を用いた超音波洗浄を行う。 As the wet cleaning, a cleaning process may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.
続いて、加熱処理を行っても良い。加熱処理の条件は、前述の加熱処理の条件を用いることができる。 Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.
次に、絶縁体２２４、酸化物２３０ａ、および酸化物２３０ｂの上に、酸化膜２３０Ｃ、絶縁膜２５０Ａ、導電膜２６０Ａ、導電膜２６０Ｂ、絶縁膜２７０Ａ、および絶縁膜２７１Ａを順に成膜する（図１５参照。）。 Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, the conductive film 260B, the insulating film 270A, and the insulating film 271A are sequentially formed over the insulator 224, the oxide 230a, and the oxide 230b (FIG. 15).
酸化膜２３０Ｃの成膜はスパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。酸化物２３０ｃに求める特性に合わせて、酸化膜２３０Ａ、または酸化膜２３０Ｂと同様の成膜方法を用いて、酸化膜２３０Ｃを成膜すればよい。本実施の形態では、酸化膜２３０Ｃとして、スパッタリング法によって、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］のターゲットを用いて成膜する。 The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with characteristics required for the oxide 230c. In this embodiment, the oxide film 230C is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].
絶縁膜２５０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。 The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
なお、マイクロ波で酸素を励起し、高密度な酸素プラスマを発生させ、該酸素プラズマに絶縁膜２５０Ａを曝すことで、絶縁膜２５０Ａ、酸化物２３０ａ、酸化物２３０ｂ、および酸化膜２３０Ｃへ酸素を導入することができる。 Note that oxygen is excited by microwaves, high-density oxygen plasma is generated, and the insulating film 250A is exposed to the oxygen plasma, so that oxygen is supplied to the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.
また、加熱処理を行ってもよい。加熱処理は、前述の加熱処理条件を用いることができる。該加熱処理によって、絶縁膜２５０Ａの水分濃度および水素濃度を低減させることができる。 Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.
導電膜２６０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。本実施の形態では、導電膜２６０Ａとしてスパッタリング法を用いて窒化チタンを形成した。 The conductive film 260A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, titanium nitride is formed as the conductive film 260A by a sputtering method.
また、導電膜２６０Ｂは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。導電膜２６０Ｂとして、低抵抗の金属膜を積層することで、駆動電圧が小さなトランジスタを提供することができる。本実施の形態では、導電膜２６０Ｂとしてスパッタリング法を用いてタングステンを形成した。 The conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. By stacking a low-resistance metal film as the conductive film 260B, a transistor with a low driving voltage can be provided. In this embodiment, tungsten is formed as the conductive film 260B by a sputtering method.
また、絶縁膜２５０Ａと導電膜２６０Ａの間にさらに導電体を設けてもよい。当該導電体は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。ここで、例えば、酸化物２３０として用いることができる酸化物半導体は、低抵抗化処理を施すことで、導電性酸化物となる。そこで、酸化物２３０として用いることができる酸化物を成膜し、後の工程で該酸化物を低抵抗化してもよい。なお、絶縁膜２５０Ａ上に、酸化物２３０として用いることができる酸化物を、酸素を含む雰囲気において、スパッタリング法を用いて成膜することで、絶縁膜２５０Ａに酸素を添加することができる。絶縁膜２５０Ａに酸素を添加することで、添加された酸素は、絶縁膜２５０Ａを介して、酸化物２３０に酸素を供給することが可能となる。 Further, a conductor may be further provided between the insulating film 250A and the conductive film 260A. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, for example, an oxide semiconductor that can be used as the oxide 230 becomes a conductive oxide by performing resistance reduction treatment. Thus, an oxide that can be used as the oxide 230 may be formed, and the resistance of the oxide may be reduced in a later step. Note that oxygen can be added to the insulating film 250A by forming an oxide that can be used as the oxide 230 over the insulating film 250A by a sputtering method in an atmosphere containing oxygen. By adding oxygen to the insulating film 250A, the added oxygen can supply oxygen to the oxide 230 through the insulating film 250A.
続いて、加熱処理を行うことができる。加熱処理は、前述の加熱処理条件を用いることができる。なお、加熱処理は行わなくてもよい場合がある。本実施の形態では、窒素雰囲気にて４００℃の温度で１時間の処理を行う。 Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed. In this embodiment, treatment is performed at a temperature of 400 ° C. for 1 hour in a nitrogen atmosphere.
絶縁膜２７０Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。絶縁膜２７０Ａは、バリア膜として機能するため、水または水素などの不純物、および酸素の透過を抑制する機能を有する絶縁性材料を用いる。例えば、酸化アルミニウム、酸化ハフニウム、またはハフニウムアルミネートなどを用いることが好ましい。これにより、導電体２６０の酸化を防ぐことができる。また、導電体２６０および絶縁体２５０を介して、水または水素などの不純物が酸化物２３０に混入することを防ぐことができる。 The insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, it is preferable to use aluminum oxide, hafnium oxide, hafnium aluminate, or the like. Thereby, oxidation of the conductor 260 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.
絶縁膜２７１Ａは、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて成膜することができる。ここで、絶縁膜２７１Ａの膜厚は、後の工程で成膜する絶縁膜２７２Ａの膜厚より厚くすることが好ましい。これにより、後の工程で絶縁体２７２を形成する際、導電体２６０の上に絶縁体２７１を、容易に残存させることができる。 The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A to be formed in a later step. Accordingly, when the insulator 272 is formed in a later step, the insulator 271 can be easily left on the conductor 260.
また、絶縁体２７１は、ハードマスクとして機能する。絶縁体２７１を設けることで、絶縁体２５０の側面、導電体２６０ａの側面、導電体２６０ｂの側面、および絶縁体２７０の側面を、基板に対し、概略垂直に形成することができる。 The insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the insulator 250, the side surface of the conductor 260 a, the side surface of the conductor 260 b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.
次に、絶縁膜２７１Ａを、エッチングし、絶縁体２７１を形成する。続いて、絶縁体２７１をマスクとして、絶縁膜２５０Ａ、導電膜２６０Ａ、導電膜２６０Ｂ、および絶縁膜２７０Ａを、エッチングし、絶縁体２５０、導電体２６０（導電体２６０ａ、導電体２６０ｂ）、および絶縁体２７０を形成する（図１６参照。）。なお、当該加工後も、絶縁体２７１は除去せずに後工程を進めてもよい。絶縁体２７１は、後工程で実施されるドーパントの添加においてもハードマスクとして機能することができる。 Next, the insulating film 271A is etched to form the insulator 271. Subsequently, using the insulator 271 as a mask, the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form the insulator 250, the conductor 260 (conductor 260a, conductor 260b), and the insulating film. A body 270 is formed (see FIG. 16). Note that a post-process may be performed without removing the insulator 271 even after the processing. The insulator 271 can function as a hard mask even when a dopant is added in a later step.
また、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面は、同一面内であることが好ましい。また、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面が共有する同一面は、基板に対し、概略垂直であることが好ましい。つまり、断面形状において、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面は、酸化物２３０の上面に対する角度が、鋭角、かつ大きいほど好ましい。なお、断面形状において、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面と、絶縁体２５０と接する酸化物２３０の上面のなす角が鋭角になる構成にしてもよい。その場合、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面と、絶縁体２５０と接する酸化物２３０の上面のなす角は大きいほど好ましい。 In addition, the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably in the same plane. In addition, the same surface shared by the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 is preferably substantially perpendicular to the substrate. That is, in the cross-sectional shape, the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably as acute and large as possible with respect to the top surface of the oxide 230. Note that a cross-sectional shape of the side surface of the insulator 250, the side surface of the conductor 260, the side surface of the insulator 270, and the top surface of the oxide 230 in contact with the insulator 250 may be an acute angle. In that case, the angle formed by the side surface of the insulator 250, the side surface of the conductor 260, the side surface of the insulator 270, and the top surface of the oxide 230 in contact with the insulator 250 is preferably as large as possible.
また、絶縁体２５０、導電体２６０、および絶縁体２７０は、少なくとも一部が、導電体２０５および酸化物２３０と重なるように形成する。 The insulator 250, the conductor 260, and the insulator 270 are formed so that at least a part thereof overlaps with the conductor 205 and the oxide 230.
また、上記エッチングにより、酸化膜２３０Ｃの絶縁体２５０と重ならない領域の上部がエッチングされる場合がある。この場合、酸化膜２３０Ｃの絶縁体２５０と重なる領域の膜厚が、絶縁体２５０と重ならない領域の膜厚より厚くなる場合がある。 In addition, the etching may etch the upper portion of the region of the oxide film 230C that does not overlap with the insulator 250. In this case, the thickness of the region of the oxide film 230C that overlaps with the insulator 250 may be larger than the thickness of the region that does not overlap with the insulator 250.
次に、酸化膜２３０Ｃ、絶縁体２５０、導電体２６０、絶縁体２７０、および絶縁体２７１を覆って、絶縁膜２７２Ａを成膜する（図１７参照。）。絶縁膜２７２Ａとして、被覆性に優れたＡＬＤ法により成膜することが好ましい。ＡＬＤ法を用いることで、導電体２６０などにより形成された段差部においても、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面に対して、均一な厚さを有する絶縁膜２７２Ａを形成することができる。 Next, an insulating film 272A is formed to cover the oxide film 230C, the insulator 250, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 17). The insulating film 272A is preferably formed by an ALD method with excellent coverage. By using the ALD method, an insulating film having a uniform thickness with respect to the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 even in the step portion formed by the conductor 260 and the like. 272A can be formed.
次に、絶縁膜２７２Ａに異方性のエッチング処理を行い、絶縁体２５０の側面、導電体２６０の側面、および絶縁体２７０の側面に接して、絶縁体２７２を形成する（図１８参照。）。異方性のエッチング処理としては、ドライエッチング処理を行うことが好ましい。これにより、基板面に略平行な面に成膜された該絶縁膜を除去して、絶縁体２７２を自己整合的に形成することができる。 Next, anisotropic etching is performed on the insulating film 272A, so that the insulator 272 is formed in contact with the side surface of the insulator 250, the side surface of the conductor 260, and the side surface of the insulator 270 (see FIG. 18). . As an anisotropic etching process, it is preferable to perform a dry etching process. Thus, the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.
ここで、絶縁体２７０上に絶縁体２７１を形成しておくことで、絶縁体２７０上部の絶縁膜２７２Ａが除去されても、絶縁体２７１がマスクとなり、絶縁体２７０を残存させることができる。また、絶縁体２５０、導電体２６０、絶縁体２７０、および絶縁体２７１からなる構造体の高さを、酸化物２３０ａ、酸化物２３０ｂ、および酸化膜２３０Ｃの高さよりも、高くすることで、酸化膜２３０Ｃを介した酸化物２３０ａ、酸化物２３０ｂの側面の絶縁膜２７２Ａを、除去することができる。さらに、酸化物２３０ａ、酸化物２３０ｂの端部をラウンド形状にしておくと、酸化物２３０ａ、酸化物２３０ｂの側面に、酸化膜２３０Ｃを介して成膜された絶縁膜２７２Ａを除去するための時間が短縮され、より容易に絶縁体２７２を形成することができる。 Here, by forming the insulator 271 over the insulator 270, even if the insulating film 272A over the insulator 270 is removed, the insulator 271 can serve as a mask and the insulator 270 can remain. Further, the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 is set higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C, thereby oxidizing the oxide. The insulating film 272A on the side surfaces of the oxide 230a and the oxide 230b through the film 230C can be removed. Further, when the end portions of the oxides 230a and 230b are rounded, the time for removing the insulating film 272A formed on the side surfaces of the oxides 230a and 230b with the oxide film 230C interposed therebetween And the insulator 272 can be formed more easily.
次に、絶縁体２５０、導電体２６０、絶縁体２７０、絶縁体２７１、および絶縁体２７２をマスクとして、酸化膜２３０Ｃをエッチングし、酸化膜２３０Ｃの一部を除去し、酸化物２３０ｃを形成する（図１９参照。）。なお、本工程により、酸化物２３０ｂの上面および側面の一部と、酸化物２３０ａの側面の一部が除去される場合がある。 Next, using the insulator 250, the conductor 260, the insulator 270, the insulator 271, and the insulator 272 as a mask, the oxide film 230C is etched, and part of the oxide film 230C is removed to form the oxide 230c. (See FIG. 19.) Note that in this step, part of the top surface and side surfaces of the oxide 230b and part of side surfaces of the oxide 230a may be removed.
ここで、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃにおいて、図２に示すように、領域２３１、接合領域２３２、および領域２３４を形成してもよい。領域２３１、および接合領域２３２は、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃとして設けられた金属酸化物に、インジウムなどの金属原子、または不純物を添加し、低抵抗化した領域である。なお、各領域は、少なくとも、領域２３４における酸化物２３０ｂよりも、導電性が高い。 Here, in the oxide 230a, the oxide 230b, and the oxide 230c, as illustrated in FIG. 2, a region 231, a junction region 232, and a region 234 may be formed. The region 231 and the junction region 232 are regions in which a metal atom such as indium or an impurity is added to a metal oxide provided as the oxide 230a, the oxide 230b, and the oxide 230c to reduce resistance. Note that each region has higher conductivity than at least the oxide 230b in the region 234.
領域２３１および接合領域２３２を低抵抗化するために、例えば、インジウムなどの金属元素、および不純物の少なくとも一であるドーパントを添加すればよい。 In order to reduce the resistance of the region 231 and the junction region 232, for example, a metal element such as indium and a dopant that is at least one of impurities may be added.
なお、ドーパントの添加方法としては、イオン化された原料ガスを質量分離して添加するイオン注入法、イオン化された原料ガスを質量分離せずに添加するイオンドーピング法、プラズマイマージョンイオンインプランテーション法などを用いることができる。質量分離を行う場合、添加するイオン種およびその濃度を厳密に制御することができる。一方、質量分離を行わない場合、短時間で高濃度のイオンを添加することができる。また、原子または分子のクラスターを生成してイオン化するイオンドーピング法を用いてもよい。なお、ドーパントを、イオン、ドナー、アクセプター、不純物または元素などと言い換えてもよい。 The dopant is added by an ion implantation method in which ionized source gas is added by mass separation, an ion doping method in which ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like. Can be used. When mass separation is performed, the ionic species to be added and the concentration thereof can be strictly controlled. On the other hand, when mass separation is not performed, high-concentration ions can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be used. Note that the dopant may be referred to as an ion, a donor, an acceptor, an impurity, an element, or the like.
また、ドーパントは、プラズマ処理にて添加されてもよい。この場合、プラズマＣＶＤ装置、ドライエッチング装置、アッシング装置を用いてプラズマ処理を行い、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃにドーパントを添加することができる。 Further, the dopant may be added by plasma treatment. In this case, plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, or an ashing apparatus, and the dopant can be added to the oxides 230a, 230b, and 230c.
また、不純物をドーパントとして添加する場合、領域２３１に接するようにドーパントを含む膜を成膜してもよい。例えば、ドーパントとして水素、ホウ素、炭素、窒素、フッ素、またはリンなどを含む絶縁体２７４を酸化物２３０の領域２３１に接するように成膜する（図２０参照。）。絶縁体２７４の成膜や成膜後の熱処理により、領域２３１は低抵抗化し、接合領域２３２が形成される。絶縁体２７４に含まれるドーパントが領域２３１および接合領域２３２へ拡散し、当該領域は低抵抗化すると考えられる。 In addition, when an impurity is added as a dopant, a film containing the dopant may be formed so as to be in contact with the region 231. For example, an insulator 274 containing hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, or the like as a dopant is formed so as to be in contact with the region 231 of the oxide 230 (see FIG. 20). By the film formation of the insulator 274 and the heat treatment after the film formation, the resistance of the region 231 is reduced and the bonding region 232 is formed. It is considered that the dopant contained in the insulator 274 diffuses into the region 231 and the junction region 232 and the region has a low resistance.
酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃは、インジウムの含有率を高くすることで、キャリア密度を高くし、低抵抗化を図ることができる。よって、ドーパントとして酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃのキャリア密度を向上させるインジウムなどの金属元素を用いることができる。 The oxide 230a, the oxide 230b, and the oxide 230c can have high carrier density and low resistance by increasing the content of indium. Therefore, a metal element such as indium that improves the carrier density of the oxide 230a, the oxide 230b, and the oxide 230c can be used as the dopant.
つまり、領域２３１、および接合領域２３２において、酸化物２３０ａ、酸化物２３０ｂ、および酸化物２３０ｃのインジウムなどの金属原子の含有率を高くすることで、電子移動度を高くし、低抵抗化を図ることができる。 That is, in the region 231 and the junction region 232, the content of metal atoms such as indium in the oxide 230a, the oxide 230b, and the oxide 230c is increased, so that the electron mobility is increased and the resistance is reduced. be able to.
従って、少なくとも領域２３１における元素Ｍに対するインジウムの原子数の比が、領域２３４の元素Ｍに対するインジウムの原子数の比よりも大きくなる。 Accordingly, at least the ratio of the number of indium atoms to the element M in the region 231 is larger than the ratio of the number of indium atoms to the element M in the region 234.
また、ドーパントとしては、上述の酸素欠損を形成する元素、または酸素欠損に捕獲される元素などを用いればよい。このような元素としては、代表的には水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が挙げられる。また、希ガス元素の代表例としては、ヘリウム、ネオン、アルゴン、クリプトン、及びキセノン等がある。 As the dopant, the above-described element that forms oxygen vacancies or an element that is trapped by oxygen vacancies may be used. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.
また、トランジスタ２００において、接合領域２３２を設けることで、ソース領域およびドレイン領域として機能する領域２３１と、チャネルが形成される領域２３４との間に高抵抗領域が形成されないため、トランジスタのオン電流、および移動度を大きくすることができる。また、接合領域２３２を有することで、チャネル長方向において、ソース領域およびドレイン領域と、ゲートとが重ならないため、不要な容量が形成されるのを抑制することができる。また、接合領域２３２を有することで、非導通時のリーク電流を小さくすることができる。 In the transistor 200, since the junction region 232 is provided, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; And mobility can be increased. In addition, since the junction region 232 includes the source region and the drain region and the gate do not overlap with each other in the channel length direction, formation of unnecessary capacitance can be suppressed. In addition, since the junction region 232 is provided, leakage current at the time of non-conduction can be reduced.
従って、領域２３１ａ、および領域２３１ｂの範囲を適宜選択することにより、回路設計に合わせて、要求に見合う電気特性を有するトランジスタを容易に提供することができる。 Therefore, by appropriately selecting the range of the region 231a and the region 231b, a transistor having electrical characteristics that meet requirements can be easily provided in accordance with circuit design.
本実施の形態では、絶縁体２２４、酸化物２３０、絶縁体２７１、および絶縁体２７２を覆って、絶縁体２７４を成膜する（図２０参照。）。 In this embodiment, the insulator 274 is formed to cover the insulator 224, the oxide 230, the insulator 271, and the insulator 272 (see FIG. 20).
絶縁体２７４として、例えばＣＶＤ法を用いて形成した、窒化シリコン、窒化酸化シリコン、酸化窒化シリコンを用いることができる。本実施の形態では、絶縁体２７４として、窒化酸化シリコンを用いる。 As the insulator 274, for example, silicon nitride, silicon nitride oxide, or silicon oxynitride formed by a CVD method can be used. In this embodiment, silicon nitride oxide is used as the insulator 274.
酸化物２３０に接して、窒素などの不純物となる元素を含む絶縁体２７４を成膜することで、領域２３１ａ、および領域２３１ｂは、絶縁体２７４の成膜雰囲気に含まれる、水素または窒素などの不純物元素が添加される。酸化物２３０の絶縁体２７４と接する領域を中心に、添加された不純物元素により酸素欠損が形成され、さらに当該不純物元素が酸素欠損に入り込むことで、キャリア密度が高くなり、低抵抗化される。その際、絶縁体２７４と接しない接合領域２３２にも不純物が拡散することで、低抵抗化される。 By forming the insulator 274 containing an element that becomes an impurity such as nitrogen in contact with the oxide 230, the region 231a and the region 231b can be formed in a film formation atmosphere of the insulator 274 such as hydrogen or nitrogen. Impurity elements are added. Oxygen vacancies are formed by the added impurity element around the region in contact with the insulator 274 of the oxide 230, and the impurity element enters the oxygen vacancies, whereby the carrier density is increased and the resistance is reduced. At that time, the impurity diffuses also in the junction region 232 that is not in contact with the insulator 274, so that the resistance is reduced.
よって、領域２３１ａ、および領域２３１ｂは、領域２３４より、水素および窒素の少なくとも一方の濃度が大きくなることが好ましい。水素または窒素の濃度は、二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）などを用いて測定すればよい。ここで、領域２３４の水素または窒素の濃度としては、酸化物２３０ｂの絶縁体２５０と重なる領域の中央近傍（例えば、酸化物２３０ｂにおいて、絶縁体２５０のチャネル長方向の両側面からの距離が概略等しい部分と重なる部分）の水素または窒素の濃度を測定すればよい。 Therefore, it is preferable that the concentration of at least one of hydrogen and nitrogen be higher in the region 231a and the region 231b than in the region 234. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like. Here, as the concentration of hydrogen or nitrogen in the region 234, the distance from the vicinity of the center of the region overlapping the insulator 250 of the oxide 230b (for example, the distance from both side surfaces in the channel length direction of the insulator 250 in the oxide 230b) is approximately. What is necessary is just to measure the density | concentration of hydrogen or nitrogen of the part overlapped with an equal part.
なお、領域２３１、および接合領域２３２は、酸素欠損を形成する元素、または酸素欠損に捕獲される元素を添加されることで低抵抗化される。このような元素としては、代表的には水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が挙げられる。また、希ガス元素の代表例としては、ヘリウム、ネオン、アルゴン、クリプトン、及びキセノン等がある。よって、領域２３１、および接合領域２３２は、上記元素の一つまたは複数を含む構成にすればよい。 Note that the resistance of the region 231 and the junction region 232 is reduced by adding an element that forms oxygen vacancies or an element that is captured by oxygen vacancies. Examples of such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the region 231 and the bonding region 232 may have a structure including one or more of the above elements.
または、絶縁体２７４として、領域２３１、および接合領域２３２に含まれる酸素を引き抜き、吸収する膜を用いてもよい。酸素が引き抜かれると、領域２３１、および接合領域２３２には酸素欠損が生じる。酸素欠損に水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が捕獲されることにより、領域２３１、および接合領域２３２は低抵抗化する。 Alternatively, as the insulator 274, a film that extracts and absorbs oxygen contained in the region 231 and the bonding region 232 may be used. When oxygen is extracted, oxygen vacancies are generated in the region 231 and the junction region 232. When hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like is trapped in the oxygen vacancies, the resistance of the region 231 and the junction region 232 is reduced.
不純物となる元素を含む絶縁体、あるいは酸化物２３０から酸素を引き抜く絶縁体として絶縁体２７４を成膜する場合、絶縁体２７４の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。 In the case where the insulator 274 is formed as an insulator including an element serving as an impurity or an insulator from which oxygen is extracted from the oxide 230, the insulator 274 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD. This can be done using methods.
不純物となる元素を含む絶縁体２７４の成膜は、窒素または水素の少なくとも一方を含む雰囲気で行うことが好ましい。このような雰囲気で成膜を行うことで、酸化物２３０ｂおよび酸化物２３０ｃの絶縁体２５０と重ならない領域を中心に、酸素欠損を形成し、当該酸素欠損と窒素または水素などの不純物元素を結合させて、キャリア密度を高くすることができる。このようにして、低抵抗化された、領域２３１ａおよび領域２３１ｂを形成することができる。絶縁体２７４として、例えばＣＶＤ法を用いて、窒化シリコン、窒化酸化シリコン、酸化窒化シリコンを用いることができる。本実施の形態では、絶縁体２７４として、窒化酸化シリコンを用いる。 The insulator 274 including the element serving as an impurity is preferably formed in an atmosphere containing at least one of nitrogen and hydrogen. By performing deposition in such an atmosphere, oxygen vacancies are formed around the oxide 230b and the oxide 250c that do not overlap with the insulator 250, and the oxygen vacancies are bonded to an impurity element such as nitrogen or hydrogen. Thus, the carrier density can be increased. In this manner, the region 231a and the region 231b with reduced resistance can be formed. As the insulator 274, silicon nitride, silicon nitride oxide, or silicon oxynitride can be used by, for example, a CVD method. In this embodiment, silicon nitride oxide is used as the insulator 274.
従って、絶縁体２７４の成膜により、ソース領域およびドレイン領域を自己整合的に形成することができる。よって、微細化または高集積化された半導体装置も、歩留まり良く製造することができる。 Therefore, the source region and the drain region can be formed in a self-aligned manner by forming the insulator 274. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.
ここで、導電体２６０の上面および側面、および絶縁体２５０の側面を、絶縁体２７０および絶縁体２７２で覆っておくことで、窒素または水素などの不純物元素が、導電体２６０および絶縁体２５０に混入することを防ぐことができる。これにより、窒素または水素などの不純物元素が、導電体２６０および絶縁体２５０を通って、トランジスタ２００のチャネル形成領域として機能する領域２３４に混入することを防ぐことができる。従って、良好な電気特性を有するトランジスタ２００を提供することができる。 Here, by covering the top surface and the side surface of the conductor 260 and the side surface of the insulator 250 with the insulator 270 and the insulator 272, an impurity element such as nitrogen or hydrogen is transferred to the conductor 260 and the insulator 250. Mixing can be prevented. Thus, an impurity element such as nitrogen or hydrogen can be prevented from entering the region 234 functioning as a channel formation region of the transistor 200 through the conductor 260 and the insulator 250. Therefore, the transistor 200 having favorable electrical characteristics can be provided.
なお、上記において、絶縁体２７４の成膜により酸化物２３０を低抵抗化することで、領域２３１、接合領域２３２、および領域２３４を形成したが、本実施の形態はこれに限られるものではない。例えば、ドーパントの添加処理、またはプラズマ処理を用いてもよいし、これらを複数組み合わせて、領域２３１、接合領域２３２、および領域２３４を形成してもよい。 Note that in the above, the region 231, the junction region 232, and the region 234 are formed by reducing the resistance of the oxide 230 by forming the insulator 274, but this embodiment is not limited to this. . For example, a dopant addition treatment or plasma treatment may be used, or a plurality of these may be combined to form the region 231, the junction region 232, and the region 234.
例えば、絶縁体２５０、導電体２６０、絶縁体２７２、絶縁体２７０、および絶縁体２７１をマスクとして、酸化物２３０にプラズマ処理を行ってもよい。プラズマ処理は、上述の酸素欠損を形成する元素、または酸素欠損に捕獲される元素を含む雰囲気などで行えばよい。例えば、アルゴンガスと窒素ガスを用いてプラズマ処理を行えばよい。 For example, plasma treatment may be performed on the oxide 230 using the insulator 250, the conductor 260, the insulator 272, the insulator 270, and the insulator 271 as a mask. The plasma treatment may be performed in an atmosphere containing an element that forms oxygen vacancies or an element trapped by oxygen vacancies. For example, plasma treatment may be performed using argon gas and nitrogen gas.
続いて、加熱処理を行うことができる。加熱処理は、前述の加熱処理条件を用いることができる。加熱処理を行うことで、添加されたドーパントが、酸化物２３０の接合領域２３２へと拡散し、オン電流を大きくすることができる。 Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By performing the heat treatment, the added dopant diffuses into the junction region 232 of the oxide 230, so that the on-state current can be increased.
次に、絶縁体２７４の上に、絶縁体２８０を成膜する（図２１参照。）。絶縁体２８０の成膜は、スパッタリング法、ＣＶＤ法、ＭＢＥ法、ＰＬＤ法またはＡＬＤ法などを用いて行うことができる。または、スピンコート法、ディップ法、液滴吐出法（インクジェット法など）、印刷法（スクリーン印刷、オフセット印刷など）、ドクターナイフ法、ロールコーター法またはカーテンコーター法などを用いて行うことができる。本実施の形態では、該絶縁膜として、酸化窒化シリコンを用いる。 Next, the insulator 280 is formed over the insulator 274 (see FIG. 21). The insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used. In this embodiment, silicon oxynitride is used as the insulating film.
なお、絶縁体２８０は、上面が平坦性を有するように形成することが好ましい。例えば、絶縁体２８０は、絶縁体２８０となる絶縁膜として成膜した直後に上面が平坦性を有していてもよい。または、例えば、絶縁体２８０は、成膜後に基板裏面などの基準面と平行になるよう絶縁体などを上面から除去していくことで平坦性を有してもよい。このような処理を、平坦化処理と呼ぶ。平坦化処理としては、ＣＭＰ処理、ドライエッチング処理などがある。本実施の形態では、平坦化処理として、ＣＭＰ処理を用いる。ただし、絶縁体２８０の上面は必ずしも平坦性を有さなくてもよい。 Note that the insulator 280 is preferably formed so that an upper surface thereof has flatness. For example, the top surface of the insulator 280 may have flatness immediately after being formed as an insulating film to be the insulator 280. Alternatively, for example, the insulator 280 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. Note that the top surface of the insulator 280 is not necessarily flat.
次に、絶縁体２８０、および絶縁体２７４に酸化物２３０の領域２３１に達する開口、絶縁体２８０、絶縁体２７４、絶縁体２７１、および絶縁体２７０に導電体２６０に達する開口、絶縁体２８０、絶縁体２７４、絶縁体２２４、絶縁体２２２、および絶縁体２２０に導電体２０５に達する開口を形成する。当該開口の形成は、リソグラフィー法を用いて行えばよい。 Next, the insulator 280 and an opening reaching the region 231 of the oxide 230 in the insulator 274, the insulator 280, the insulator 274, the insulator 271, and the opening reaching the conductor 260 in the insulator 270, the insulator 280, An opening reaching the conductor 205 is formed in the insulator 274, the insulator 224, the insulator 222, and the insulator 220. The opening may be formed using a lithography method.
なお、導電体２５２１、および導電体２５２２が酸化物２３０の側面に接して設けられるように、酸化物２３０に達する開口において、酸化物２３０の側面が露出するように、当該開口を形成する。 Note that the opening is formed so that the side surface of the oxide 230 is exposed in the opening reaching the oxide 230 so that the conductor 2521 and the conductor 2522 are provided in contact with the side surface of the oxide 230.
次に、＜導電体の作製方法２＞で説明した導電体２５２（導電体２５２１、導電体２５２２、導電体２５２３、導電体２５２４）を形成する（図２３参照。）。また、必要に応じて導電体２５２と電気的に接続する導電体２５６を形成してもよい（図１参照。）。 Next, the conductor 252 (the conductor 2521, the conductor 2522, the conductor 2523, and the conductor 2524) described in <Conductor manufacturing method 2> is formed (see FIG. 23). Further, a conductor 256 that is electrically connected to the conductor 252 may be formed as needed (see FIG. 1).
以上により、トランジスタ２００を有する半導体装置を作製することができる。図１２乃至図２２に示すように、本実施の形態に示す半導体装置の作製方法を用いることで、トランジスタ２００を作成することができる。 Through the above steps, a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 12 to 22, the transistor 200 can be manufactured using the method for manufacturing the semiconductor device described in this embodiment.
＜導電体の作製方法１＞または＜導電体の作製方法２＞に示す方法を用いて導電体２０５および導電体２５２を作製することにより、導電体２０５および導電体２５２の表面には、キーホールなどの凹凸による形状不良を抑制することができる。 By manufacturing the conductor 205 and the conductor 252 using the method shown in <Method 1 for manufacturing a conductor> or <Method 2 for manufacturing a conductor>, a keyhole is formed on the surfaces of the conductor 205 and the conductor 252. It is possible to suppress shape defects due to unevenness.
なお、本実施の形態では、導電体２０５および導電体２５２において、導電性バリア膜を複数設ける構成について説明したが、これに限らない。半導体装置において必要とされる特性や仕様に応じて、導電体２０５および導電体２５２の少なくとも一方において、導電性バリア膜を複数設ける構成とすればよい。 Note that although a structure in which a plurality of conductive barrier films are provided in the conductor 205 and the conductor 252 has been described in this embodiment, the present invention is not limited thereto. A plurality of conductive barrier films may be provided in at least one of the conductor 205 and the conductor 252 in accordance with characteristics and specifications required for the semiconductor device.
本発明の一態様により、微細化または高集積化が可能な半導体装置を提供することができる。または、本発明の一態様により、良好な電気特性を有する半導体装置を提供することができる。または、本発明の一態様により、オフ電流の小さい半導体装置を提供することができる。または、本発明の一態様により、オン電流の大きいトランジスタを提供することができる。または、本発明の一態様により、信頼性の高い半導体装置を提供することができる。または、本発明の一態様により、消費電力が低減された半導体装置を提供することができる。または、本発明の一態様により、生産性の高い半導体装置を提供することができる。 According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.
以上、本実施の形態に示す構成、方法などは、他の実施の形態に示す構成、方法などと適宜組み合わせて用いることができる。 The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
（実施の形態２）
本実施の形態では、半導体装置の一形態を、図２３を用いて説明する。 (Embodiment 2)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.
［記憶装置１］
図２３に示す記憶装置は、トランジスタ２００、容量素子１００、およびトランジスタ３００と、を有している。 [Storage device 1]
The memory device illustrated in FIG. 23 includes the transistor 200, the capacitor 100, and the transistor 300.
トランジスタ２００は、酸化物半導体を有する半導体層にチャネルが形成されるトランジスタである。トランジスタ２００は、オフ電流が小さいため、これを記憶装置に用いることにより長期にわたり記憶内容を保持することが可能である。つまり、リフレッシュ動作を必要としない、あるいは、リフレッシュ動作の頻度が極めて少ないため、記憶装置の消費電力を十分に低減することができる。 The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, stored data can be held for a long time by using the transistor 200 for a memory device. That is, the refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced.
図２３に示す記憶装置において、配線３００１はトランジスタ３００のソースと電気的に接続され、配線３００２はトランジスタ３００のドレインと電気的に接続されている。また、配線３００３はトランジスタ２００のソースおよびドレインの一方と電気的に接続され、配線３００４はトランジスタ２００の第１のゲートと電気的に接続され、配線３００６はトランジスタ２００の第２のゲートと電気的に接続されている。そして、トランジスタ３００のゲート、およびトランジスタ２００のソースおよびドレインの他方は、容量素子１００の電極の一方と電気的に接続され、配線３００５は容量素子１００の電極の他方と電気的に接続されている。 In the memory device illustrated in FIG. 23, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 3004 is electrically connected to the first gate of the transistor 200, and the wiring 3006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .
図２３に示す記憶装置は、トランジスタ３００のゲートの電位が保持可能という特性を有することで、以下に示すように、情報の書き込み、保持、読み出しが可能である。 The memory device illustrated in FIG. 23 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read as described below.
情報の書き込みおよび保持について説明する。まず、第４の配線３００４の電位を、トランジスタ２００が導通状態となる電位にして、トランジスタ２００を導通状態とする。これにより、第３の配線３００３の電位が、トランジスタ３００のゲート、および容量素子１００の電極の一方と電気的に接続するノードＦＧに与えられる。即ち、トランジスタ３００のゲートには、所定の電荷が与えられる（書き込み）。ここでは、異なる二つの電位レベルを与える電荷（以下Ｌｏｗレベル電荷、Ｈｉｇｈレベル電荷という。）のどちらかが与えられるものとする。その後、第４の配線３００４の電位を、トランジスタ２００が非導通状態となる電位にして、トランジスタ２００を非導通状態とすることにより、ノードＦＧに電荷が保持される（保持）。 Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).
トランジスタ２００のオフ電流が小さい場合、ノードＦＧの電荷は長期間にわたって保持される。 When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long time.
次に情報の読み出しについて説明する。第１の配線３００１に所定の電位（定電位）を与えた状態で、第５の配線３００５に適切な電位（読み出し電位）を与えると、第２の配線３００２は、ノードＦＧに保持された電荷量に応じた電位をとる。これは、トランジスタ３００をｎチャネル型とすると、トランジスタ３００のゲートにＨｉｇｈレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｈは、トランジスタ３００のゲートにＬｏｗレベル電荷が与えられている場合の見かけ上のしきい値電圧Ｖｔｈ＿Ｌより低くなるためである。ここで、見かけ上のしきい値電圧とは、トランジスタ３００を「導通状態」とするために必要な第５の配線３００５の電位をいうものとする。したがって、第５の配線３００５の電位をＶｔｈ＿ＨとＶｔｈ＿Ｌの間の電位Ｖ０とすることにより、ノードＦＧに与えられた電荷を判別できる。例えば、書き込みにおいて、ノードＦＧにＨｉｇｈレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＞Ｖｔｈ＿Ｈ）となれば、トランジスタ３００は「導通状態」となる。一方、ノードＦＧにＬｏｗレベル電荷が与えられていた場合には、第５の配線３００５の電位がＶ０（＜Ｖｔｈ＿Ｌ）となっても、トランジスタ３００は「非導通状態」のままである。このため、第２の配線３００２の電位を判別することで、ノードＦＧに保持されている情報を読み出すことができる。 Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V th_H when the gate of the transistor 300 is supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by setting the potential of the fifth wiring 3005 to a potential V 0 between V th_H and V th_L , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V 0 (> V th_H ). On the other hand, when a low-level charge is supplied to the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V 0 (<V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
＜記憶装置１の構造＞
本発明の一態様の記憶装置は、図２３に示すようにトランジスタ３００、トランジスタ２００、容量素子１００を有する。トランジスタ２００はトランジスタ３００の上方に設けられ、容量素子１００はトランジスタ３００、およびトランジスタ２００の上方に設けられている。 <Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.
トランジスタ３００は、基板３１１上に設けられ、導電体３１６、絶縁体３１５、基板３１１の一部からなる半導体領域３１３、およびソース領域またはドレイン領域として機能する低抵抗領域３１４ａ、および低抵抗領域３１４ｂを有する。 The transistor 300 includes a conductor 316, an insulator 315, a semiconductor region 313 including a part of the substrate 311, a low resistance region 314a which functions as a source region or a drain region, and a low resistance region 314b. Have.
トランジスタ３００は、ｐチャネル型、あるいはｎチャネル型のいずれでもよい。 The transistor 300 may be either a p-channel type or an n-channel type.
半導体領域３１３のチャネルが形成される領域、その近傍の領域、ソース領域、またはドレイン領域となる低抵抗領域３１４ａ、および低抵抗領域３１４ｂなどにおいて、シリコン系半導体などの半導体を含むことが好ましく、単結晶シリコンを含むことが好ましい。または、Ｇｅ（ゲルマニウム）、ＳｉＧｅ（シリコンゲルマニウム）、ＧａＡｓ（ガリウムヒ素）、ＧａＡｌＡｓ（ガリウムアルミニウムヒ素）などを有する材料で形成してもよい。結晶格子に応力を与え、格子間隔を変化させることで有効質量を制御したシリコンを用いた構成としてもよい。またはＧａＡｓとＧａＡｌＡｓ等を用いることで、トランジスタ３００をＨＥＭＴ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）としてもよい。 The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low resistance region 314a that serves as the source region or the drain region, the low resistance region 314b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.
低抵抗領域３１４ａ、および低抵抗領域３１４ｂは、半導体領域３１３に適用される半導体材料に加え、ヒ素、リンなどのｎ型の導電性を付与する元素、またはホウ素などのｐ型の導電性を付与する元素を含む。 The low-resistance region 314a and the low-resistance region 314b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material used for the semiconductor region 313. Containing elements.
ゲート電極として機能する導電体３１６は、ヒ素、リンなどのｎ型の導電性を付与する元素、もしくはホウ素などのｐ型の導電性を付与する元素を含むシリコンなどの半導体材料、金属材料、合金材料、または金属酸化物材料などの導電性材料を用いることができる。 The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.
なお、導電体の材料により、仕事関数を定めることで、しきい値電圧を調整することができる。具体的には、導電体に窒化チタンや窒化タンタルなどの材料を用いることが好ましい。さらに導電性と埋め込み性を両立するために導電体にタングステンやアルミニウムなどの金属材料を積層として用いることが好ましく、特にタングステンを用いることが耐熱性の点で好ましい。 Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.
なお、図２３に示すトランジスタ３００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。 Note that the transistor 300 illustrated in FIGS. 23A and 23B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
トランジスタ３００を覆って、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６が順に積層して設けられている。 An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.
絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６として、例えば、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、窒化アルミニウムなどを用いればよい。 As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.
絶縁体３２２は、その下方に設けられるトランジスタ３００などによって生じる段差を平坦化する平坦化膜としての機能を有していてもよい。例えば、絶縁体３２２の上面は、平坦性を高めるために化学機械研磨（ＣＭＰ）法等を用いた平坦化処理により平坦化されていてもよい。 The insulator 322 may function as a planarization film for planarizing a step generated by the transistor 300 or the like provided thereunder. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
また、絶縁体３２４には、基板３１１、またはトランジスタ３００などから、トランジスタ２００が設けられる領域に、水素や不純物が拡散しないようなバリア性を有する膜を用いることが好ましい。 The insulator 324 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311 or the transistor 300 to a region where the transistor 200 is provided.
水素に対するバリア性を有する膜の一例として、例えば、ＣＶＤ法で形成した窒化シリコンを用いることができる。ここで、トランジスタ２００等の酸化物半導体を有する半導体素子に、水素が拡散することで、該半導体素子の特性が低下する場合がある。従って、トランジスタ２００と、トランジスタ３００との間に、水素の拡散を抑制する膜を用いることが好ましい。水素の拡散を抑制する膜とは、具体的には、水素の脱離量が少ない膜とする。 As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
水素の脱離量は、例えば、昇温脱離ガス分析法（ＴＤＳ）などを用いて分析することができる。例えば、絶縁体３２４の水素の脱離量は、ＴＤＳ分析において、５０℃から５００℃の範囲において、水素原子に換算した脱離量が、絶縁体３２４の面積当たりに換算して、１０×１０１５ａｔｏｍｓ／ｃｍ２以下、好ましくは５×１０１５ａｔｏｍｓ／ｃｍ２以下であればよい。 The amount of desorption of hydrogen can be analyzed using, for example, a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be 15 atoms / cm 2 or less, preferably 5 × 10 15 atoms / cm 2 or less.
なお、絶縁体３２６は、絶縁体３２４よりも誘電率が低いことが好ましい。例えば、絶縁体３２６の比誘電率は４未満が好ましく、３未満がより好ましい。また例えば、絶縁体３２６の比誘電率は、絶縁体３２４の比誘電率の０．７倍以下が好ましく、０．６倍以下がより好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。 Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably equal to or less than 0.7 times, more preferably equal to or less than 0.6 times that of the insulator 324. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.
また、絶縁体３２０、絶縁体３２２、絶縁体３２４、および絶縁体３２６には容量素子１００、またはトランジスタ２００と電気的に接続する導電体３２８、および導電体３３０等が埋め込まれている。なお、導電体３２８、および導電体３３０はプラグ、または配線としての機能を有する。また、プラグまたは配線としての機能を有する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。 The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like. Note that the conductor 328 and the conductor 330 function as plugs or wirings. In addition, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
各プラグ、および配線（導電体３２８、および導電体３３０等）の材料としては、金属材料、合金材料、金属窒化物材料、または金属酸化物材料などの導電性材料を、単層または積層して用いることができる。耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましく、タングステンを用いることが好ましい。または、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。 As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.
絶縁体３２６、および導電体３３０上に、配線層を設けてもよい。例えば、図２３において、絶縁体３５０、絶縁体３５２、及び絶縁体３５４が順に積層して設けられている。また、絶縁体３５０、絶縁体３５２、及び絶縁体３５４には、導電体３５６が形成されている。導電体３５６は、プラグ、または配線としての機能を有する。なお導電体３５６は、導電体３２８、および導電体３３０と同様の材料を用いて設けることができる。 A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 23, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３５０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３５６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３５０が有する開口部に、水素に対するバリア性を有する導電体が形成される。当該構成により、トランジスタ３００とトランジスタ２００とは、バリア層により分離することができ、トランジスタ３００からトランジスタ２００への水素の拡散を抑制することができる。 For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.
なお、水素に対するバリア性を有する導電体としては、例えば、窒化タンタル等を用いるとよい。また、窒化タンタルと導電性が高いタングステンを積層することで、配線としての導電性を保持したまま、トランジスタ３００からの水素の拡散を抑制することができる。この場合、水素に対するバリア性を有する窒化タンタル層が、水素に対するバリア性を有する絶縁体３５０と接する構造であることが好ましい。 For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.
絶縁体３５４、および導電体３５６上に、配線層を設けてもよい。例えば、図２３において、絶縁体３６０、絶縁体３６２、及び絶縁体３６４が順に積層して設けられている。また、絶縁体３６０、絶縁体３６２、及び絶縁体３６４には、導電体３６６が形成されている。導電体３６６は、プラグ、または配線としての機能を有する。なお導電体３６６は、導電体３２８、および導電体３３０と同様の材料を用いて設けることができる。 A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 23, an insulator 360, an insulator 362, and an insulator 364 are provided in this order. Further, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３６０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３６６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３６０が有する開口部に、水素に対するバリア性を有する導電体が形成される。当該構成により、トランジスタ３００とトランジスタ２００とは、バリア層により分離することができ、トランジスタ３００からトランジスタ２００への水素の拡散を抑制することができる。 Note that for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, similarly to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.
絶縁体３６４、および導電体３６６上に、配線層を設けてもよい。例えば、図２３において、絶縁体３７０、絶縁体３７２、及び絶縁体３７４が順に積層して設けられている。また、絶縁体３７０、絶縁体３７２、及び絶縁体３７４には、導電体３７６が形成されている。導電体３７６は、プラグ、または配線としての機能を有する。なお導電体３７６は、導電体３２８、および導電体３３０と同様の材料を用いて設けることができる。 A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 23, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３７０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３７６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３７０が有する開口部に、水素に対するバリア性を有する導電体が形成される。当該構成により、トランジスタ３００とトランジスタ２００とは、バリア層により分離することができ、トランジスタ３００からトランジスタ２００への水素の拡散を抑制することができる。 Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 370. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.
絶縁体３７４、および導電体３７６上に、配線層を設けてもよい。例えば、図２３において、絶縁体３８０、絶縁体３８２、及び絶縁体３８４が順に積層して設けられている。また、絶縁体３８０、絶縁体３８２、及び絶縁体３８４には、導電体３８６が形成されている。導電体３８６は、プラグ、または配線としての機能を有する。なお導電体３８６は、導電体３２８、および導電体３３０と同様の材料を用いて設けることができる。 A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 23, an insulator 380, an insulator 382, and an insulator 384 are stacked in this order. A conductor 386 is formed over the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.
なお、例えば、絶縁体３８０は、絶縁体３２４と同様に、水素に対するバリア性を有する絶縁体を用いることが好ましい。また、導電体３８６は、水素に対するバリア性を有する導電体を含むことが好ましい。特に、水素に対するバリア性を有する絶縁体３８０が有する開口部に、水素に対するバリア性を有する導電体が形成される。当該構成により、トランジスタ３００とトランジスタ２００とは、バリア層により分離することができ、トランジスタ３００からトランジスタ２００への水素の拡散を抑制することができる。 Note that for example, as the insulator 324, an insulator having a barrier property against hydrogen is preferably used as the insulator 380. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.
絶縁体３８４、および導電体３８６上には絶縁体２１０、および絶縁体２１２が、順に積層して設けられている。絶縁体２１０、および絶縁体２１２のいずれかは、酸素や水素に対してバリア性のある物質を用いることが好ましい。 An insulator 210 and an insulator 212 are sequentially stacked over the insulator 384 and the conductor 386. Any of the insulator 210 and the insulator 212 is preferably formed using a substance having a barrier property against oxygen or hydrogen.
絶縁体２１０、および絶縁体２１２には、導電体２１８が形成されている。導電体２１８は、導電体２０３と同時に形成することができる。 A conductor 218 is formed on the insulator 210 and the insulator 212. The conductor 218 can be formed at the same time as the conductor 203.
絶縁体２１０には、例えば、基板３１１、またはトランジスタ３００を設ける領域などから、トランジスタ２００を設ける領域に、水素や不純物が拡散しないようなバリア性を有する膜を用いることが好ましい。従って、絶縁体３２４と同様の材料を用いることができる。 For the insulator 210, for example, a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.
水素に対するバリア性を有する膜の一例として、ＣＶＤ法で形成した窒化シリコンを用いることができる。ここで、トランジスタ２００等の酸化物半導体を有する半導体素子に、水素が拡散することで、該半導体素子の特性が低下する場合がある。従って、トランジスタ２００と、トランジスタ３００との間に、水素の拡散を抑制する膜を用いることが好ましい。水素の拡散を抑制する膜とは、具体的には、水素の脱離量が少ない膜とする。 As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.
また、水素に対するバリア性を有する膜として、例えば、絶縁体２１０には、酸化アルミニウム、酸化ハフニウム、酸化タンタルなどの金属酸化物を用いることが好ましい。 As the film having a barrier property against hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210.
特に、酸化アルミニウムは、酸素、およびトランジスタの電気特性の変動要因となる水素、水分などの不純物、の両方に対して膜を透過させない遮断効果が高い。したがって、酸化アルミニウムは、トランジスタの作製工程中および作製後において、水素、水分などの不純物のトランジスタ２００への混入を防止することができる。また、トランジスタ２００を構成する酸化物からの酸素の放出を抑制することができる。そのため、トランジスタ２００に対する保護膜として用いることに適している。 In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.
また、例えば、絶縁体２１２には、絶縁体３２０と同様の材料を用いることができる。また、比較的誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。例えば、絶縁体２１２として、酸化シリコン膜や酸化窒化シリコン膜などを用いることができる。 For example, the insulator 212 can be formed using the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 212, a silicon oxide film, a silicon oxynitride film, or the like can be used.
絶縁体２１２、導電体２０３、および導電体２１８上には、絶縁体２１６が設けられている。絶縁体２１６には、導電体２１９、及びトランジスタ２００を構成する導電体（導電体２０５）等が埋め込まれている。なお、導電体２１９は、容量素子１００、またはトランジスタ３００と電気的に接続するプラグ、または配線としての機能を有する。導電体２１９は、導電体２０５と同時に形成することができる。 An insulator 216 is provided over the insulator 212, the conductor 203, and the conductor 218. In the insulator 216, a conductor 219, a conductor included in the transistor 200 (conductor 205), and the like are embedded. Note that the conductor 219 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 219 can be formed at the same time as the conductor 205.
特に、絶縁体２１０と接する領域の導電体２１９は、酸素、水素、および水に対するバリア性を有する導電体であることが好ましい。当該構成により、トランジスタ３００とトランジスタ２００とは、酸素、水素、および水に対するバリア性を有する層により分離することができ、トランジスタ３００からトランジスタ２００への水素の拡散を抑制することができる。 In particular, the conductor 219 in a region in contact with the insulator 210 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 can be separated from each other by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.
絶縁体２１２の上方には、トランジスタ２００が設けられている。なお、トランジスタ２００の構造は、先の実施の形態で説明したトランジスタ２００を用いればよい。また、図２３に示すトランジスタ２００は一例であり、その構造に限定されず、回路構成や駆動方法に応じて適切なトランジスタを用いればよい。 A transistor 200 is provided above the insulator 212. Note that the transistor 200 described in the above embodiment may be used as the structure of the transistor 200. Further, the transistor 200 illustrated in FIGS. 23A and 23B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.
トランジスタ２００の上方には容量素子１００が設けられる。容量素子１００の電極の一方には、トランジスタ２００のソースおよびドレインの他方と電気的に接続する導電体２５６を用いる。導電体２５６は、トランジスタ３００のゲートと電気的に接続する。導電体２５６上には、容量素子１００の誘電体として機能する絶縁体１２０が設けられる。また、絶縁体１２０を間に挟んで、導電体２５６と重なるように導電体１３０が設けられる。導電体１３０は容量素子１００の電極の他方として機能し、配線３００５と電気的に接続する。 A capacitor 100 is provided above the transistor 200. For one of the electrodes of the capacitor 100, a conductor 256 that is electrically connected to the other of the source and the drain of the transistor 200 is used. The conductor 256 is electrically connected to the gate of the transistor 300. An insulator 120 that functions as a dielectric of the capacitor 100 is provided over the conductor 256. Further, the conductor 130 is provided so as to overlap with the conductor 256 with the insulator 120 interposed therebetween. The conductor 130 functions as the other electrode of the capacitor 100 and is electrically connected to the wiring 3005.
絶縁体１２０は、導電体２５６の側面を覆うように設けてもよい。また、導電体１３０は、絶縁体１２０を介して導電体２５６の側面に設けられてもよい。このような構成にすることで、導電体２５６の上面とそれと向かい合う導電体１３０だけでなく、導電体２５６の側面とそれと向かい合う導電体１３０で容量素子１００を構成することができ、容量素子１００の上面面積を増やすことなく容量値を増加させることができ、好ましい。 The insulator 120 may be provided so as to cover the side surface of the conductor 256. The conductor 130 may be provided on the side surface of the conductor 256 with the insulator 120 interposed therebetween. With such a configuration, the capacitor element 100 can be formed using not only the upper surface of the conductor 256 and the conductor 130 facing it, but also the side surface of the conductor 256 and the conductor 130 facing it. The capacitance value can be increased without increasing the upper surface area, which is preferable.
以上が構成例についての説明である。本構成を用いることで、酸化物半導体を有するトランジスタを用いた半導体装置において、電気特性の変動を抑制すると共に、信頼性を向上させることができる。または、オン電流が大きい酸化物半導体を有するトランジスタを提供することができる。または、オフ電流が小さい酸化物半導体を有するトランジスタを提供することができる。または、消費電力が低減された半導体装置を提供することができる。 The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.
以上、本実施の形態に示す構成、方法などは、他の実施の形態に示す構成、方法などと適宜組み合わせて用いることができる。 The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.
（実施の形態３）
本実施の形態では、図２４および図２５を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ（以下、ＯＳトランジスタと呼ぶ。）、および容量素子が適用されている記憶装置の一例として、ＮＯＳＲＡＭについて説明する。ＮＯＳＲＡＭ（登録商標）とは「Ｎｏｎｖｏｌａｔｉｌｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」の略称であり、ゲインセル型（２Ｔ型、３Ｔ型）のメモリセルを有するＲＡＭを指す。なお、以下において、ＮＯＳＲＡＭのようにＯＳトランジスタを用いたメモリ装置を、ＯＳメモリと呼ぶ場合がある。 (Embodiment 3)
In this embodiment, with reference to FIGS. 24 and 25, a transistor in which an oxide is used for a semiconductor (hereinafter referred to as an OS transistor) and a capacitor according to one embodiment of the present invention is applied. As an example of the apparatus, NOSRAM will be described. NOSRAM (registered trademark) is an abbreviation of “Nonvolatile Oxide Semiconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Hereinafter, a memory device using an OS transistor such as NOSRAM may be referred to as an OS memory.
ＮＯＳＲＡＭでは、メモリセルにＯＳトランジスタが用いられるメモリ装置（以下、「ＯＳメモリ」と呼ぶ。）が適用されている。ＯＳメモリは、少なくとも容量素子と、容量素子の充放電を制御するＯＳトランジスタを有するメモリである。ＯＳトランジスタが極小オフ電流のトランジスタであるので、ＯＳメモリは優れた保持特性をもち、不揮発性メモリとして機能させることができる。 In the NOSRAM, a memory device using an OS transistor as a memory cell (hereinafter referred to as “OS memory”) is applied. The OS memory is a memory that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with a minimum off-state current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.
＜＜ＮＯＳＲＡＭ＞＞
図２４にＮＯＳＲＡＭの構成例を示す。図２４に示すＮＯＳＲＡＭ１６００は、メモリセルアレイ１６１０、コントローラ１６４０、行ドライバ１６５０、列ドライバ１６６０、出力ドライバ１６７０を有する。なお、ＮＯＳＲＡＭ１６００は、１のメモリセルで多値データを記憶する多値ＮＯＳＲＡＭである。 << NOSRAM >>
FIG. 24 shows a configuration example of NOSRAM. A NOSRAM 1600 illustrated in FIG. 24 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. Note that the NOSRAM 1600 is a multi-value NOSRAM that stores multi-value data in one memory cell.
メモリセルアレイ１６１０は複数のメモリセル１６１１、複数のワード線ＷＷＬ、ＲＷＬ、ビット線ＢＬ、ソース線ＳＬを有する。ワード線ＷＷＬは書き込みワード線であり、ワード線ＲＷＬは読み出しワード線である。ＮＯＳＲＡＭ１６００では、１のメモリセル１６１１で３ビット（８値）のデータを記憶する。 The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (eight values) data.
コントローラ１６４０は、ＮＯＳＲＡＭ１６００全体を統括的に制御し、データＷＤＡ［３１：０］の書き込み、データＲＤＡ［３１：０］の読み出しを行う。コントローラ１６４０は、外部からのコマンド信号（例えば、チップイネーブル信号、書き込みイネーブル信号など）を処理して、行ドライバ１６５０、列ドライバ１６６０および出力ドライバ１６７０の制御信号を生成する。 The controller 1640 comprehensively controls the entire NOSRAM 1600 and writes data WDA [31: 0] and reads data RDA [31: 0]. The controller 1640 processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.), and generates control signals for the row driver 1650, the column driver 1660, and the output driver 1670.
行ドライバ１６５０は、アクセスする行を選択する機能を有する。行ドライバ１６５０は、行デコーダ１６５１、およびワード線ドライバ１６５２を有する。 The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.
列ドライバ１６６０は、ソース線ＳＬおよびビット線ＢＬを駆動する。列ドライバ１６６０は、列デコーダ１６６１、書き込みドライバ１６６２、ＤＡＣ（デジタル‐アナログ変換回路）１６６３を有する。 The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-analog conversion circuit) 1663.
ＤＡＣ１６６３は３ビットのデジタルデータをアナログ電圧に変換する。ＤＡＣ１６６３は３２ビットのデータＷＤＡ［３１：０］を３ビットごとに、アナログ電圧に変換する。 The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into an analog voltage every 3 bits.
書き込みドライバ１６６２は、ソース線ＳＬをプリチャージする機能、ソース線ＳＬを電気的に浮遊状態にする機能、ソース線ＳＬを選択する機能、選択されたソース線ＳＬにＤＡＣ１６６３で生成した書き込み電圧を入力する機能、ビット線ＢＬをプリチャージする機能、ビット線ＢＬを電気的に浮遊状態にする機能等を有する。 The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and a write voltage generated by the DAC 1663 to the selected source line SL. A function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.
出力ドライバ１６７０は、セレクタ１６７１、ＡＤＣ（アナログ‐デジタル変換回路）１６７２、出力バッファ１６７３を有する。セレクタ１６７１は、アクセスするソース線ＳＬを選択し、選択されたソース線ＳＬの電圧をＡＤＣ１６７２に送信する。ＡＤＣ１６７２は、アナログ電圧を３ビットのデジタルデータに変換する機能を持つ。ソース線ＳＬの電圧はＡＤＣ１６７２において、３ビットのデータに変換され、出力バッファ１６７３はＡＤＣ１６７２から出力されるデータを保持する。 The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds data output from the ADC 1672.
＜メモリセル＞
図２５（Ａ）はメモリセル１６１１の構成例を示す回路図である。メモリセル１６１１は２Ｔ型のゲインセルであり、メモリセル１６１１はワード線ＷＷＬ、ＲＷＬ、ビット線ＢＬ、ソース線ＳＬ、配線ＢＧＬに電気的に接続されている。メモリセル１６１１は、ノードＳＮ、ＯＳトランジスタＭＯ６１、トランジスタＭＰ６１、容量素子Ｃ６１を有する。ＯＳトランジスタＭＯ６１は書き込みトランジスタである。トランジスタＭＰ６１は読み出しトランジスタであり、例えばｐチャネル型Ｓｉトランジスタで構成される。容量素子Ｃ６１はノードＳＮの電圧を保持するための保持容量である。ノードＳＮはデータの保持ノードであり、ここではトランジスタＭＰ６１のゲートに相当する。 <Memory cell>
FIG. 25A is a circuit diagram illustrating a structural example of the memory cell 1611. The memory cell 1611 is a 2T type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitor for holding the voltage of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.
メモリセル１６１１の書き込みトランジスタがＯＳトランジスタＭＯ６１で構成されているため、ＮＯＳＲＡＭ１６００は長時間データを保持することが可能である。 Since the write transistor of the memory cell 1611 includes the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.
図２５（Ａ）の例では、ビット線は、書き込みと読み出しで共通のビット線であるが、図２５（Ｂ）に示すように、書き込みビット線ＷＢＬと、読み出しビット線ＲＢＬとを設けてもよい。 In the example of FIG. 25A, the bit line is a common bit line for writing and reading. However, as shown in FIG. 25B, a writing bit line WBL and a reading bit line RBL may be provided. Good.
図２５（Ｃ）−図２５（Ｅ）にメモリセルの他の構成例を示す、図２５（Ｃ）−図２５（Ｅ）には、書き込み用ビット線と読み出し用ビット線を設けた例を示しているが、図２５（Ａ）のように書き込みと読み出しで共有されるビット線を設けてもよい。 FIGS. 25C to 25E show other configuration examples of the memory cell. FIGS. 25C to 25E show an example in which a write bit line and a read bit line are provided. Although shown, a bit line shared by writing and reading may be provided as shown in FIG.
図２５（Ｃ）に示すメモリセル１６１２は、メモリセル１６１１の変形例であり、読み出しトランジスタをｎチャネル型トランジスタ（ＭＮ６１）に変更したものである。トランジスタＭＮ６１はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。 A memory cell 1612 illustrated in FIG. 25C is a modification example of the memory cell 1611 in which the reading transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.
メモリセル１６１１、１６１２において、ＯＳトランジスタＭＯ６１はバックゲートの無いＯＳトランジスタであってもよい。 In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a back gate.
図２５（Ｄ）に示すメモリセル１６１３は、３Ｔ型ゲインセルであり、ワード線ＷＷＬ、ＲＷＬ、ビット線ＷＢＬ、ＲＢＬ、ソース線ＳＬ、配線ＢＧＬ、ＰＣＬに電気的に接続されている。メモリセル１６１３は、ノードＳＮ、ＯＳトランジスタＭＯ６２、トランジスタＭＰ６２、トランジスタＭＰ６３、容量素子Ｃ６２を有する。ＯＳトランジスタＭＯ６２は書き込みトランジスタである。トランジスタＭＰ６２は読み出しトランジスタであり、トランジスタＭＰ６３は選択トランジスタである。 A memory cell 1613 illustrated in FIG. 25D is a 3T type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.
図２５（Ｅ）に示すメモリセル１６１４は、メモリセル１６１３の変形例であり、読み出しトランジスタおよび選択トランジスタをｎチャネル型トランジスタ（ＭＮ６２、ＭＮ６３）に変更したものである。トランジスタＭＮ６２、ＭＮ６３はＯＳトランジスタであってもよいし、Ｓｉトランジスタであってもよい。 A memory cell 1614 shown in FIG. 25E is a modification example of the memory cell 1613, in which a read transistor and a selection transistor are changed to n-channel transistors (MN62 and MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.
メモリセル１６１１−１６１４に設けられるＯＳトランジスタは、バックゲートの無いトランジスタでもよいし、バックゲートが有るトランジスタであってもよい。 The OS transistor provided in the memory cells 1611 to 1614 may be a transistor without a back gate or a transistor with a back gate.
容量素子Ｃ６１の充放電によってデータを書き換えるため、ＮＯＳＲＡＭ１６００は原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込みおよび読み出しが可能である。また、長時間データを保持することが可能であるので、リフレッシュ頻度を低減できる。 Since data is rewritten by charging / discharging the capacitive element C61, the NOSRAM 1600 has no restriction on the number of times of rewriting in principle, and can write and read data with low energy. Further, since the data can be held for a long time, the refresh frequency can be reduced.
上記実施の形態に示す半導体装置をメモリセル１６１１、１６１２、１６１３、１６１４に用いる場合、ＯＳトランジスタＭＯ６１、ＭＯ６２としてトランジスタ２００を用い、容量素子Ｃ６１、Ｃ６２として容量素子１００を用い、トランジスタＭＰ６１、ＭＮ６２としてトランジスタ３００を用いることができる。これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、本実施の形態に係る記憶装置をさらに高集積化させることができる。よって、本実施の形態に係る記憶装置の単位面積当たりの記憶容量を増加させることができる。 When the semiconductor device described in any of the above embodiments is used for the memory cells 1611, 1612, 1613, and 1614, the transistor 200 is used as the OS transistors MO61 and MO62, the capacitor 100 is used as the capacitors C61 and C62, and the transistors MP61 and MN62 are used. The transistor 300 can be used. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be further integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態４）
本実施の形態では、図２６および図２７を用いて、本発明の一態様に係る、ＯＳトランジスタ、および容量素子が適用されている記憶装置の一例として、ＤＯＳＲＡＭについて説明する。ＤＯＳＲＡＭ（登録商標）とは、「Ｄｙｎａｍｉｃ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ＲＡＭ」の略称であり、１Ｔ（トランジスタ）１Ｃ（容量）型のメモリセルを有するＲＡＭを指す。ＤＯＳＲＡＭも、ＮＯＳＲＡＭと同様に、ＯＳメモリが適用されている。 (Embodiment 4)
In this embodiment, DOSRAM is described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. DOSRAM (registered trademark) is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having 1T (transistor) 1C (capacitance) type memory cells. OS memory is applied to DOSRAM as well as NOSRAM.
＜＜ＤＯＳＲＡＭ１４００＞＞
図２６にＤＯＳＲＡＭの構成例を示す。図２６に示すように、ＤＯＳＲＡＭ１４００は、コントローラ１４０５、行回路１４１０、列回路１４１５、メモリセルおよびセンスアンプアレイ１４２０（以下、「ＭＣ−ＳＡアレイ１４２０」と呼ぶ。）を有する。 << DOSRAM 1400 >>
FIG. 26 shows a configuration example of the DOSRAM. As shown in FIG. 26, the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell, and a sense amplifier array 1420 (hereinafter referred to as “MC-SA array 1420”).
行回路１４１０はデコーダ１４１１、ワード線ドライバ回路１４１２、列セレクタ１４１３、センスアンプドライバ回路１４１４を有する。列回路１４１５はグローバルセンスアンプアレイ１４１６、入出力回路１４１７を有する。グローバルセンスアンプアレイ１４１６は複数のグローバルセンスアンプ１４４７を有する。ＭＣ−ＳＡアレイ１４２０はメモリセルアレイ１４２２、センスアンプアレイ１４２３、グローバルビット線ＧＢＬＬ、ＧＢＬＲを有する。 The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.
（ＭＣ−ＳＡアレイ１４２０）
ＭＣ−ＳＡアレイ１４２０は、メモリセルアレイ１４２２をセンスアンプアレイ１４２３上に積層した積層構造をもつ。グローバルビット線ＧＢＬＬ、ＧＢＬＲはメモリセルアレイ１４２２上に積層されている。ＤＯＳＲＡＭ１４００では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。 (MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure in which a local bit line and a global bit line are hierarchized is adopted as the bit line structure.
メモリセルアレイ１４２２は、Ｎ個（Ｎは２以上の整数）のローカルメモリセルアレイ１４２５＜０＞—１４２５＜Ｎ−１＞を有する。図２７（Ａ）にローカルメモリセルアレイ１４２５の構成例を示す。ローカルメモリセルアレイ１４２５は、複数のメモリセル１４４５、複数のワード線ＷＬ、複数のビット線ＢＬＬ、ＢＬＲを有する。図２７（Ａ）の例では、ローカルメモリセルアレイ１４２５の構造はオープンビット線型であるが、フォールデッドビット線型であってもよい。 The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> -1425 <N-1>. FIG. 27A illustrates a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 27A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.
図２７（Ｂ）にメモリセル１４４５の回路構成例を示す。メモリセル１４４５はトランジスタＭＷ１、容量素子ＣＳ１、端子Ｂ１、Ｂ２を有する。トランジスタＭＷ１は容量素子ＣＳ１の充放電を制御する機能をもつ。トランジスタＭＷ１のゲートはワード線ＷＬに電気的に接続され、第１端子はビット線（ＢＬＬ、またはＢＬＲ）に電気的に接続され、第２端子は容量素子ＣＳ１の第１端子に電気的に接続されている。容量素子ＣＳ１の第２端子は端子Ｂ２に電気的に接続されている。端子Ｂ２には、定電圧（例えば、低電源電圧）が入力される。 FIG. 27B illustrates a circuit configuration example of the memory cell 1445. The memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2. The transistor MW1 has a function of controlling charging / discharging of the capacitor CS1. The gate of the transistor MW1 is electrically connected to the word line WL, the first terminal is electrically connected to the bit line (BLL or BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1. Has been. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, a low power supply voltage) is input to the terminal B2.
上記実施の形態に示す半導体装置をメモリセル１４４５に用いる場合、トランジスタＭＷ１としてトランジスタ２００を用い、容量素子ＣＳ１として容量素子１００を用いることができる。これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、本実施の形態に係る記憶装置を高集積化させることができる。よって、本実施の形態に係る記憶装置の単位面積当たりの記憶容量を増加させることができる。 In the case where the semiconductor device described in any of the above embodiments is used for the memory cell 1445, the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1. Thus, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the memory device according to this embodiment can be highly integrated. Thus, the storage capacity per unit area of the storage device according to this embodiment can be increased.
トランジスタＭＷ１はバックゲートを備えており、バックゲートは端子Ｂ１に電気的に接続されている。そのため、端子Ｂ１の電圧によって、トランジスタＭＷ１の閾値電圧を変更することができる。例えば、端子Ｂ１の電圧は固定電圧（例えば、負の定電圧）であってもよいし、ＤＯＳＲＡＭ１４００の動作に応じて、端子Ｂ１の電圧を変化させてもよい。 The transistor MW1 includes a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage at the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage at the terminal B1 may be changed according to the operation of the DOSRAM 1400.
トランジスタＭＷ１のバックゲートをトランジスタＭＷ１のゲート、第１の端子、または第２の端子に電気的に接続してもよい。あるいは、トランジスタＭＷ１にバックゲートを設けなくてもよい。 The back gate of the transistor MW1 may be electrically connected to the gate, the first terminal, or the second terminal of the transistor MW1. Alternatively, a back gate is not necessarily provided in the transistor MW1.
センスアンプアレイ１４２３は、Ｎ個のローカルセンスアンプアレイ１４２６＜０＞—１４２６＜Ｎ−１＞を有する。ローカルセンスアンプアレイ１４２６は、１のスイッチアレイ１４４４、複数のセンスアンプ１４４６を有する。センスアンプ１４４６には、ビット線対が電気的に接続されている。センスアンプ１４４６は、ビット線対をプリチャージする機能、ビット線対の電圧差を増幅する機能、この電圧差を保持する機能を有する。スイッチアレイ１４４４は、ビット線対を選択し、選択したビット線対とグローバルビット線対との間を導通状態にする機能を有する。 The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> -1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to the sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the voltage difference between the bit line pair, and a function of holding this voltage difference. The switch array 1444 has a function of selecting a bit line pair and bringing the selected bit line pair and the global bit line pair into a conductive state.
ここで、ビット線対とは、センスアンプによって、同時に比較される２本のビット線のことをいう。グローバルビット線対とは、グローバルセンスアンプによって、同時に比較される２本のグローバルビット線のことをいう。ビット線対を一対のビット線と呼ぶことができ、グローバルビット線対を一対のグローバルビット線と呼ぶことができる。ここでは、ビット線ＢＬＬとビット線ＢＬＲが１組のビット線対を成す。グローバルビット線ＧＢＬＬとグローバルビット線ＧＢＬＲとが１組のグローバルビット線対をなす。以下、ビット線対（ＢＬＬ，ＢＬＲ）、グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）とも表す。 Here, the bit line pair refers to two bit lines that are simultaneously compared by the sense amplifier. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the bit line pair (BLL, BLR) and the global bit line pair (GBLL, GBLR) are also represented.
（コントローラ１４０５）
コントローラ１４０５は、ＤＯＳＲＡＭ１４００の動作全般を制御する機能を有する。コントローラ１４０５は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路１４１０、列回路１４１５の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。 (Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and a function to generate control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , A function of holding an address signal input from the outside, and a function of generating an internal address signal.
（行回路１４１０）
行回路１４１０は、ＭＣ−ＳＡアレイ１４２０を駆動する機能を有する。デコーダ１４１１はアドレス信号をデコードする機能を有する。ワード線ドライバ回路１４１２は、アクセス対象行のワード線ＷＬを選択する選択信号を生成する。 (Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the access target row.
列セレクタ１４１３、センスアンプドライバ回路１４１４はセンスアンプアレイ１４２３を駆動するための回路である。列セレクタ１４１３は、アクセス対象列のビット線を選択するための選択信号を生成する機能をもつ。列セレクタ１４１３の選択信号によって、各ローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４が制御される。センスアンプドライバ回路１４１４の制御信号によって、複数のローカルセンスアンプアレイ１４２６は独立して駆動される。 A column selector 1413 and a sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting the bit line of the access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by a selection signal from the column selector 1413. The plurality of local sense amplifier arrays 1426 are independently driven by the control signal of the sense amplifier driver circuit 1414.
（列回路１４１５）
列回路１４１５は、データ信号ＷＤＡ［３１：０］の入力を制御する機能、データ信号ＲＤＡ［３１：０］の出力を制御する機能を有する。データ信号ＷＤＡ［３１：０］は書き込みデータ信号であり、データ信号ＲＤＡ［３１：０］は読み出しデータ信号である。 (Column circuit 1415)
The column circuit 1415 has a function of controlling input of the data signal WDA [31: 0] and a function of controlling output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.
グローバルセンスアンプ１４４７はグローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）に電気的に接続されている。グローバルセンスアンプ１４４７はグローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）間の電圧差を増幅する機能、この電圧差を保持する機能を有する。グローバルビット線対（ＧＢＬＬ，ＧＢＬＲ）へのデータの書き込み、および読み出しは、入出力回路１４１７によって行われる。 The global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Data input / output to / from the global bit line pair (GBLL, GBLR) is performed by an input / output circuit 1417.
ＤＯＳＲＡＭ１４００の書き込み動作の概要を説明する。入出力回路１４１７によって、データがグローバルビット線対に書き込まれる。グローバルビット線対のデータは、グローバルセンスアンプアレイ１４１６によって保持される。アドレス信号が指定するローカルセンスアンプアレイ１４２６のスイッチアレイ１４４４によって、グローバルビット線対のデータが、対象列のビット線対に書き込まれる。ローカルセンスアンプアレイ１４２６は、書き込まれたデータを増幅し、保持する。指定されたローカルメモリセルアレイ１４２５において、行回路１４１０によって、対象行のワード線ＷＬが選択され、選択行のメモリセル１４４５にローカルセンスアンプアレイ１４２６の保持データが書き込まれる。 An outline of the writing operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by the input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 specified by the address signal. The local sense amplifier array 1426 amplifies and holds the written data. In the specified local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held in the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.
ＤＯＳＲＡＭ１４００の読み出し動作の概要を説明する。アドレス信号によって、ローカルメモリセルアレイ１４２５の１行が指定される。指定されたローカルメモリセルアレイ１４２５において、対象行のワード線ＷＬが選択状態となり、メモリセル１４４５のデータがビット線に書き込まれる。ローカルセンスアンプアレイ１４２６によって、各列のビット線対の電圧差がデータとして検出され、かつ保持される。スイッチアレイ１４４４によって、ローカルセンスアンプアレイ１４２６の保持データの内、アドレス信号が指定する列のデータが、グローバルビット線対に書き込まれる。グローバルセンスアンプアレイ１４１６は、グローバルビット線対のデータを検出し、保持する。グローバルセンスアンプアレイ１４１６の保持データは入出力回路１４１７に出力される。以上で、読み出し動作が完了する。 An outline of the reading operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data in the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the voltage difference between the bit line pairs in each column as data. The switch array 1444 writes the data in the column specified by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair. The global sense amplifier array 1416 detects and holds data of the global bit line pair. Data held in the global sense amplifier array 1416 is output to the input / output circuit 1417. This completes the read operation.
容量素子ＣＳ１の充放電によってデータを書き換えるため、ＤＯＳＲＡＭ１４００には原理的には書き換え回数に制約はなく、かつ、低エネルギーで、データの書き込みおよび読み出しが可能である。また、メモリセル１４４５の回路構成が単純であるため、大容量化が容易である。 Since data is rewritten by charging / discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of times of rewriting in principle, and data can be written and read with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.
トランジスタＭＷ１はＯＳトランジスタである。ＯＳトランジスタはオフ電流が極めて小さいため、容量素子ＣＳ１から電荷がリークすることを抑えることができる。したがって、ＤＯＳＲＡＭ１４００の保持時間はＤＲＡＭに比べて非常に長い。したがってリフレッシュの頻度を低減できるため、リフレッシュ動作に要する電力を削減できる。よって、ＤＯＳＲＡＭ１４００は大容量のデータを高頻度で書き換えるメモリ装置、例えば、画像処理に利用されるフレームメモリに好適である。 The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of the DOSRAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data at a high frequency, for example, a frame memory used for image processing.
ＭＣ−ＳＡアレイ１４２０が積層構造であることよって、ローカルセンスアンプアレイ１４２６の長さと同程度の長さにビット線を短くすることができる。ビット線を短くすることで、ビット線容量が小さくなり、メモリセル１４４５の保持容量を低減することができる。また、ローカルセンスアンプアレイ１４２６にスイッチアレイ１４４４を設けることで、長いビット線の本数を減らすことができる。以上の理由から、ＤＯＳＲＡＭ１４００のアクセス時に駆動する負荷が低減され、消費電力を低減することができる。 Since the MC-SA array 1420 has a stacked structure, the bit line can be shortened to the same length as the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacity of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven when accessing the DOSRAM 1400 is reduced, and the power consumption can be reduced.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態５）
本実施の形態では、図２８から図３１を用いて、本発明の一態様に係る、ＯＳトランジスタ、および容量素子が適用されている半導体装置の一例として、ＦＰＧＡ（フィールドプログラマブルゲートアレイ）について説明する。本実施の形態のＦＰＧＡは、コンフィギュレーションメモリ、およびレジスタにＯＳメモリが適用されている。ここでは、このようなＦＰＧＡを「ＯＳ−ＦＰＧＡ」と呼ぶ。 (Embodiment 5)
In this embodiment, an FPGA (field programmable gate array) is described as an example of a semiconductor device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, with reference to FIGS. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and the register. Here, such FPGA is referred to as “OS-FPGA”.
＜＜ＯＳ−ＦＰＧＡ＞＞
図２８（Ａ）にＯＳ−ＦＰＧＡの構成例を示す。図２８（Ａ）に示すＯＳ−ＦＰＧＡ３１１０は、マルチコンテキスト構造によるコンテキスト切り替えとＰＬＥ毎の細粒度パワーゲーティングを実行するＮＯＦＦ（ノーマリオフ）コンピューティングが可能である。ＯＳ−ＦＰＧＡ３１１０は、コントローラ（Ｃｏｎｔｒｏｌｌｅｒ）３１１１、ワードドライバ（Ｗｏｒｄ　ｄｒｉｖｅｒ）３１１２、データドライバ（Ｄａｔａ　ｄｒｉｖｅｒ）３１１３、プログラマブルエリア（Ｐｒｏｇｒａｍｍａｂｌｅ　ａｒｅａ）３１１５を有する。 << OS-FPGA >>
FIG. 28A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 28A is capable of NOFF (normally off) computing that performs context switching by a multi-context structure and fine-grain power gating for each PLE. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.
プログラマブルエリア３１１５は、２個の入出力ブロック（ＩＯＢ）３１１７、コア（Ｃｏｒｅ）３１１９を有する。ＩＯＢ３１１７は複数のプログラマブル入出力回路を有する。コア３１１９は、複数のロジックアレイブロック（ＬＡＢ）３１２０、複数のスイッチアレイブロック（ＳＡＢ）３１３０を有する。ＬＡＢ３１２０は複数のＰＬＥ３１２１を有する。図２８（Ｂ）には、ＬＡＢ３１２０を５個のＰＬＥ３１２１で構成する例を示す。図２８（Ｃ）に示すようにＳＡＢ３１３０はアレイ状に配列された複数のスイッチブロック（ＳＢ）３１３１を有する。ＬＡＢ３１２０は自身の入力端子と、ＳＡＢ３１３０を介して４（上下左右）方向のＬＡＢ３１２０に接続される。 The programmable area 3115 includes two input / output blocks (IOB) 3117 and a core (Core) 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. The LAB 3120 includes a plurality of PLE 3121s. FIG. 28B shows an example in which the LAB 3120 is composed of five PLE 3121s. As shown in FIG. 28C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in the 4 (up / down / left / right) direction via the SAB 3130.
図２９（Ａ）乃至図２９（Ｃ）を参照して、ＳＢ３１３１について説明する。図２９（Ａ）に示すＳＢ３１３１には、ｄａｔａ、ｄａｔａｂ、信号ｃｏｎｔｅｘｔ［１：０］、ｗｏｒｄ［１：０］が入力される。ｄａｔａ、ｄａｔａｂはコンフィギュレーションデータであり、ｄａｔａとｄａｔａｂは論理が相補的な関係にある。ＯＳ−ＦＰＧＡ３１１０のコンテキスト数は２であり、信号ｃｏｎｔｅｘｔ［１：０］はコンテキスト選択信号である。信号ｗｏｒｄ［１：０］はワード線選択信号であり、信号ｗｏｒｄ［１：０］が入力される配線がそれぞれワード線である。 The SB 3131 will be described with reference to FIGS. 29 (A) to 29 (C). Data, dataab, signals context [1: 0], and word [1: 0] are input to SB3131 shown in FIG. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of the OS-FPGA 3110 is 2, and the signal context [1: 0] is a context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.
ＳＢ３１３１は、ＰＲＳ（プログラマブルルーティングスイッチ）３１３３［０］、３１３３［１］を有する。ＰＲＳ３１３３［０］、３１３３［１］は、相補データを格納できるコンフィギュレーションメモリ（ＣＭ）を有する。なお、ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とを区別しない場合、ＰＲＳ３１３３と呼ぶ。他の要素についても同様である。 The SB 3131 includes PRSs (programmable routing switches) 3133 [0] and 3133 [1]. The PRSs 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. Note that PRS 3133 [0] and PRS 3133 [1] are referred to as PRS 3133 when they are not distinguished. The same applies to other elements.
図２９（Ｂ）にＰＲＳ３１３３［０］の回路構成例を示す。ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とは同じ回路構成を有する。ＰＲＳ３１３３［０］とＰＲＳ３１３３［１］とは入力されるコンテキスト選択信号、ワード線選択信号が異なる。信号ｃｏｎｔｅｘｔ［０］、ｗｏｒｄ［０］はＰＲＳ３１３３［０］に入力され、信号ｃｏｎｔｅｘｔ［１］、ｗｏｒｄ［１］はＰＲＳ３１３３［１］に入力される。例えば、ＳＢ３１３１において、信号ｃｏｎｔｅｘｔ［０］が“Ｈ”になることで、ＰＲＳ３１３３［０］がアクティブになる。 FIG. 29B illustrates a circuit configuration example of the PRS 3133 [0]. PRS 3133 [0] and PRS 3133 [1] have the same circuit configuration. PRS 3133 [0] and PRS 3133 [1] are different in the input context selection signal and word line selection signal. The signals context [0] and word [0] are input to the PRS 3133 [0], and the signals context [1] and word [1] are input to the PRS 3133 [1]. For example, in the SB 3131, when the signal context [0] becomes “H”, the PRS 3133 [0] becomes active.
ＰＲＳ３１３３［０］は、ＣＭ３１３５、ＳｉトランジスタＭ３１を有する。ＳｉトランジスタＭ３１は、ＣＭ３１３５により制御されるパストランジスタである。ＣＭ３１３５は、メモリ回路３１３７、３１３７Ｂを有する。メモリ回路３１３７、３１３７Ｂは同じ回路構成である。メモリ回路３１３７は、容量素子Ｃ３１、ＯＳトランジスタＭＯ３１、ＭＯ３２を有する。メモリ回路３１３７Ｂは、容量素子ＣＢ３１、ＯＳトランジスタＭＯＢ３１、ＭＯＢ３２を有する。 The PRS 3133 [0] includes a CM 3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 includes memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32. The memory circuit 3137B includes a capacitor CB31 and OS transistors MOB31 and MOB32.
上記実施の形態に示す半導体装置をＳＡＢ３１３０に用いる場合、ＯＳトランジスタＭＯ３１、ＭＯＢ３１としてトランジスタ２００を用い、容量素子Ｃ３１、ＣＢ３１として容量素子１００を用いることができる。これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、本実施の形態に係る半導体装置を高集積化させることができる。 In the case where the semiconductor device described in any of the above embodiments is used for the SAB 3130, the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitor 100 can be used as the capacitors C31 and CB31. Accordingly, the area occupied by the transistor and the capacitor element in a top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.
ＯＳトランジスタＭＯ３１、ＭＯ３２、ＭＯＢ３１、ＭＯＢ３２はバックゲートを有し、これらバックゲートはそれぞれ固定電圧を供給する電源線に電気的に接続されている。 The OS transistors MO31, MO32, MOB31, and MOB32 each have a back gate, and each of these back gates is electrically connected to a power supply line that supplies a fixed voltage.
ＳｉトランジスタＭ３１のゲートがノードＮ３１であり、ＯＳトランジスタＭＯ３２のゲートがノードＮ３２であり、ＯＳトランジスタＭＯＢ３２のゲートがノードＮＢ３２である。ノードＮ３２、ＮＢ３２はＣＭ３１３５の電荷保持ノードである。ＯＳトランジスタＭＯ３２はノードＮ３１と信号ｃｏｎｔｅｘｔ［０］用の信号線との間の導通状態を制御する。ＯＳトランジスタＭＯＢ３２はノードＮ３１と低電位電源線ＶＳＳとの間の導通状態を制御する。 The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. Nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls a conduction state between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls a conduction state between the node N31 and the low potential power supply line VSS.
メモリ回路３１３７、３１３７Ｂが保持するデータの論理は相補的な関係にある。したがって、ＯＳトランジスタＭＯ３２またはＭＯＢ３２の何れか一方が導通する。 The logic of data held in the memory circuits 3137 and 3137B has a complementary relationship. Therefore, either one of the OS transistors MO32 or MOB32 becomes conductive.
図２９（Ｃ）を参照して、ＰＲＳ３１３３［０］の動作例を説明する。ＰＲＳ３１３３［０］にコンフィギュレーションデータが既に書き込まれており、ＰＲＳ３１３３［０］のノードＮ３２は“Ｈ”であり、ノードＮＢ３２は“Ｌ”である。 With reference to FIG. 29C, an example of operation of PRS3133 [0] will be described. Configuration data has already been written in the PRS 3133 [0], the node N32 of the PRS 3133 [0] is “H”, and the node NB32 is “L”.
信号ｃｏｎｔｅｘｔ［０］が“Ｌ”である間はＰＲＳ３１３３［０］は非アクティブである。この期間に、ＰＲＳ３１３３［０］の入力端子が“Ｈ”に遷移しても、ＳｉトランジスタＭ３１のゲートは“Ｌ”が維持され、ＰＲＳ３１３３［０］の出力端子も“Ｌ”が維持される。 While the signal context [0] is “L”, the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained at “L”.
信号ｃｏｎｔｅｘｔ［０］が“Ｈ”である間はＰＲＳ３１３３［０］はアクティブである。信号ｃｏｎｔｅｘｔ［０］が“Ｈ”に遷移すると、ＣＭ３１３５が記憶するコンフィギュレーションデータによって、ＳｉトランジスタＭ３１のゲートは“Ｈ”に遷移する。 While the signal context [0] is “H”, the PRS 3133 [0] is active. When the signal context [0] changes to “H”, the gate of the Si transistor M31 changes to “H” according to the configuration data stored in the CM 3135.
ＰＲＳ３１３３［０］がアクティブである期間に、入力端子が“Ｈ”に遷移すると、メモリ回路３１３７のＯＳトランジスタＭＯ３２がソースフォロアであるために、ブースティング（ｂｏｏｓｔｉｎｇ）によってＳｉトランジスタＭ３１のゲート電圧は上昇する。その結果、メモリ回路３１３７のＯＳトランジスタＭＯ３２は駆動能力を失い、ＳｉトランジスタＭ３１のゲートは浮遊状態となる。 When the input terminal changes to “H” during the period in which PRS 3133 [0] is active, the OS transistor MO32 of the memory circuit 3137 is a source follower, so that the gate voltage of the Si transistor M31 increases due to boosting. To do. As a result, the OS transistor MO32 of the memory circuit 3137 loses drive capability, and the gate of the Si transistor M31 is in a floating state.
マルチコンテキスト機能を備えるＰＲＳ３１３３において、ＣＭ３１３５はマルチプレクサの機能を併せ持つ。 In the PRS 3133 having a multi-context function, the CM 3135 also has a multiplexer function.
図３０にＰＬＥ３１２１の構成例を示す。ＰＬＥ３１２１はＬＵＴ（ルックアップテーブル）ブロック（ＬＵＴ　ｂｌｏｃｋ）３１２３、レジスタブロック３１２４、セレクタ３１２５、ＣＭ３１２６を有する。ＬＵＴブロック３１２３は、入力ｉｎＡ−ｉｎＤに従ってデータを選択し、出力する構成である。セレクタ３１２５は、ＣＭ３１２６が格納するコンフィギュレーションデータに従って、ＬＵＴブロック３１２３の出力またはレジスタブロック３１２４の出力を選択する。 FIG. 30 shows a configuration example of the PLE 3121. The PLE 3121 includes an LUT (Look Up Table) block (LUT block) 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to select and output data according to the inputs inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM 3126.
ＰＬＥ３１２１は、パワースイッチ３１２７を介して電圧ＶＤＤ用の電源線に電気的に接続されている。パワースイッチ３１２７のオンオフは、ＣＭ３１２８が格納するコンフィギュレーションデータによって設定される。各ＰＬＥ３１２１にパワースイッチ３１２７を設けることで、細粒度パワーゲーティングが可能である。細粒度パワーゲーティング機能により、コンテキストの切り替え後に使用されないＰＬＥ３１２１をパワーゲーティングすることができるので、待機電力を効果的に低減できる。 The PLE 3121 is electrically connected to the power line for the voltage VDD via the power switch 3127. On / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing a power switch 3127 for each PLE 3121, fine-grain power gating is possible. Since the fine-grained power gating function can power gating the PLE 3121 that is not used after context switching, standby power can be effectively reduced.
ＮＯＦＦコンピューティングを実現するため、レジスタブロック３１２４は、不揮発性レジスタで構成される。ＰＬＥ３１２１内の不揮発性レジスタはＯＳメモリを備えるフリップフロップ（以下［ＯＳ−ＦＦ］と呼ぶ）である。 In order to realize NOFF computing, the register block 3124 is configured by a nonvolatile register. The nonvolatile register in the PLE 3121 is a flip-flop (hereinafter referred to as [OS-FF]) including an OS memory.
レジスタブロック３１２４は、ＯＳ−ＦＦ３１４０［１］、３１４０［２］を有する。信号ｕｓｅｒ＿ｒｅｓ、ｌｏａｄ、ｓｔｏｒｅがＯＳ−ＦＦ３１４０［１］、３１４０［２］に入力される。クロック信号ＣＬＫ１はＯＳ−ＦＦ３１４０［１］に入力され、クロック信号ＣＬＫ２はＯＳ−ＦＦ３１４０［２］に入力される。図３１（Ａ）にＯＳ−ＦＦ３１４０の構成例を示す。 The register block 3124 includes OS-FFs 3140 [1] and 3140 [2]. Signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 31A illustrates a configuration example of the OS-FF 3140.
ＯＳ−ＦＦ３１４０は、ＦＦ３１４１、シャドウレジスタ３１４２を有する。ＦＦ３１４１は、ノードＣＫ、Ｒ、Ｄ、Ｑ、ＱＢを有する。ノードＣＫにはクロック信号が入力される。ノードＲには信号ｕｓｅｒ＿ｒｅｓが入力される。信号ｕｓｅｒ＿ｒｅｓはリセット信号である。ノードＤはデータ入力ノードであり、ノードＱはデータ出力ノードである。ノードＱとノードＱＢとは論理が相補関係にある。 The OS-FF 3140 includes an FF 3141 and a shadow register 3142. The FF 3141 includes nodes CK, R, D, Q, and QB. A clock signal is input to the node CK. A signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. Nodes Q and QB have a complementary logic relationship.
シャドウレジスタ３１４２は、ＦＦ３１４１のバックアップ回路として機能する。シャドウレジスタ３１４２は、信号ｓｔｏｒｅに従いノードＱ、ＱＢのデータをそれぞれバックアップし、また、信号ｌｏａｄに従い、バックアップしたデータをノードＱ、ＱＢに書き戻す。 The shadow register 3142 functions as a backup circuit for the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back up the backed up data to the nodes Q and QB according to the signal load.
シャドウレジスタ３１４２は、インバータ回路３１８８、３１８９、ＳｉトランジスタＭ３７、ＭＢ３７、メモリ回路３１４３、３１４３Ｂを有する。メモリ回路３１４３、３１４３Ｂは、ＰＲＳ３１３３のメモリ回路３１３７と同じ回路構成である。メモリ回路３１４３は容量素子Ｃ３６、ＯＳトランジスタＭＯ３５、ＭＯ３６を有する。メモリ回路３１４３Ｂは容量素子ＣＢ３６、ＯＳトランジスタＭＯＢ３５、ＯＳトランジスタＭＯＢ３６を有する、ノードＮ３６、ＮＢ３６はＯＳトランジスタＭＯ３６、ＯＳトランジスタＭＯＢ３６のゲートであり、それぞれ電荷保持ノードである。ノードＮ３７、ＮＢ３７は、ＳｉトランジスタＭ３７、ＭＢ３７のゲートである。 The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36 and OS transistors MO35 and MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge holding nodes. Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.
上記実施の形態に示す半導体装置をＬＡＢ３１２０に用いる場合、ＯＳトランジスタＭＯ３５、ＭＯＢ３５としてトランジスタ２００を用い、容量素子Ｃ３６、ＣＢ３６として容量素子１００を用いることができる、これにより、トランジスタと容量素子一組当たりの上面視における占有面積を低減することができるので、本実施の形態に係る半導体装置を高集積化させることができる。 In the case where the semiconductor device described in any of the above embodiments is used for the LAB 3120, the transistor 200 can be used as the OS transistors MO35 and MOB35, and the capacitor 100 can be used as the capacitors C36 and CB36. Since the occupation area in the top view can be reduced, the semiconductor device according to this embodiment can be highly integrated.
ＯＳトランジスタＭＯ３５、ＭＯ３６、ＭＯＢ３５、ＭＯＢ３６はバックゲートを有し、これらバックゲートはそれぞれ固定電圧を供給する電源線に電気的に接続されている。 The OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, and these back gates are each electrically connected to a power supply line that supplies a fixed voltage.
図３１（Ｂ）を参照して、ＯＳ−ＦＦ３１４０の動作方法例を説明する。 An example of an operation method of the OS-FF 3140 will be described with reference to FIG.
（バックアップ（Ｂａｃｋｕｐ））
“Ｈ”の信号ｓｔｏｒｅがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はＦＦ３１４１のデータをバックアップする。ノードＮ３６は、ノードＱのデータが書き込まれることで、“Ｌ”となり、ノードＮＢ３６は、ノードＱＢのデータが書き込まれることで、“Ｈ”となる。しかる後、パワーゲーティングが実行され、パワースイッチ３１２７をオフにする。ＦＦ３１４１のノードＱ、ＱＢのデータは消失するが、電源オフであっても、シャドウレジスタ３１４２はバックアップしたデータを保持する。 (Backup)
When the “H” signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data in the FF 3141. The node N36 becomes “L” when the data of the node Q is written, and the node NB36 becomes “H” when the data of the node QB is written. Thereafter, power gating is executed and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 holds the backed up data even when the power is turned off.
（リカバリ（Ｒｅｃｏｖｅｒｙ））
パワースイッチ３１２７をオンにし、ＰＬＥ３１２１に電源を供給する。しかる後、“Ｈ”の信号ｌｏａｄがＯＳ−ＦＦ３１４０に入力されると、シャドウレジスタ３１４２はバックアップしているデータをＦＦ３１４１に書き戻す。ノードＮ３６は“Ｌ”であるので、ノードＮ３７は“Ｌ”が維持され、ノードＮＢ３６は“Ｈ”であるので、ノードＮＢ３７は“Ｈ”となる。よって、ノードＱは“Ｈ”になり、ノードＱＢは“Ｌ”になる。つまり、ＯＳ−ＦＦ３１４０はバックアップ動作時の状態に復帰する。 (Recovery)
The power switch 3127 is turned on to supply power to the PLE 3121. After that, when the “H” signal load is input to the OS-FF 3140, the shadow register 3142 writes back-up data back to the FF 3141. Since the node N36 is “L”, the node N37 is maintained at “L”, and the node NB36 is “H”, so that the node NB37 is “H”. Therefore, the node Q becomes “H” and the node QB becomes “L”. That is, the OS-FF 3140 returns to the state during the backup operation.
細粒度パワーゲーティングと、ＯＳ−ＦＦ３１４０のバックアップ／リカバリ動作とを組み合わせることで、ＯＳ−ＦＰＧＡ３１１０の消費電力を効果的に低減できる。 By combining the fine grain power gating and the backup / recovery operation of the OS-FF 3140, the power consumption of the OS-FPGA 3110 can be effectively reduced.
メモリ回路において発生しうるエラーとして放射線の入射によるソフトエラーが挙げられる。ソフトエラーは、メモリやパッケージを構成する材料などから放出されるα線や、宇宙から大気に入射した一次宇宙線が大気中に存在する原子の原子核と核反応を起こすことにより発生する二次宇宙線中性子などがトランジスタに照射され、電子正孔対が生成されることにより、メモリに保持されたデータが反転するなどの誤作動が生じる現象である。ＯＳトランジスタを用いたＯＳメモリはソフトエラー耐性が高い。そのたため、ＯＳメモリを搭載することで、信頼性の高いＯＳ−ＦＰＧＡ３１１０を提供することができる。 An error that may occur in the memory circuit is a soft error due to the incidence of radiation. A soft error is a secondary universe that is generated when a nuclear reaction occurs between alpha rays emitted from the materials that make up the memory and package, or primary cosmic rays incident on the atmosphere from space and atomic nuclei in the atmosphere. This is a phenomenon in which a malfunction such as inversion of data held in a memory occurs due to irradiation of a line neutron or the like to a transistor to generate an electron-hole pair. An OS memory using an OS transistor has high soft error resistance. Therefore, by installing the OS memory, a highly reliable OS-FPGA 3110 can be provided.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態６）
本実施の形態では、図３２を用いて、上記実施の形態に示す半導体装置を適用した、ＡＩシステムについて説明を行う。 (Embodiment 6)
In this embodiment, an AI system to which the semiconductor device described in any of the above embodiments is applied will be described with reference to FIGS.
図３２はＡＩシステム４０４１の構成例を示すブロック図である。ＡＩシステム４０４１は、演算部４０１０と、制御部４０２０と、入出力部４０３０を有する。 FIG. 32 is a block diagram illustrating a configuration example of the AI system 4041. The AI system 4041 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.
演算部４０１０は、アナログ演算回路４０１１と、ＤＯＳＲＡＭ４０１２と、ＮＯＳＲＡＭ４０１３と、ＦＰＧＡ４０１４と、を有する。ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４として、上記実施の形態に示す、ＤＯＳＲＡＭ１４００、ＮＯＳＲＡＭ１６００、およびＯＳ−ＦＰＧＡ３１１０を用いることができる。 The arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014. As the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.
制御部４０２０は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）４０２１と、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）４０２２と、ＰＬＬ（Ｐｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ）４０２３と、ＳＲＡＭ（Ｓｔａｔｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）４０２４と、ＰＲＯＭ（Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）４０２５と、メモリコントローラ４０２６と、電源回路４０２７と、ＰＭＵ（Ｐｏｗｅｒ　Ｍａｎａｇｅｍｅｎｔ　Ｕｎｉｔ）４０２８と、を有する。 The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a SRAM (Static Random Access MemoryPROM 40 Memory, Memory Memory 4024). A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.
入出力部４０３０は、外部記憶制御回路４０３１と、音声コーデック４０３２と、映像コーデック４０３３と、汎用入出力モジュール４０３４と、通信モジュール４０３５と、を有する。 The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input / output module 4034, and a communication module 4035.
演算部４０１０は、ニューラルネットワークによる学習または推論を実行することができる。 The arithmetic unit 4010 can execute learning or inference using a neural network.
アナログ演算回路４０１１はＡ／Ｄ（アナログ／デジタル）変換回路、Ｄ／Ａ（デジタル／アナログ）変換回路、および積和演算回路を有する。 The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.
アナログ演算回路４０１１はＯＳトランジスタを用いて形成することが好ましい。ＯＳトランジスタを用いたアナログ演算回路４０１１は、アナログメモリを有し、学習または推論に必要な積和演算を、低消費電力で実行することが可能になる。 The analog arithmetic circuit 4011 is preferably formed using an OS transistor. An analog operation circuit 4011 using an OS transistor has an analog memory, and can perform a product-sum operation necessary for learning or inference with low power consumption.
ＤＯＳＲＡＭ４０１２は、ＯＳトランジスタを用いて形成されたＤＲＡＭであり、ＤＯＳＲＡＭ４０１２は、ＣＰＵ４０２１から送られてくるデジタルデータを一時的に格納するメモリである。ＤＯＳＲＡＭ４０１２は、ＯＳトランジスタを含むメモリセルと、Ｓｉトランジスタを含む読み出し回路部を有する。上記メモリセルと読み出し回路部は、積層された異なる層に設けることができるため、ＤＯＳＲＡＭ４０１２は、全体の回路面積を小さくすることができる。 The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. The DOSRAM 4012 includes a memory cell including an OS transistor and a reading circuit portion including a Si transistor. Since the memory cell and the reading circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.
ニューラルネットワークを用いた計算は、入力データが１０００を超えることがある。上記入力データをＳＲＡＭに格納する場合、ＳＲＡＭは回路面積に制限があり、記憶容量が小さいため、上記入力データを小分けにして格納せざるを得ない。ＤＯＳＲＡＭ４０１２は、限られた回路面積でも、メモリセルを高集積に配置することが可能であり、ＳＲＡＭに比べて記憶容量が大きい。そのため、ＤＯＳＲＡＭ４０１２は、上記入力データを効率よく格納することができる。 In the calculation using the neural network, the input data may exceed 1000. When the input data is stored in the SRAM, the SRAM has a limited circuit area and has a small storage capacity, so the input data must be stored in small portions. The DOSRAM 4012 can arrange memory cells highly integrated even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOSRAM 4012 can store the input data efficiently.
ＮＯＳＲＡＭ４０１３はＯＳトランジスタを用いた不揮発性メモリである。ＮＯＳＲＡＭ４０１３は、フラッシュメモリや、ＲｅＲＡＭ（Ｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＭＲＡＭ（Ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）などの他の不揮発性メモリと比べて、データを書き込む際の消費電力が小さい。また、フラッシュメモリやＲｅＲＡＭのように、データを書き込む際に素子が劣化することもなく、データの書き込み可能回数に制限が無い。 A NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data than other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetorescent Random Access Memory). Further, unlike the flash memory and the ReRAM, the element is not deteriorated when data is written, and the number of times data can be written is not limited.
また、ＮＯＳＲＡＭ４０１３は、１ビットの２値データの他に、２ビット以上の多値データを記憶することができる。ＮＯＳＲＡＭ４０１３は多値データを記憶することで、１ビット当たりのメモリセル面積を小さくすることができる。 The NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 stores multi-value data, so that the memory cell area per bit can be reduced.
また、ＮＯＳＲＡＭ４０１３は、デジタルデータの他にアナログデータを記憶することができる。そのため、アナログ演算回路４０１１は、ＮＯＳＲＡＭ４０１３をアナログメモリとして用いることもできる。ＮＯＳＲＡＭ４０１３は、アナログデータのまま記憶することができるため、Ｄ／Ａ変換回路やＡ／Ｄ変換回路が不要である。そのため、ＮＯＳＲＡＭ４０１３は周辺回路の面積を小さくすることができる。なお、本明細書においてアナログデータとは、３ビット（８値）以上分解能を有するデータのことを指す。上述した多値データがアナログデータに含まれる場合もある。 The NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit. Note that in this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. The multi-value data described above may be included in the analog data.
ニューラルネットワークの計算に用いられるデータやパラメータは、一旦、ＮＯＳＲＡＭ４０１３に格納することができる。上記データやパラメータは、ＣＰＵ４０２１を介して、ＡＩシステム４０４１の外部に設けられたメモリに格納してもよいが、内部に設けられたＮＯＳＲＡＭ４０１３の方が、より高速且つ低消費電力に上記データやパラメータを格納することができる。また、ＮＯＳＲＡＭ４０１３は、ＤＯＳＲＡＭ４０１２よりもビット線を長くすることができるので、記憶容量を大きくすることができる。 Data and parameters used for calculation of the neural network can be temporarily stored in the NOSRAM 4013. The data and parameters may be stored in the memory provided outside the AI system 4041 via the CPU 4021. However, the data and parameters provided by the internal NOSRAM 4013 are faster and consume less power. Can be stored. Further, since the bit line of the NOSRAM 4013 can be made longer than that of the DOSRAM 4012, the storage capacity can be increased.
ＦＰＧＡ４０１４は、ＯＳトランジスタを用いたＦＰＧＡである。ＡＩシステム４０４１は、ＦＰＧＡ４０１４を用いることによって、ハードウェアで後述する、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの、ニューラルネットワークの接続を構成することができる。上記のニューラルネットワークの接続をハードウェアで構成することで、より高速に実行することができる。 The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses a FPGA 4014, which will be described later in hardware, a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM). A neural network connection, such as a deep belief network (DBN), can be constructed. By configuring the above-mentioned neural network connection with hardware, it can be executed at higher speed.
ＦＰＧＡ４０１４はＯＳトランジスタを有するＦＰＧＡである。ＯＳ‐ＦＰＧＡは、ＳＲＡＭで構成されるＦＰＧＡよりもメモリの面積を小さくすることができる。そのため、コンテキスト切り替え機能を追加しても面積増加が少ない。また、ＯＳ‐ＦＰＧＡはブースティングによりデータやパラメータを高速に伝えることができる。 The FPGA 4014 is an FPGA having an OS transistor. The OS-FPGA can reduce the area of the memory compared to the FPGA configured with the SRAM. Therefore, even if a context switching function is added, the area increase is small. The OS-FPGA can transmit data and parameters at high speed by boosting.
ＡＩシステム４０４１は、アナログ演算回路４０１１、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４を１つのダイ（チップ）の上に設けることができる。そのため、ＡＩシステム４０４１は、高速且つ低消費電力に、ニューラルネットワークの計算を実行することができる。また、アナログ演算回路４０１１、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４は、同じ製造プロセスで作製することができる。そのため、ＡＩシステム４０４１は、低コストで作製することができる。 In the AI system 4041, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can execute neural network calculations at high speed and with low power consumption. In addition, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured through the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.
なお、演算部４０１０は、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４を、全て有する必要はない。ＡＩシステム４０４１が解決したい課題に応じて、ＤＯＳＲＡＭ４０１２、ＮＯＳＲＡＭ４０１３、およびＦＰＧＡ４０１４の一または複数を、選択して設ければよい。 Note that the arithmetic unit 4010 need not have all of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided depending on the problem that the AI system 4041 wants to solve.
ＡＩシステム４０４１は、解決したい課題に応じて、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの手法を実行することができる。ＰＲＯＭ４０２５は、これらの手法の少なくとも１つを実行するためのプログラムを保存することができる。また、当該プログラムの一部または全てを、ＮＯＳＲＡＭ４０１３に保存してもよい。 The AI system 4041 includes a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network (DBM). DBN) etc. can be performed. The PROM 4025 can store a program for executing at least one of these methods. Also, a part or all of the program may be stored in the NOSRAM 4013.
ライブラリとして存在する既存のプログラムは、ＧＰＵの処理を前提としているものが多い。そのため、ＡＩシステム４０４１はＧＰＵ４０２２を有することが好ましい。ＡＩシステム４０４１は、学習と推論で用いられる積和演算のうち、律速となる積和演算を演算部４０１０で実行し、それ以外の積和演算をＧＰＵ４０２２で実行することができる。そうすることで、学習と推論を高速に実行することができる。 Many existing programs that exist as libraries are premised on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. The AI system 4041 can execute a product-sum operation that is rate-limiting among the product-sum operations used in learning and inference by the arithmetic unit 4010, and can execute other product-sum operations by the GPU 4022. By doing so, learning and inference can be performed at high speed.
電源回路４０２７は、論理回路用の低電源電位を生成するだけではなく、アナログ演算のための電位生成も行う。電源回路４０２７はＯＳメモリを用いてもよい。電源回路４０２７は、基準電位をＯＳメモリに保存することで、消費電力を下げることができる。 The power supply circuit 4027 not only generates a low power supply potential for a logic circuit but also generates a potential for analog calculation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.
ＰＭＵ４０２８は、ＡＩシステム４０４１の電力供給を一時的にオフにする機能を有する。 The PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.
ＣＰＵ４０２１およびＧＰＵ４０２２は、レジスタとしてＯＳメモリを有することが好ましい。ＣＰＵ４０２１およびＧＰＵ４０２２はＯＳメモリを有することで、電力供給がオフになっても、ＯＳメモリ中にデータ（論理値）を保持し続けることができる。その結果、ＡＩシステム４０４１は、電力を節約することができる。 The CPU 4021 and the GPU 4022 preferably have an OS memory as a register. Since the CPU 4021 and the GPU 4022 have the OS memory, even if the power supply is turned off, the data (logical value) can be continuously held in the OS memory. As a result, the AI system 4041 can save power.
ＰＬＬ４０２３は、クロックを生成する機能を有する。ＡＩシステム４０４１は、ＰＬＬ４０２３が生成したクロックを基準に動作を行う。ＰＬＬ４０２３はＯＳメモリを有することが好ましい。ＰＬＬ４０２３はＯＳメモリを有することで、クロックの発振周期を制御するアナログ電位を保持することができる。 The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential for controlling the clock oscillation period.
ＡＩシステム４０４１は、ＤＲＡＭなどの外部メモリにデータを保存してもよい。そのため、ＡＩシステム４０４１は、外部のＤＲＡＭとのインターフェースとして機能するメモリコントローラ４０２６を有することが好ましい。また、メモリコントローラ４０２６は、ＣＰＵ４０２１またはＧＰＵ４０２２の近くに配置することが好ましい。そうすることで、データのやり取りを高速に行うことができる。 The AI system 4041 may store data in an external memory such as a DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM. The memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022. By doing so, data can be exchanged at high speed.
制御部４０２０に示す回路の一部または全ては、演算部４０１０と同じダイの上に形成することができる。そうすることで、ＡＩシステム４０４１は、高速且つ低消費電力に、ニューラルネットワークの計算を実行することができる。 Part or all of the circuit shown in the controller 4020 can be formed on the same die as the arithmetic unit 4010. By doing so, the AI system 4041 can execute the calculation of the neural network at high speed and with low power consumption.
ニューラルネットワークの計算に用いられるデータは外部記憶装置（ＨＤＤ（Ｈａｒｄ　Ｄｉｓｋ　Ｄｒｉｖｅ）、ＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）など）に保存される場合が多い。そのため、ＡＩシステム４０４１は、外部記憶装置とのインターフェースとして機能する外部記憶制御回路４０３１を有することが好ましい。 Data used for neural network calculation is often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.
ニューラルネットワークを用いた学習と推論は、音声や映像を扱うことが多いので、ＡＩシステム４０４１は音声コーデック４０３２および映像コーデック４０３３を有する。音声コーデック４０３２は、音声データのエンコード（符号化）およびデコード（復号）を行い、映像コーデック４０３３は、映像データのエンコードおよびデコードを行う。 Since learning and inference using a neural network often handle audio and video, the AI system 4041 includes an audio codec 4032 and a video codec 4033. The audio codec 4032 performs encoding (encoding) and decoding (decoding) of audio data, and the video codec 4033 encodes and decodes video data.
ＡＩシステム４０４１は、外部センサから得られたデータを用いて学習または推論を行うことができる。そのため、ＡＩシステム４０４１は汎用入出力モジュール４０３４を有する。汎用入出力モジュール４０３４は、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）やＩ２Ｃ（Ｉｎｔｅｒ−Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）などを含む。 The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).
ＡＩシステム４０４１は、インターネットを経由して得られたデータを用いて学習または推論を行うことができる。そのため、ＡＩシステム４０４１は、通信モジュール４０３５を有することが好ましい。 The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably includes a communication module 4035.
アナログ演算回路４０１１は、多値のフラッシュメモリをアナログメモリとして用いてもよい。しかし、フラッシュメモリは書き換え可能回数に制限がある。また、多値のフラッシュメモリは、エンベディッドで形成する（演算回路とメモリを同じダイの上に形成する）ことが非常に難しい。 The analog arithmetic circuit 4011 may use a multi-value flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. In addition, it is very difficult to form a multi-level flash memory in an embedded manner (an arithmetic circuit and a memory are formed on the same die).
また、アナログ演算回路４０１１は、ＲｅＲＡＭをアナログメモリとして用いてもよい。しかし、ＲｅＲＡＭは書き換え可能回数に制限があり、記憶精度の点でも問題がある。さらに、２端子でなる素子であるため、データの書き込みと読み出しを分ける回路設計が複雑になる。 The analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and has a problem in terms of storage accuracy. Furthermore, since the device has two terminals, circuit design for separating data writing and reading becomes complicated.
また、アナログ演算回路４０１１は、ＭＲＡＭをアナログメモリとして用いてもよい。しかし、ＭＲＡＭは抵抗変化率が低く、記憶精度の点で問題がある。 The analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has a problem in terms of storage accuracy.
以上を鑑み、アナログ演算回路４０１１は、ＯＳメモリをアナログメモリとして用いることが好ましい。 In view of the above, the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態７）
＜ＡＩシステムの応用例＞
本実施の形態では、上記実施の形態に示すＡＩシステムの応用例について図３３を用いて説明を行う。 (Embodiment 7)
<Application example of AI system>
In this embodiment, application examples of the AI system described in the above embodiment are described with reference to FIGS.
図３３（Ａ）は、図３２で説明したＡＩシステム４０４１を並列に配置し、バス線を介してシステム間での信号の送受信を可能にした、ＡＩシステム４０４１Ａである。 FIG. 33A shows an AI system 4041A in which the AI systems 4041 described in FIG. 32 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.
図３３（Ａ）に図示するＡＩシステム４０４１Ａは、複数のＡＩシステム４０４１＿１乃至ＡＩシステム４０４１＿ｎ（ｎは自然数）を有する。ＡＩシステム４０４１＿１乃至ＡＩシステム４０４１＿ｎは、バス線４０９８を介して互いに接続されている。 An AI system 4041A illustrated in FIG. 33A includes a plurality of AI systems 4041_1 to 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.
また図３３（Ｂ）は、図３２で説明したＡＩシステム４０４１を図３３（Ａ）と同様に並列に配置し、ネットワークを介してシステム間での信号の送受信を可能にした、ＡＩシステム４０４１Ｂである。 FIG. 33B shows an AI system 4041B in which the AI system 4041 described in FIG. 32 is arranged in parallel as in FIG. 33A, and signals can be transmitted and received between systems via a network. is there.
図３３（Ｂ）に図示するＡＩシステム４０４１Ｂは、複数のＡＩシステム４０４１＿１乃至ＡＩシステム４０４１＿ｎを有する。ＡＩシステム４０４１＿１乃至ＡＩシステム４０４１＿ｎは、ネットワーク４０９９を介して互いに接続されている。 An AI system 4041B illustrated in FIG. 33B includes a plurality of AI systems 4041_1 to 4041_n. The AI systems 4041_1 to 4041_n are connected to each other via a network 4099.
ネットワーク４０９９は、ＡＩシステム４０４１＿１乃至ＡＩシステム４０４１＿ｎのそれぞれに通信モジュールを設け、無線または有線による通信を行う構成とすればよい。通信モジュールは、アンテナを介して通信を行うことができる。例えばＷｏｒｌｄ　Ｗｉｄｅ　Ｗｅｂ（ＷＷＷ）の基盤であるインターネット、イントラネット、エクストラネット、ＰＡＮ（Ｐｅｒｓｏｎａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＣＡＮ（Ｃａｍｐｕｓ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＭＡＮ（Ｍｅｔｒｏｐｏｌｉｔａｎ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＷＡＮ（Ｗｉｄｅ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、ＧＡＮ（Ｇｌｏｂａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）等のコンピュータネットワークに各電子装置を接続させ、通信を行うことができる。無線通信を行う場合、通信プロトコル又は通信技術として、ＬＴＥ（Ｌｏｎｇ　Ｔｅｒｍ　Ｅｖｏｌｕｔｉｏｎ）、ＧＳＭ（Ｇｌｏｂａｌ　Ｓｙｓｔｅｍ　ｆｏｒ　Ｍｏｂｉｌｅ　Ｃｏｍｍｕｎｉｃａｔｉｏｎ：登録商標）、ＥＤＧＥ（Ｅｎｈａｎｃｅｄ　Ｄａｔａ　Ｒａｔｅｓ　ｆｏｒ　ＧＳＭ　Ｅｖｏｌｕｔｉｏｎ）、ＣＤＭＡ２０００（Ｃｏｄｅ　Ｄｉｖｉｓｉｏｎ　Ｍｕｌｔｉｐｌｅ　Ａｃｃｅｓｓ　２０００）、Ｗ−ＣＤＭＡ（登録商標）などの通信規格、またはＷｉ−Ｆｉ（登録商標）、Ｂｌｕｅｔｏｏｔｈ（登録商標）、ＺｉｇＢｅｅ（登録商標）等のＩＥＥＥにより通信規格化された仕様を用いることができる。 The network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication. The communication module can communicate via an antenna. For example, the Internet, Intranet, Extranet, PAN (Personal Area Network), LAN (Local Area Network), MAN (Campure Area Network, MAN (MetropoliAwareNetwork), MAN (MetropoliAureNetwork), which are the foundations of the World Wide Web (WWW). Each electronic device can be connected to a computer network such as Network) or GAN (Global Area Network) to perform communication. When performing wireless communication, as communication protocols or communication technologies, LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolvement, CDMA Emulsion, CDMA Emulsion) , Communication standards such as W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark) can be used.
図３３（Ａ）、（Ｂ）の構成とすることで、外部のセンサ等で得られたアナログ信号を別々のＡＩシステムで処理することができる。例えば、生体情報のように、脳波、脈拍、血圧、体温等といった情報を脳波センサ、脈波センサ、血圧センサ、温度センサといった各種センサで取得し、別々のＡＩシステムでアナログ信号を処理することができる。別々のＡＩシステムのそれぞれで信号の処理、または学習を行うことで一つのＡＩシステムあたりの情報処理量を少なくできる。そのため、より少ない演算量で信号の処理、または学習を行うことができる。その結果、認識精度を高めることができる。それぞれのＡＩシステムで得られた情報から、複雑に変化する生体情報の変化を瞬時に統合的に把握することができるといったことが期待できる。 With the configurations shown in FIGS. 33A and 33B, analog signals obtained by an external sensor or the like can be processed by separate AI systems. For example, information such as electroencephalogram, pulse, blood pressure, body temperature, etc., such as biological information, can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and analog signals can be processed by separate AI systems. it can. By performing signal processing or learning in each separate AI system, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be increased. From the information obtained by each AI system, it can be expected that changes in biological information that change in a complex manner can be instantaneously and integratedly grasped.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態８）
本実施の形態は、上記実施の形態に示すＡＩシステムが組み込まれたＩＣの一例を示す。 (Embodiment 8)
This embodiment shows an example of an IC in which the AI system described in the above embodiment is incorporated.
上記実施の形態に示すＡＩシステムは、ＣＰＵ等のＳｉトランジスタでなるデジタル処理回路と、ＯＳトランジスタを用いたアナログ演算回路、ＯＳ−ＦＰＧＡおよびＤＯＳＲＡＭ、ＮＯＳＲＡＭ等のＯＳメモリを、１のダイに集積することができる。 The AI system described in the above embodiment integrates a digital processing circuit composed of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, and OS memories such as OS-FPGA, DOSRAM, and NOSRAM into one die. be able to.
図３４に、ＡＩシステムを組み込んだＩＣの一例を示す。図３４に示すＡＩシステムＩＣ７０００は、リード７００１及び回路部７００３を有する。ＡＩシステムＩＣ７０００は、例えばプリント基板７００２に実装される。このようなＩＣチップが複数組み合わされて、それぞれがプリント基板７００２上で電気的に接続されることで電子部品が実装された基板（実装基板７００４）が完成する。回路部７００３には、上記実施の形態で示した各種の回路が１のダイに設けられている。回路部７００３は積層構造をもち、Ｓｉトランジスタ層７０３１、配線層７０３２、ＯＳトランジスタ層７０３３に大別される。ＯＳトランジスタ層７０３３をＳｉトランジスタ層７０３１に積層して設けることができるため、ＡＩシステムＩＣ７０００の小型化が容易である。 FIG. 34 shows an example of an IC incorporating an AI system. An AI system IC 7000 shown in FIG. 34 includes a lead 7001 and a circuit portion 7003. The AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and each is electrically connected on the printed circuit board 7002 to complete a substrate on which electronic components are mounted (a mounting substrate 7004). The circuit portion 7003 is provided with the various circuits described in the above embodiment in one die. The circuit portion 7003 has a stacked structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked over the Si transistor layer 7031, the AI system IC 7000 can be easily downsized.
図３４では、ＡＩシステムＩＣ７０００のパッケージにＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）を適用しているが、パッケージの態様はこれに限定されない。 In FIG. 34, QFP (Quad Flat Package) is applied to the package of the AI system IC 7000, but the form of the package is not limited to this.
ＣＰＵ等のデジタル処理回路と、ＯＳトランジスタを用いたアナログ演算回路、ＯＳ−ＦＰＧＡおよびＤＯＳＲＡＭ、ＮＯＳＲＡＭ等のＯＳメモリは、全て、Ｓｉトランジスタ層７０３１、配線層７０３２およびＯＳトランジスタ層７０３３に形成することができる。すなわち、上記ＡＩシステムを構成する素子は、同一の製造プロセスで形成することが可能である。そのため、本実施の形態に示すＩＣは、構成する素子が増えても製造プロセスを増やす必要がなく、上記ＡＩシステムを低コストで組み込むことができる。 A digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, and OS memories such as OS-FPGA and DOSRAM and NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. it can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not need to increase the manufacturing process even if the number of elements constituting the IC is increased, and the AI system can be incorporated at low cost.
本実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて用いることができる。 The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.
（実施の形態９）
＜電子機器＞
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図３５に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。 (Embodiment 9)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 35 illustrates specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.
　図３５（Ａ）に、モニタ８３０を示す。モニタ８３０は、表示部８３１、筐体８３２、スピーカ８３３等を有する。さらに、ＬＥＤランプ、操作キー（電源スイッチ、または操作スイッチを含む）、接続端子、各種センサ、マイクロフォン等を有することができる。またモニタ８３０は、リモコン操作機８３４により、操作することができる。 FIG. 35A shows the monitor 830. The monitor 830 includes a display portion 831, a housing 832, a speaker 833, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided. The monitor 830 can be operated with a remote controller 834.
　またモニタ８３０は、放送電波を受信して、テレビジョン装置として機能することができる。 Further, the monitor 830 can function as a television device by receiving broadcast radio waves.
　モニタ８３０が受信できる放送電波としては、地上波、または衛星から送信される電波などが挙げられる。また放送電波として、アナログ放送、デジタル放送などがあり、また映像及び音声、または音声のみの放送などがある。例えばＵＨＦ帯（３００ＭＨｚ以上３ＧＨｚ以下）またはＶＨＦ帯（３０ＭＨｚ以上３００ＭＨｚ以下）のうちの特定の周波数帯域で送信される放送電波を受信することができる。また例えば、複数の周波数帯域で受信した複数のデータを用いることで、転送レートを高くすることができ、より多くの情報を得ることができる。これによりフルハイビジョンを超える解像度を有する映像を、表示部８３１に表示させることができる。例えば、４Ｋ−２Ｋ、８Ｋ−４Ｋ、１６Ｋ−８Ｋ、またはそれ以上の解像度を有する映像を表示させることができる。 Broadcast radio waves that can be received by the monitor 830 include terrestrial waves or radio waves transmitted from satellites. As broadcast radio waves, there are analog broadcasts, digital broadcasts, etc., and video and audio, or audio-only broadcasts. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. In addition, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. Thereby, an image having a resolution exceeding full high-definition can be displayed on the display unit 831. For example, an image having a resolution of 4K-2K, 8K-4K, 16K-8K, or higher can be displayed.
　また、インターネットやＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）、Ｗｉ−Ｆｉ（登録商標）などのコンピュータネットワークを介したデータ伝送技術により送信された放送のデータを用いて、表示部８３１に表示する画像を生成する構成としてもよい。このとき、モニタ８３０にチューナを有さなくてもよい。 In addition, a configuration for generating an image to be displayed on the display unit 831 using broadcast data transmitted by a data transmission technique via a computer network such as the Internet, a LAN (Local Area Network), or Wi-Fi (registered trademark). It is good. At this time, the monitor 830 may not have a tuner.
また、モニタ８３０は、コンピュータと接続し、コンピュータ用モニタとして用いることができる。また、コンピュータと接続したモニタ８３０は、複数の人が同時に閲覧可能となり、会議システムに用いることができる。また、ネットワークを介したコンピュータの情報の表示や、モニタ８３０自体のネットワークへの接続により、モニタ８３０をテレビ会議システムに用いることができる。 The monitor 830 can be connected to a computer and used as a computer monitor. A monitor 830 connected to a computer can be viewed by a plurality of people at the same time, and can be used for a conference system. Further, the monitor 830 can be used in a video conference system by displaying computer information via the network or connecting the monitor 830 itself to the network.
また、モニタ８３０はデジタルサイネージとして用いることもできる。 The monitor 830 can also be used as digital signage.
例えば、本発明の一態様の半導体装置を表示部の駆動回路や、画像処理部に用いることができる。本発明の一態様の半導体装置を表示部の駆動回路や、画像処理部に用いることで、高速な動作や信号処理を低消費電力にて実現できる。 For example, the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. By using the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
また、本発明の一態様の半導体装置を用いたＡＩシステムをモニタ８３０の画像処理部に用いることで、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理などの画像処理を行うことができる。また、解像度のアップコンバートに伴う画素間補間処理や、フレーム周波数のアップコンバートに伴うフレーム間補間処理などを実行することができる。また、階調変換処理は、画像の階調数を変換するだけでなく、階調数を大きくする場合の階調値の補間を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 In addition, by using an AI system including the semiconductor device of one embodiment of the present invention for the image processing unit of the monitor 830, image processing such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing is performed. Can do. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed. In addition, the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
図３５（Ｂ）に示すビデオカメラ２９４０は、筐体２９４１、筐体２９４２、表示部２９４３、操作スイッチ２９４４、レンズ２９４５、および接続部２９４６等を有する。操作スイッチ２９４４およびレンズ２９４５は筐体２９４１に設けられており、表示部２９４３は筐体２９４２に設けられている。また、ビデオカメラ２９４０は、筐体２９４１の内側にアンテナ、バッテリなどを備える。そして、筐体２９４１と筐体２９４２は、接続部２９４６により接続されており、筐体２９４１と筐体２９４２の間の角度は、接続部２９４６により変えることが可能な構造となっている。筐体２９４１に対する筐体２９４２の角度によって、表示部２９４３に表示される画像の向きの変更や、画像の表示／非表示の切り換えを行うことができる。 A video camera 2940 illustrated in FIG. 35B includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.
例えば、本発明の一態様の半導体装置を表示部の駆動回路や、画像処理部に用いることができる。本発明の一態様の半導体装置を表示部の駆動回路や、画像処理部に用いることで、高速な動作や信号処理を低消費電力にて実現できる。 For example, the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion. By using the semiconductor device of one embodiment of the present invention for the driver circuit of the display portion or the image processing portion, high-speed operation and signal processing can be realized with low power consumption.
また、本発明の一態様の半導体装置を用いたＡＩシステムをビデオカメラ２９４０の画像処理部に用いることで、ビデオカメラ２９４０周囲の環境に応じた撮影が実現できる。具体的には、周囲の明るさに応じて最適な露出で撮影を行うことができる。また、逆光における撮影や屋内と屋外など、明るさの異なる状況を同時に撮影する場合では、ハイダイナミックレンジ（ＨＤＲ）撮影を行うことができる。 Further, by using an AI system including the semiconductor device of one embodiment of the present invention for the image processing portion of the video camera 2940, shooting according to the environment around the video camera 2940 can be realized. Specifically, shooting can be performed with an optimal exposure according to the ambient brightness. In addition, when shooting under different lighting conditions, such as shooting in backlight or indoor and outdoor, high dynamic range (HDR) shooting can be performed.
また、ＡＩシステムは、撮影者の癖を学習し、撮影のアシストを行うことができる。具体的には、撮影者の手振れの癖を学習し、撮影中の手振れを補正することで、撮影した画像には手振れによる画像の乱れが極力含まれないようにすることができる。また、撮影中にズーム機能を用いる際には、被写体が常に画像の中心で撮影されるようにレンズの向きなどを制御することができる。 Further, the AI system can learn a photographer's habit and can assist in photographing. Specifically, by learning the camera shake of the photographer and correcting the camera shake during shooting, it is possible to minimize the image disturbance caused by the camera shake. Further, when using the zoom function during shooting, the direction of the lens and the like can be controlled so that the subject is always shot at the center of the image.
図３５（Ｃ）に示す情報端末２９１０は、筐体２９１１、表示部２９１２、マイク２９１７、スピーカ部２９１４、カメラ２９１３、外部接続部２９１６、および操作スイッチ２９１５等を有する。表示部２９１２には、可撓性基板が用いられた表示パネルおよびタッチスクリーンを備える。また、情報端末２９１０は、筐体２９１１の内側にアンテナ、バッテリなどを備える。情報端末２９１０は、例えば、スマートフォン、携帯電話、タブレット型情報端末、タブレット型パーソナルコンピュータ、電子書籍端末等として用いることができる。 An information terminal 2910 illustrated in FIG. 35C includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.
例えば、本発明の一態様の半導体装置を用いた記憶装置は、上述した情報端末２９１０の制御情報や、制御プログラムなどを長期間保持することができる。 For example, a memory device using the semiconductor device of one embodiment of the present invention can hold the control information of the above-described information terminal 2910, the control program, and the like for a long period.
また、本発明の一態様の半導体装置を用いたＡＩシステムを情報端末２９１０の画像処理部に用いることで、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理などの画像処理を行うことができる。また、解像度のアップコンバートに伴う画素間補間処理や、フレーム周波数のアップコンバートに伴うフレーム間補間処理などを実行することができる。また、階調変換処理は、画像の階調数を変換するだけでなく、階調数を大きくする場合の階調値の補間を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 In addition, by using an AI system including the semiconductor device of one embodiment of the present invention for the image processing portion of the information terminal 2910, image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed. be able to. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed. In addition, the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
また、ＡＩシステムは、ユーザーの癖を学習し、情報端末２９１０の操作のアシストを行うことができる。ＡＩシステムを搭載した情報端末２９１０は、ユーザーの指の動きや、目線などからタッチ入力を予測することができる。 In addition, the AI system can learn the user's habit and assist the operation of the information terminal 2910. An information terminal 2910 equipped with an AI system can predict a touch input from the movement of a user's finger, the line of sight, and the like.
図３５（Ｄ）に示すラップトップ型パーソナルコンピュータ２９２０は、筐体２９２１、表示部２９２２、キーボード２９２３、およびポインティングデバイス２９２４等を有する。また、ラップトップ型パーソナルコンピュータ２９２０は、筐体２９２１の内側にアンテナ、バッテリなどを備える。 A laptop personal computer 2920 illustrated in FIG. 35D includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.
例えば、本発明の一態様の半導体装置を用いた記憶装置は、ラップトップ型パーソナルコンピュータ２９２０の制御情報や、制御プログラムなどを長期間保持することができる。 For example, a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the laptop personal computer 2920 for a long period.
また、本発明の一態様の半導体装置を用いたＡＩシステムをラップトップ型パーソナルコンピュータ２９２０の画像処理部に用いることで、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理などの画像処理を行うことができる。また、解像度のアップコンバートに伴う画素間補間処理や、フレーム周波数のアップコンバートに伴うフレーム間補間処理などを実行することができる。また、階調変換処理は、画像の階調数を変換するだけでなく、階調数を大きくする場合の階調値の補間を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 In addition, by using the AI system including the semiconductor device of one embodiment of the present invention for the image processing portion of the laptop personal computer 2920, images such as noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing can be used. Processing can be performed. Also, inter-pixel interpolation processing associated with resolution up-conversion, inter-frame interpolation processing associated with frame frequency up-conversion, and the like can be performed. In addition, the gradation conversion process can not only convert the number of gradations of an image but also perform interpolation of gradation values when the number of gradations is increased. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
また、ＡＩシステムは、ユーザーの癖を学習し、ラップトップ型パーソナルコンピュータ２９２０の操作のアシストを行うことができる。ＡＩシステムを搭載したラップトップ型パーソナルコンピュータ２９２０は、ユーザーの指の動きや、目線などから表示部２９２２へのタッチ入力を予測することができる。また、テキストの入力においては、過去のテキスト入力情報や、前後のテキストや写真などの図から入力予測を行い、変換のアシストを行う。これにより、入力ミスや変換ミスを極力低減することができる。 In addition, the AI system can learn a user's habit and assist the operation of the laptop personal computer 2920. A laptop personal computer 2920 equipped with an AI system can predict a touch input to the display unit 2922 from the movement of a user's finger, a line of sight, or the like. In addition, in text input, input prediction is performed based on past text input information and figures such as preceding and following texts and photographs, and conversion is assisted. Thereby, input mistakes and conversion mistakes can be reduced as much as possible.
図３５（Ｅ）は、自動車の一例を示す外観図、図３５（Ｆ）は、ナビゲーション装置８６０を示している。自動車２９８０は、車体２９８１、車輪２９８２、ダッシュボード２９８３、およびライト２９８４等を有する。また、自動車２９８０は、アンテナ、バッテリなどを備える。ナビゲーション装置８６０は、表示部８６１、操作ボタン８６２、及び外部入力端子８６３を具備する。自動車２９８０とナビゲーション装置８６０は、それぞれ独立していても良いが、ナビゲーション装置８６０が自動車２９８０に組み込まれ、連動して機能する構成とするのが好ましい。 FIG. 35E illustrates an external view of an example of an automobile, and FIG. 35F illustrates a navigation device 860. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like. The navigation device 860 includes a display unit 861, operation buttons 862, and an external input terminal 863. The automobile 2980 and the navigation device 860 may be independent of each other, but it is preferable that the navigation device 860 is incorporated in the automobile 2980 and functions in conjunction with the automobile 2980.
例えば、本発明の一態様の半導体装置を用いた記憶装置は、自動車２９８０やナビゲーション装置８６０の制御情報や、制御プログラムなどを長期間保持することができる。また、本発明の一態様の半導体装置を用いたＡＩシステムを自動車２９８０の制御装置などに用いることで、ＡＩシステムは、ドライバーの運転技術や癖を学習し、安全運転のアシストや、ガソリンやバッテリなどの燃料を効率的に利用する運転のアシストを行うことができる。安全運転のアシストとしては、ドライバーの運転技術や癖を学習するだけでなく、自動車２９８０の速度や移動方法といった自動車の挙動、ナビゲーション装置８６０に保存された道路情報などを複合的に学習し、走行中のレーンから外れることの防止や、他の自動車、歩行者、構造体などとの衝突回避が実現できる。具体的には、進行方向に急カーブが存在する場合、ナビゲーション装置８６０はその道路情報を自動車２９８０に送信し、自動車２９８０の速度の制御や、ハンドル操作のアシストを行うことができる。 For example, a memory device using the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the automobile 2980 and the navigation device 860 for a long period. In addition, by using the AI system using the semiconductor device of one embodiment of the present invention for a control device of an automobile 2980, the AI system learns driving skills and habits of the driver, assists in safe driving, and uses gasoline or batteries. It is possible to assist driving that efficiently uses such fuel. Assisting safe driving not only learns the driver's driving skills and habits, but also learns driving behavior such as the speed and movement method of the car 2980, road information stored in the navigation device 860, etc. It is possible to prevent the vehicle from coming off from the inside lane and avoid collisions with other automobiles, pedestrians, and structures. Specifically, when there is a sharp curve in the traveling direction, the navigation device 860 can transmit the road information to the automobile 2980 to control the speed of the automobile 2980 and assist the steering operation.
本実施の形態は、他の実施の形態や実施例などに記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and examples.
本実施例では、＜導電体の作製方法１＞に基づき作成した導電体の例を図３６および図３７に示す。なお、図３６および図３７に示す試料の断面写真の取得には、日立ハイテクノロジーズ社製走査透過電子顕微鏡（ＳＴＥＭ：Ｓｃａｎｎｉｎｇ　Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）（型番：ＨＤ−２３００）を用いた。また、試料の観察条件は、加速電圧を２００ｋＶ、ビーム径を約０．５ｎｍφとした。 In this example, examples of a conductor created based on <Conductor manufacturing method 1> are shown in FIGS. Note that a scanning transmission electron microscope (STEM: Scanning Transmission Electron Microscope) (model number: HD-2300) manufactured by Hitachi High-Technologies Corporation was used to obtain the cross-sectional photographs of the samples shown in FIGS. The sample observation conditions were an acceleration voltage of 200 kV and a beam diameter of about 0.5 nmφ.
まず、基板上に熱酸化膜（ＳｉＯｘ）を形成し、スパッタリング法にて熱酸化膜上に酸化アルミニウム（ＡｌＯｘ）を４０ｎｍ、プラズマＣＶＤ法にて酸化窒化シリコン（ＳｉＯＮ）を２００ｎｍ順に成膜した。本実施例では、基板としてシリコン基板を用いた。 First, a thermal oxide film (SiOx) was formed on a substrate, and aluminum oxide (AlOx) was deposited on the thermal oxide film by sputtering to a thickness of 40 nm, and silicon oxynitride (SiON) was deposited in a thickness of 200 nm by a plasma CVD method. In this example, a silicon substrate was used as the substrate.
次に、酸化窒化シリコン上にマスクを形成し、当該マスクを用いて酸化窒化シリコンをエッチングにより開口し、導電体形成用の溝を形成した。本実施例では、酸化窒化シリコン上にタングステンを３５ｎｍ成膜し、レジストマスクを用いてエッチングすることで得られたハードマスク（ＨＭ）を用いて酸化窒化シリコンのエッチングを行った。その後レジストマスクを除去した。本実施例では、ハードマスクとしてタングステンを用いたが、ハードマスクの材料はこれに限らない。また、ハードマスクを用いず、レジストマスクのみで酸化窒化シリコンをエッチングしてもよい。また、本実施例では、ハードマスク形成後にレジストマスクを除去せず、酸化窒化シリコンのエッチングを行ったが、ハードマスク形成後にレジストマスクを除去してからハードマスクのみをマスクとして用いて酸化窒化シリコンのエッチングを行ってもよい。 Next, a mask was formed over the silicon oxynitride, and the silicon oxynitride was opened by etching using the mask to form a conductor formation groove. In this embodiment, silicon oxynitride was etched using a hard mask (HM) obtained by forming a tungsten film with a thickness of 35 nm on silicon oxynitride and performing etching using a resist mask. Thereafter, the resist mask was removed. In this embodiment, tungsten is used as the hard mask, but the material of the hard mask is not limited to this. Alternatively, silicon oxynitride may be etched using only a resist mask without using a hard mask. In this example, the silicon oxide oxynitride was etched without removing the resist mask after the hard mask was formed. However, the silicon oxynitride was formed using only the hard mask as a mask after removing the resist mask after the hard mask was formed. Etching may be performed.
次に、酸化シリコン、ハードマスクを覆うように、溝の内部に導電体を形成する。導電体の形成において、第１の導電性バリアとして、スパッタリング法にて窒化タンタル（ＴａＮ）を４０ｎｍ、第２の導電性バリアとしてＡＬＤ法にて窒化チタン（ＴｉＮ）を５ｎｍ、さらに導電体としてＣＶＤ法にてタングステン（Ｗ）を２５０ｎｍ順に成膜した。 Next, a conductor is formed inside the trench so as to cover the silicon oxide and the hard mask. In the formation of the conductor, tantalum nitride (TaN) is 40 nm by sputtering as a first conductive barrier, titanium nitride (TiN) is 5 nm by ALD as a second conductive barrier, and CVD is also used as a conductor. Tungsten (W) was deposited in the order of 250 nm by the method.
図３６（Ａ）、図３６（Ｂ）、および図３６（Ｃ）は、導電体形成後の断面写真である。図３６（Ａ）、図３６（Ｂ）、および図３６（Ｃ）は、図５（Ａ）の断面図に対応する。図３６（Ｂ）は、図３６（Ａ）をさらに拡大した断面写真である。また、図３６（Ｃ）は、図３６（Ｂ）の暗視野像である。溝の中央部に位置するタングステンにおいて、破線で囲われた部分にてシームが確認された。 FIG. 36A, FIG. 36B, and FIG. 36C are cross-sectional photographs after conductor formation. 36A, 36B, and 36C correspond to the cross-sectional view of FIG. FIG. 36B is a cross-sectional photograph in which FIG. 36A is further enlarged. FIG. 36C is a dark field image of FIG. In tungsten located at the center of the groove, a seam was confirmed at a portion surrounded by a broken line.
次に、タングステン、窒化チタン、窒化タンタル、およびハードマスクをＣＭＰ法により研磨した。研磨装置には、東京精密社製のＣＭＰ装置（ＣｈａＭＰ−２１１）を用いた。また、研磨は２工程に分けて行った。まず、研磨布には、ニッタハース社製ＩＣ１０００／ＳＵＢＡ４００　ＸＹ−Ｐを用い、スラリーには、コロイダルシリカを含む酸性のスラリーであるキャボット社製のＷ７３００−Ｂ２１を２倍に希釈したものに、２％過酸化水素水（Ｈ２Ｏ２）を添加したものを用いて１回目の研磨を行った。次に、研磨布には、ＩＣ１０００／ＳＵＢＡ４００　ＸＹ−Ｐを用い、スラリーには、ヒュームドシリカを含むアルカリ性のスラリーであるキャボット社製のＳｅｍｉ−Ｓｐｅｒｓｅ　２５（ＳＳ２５）を２倍に希釈したものを用いて２回目の研磨を行った。 Next, tungsten, titanium nitride, tantalum nitride, and a hard mask were polished by a CMP method. A CMP apparatus (ChaMP-211) manufactured by Tokyo Seimitsu Co., Ltd. was used as the polishing apparatus. Polishing was performed in two steps. First, the polishing cloth used is IC1000 / SUBA400 XY-P manufactured by Nitta Haas, and the slurry is an acidic slurry containing colloidal silica diluted to 2 times diluted W7300-B21 manufactured by Cabot. The first polishing was performed using a solution to which hydrogen peroxide water (H 2 O 2 ) was added. Next, IC1000 / SUBA400 XY-P is used for the polishing cloth, and the slurry is a two-fold dilution of Semi-Sperse 25 (SS25) manufactured by Cabot, which is an alkaline slurry containing fumed silica. A second polishing was performed.
図３６（Ｄ）および図３６（Ｅ）は、タングステン、窒化チタン、窒化タンタル、およびハードマスクをＣＭＰ法により研磨した後の断面写真である。図３６（Ｅ）は、図３６（Ｄ）の暗視野像である。図３６（Ｄ）および図３６（Ｅ）は、図５（Ｂ）の断面図に対応する。タングステンの表面には凹凸が存在し、溝の中央部に位置するタングステンにおいて、破線で囲われた部分にキーホールが確認された。 36D and 36E are cross-sectional photographs after polishing tungsten, titanium nitride, tantalum nitride, and a hard mask by a CMP method. FIG. 36E is the dark field image of FIG. 36D and 36E correspond to the cross-sectional view of FIG. There are irregularities on the surface of tungsten, and a keyhole was confirmed in a portion surrounded by a broken line in tungsten located at the center of the groove.
次に、溝内部のタングステンをハーフエッチングし、キーホールを除去する。タングステンのハーフエッチングには、ドライエッチングを用いた。ドライエッチングには、ＣＦ４、Ｏ２、Ｃｌ２の混合ガスを用いた。 Next, the tungsten inside the groove is half-etched to remove the keyhole. Dry etching was used for half etching of tungsten. For dry etching, a mixed gas of CF 4 , O 2 , and Cl 2 was used.
図３７（Ａ）および図３７（Ｂ）は、タングステンのハーフエッチング後の断面写真である。図３７（Ａ）および図３７（Ｂ）は、図６（Ｂ）の断面図に対応する。図３７（Ｂ）は、図３７（Ａ）の暗視野像である。図３７（Ａ）および図３７（Ｂ）において、タングステンは約７０ｎｍエッチングされ、溝の内部には、約１００ｎｍのタングステンが残っている。また、酸化窒化シリコン膜の上面より上方に突き出ているのは、窒化タンタルおよび窒化チタンである。 37A and 37B are cross-sectional photographs after half etching of tungsten. FIGS. 37A and 37B correspond to the cross-sectional view of FIG. FIG. 37B is a dark field image of FIG. In FIGS. 37A and 37B, tungsten is etched by about 70 nm, and about 100 nm of tungsten remains inside the groove. Further, tantalum nitride and titanium nitride protrude above the upper surface of the silicon oxynitride film.
次に、酸化窒化シリコン、タングステン、窒化チタン、窒化タンタルを覆い、溝の内部に導電体を形成する。導電体の形成において、第３の導電性バリアとして、ＡＬＤ法にて窒化チタン（ＴｉＮ）を５ｎｍ、さらに導電体としてＣＶＤ法にてタングステン（Ｗ）を１５０ｎｍ順に成膜した。 Next, a silicon oxynitride, tungsten, titanium nitride, and tantalum nitride are covered, and a conductor is formed inside the groove. In the formation of the conductor, titanium nitride (TiN) was deposited in a thickness of 5 nm by an ALD method as a third conductive barrier, and tungsten (W) was deposited in a thickness of 150 nm by a CVD method as a conductor.
図３７（Ｃ）および図３７（Ｄ）は、導電体形成後の断面写真である。図３７（Ｃ）および図３７（Ｄ）は、図６（Ｃ）の断面図に対応する。図３７（Ｄ）は、図３７（Ｃ）の暗視野像である。タングステンにおいて、破線で囲まれた部分にシームが確認されたが、溝の内部にシームは確認されなかった。 FIG. 37C and FIG. 37D are cross-sectional photographs after the conductor is formed. FIGS. 37C and 37D correspond to the cross-sectional view of FIG. FIG. 37D is a dark field image of FIG. In tungsten, a seam was confirmed in a portion surrounded by a broken line, but no seam was confirmed in the groove.
次に、タングステンおよび窒化チタン、そして酸化窒化シリコン膜の上面より上方に突き出た窒化タンタルおよび窒化チタンをＣＭＰ法により研磨した。研磨装置には、東京精密社製のＣＭＰ装置（ＣｈａＭＰ−２１１）を用いた。また、研磨は２工程に分けて行った。まず、研磨布には、ＩＣ１０００／ＳＵＢＡ４００　ＸＹ−Ｐを用い、スラリーには、Ｗ７３００−Ｂ２１を２倍に希釈したものに、２％過酸化水素水（Ｈ２Ｏ２）を添加したものを用いて１回目の研磨を行った。次に、研磨布には、ＩＣ１０００／ＳＵＢＡ４００　ＸＹ−Ｐを用い、スラリーには、ＳＳ２５を２倍に希釈したものを用いて２回目の研磨を行った。 Next, tungsten and titanium nitride, and tantalum nitride and titanium nitride protruding above the upper surface of the silicon oxynitride film were polished by CMP. A CMP apparatus (ChaMP-211) manufactured by Tokyo Seimitsu Co., Ltd. was used as the polishing apparatus. Polishing was performed in two steps. First, IC1000 / SUBA400 XY-P is used for the polishing cloth, and a slurry obtained by diluting W7300-B21 twice and adding 2% aqueous hydrogen peroxide (H 2 O 2 ) is used for the slurry. The first polishing was performed. Next, IC1000 / SUBA400 XY-P was used for the polishing cloth, and the second polishing was performed using a slurry obtained by diluting SS25 twice.
図３７（Ｅ）および図３７（Ｆ）は、タングステンおよび窒化チタンなどをＣＭＰ法により研磨した後の断面写真である。図３７（Ｆ）は、図３７（Ｅ）の暗視野像である。図３７（Ｅ）および図３７（Ｆ）は、図６（Ｄ）の断面図に対応する。タングステン表面の凹凸は、図３６（Ｄ）および図３６（Ｅ）に比べて低減し、タングステンにキーホールは確認されなかった。 FIG. 37E and FIG. 37F are cross-sectional photographs after polishing tungsten, titanium nitride, and the like by a CMP method. FIG. 37F is the dark field image of FIG. FIGS. 37E and 37F correspond to the cross-sectional view of FIG. The unevenness of the tungsten surface was reduced as compared with FIGS. 36D and 36E, and no keyhole was observed in tungsten.
本発明により、平坦性の改善された導電体を形成することができた。 According to the present invention, a conductor having improved flatness can be formed.
本実施例は、他の実施の形態などに記載した構成と適宜組み合わせて実施することが可能である。 This example can be implemented in combination with any of the structures described in the other embodiments as appropriate.
１００　　容量素子
１０１　　ハードマスク
１０３　　レジストマスク
１０５　　シーム
１０７　　キーホール
１０９　　凹部
１１１　　シーム
１１３　　ハードマスク
１１５　　レジストマスク
１１７　　シーム
１１９　　キーホール
１２０　　絶縁体
１２１　　シーム
１２３　　シーム
１３０　　導電体
１６１　　メモリセル
２００　　トランジスタ
２０１　　トランジスタ
２０３　　導電体
２０３ａ　　導電体
２０３ｂ　　導電体
２０５　　導電体
２０５ａ　　導電体
２０５Ａ　　導電体
２０５ａＡ　　導電体
２０５ａＢ　　導電体
２０５ｂ　　導電体
２０５Ｂ　　導電体
２０５ｂＡ　　導電体
２０５ｂＢ　　導電体
２０５ｃ　　導電体
２０５ｃＡ　　導電体
２０５ｃＢ　　導電体
２０５ｃＣ　　導電体
２０５ｄ　　導電体
２０５ｄＡ　　導電体
２０５ｅ　　導電体
２０５ｅＡ　　導電体
２０８　　絶縁体
２１０　　絶縁体
２１２　　絶縁体
２１６　　絶縁体
２１８　　導電体
２１９　　導電体
２２０　　絶縁体
２２２　　絶縁体
２２４　　絶縁体
２３０　　酸化物
２３０ａ　　酸化物
２３０Ａ　　酸化膜
２３０ｂ　　酸化物
２３０Ｂ　　酸化膜
２３０ｃ　　酸化物
２３０Ｃ　　酸化膜
２３０ｄ　　酸化物
２３１　　領域
２３１ａ　　領域
２３１ｂ　　領域
２３２　　接合領域
２３２ａ　　接合領域
２３２ｂ　　接合領域
２３４　　領域
２３９　　領域
２４０　　絶縁体
２５０　　絶縁体
２５０Ａ　　絶縁膜
２５２　　導電体
２５２ａ　　導電体
２５２Ａ　　導電体
２５２ａＡ　　導電体
２５２ａＣ　　導電体
２５２ａＤ　　導電体
２５２ｂ　　導電体
２５２Ｂ　　導電体
２５２ｂＡ　　導電体
２５２ｂＢ　　導電体
２５２ｂＣ　　導電体
２５２ｂＤ　　導電体
２５２ｂＥ　　導電体
２５２ｃ　　導電体
２５２Ｃ　　導電体
２５２ｃＡ　　導電体
２５２ｃＢ　　導電体
２５２ｃＣ　　導電体
２５２ｄ　　導電体
２５２Ｄ　　導電体
２５２ｄＡ　　導電体
２５２ｄＢ　　導電体
２５２ｄＣ　　導電体
２５６　　導電体
２５６ａ　　導電体
２５６ｂ　　導電体
２５６ｃ　　導電体
２６０　　導電体
２６０ａ　　導電体
２６０Ａ　　導電膜
２６０ｂ　　導電体
２６０Ｂ　　導電膜
２７０　　絶縁体
２７０Ａ　　絶縁膜
２７１　　絶縁体
２７１Ａ　　絶縁膜
２７２　　絶縁体
２７２Ａ　　絶縁膜
２７４　　絶縁体
２８０　　絶縁体
２８５　　導電体
２８６　　絶縁体
２８７　　絶縁体
２８８　　絶縁体
２８９　　絶縁体
３００　　トランジスタ
３１１　　基板
３１３　　半導体領域
３１４ａ　　低抵抗領域
３１４ｂ　　低抵抗領域
３１５　　絶縁体
３１６　　導電体
３２０　　絶縁体
３２２　　絶縁体
３２４　　絶縁体
３２６　　絶縁体
３２８　　導電体
３３０　　導電体
３５０　　絶縁体
３５２　　絶縁体
３５４　　絶縁体
３５６　　導電体
３６０　　絶縁体
３６２　　絶縁体
３６４　　絶縁体
３６６　　導電体
３７０　　絶縁体
３７２　　絶縁体
３７４　　絶縁体
３７６　　導電体
３８０　　絶縁体
３８２　　絶縁体
３８４　　絶縁体
３８６　　導電体
８３０　　モニタ
８３１　　表示部
８３２　　筐体
８３３　　スピーカ
８３４　　リモコン操作機
８６０　　ナビゲーション装置
８６１　　表示部
８６２　　操作ボタン
８６３　　外部入力端子
１０００　　ＩＣ
１４００　　ＤＯＳＲＡＭ
１４０５　　コントローラ
１４１０　　行回路
１４１１　　デコーダ
１４１２　　ワード線ドライバ回路
１４１３　　列セレクタ
１４１４　　センスアンプドライバ回路
１４１５　　列回路
１４１６　　グローバルセンスアンプアレイ
１４１７　　入出力回路
１４２０　　センスアンプアレイ
１４２２　　メモリセルアレイ
１４２３　　センスアンプアレイ
１４２５　　ローカルメモリセルアレイ
１４２６　　ローカルセンスアンプアレイ
１４４４　　スイッチアレイ
１４４５　　メモリセル
１４４６　　センスアンプ
１４４７　　グローバルセンスアンプ
１６００　　ＮＯＳＲＡＭ
１６１０　　メモリセルアレイ
１６１１　　メモリセル
１６１１−１６１４　　メモリセル
１６１２　　メモリセル
１６１３　　メモリセル
１６１４　　メモリセル
１６４０　　コントローラ
１６５０　　行ドライバ
１６５１　　行デコーダ
１６５２　　ワード線ドライバ
１６６０　　列ドライバ
１６６１　　列デコーダ
１６６２　　ドライバ
１６６３　　ＤＡＣ
１６７０　　出力ドライバ
１６７１　　セレクタ
１６７２　　ＡＤＣ
１６７３　　出力バッファ
２０００　　ＣＤＭＡ
２５２１　　導電体
２５２２　　導電体
２５２３　　導電体
２５２４　　導電体
２９１０　　情報端末
２９１１　　筐体
２９１２　　表示部
２９１３　　カメラ
２９１４　　スピーカ部
２９１５　　操作スイッチ
２９１６　　外部接続部
２９１７　　マイク
２９２０　　ラップトップ型パーソナルコンピュータ
２９２１　　筐体
２９２２　　表示部
２９２３　　キーボード
２９２４　　ポインティングデバイス
２９４０　　ビデオカメラ
２９４１　　筐体
２９４２　　筐体
２９４３　　表示部
２９４４　　操作スイッチ
２９４５　　レンズ
２９４６　　接続部
２９８０　　自動車
２９８１　　車体
２９８２　　車輪
２９８３　　ダッシュボード
２９８４　　ライト
３００１　　配線
３００２　　配線
３００３　　配線
３００４　　配線
３００５　　配線
３００６　　配線
３１１０　　ＯＳ−ＦＰＧＡ
３１１１　　コントローラ
３１１２　　ワードドライバ
３１１３　　データドライバ
３１１５　　プログラマブルエリア
３１１７　　ＩＯＢ
３１１９　　コア
３１２０　　ＬＡＢ
３１２１　　ＰＬＥ
３１２３　　ＬＵＴブロック
３１２４　　レジスタブロック
３１２５　　セレクタ
３１２６　　ＣＭ
３１２７　　パワースイッチ
３１２８　　ＣＭ
３１３０　　ＳＡＢ
３１３１　　ＳＢ
３１３３　　ＰＲＳ
３１３５　　ＣＭ
３１３７　　メモリ回路
３１３７Ｂ　　メモリ回路
３１４０　　ＯＳ−ＦＦ
３１４１　　ＦＦ
３１４２　　シャドウレジスタ
３１４３　　メモリ回路
３１４３Ｂ　　メモリ回路
３１８８　　インバータ回路
３１８９　　インバータ回路
４０１０　　演算部
４０１１　　アナログ演算回路
４０１２　　ＤＯＳＲＡＭ
４０１３　　ＮＯＳＲＡＭ
４０１４　　ＦＰＧＡ
４０２０　　制御部
４０２１　　ＣＰＵ
４０２２　　ＧＰＵ
４０２３　　ＰＬＬ
４０２５　　ＰＲＯＭ
４０２６　　メモリコントローラ
４０２７　　電源回路
４０２８　　ＰＭＵ
４０３０　　入出力部
４０３１　　外部記憶制御回路
４０３２　　音声コーデック
４０３３　　映像コーデック
４０３４　　汎用入出力モジュール
４０３５　　通信モジュール
４０４１　　ＡＩシステム
４０４１＿ｎ　　ＡＩシステム
４０４１＿１　　ＡＩシステム
４０４１Ａ　　ＡＩシステム
４０４１Ｂ　　ＡＩシステム
４０９８　　バス線
４０９９　　ネットワーク
７０００　　ＡＩシステムＩＣ
７００１　　リード
７００３　　回路部
７０３１　　Ｓｉトランジスタ層
７０３２　　配線層
７０３３　　ＯＳトランジスタ層 100 capacitive element 101 hard mask 103 resist mask 105 seam 107 keyhole 109 recess 111 seam 113 hard mask 115 resist mask 117 seam 119 keyhole 120 insulator 121 seam 123 seam 130 conductor 161 memory cell 200 transistor 201 transistor 203 conductor 203a Conductor 203b Conductor 205 Conductor 205a Conductor 205A Conductor 205aA Conductor 205aB Conductor 205b Conductor 205B Conductor 205bA Conductor 205bB Conductor 205c Conductor 205cA Conductor 205cB Conductor 205cC Conductor 205d Conductor 205dA Conductor 205e conductor 205eA conductor 208 insulator 210 insulator 212 insulator 216 insulator 18 conductor 219 conductor 220 insulator 222 insulator 224 insulator 230 oxide 230a oxide 230A oxide film 230b oxide 230B oxide film 230c oxide 230C oxide film 230d oxide 231 region 231a region 231b region 232 junction region 232a junction Region 232b bonding region 234 region 239 region 240 insulator 250 insulator 250A insulating film 252 conductor 252a conductor 252A conductor 252aA conductor 252aC conductor 252aD conductor 252b conductor 252B conductor 252bA conductor 252bC conductor 252bC conductor 252bC 252bD conductor 252bE conductor 252c conductor 252C conductor 252cA conductor 252cB conductor 252cC conductor 252d conductor 252D conductor 52dA conductor 252dB conductor 252dC conductor 256 conductor 256a conductor 256b conductor 256c conductor 260 conductor 260a conductor 260A conductive film 260b conductor 260B conductive film 270 insulator 270A insulating film 271 insulator 271A insulating film 272 insulating Body 272A insulating film 274 insulator 280 insulator 285 conductor 286 insulator 287 insulator 288 insulator 289 insulator 300 transistor 311 substrate 313 semiconductor region 314a low resistance region 314b low resistance region 315 insulator 316 conductor 320 insulator 322 The insulator 324 The insulator 326 The insulator 328 The conductor 330 The conductor 350 The insulator 352 The insulator 354 The insulator 356 The conductor 360 The insulator 362 The insulator 364 The insulator 366 The conductor 3 70 Insulator 372 Insulator 374 Insulator 376 Conductor 380 Insulator 382 Insulator 384 Insulator 386 Conductor 830 Monitor 831 Display unit 832 Housing 833 Speaker 834 Remote control device 860 Navigation device 861 Display unit 862 Operation button 863 External input Terminal 1000 IC
1400 DOSRAM
1405 controller 1410 row circuit 1411 decoder 1412 word line driver circuit 1413 column selector 1414 sense amplifier driver circuit 1415 column circuit 1416 global sense amplifier array 1417 input / output circuit 1420 sense amplifier array 1422 memory cell array 1423 sense amplifier array 1425 local memory cell array 1426 local sense Amplifier array 1444 Switch array 1445 Memory cell 1446 Sense amplifier 1447 Global sense amplifier 1600 NOSRAM
1610 memory cell array 1611 memory cell 1611-1614 memory cell 1612 memory cell 1613 memory cell 1614 memory cell 1640 controller 1650 row driver 1651 row decoder 1652 word line driver 1660 column driver 1661 column decoder 1662 driver 1663 DAC
1670 output driver 1671 selector 1672 ADC
1673 Output buffer 2000 CDMA
2521 Conductor 2522 Conductor 2523 Conductor 2524 Conductor 2924 Information terminal 2911 Housing 2912 Display unit 2912 Display unit 2913 Camera 2914 Speaker unit 2915 External connection unit 2917 Microphone 2920 Laptop personal computer 2921 Housing 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3110 OS-FPGA
3111 Controller 3112 Word driver 3113 Data driver 3115 Programmable area 3117 IOB
3119 Core 3120 LAB
3121 PLE
3123 LUT block 3124 register block 3125 selector 3126 CM
3127 Power Switch 3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 Memory circuit 3137B Memory circuit 3140 OS-FF
3141 FF
3142 Shadow register 3143 Memory circuit 3143B Memory circuit 3188 Inverter circuit 3189 Inverter circuit 4010 Operation unit 4011 Analog operation circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 control unit 4021 CPU
4022 GPU
4023 PLL
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 Input / output unit 4031 External storage control circuit 4032 Audio codec 4033 Video codec 4034 General-purpose input / output module 4035 Communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 Bus line 4099 Network 7000 AI system IC
7001 Lead 7003 Circuit part 7031 Si transistor layer 7032 Wiring layer 7033 OS transistor layer

Claims (20)

  1. 　開口を有する第１の絶縁体と、
    　前記開口の内部に設けられ、且つ第１の凹部を有する第１の導電体と、
    　前記第１の凹部の底面に接する第２の導電体と、
    　前記第１の凹部の側面と前記第２の導電体の上面に接し、且つ第２の凹部を有する第３の導電体と、
    　前記第２の凹部に設けられた第４の導電体と、を有することを特徴とする半導体装置。     A first insulator having an opening;
    A first conductor provided in the opening and having a first recess;
    A second conductor in contact with the bottom surface of the first recess;
    A third conductor in contact with the side surface of the first recess and the upper surface of the second conductor and having a second recess;
    And a fourth conductor provided in the second recess.
  2. 　請求項１において、
    　前記半導体装置は、さらに、第２の絶縁体と、酸化物と、を有し、
    　前記第２の絶縁体は、前記第１の絶縁体、前記第１の導電体、前記第２の導電体、前記第３の導電体、および前記第４の導電体上に設けられ、
    　前記酸化物は、前記第２の絶縁体を間に挟み、前記第１の導電体と重なることを特徴とする半導体装置。     In claim 1,
    The semiconductor device further includes a second insulator and an oxide,
    The second insulator is provided on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor,
    The semiconductor device is characterized in that the oxide overlaps with the first conductor with the second insulator interposed therebetween.
  3. 　請求項１において、
    　前記第１の絶縁体は、第５の導電体上に設けられ、
    　前記第１の導電体、前記第２の導電体、前記第３の導電体、および前記第４の導電体は、前記第５の導電体と電気的に接続することを特徴とする半導体装置。     In claim 1,
    The first insulator is provided on a fifth conductor;
    The semiconductor device, wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are electrically connected to the fifth conductor.
  4. 　請求項１において、
    　前記第１の導電体は、第１の材料および第２の材料を含み、
    　前記第１の材料は、前記開口の側面と底面に接し、
    　前記第２の材料は、前記第２の導電体および前記第３の導電体と接することを特徴とする半導体装置。     In claim 1,
    The first conductor includes a first material and a second material;
    The first material is in contact with a side surface and a bottom surface of the opening,
    The semiconductor device, wherein the second material is in contact with the second conductor and the third conductor.
  5. 　請求項４において、
    　前記第１の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第２の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第２の材料は、前記第１の材料と異なる材料であることを特徴とする半導体装置。     In claim 4,
    The first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The semiconductor device, wherein the second material is a material different from the first material.
  6. 　酸化物と、
    　前記酸化物を覆い、且つ開口を有する第１の絶縁体と、
    　前記開口の側面と底面に接し、且つ第１の凹部を有する第１の導電体と、
    　前記第１の凹部の底面に接する第２の導電体と、
    　前記第１の凹部の側面と前記第２の導電体の上面に接し、且つ第２の凹部を有する第３の導電体と、
    　前記第２の凹部に設けられた第４の導電体と、を有し、
    　前記第１の導電体、前記第２の導電体、前記第３の導電体、および前記第４の導電体は、前記酸化物と電気的に接続することを特徴とする半導体装置。     Oxides,
    A first insulator covering the oxide and having an opening;
    A first conductor in contact with a side surface and a bottom surface of the opening and having a first recess;
    A second conductor in contact with the bottom surface of the first recess;
    A third conductor in contact with the side surface of the first recess and the upper surface of the second conductor and having a second recess;
    A fourth conductor provided in the second recess,
    The semiconductor device, wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are electrically connected to the oxide.
  7. 　請求項６において、
    　前記第１の絶縁体は、複数の絶縁材料からなる積層体であることを特徴とする半導体装置。     In claim 6,
    The semiconductor device according to claim 1, wherein the first insulator is a stacked body made of a plurality of insulating materials.
  8. 　請求項６において、
    　前記半導体装置は、さらに、第２の絶縁体を有し、
    　前記第２の絶縁体は、前記開口の側面に設けられ、
    　前記第１の導電体は、前記第２の絶縁体を介して、前記第１の絶縁体と接することを特徴とする半導体装置。     In claim 6,
    The semiconductor device further includes a second insulator,
    The second insulator is provided on a side surface of the opening;
    The semiconductor device, wherein the first conductor is in contact with the first insulator through the second insulator.
  9. 　請求項８において、
    　前記第１の絶縁体は、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、アルミニウム、およびハフニウムの一方あるいは両方を含む酸化物のいずれか一を含み、
    　前記第２の絶縁体は、アルミニウムおよびハフニウムの一方または両方を含む酸化物を含むことを特徴とする半導体装置。     In claim 8,
    The first insulator includes any one of oxides including one or both of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum, and hafnium,
    The semiconductor device, wherein the second insulator includes an oxide containing one or both of aluminum and hafnium.
  10. 　請求項１または請求項６において、
    　前記第１の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第３の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含むことを特徴とする半導体装置。     In claim 1 or claim 6,
    The first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The semiconductor device, wherein the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride.
  11. 　請求項１または請求項６において、
    　前記第２の導電体は、タングステン、銅およびアルミニウムのいずれか一を含み、
    　前記第４の導電体は、タングステン、銅およびアルミニウムのいずれか一を含むことを特徴とする半導体装置。     In claim 1 or claim 6,
    The second conductor includes any one of tungsten, copper, and aluminum,
    The semiconductor device, wherein the fourth conductor includes any one of tungsten, copper, and aluminum.
  12. 　請求項２または請求項６において、
    　前記酸化物は、Ｉｎと、元素Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎ）と、Ｚｎと、を含むことを特徴とする半導体装置。     In claim 2 or claim 6,
    The oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  13. 　第１の絶縁体に開口を形成し、
    　前記第１の絶縁体上、および前記開口内部に第１の導電体を形成し、
    　前記第１の導電体上に第２の導電体を形成し、
    　前記絶縁体の上方に位置する前記第１の導電体および前記第２の導電体を除去し、
    　前記開口内部に位置する前記第２の導電体の一部を除去し、
    　前記絶縁体上、および前記開口内部に、前記第１の導電体および前記第２の導電体と接するように第３の導電体を形成し、
    　前記第３の導電体上に第４の導電体を形成し、
    　前記第１の絶縁体の上方に位置する前記第３の導電体および前記第４の導電体を除去することを特徴とする半導体装置の作製方法。     Forming an opening in the first insulator;
    Forming a first conductor on the first insulator and in the opening;
    Forming a second conductor on the first conductor;
    Removing the first conductor and the second conductor located above the insulator;
    Removing a portion of the second conductor located inside the opening;
    Forming a third conductor on the insulator and inside the opening so as to be in contact with the first conductor and the second conductor;
    Forming a fourth conductor on the third conductor;
    A method for manufacturing a semiconductor device, wherein the third conductor and the fourth conductor located above the first insulator are removed.
  14. 請求項１３において、
    　前記第１の絶縁体、前記第１の導電体、前記第２の導電体、前記第３の導電体、および前記第４の導電体上に第２の絶縁体を形成し、
    　前記第２の絶縁体上に、前記第４の導電体と重なるように酸化物を形成することを特徴とする半導体装置の作製方法。     In claim 13,
    Forming a second insulator on the first insulator, the first conductor, the second conductor, the third conductor, and the fourth conductor;
    A method for manufacturing a semiconductor device, wherein an oxide is formed over the second insulator so as to overlap with the fourth conductor.
  15. 　請求項１３において、
    　前記第１の導電体および前記第２の導電体の除去、および前記第３の導電体および前記第４の導電体の除去に、ＣＭＰ法を用いることが特徴の半導体装置の作製方法。     In claim 13,
    A method for manufacturing a semiconductor device, wherein a CMP method is used to remove the first conductor and the second conductor, and to remove the third conductor and the fourth conductor.
  16. 　請求項１３において、
    　前記第１の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第３の導電体は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含むことを特徴とする半導体装置の作製方法。     In claim 13,
    The first conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The method for manufacturing a semiconductor device, wherein the third conductor includes any one of titanium, titanium nitride, tantalum, and tantalum nitride.
  17. 　請求項１３において、
    　前記第１の導電体は、第１の材料および第２の材料を含み、
    　前記第１の材料は、前記開口の側面と底面に接し、
    　前記第２の材料は、前記第２の導電体および前記第３の導電体と接することを特徴とする半導体装置の作製方法。     In claim 13,
    The first conductor includes a first material and a second material;
    The first material is in contact with a side surface and a bottom surface of the opening,
    The method for manufacturing a semiconductor device, wherein the second material is in contact with the second conductor and the third conductor.
  18. 　請求項１３において、
    　前記第１の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第２の材料は、チタン、窒化チタン、タンタル、および窒化タンタルのいずれか一を含み、
    　前記第２の材料は、前記第１の材料と異なる材料であることを特徴とする半導体装置の作製方法。     In claim 13,
    The first material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The second material includes any one of titanium, titanium nitride, tantalum, and tantalum nitride,
    The method for manufacturing a semiconductor device, wherein the second material is a material different from the first material.
  19. 　請求項１３において、
    　前記第２の導電体は、タングステン、銅およびアルミニウムのいずれか一を含み、
    　前記第４の導電体は、タングステン、銅およびアルミニウムのいずれか一を含むことを特徴とする半導体装置の作製方法。     In claim 13,
    The second conductor includes any one of tungsten, copper, and aluminum,
    The method for manufacturing a semiconductor device, wherein the fourth conductor includes any one of tungsten, copper, and aluminum.
  20. 　請求項１４において、
    　前記酸化物は、Ｉｎと、元素Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎ）と、Ｚｎと、を含むことを特徴とする半導体装置の作製方法。     In claim 14,
    The method for manufacturing a semiconductor device, wherein the oxide contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
PCT/IB2018/051251 2017-03-10 2018-02-28 Conductor, method for manufacturing conductor, semiconductor device, and method for manufacturing semiconductor device WO2018163020A1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340330A (en) * 1998-05-28 1999-12-10 Toshiba Corp Manufacture of semiconductor device
JP2000049116A (en) * 1998-07-30 2000-02-18 Toshiba Corp Semiconductor device and manufacture of the same
JP2001110809A (en) * 1999-10-04 2001-04-20 Toshiba Corp Semiconductor device
JP2003031574A (en) * 2001-07-13 2003-01-31 Toshiba Corp Semiconductor device and manufacturing method therefor
JP2003163263A (en) * 2001-11-27 2003-06-06 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2004214659A (en) * 2002-12-30 2004-07-29 Tobu Denshi Kk Semiconductor device contact formation method
JP2010519723A (en) * 2006-11-15 2010-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション Interconnect structure with improved reliability against electromigration and method of manufacturing the same
JP2017045991A (en) * 2015-08-27 2017-03-02 株式会社半導体エネルギー研究所 Semiconductor device, storage device, register circuit, display device and electronic equipment

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340330A (en) * 1998-05-28 1999-12-10 Toshiba Corp Manufacture of semiconductor device
JP2000049116A (en) * 1998-07-30 2000-02-18 Toshiba Corp Semiconductor device and manufacture of the same
JP2001110809A (en) * 1999-10-04 2001-04-20 Toshiba Corp Semiconductor device
JP2003031574A (en) * 2001-07-13 2003-01-31 Toshiba Corp Semiconductor device and manufacturing method therefor
JP2003163263A (en) * 2001-11-27 2003-06-06 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2004214659A (en) * 2002-12-30 2004-07-29 Tobu Denshi Kk Semiconductor device contact formation method
JP2010519723A (en) * 2006-11-15 2010-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション Interconnect structure with improved reliability against electromigration and method of manufacturing the same
JP2017045991A (en) * 2015-08-27 2017-03-02 株式会社半導体エネルギー研究所 Semiconductor device, storage device, register circuit, display device and electronic equipment

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