JP2018181890A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a large threshold voltage; and provide a semiconductor device capable of retaining data for a long time.SOLUTION: A semiconductor device having a transistor comprises: a first conductor; a first insulator arranged on the first conductor; an oxide arranged on the first insulator so as to overlap the first conductor; a second insulator arranged on the oxide; and a second conductor arranged on the second insulator so as to overlap the first conductor and the oxide. When a voltage larger than a voltage Vis applied to the second conductor with a voltage Vbeing applied to the first conductor, a channel is formed in the oxide and -δV/δVbecomes equal to or more than 0.1 and less than 1.0.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device. A display device (a liquid crystal display device, a light emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may be considered to have a semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  In recent years, semiconductor devices have been developed, and LSIs, CPUs and memories are mainly used. The CPU is a group of semiconductor elements including a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and in which electrodes serving as connection terminals are formed.

  Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on a circuit board, for example, a printed wiring board, and used as one of components of various electronic devices.

  In addition, a technique of forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials.

  In addition, a transistor including an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor including an oxide semiconductor is low is applied is disclosed (see Patent Document 1).

  Further, for example, a memory device or the like which can hold stored data for a long time by applying a characteristic that a transistor using an oxide semiconductor has low leakage current is disclosed (see Patent Document 2).

JP 2012-257187 A JP 2011-151383 A

  An object of one embodiment of the present invention is to provide a semiconductor device with a large threshold voltage. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having normally-off electrical characteristics. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device operating at a small voltage. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics.

  An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. Alternatively, it is an object of one embodiment of the present invention to provide a semiconductor device with high information writing speed. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device whose power consumption can be suppressed. Alternatively, an object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, problems other than these are naturally apparent from the description of the specification, drawings, claims and the like, and it is possible to extract the problems other than these from the description of the specification, drawings, claims and the like. It is.

One embodiment of the present invention is a semiconductor device including a transistor, which includes a first conductor, a first insulator disposed on the first conductor, and a first insulator. A first electrical conductor and an oxide on top of the oxide disposed to overlap the first electrical conductor, a second insulator disposed on the oxide, and a second electrical insulator A voltage higher than the voltage V _th is applied to the second conductor in a state in which the voltage V _BG is applied to the first conductor. Then, a channel is formed in the oxide, and the voltage V _th and the voltage V _BG satisfy the following equation (1).

In the semiconductor device described above, the voltage V _th and the voltage V _BG further satisfy the following formula (2).

In the above, the combined capacitance C _B of the first insulator and the oxide, capacitance C _T of the first insulator, satisfies the equation (3) below, is a semiconductor device according to claim.

In the above, the oxide is a layered structure of a first oxide, a second oxide on the first oxide, and a third oxide on the second oxide, The energy at the bottom of the conduction band of the first oxide and the third oxide is greater than the energy at the bottom of the conduction band of the second oxide, and the first insulator, the first oxide, and the second oxide a combined capacitance C _B of the object, the combined capacitance C _T of the third oxide and the first insulating body, satisfy equation (4) below, is a semiconductor device according to claim.

  In the above, the oxide has a channel formation region in a region overlapping with the second conductor, and has a source region and a drain region across the channel formation region in a region not overlapping with the second conductor. A semiconductor device characterized by

Another embodiment of the present invention is a semiconductor device including a first transistor and a second transistor, and the first transistor includes a first conductor and a first conductor. A first insulator disposed on the first insulator, a first oxide disposed on the first insulator to overlap the first conductor, and a first oxide on the first oxide. A second oxide disposed to overlap the first conductor, a third oxide disposed on the second oxide to overlap the first conductor, and a third oxide And a first conductor, a first oxide, a second oxide, and a third oxide overlying the second insulator and the second insulator disposed on the object And the energy of the conduction band lower end of the first oxide and the third oxide is the energy of the conduction band lower end of the second oxide. Ri large, while the voltage V _BG is applied to the first conductor, the voltage V _th is larger than the voltage applied to the second conductor, a channel is formed in the second oxide, the voltage V _th , the voltage V _BG satisfies the following equation (5), and the second transistor has a fourth oxide formed of the same material as the third oxide; One of the source and the drain and the gate of the second transistor are electrically connected to the first conductor.

In the semiconductor device described above, the voltage V _th and the voltage V _BG further satisfy the following formula (6).

In the above, the first insulator, a first oxide, and a combined capacitance C _B of the second oxide, the combined capacitance C _T of the third oxide and the first insulator, the following formula ( 7) to satisfy the above 7).

  In the above, the second oxide has a channel formation region in a region overlapping with the second conductor, and a source region and a drain region sandwiching the channel formation region in a region not overlapping with the second conductor. A semiconductor device characterized by having:

  According to one embodiment of the present invention, a semiconductor device with a large threshold voltage can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device operating at low voltage can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided.

  Alternatively, according to one embodiment of the present invention, a semiconductor device capable of holding data for a long time can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high data writing speed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high design freedom can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device whose power consumption can be suppressed can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not have to have all of these effects. Note that effects other than these are naturally apparent from the description of the specification, drawings, claims and the like, and other effects can be extracted from the descriptions of the specification, drawings, claims and the like. It is.

7A and 7B are a schematic view of a semiconductor device according to one embodiment of the present invention, and a graph showing a voltage V _th and a voltage V _BG of the semiconductor device. 7A and 7B are a schematic view of a semiconductor device according to one embodiment of the present invention, and an equivalent circuit diagram of the semiconductor device. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. 7A and 7B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. 7A and 7B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. 7A to 7C are a block diagram, a circuit diagram, and a timing chart showing an operation example of the semiconductor device, according to one embodiment of the present invention. FIG. 18 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a circuit diagram illustrating a structural example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS The block diagram which shows the structural example of AI system which concerns on 1 aspect of this invention. The block diagram explaining the application example of the AI system concerning one mode of the present invention. The perspective view showing the example of composition of IC which incorporated the AI system concerning one mode of the present invention. FIG. 7 illustrates an electronic device according to one embodiment of the present invention. The graph which shows voltage V _th and voltage V _BG of the sample which concerns on an Example. The schematic diagram of the model of the sample which concerns on an Example, and the equivalent circuit schematic of the said model.

  Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be practiced in many different aspects and that the form and details can be variously changed without departing from the spirit and scope thereof . Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Also, in the drawings, the size, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, a layer, a resist mask, and the like may be unintentionally reduced by a process such as etching, but may be omitted for ease of understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, when referring to the same function, the hatch pattern may be the same and no reference numeral may be given.

  In particular, in order to facilitate the understanding of the invention, the description of some of the components may be omitted particularly in a top view (also referred to as a "plan view") or a perspective view. In addition, the description of some hidden lines may be omitted.

  Further, in the present specification and the like, the ordinal numbers given as the first, second and the like are used for convenience, and do not indicate the order of steps or the order of layers. Therefore, for example, "first" can be appropriately replaced with "second" or "third" and the like. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  Further, in the present specification, the terms indicating the arrangement such as “above” and “below” are used for the sake of convenience to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components is appropriately changed in accordance with the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification, and can be appropriately rephrased depending on the situation.

  For example, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected, and X and Y function. It is assumed that the case where they are connected as well as the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, the present invention is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the sentence, and anything other than the connection relationship shown in the figure or the sentence is also described in the figure or the sentence.

  Here, X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).

  As an example in the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) capable of electrically connecting X and Y An element (e.g., a switch, a transistor, a capacitive element, an inductor) that enables an electrical connection between X and Y when the element, the light emitting element, the load, etc. is not connected between X and Y , X, and Y are connected without interposing a resistance element, a diode, a display element, a light emitting element, a load, and the like.

  As an example when X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, or the like) which enables electrical connection of X and Y One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on and off. That is, the switch has a function of turning on (on) or non-conducting (off) and controlling whether current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows. In addition, when X and Y are electrically connected, the case where X and Y are directly connected shall be included.

  As an example when X and Y are functionally connected, a circuit (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit, etc.) that enables functional connection of X and Y, signal conversion Circuits (DA converter circuit, AD converter circuit, gamma correction circuit, etc.), potential level converter circuits (power supply circuit (boost circuit, step-down circuit etc.), level shifter circuit for changing signal potential level, etc.) voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. It is possible to connect one or more in between. As an example, even if another circuit is interposed between X and Y, X and Y are functionally connected if the signal output from X is transmitted to Y. Do. Note that when X and Y are functionally connected, the case where X and Y are directly connected and the case where X and Y are electrically connected are included.

  Further, in this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and the drain via the channel formation region. It is possible to flow a current. In the present specification and the like, a channel region refers to a region through which current mainly flows.

  In addition, the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification and the like, the terms “source” and “drain” may be used interchangeably.

  Note that the channel length is, for example, a region where a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in the present specification, the channel length is any one value, maximum value, minimum value or average value in the region where the channel is formed.

  The channel width refers to, for example, a region in which a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other, or in a region where a channel is formed. Say the length of the part that Note that in one transistor, the channel width may not be the same in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in the present specification, the channel width is set to any one value, maximum value, minimum value or average value in the region where the channel is formed.

  Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter, “apparently” Channel width) and may be different. For example, when the gate electrode covers the side of the semiconductor, the effective channel width may be larger than the apparent channel width, and the effect may not be negligible. For example, in a transistor in which the gate electrode covers the side surface of the semiconductor finely, the ratio of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width unless the shape of the semiconductor is accurately known.

  Thus, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. Also, in the present specification, the term “channel width only” may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that the impurity of a semiconductor means, for example, elements other than the main components of the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. The inclusion of impurities may cause, for example, an increase in the DOS (Density of States) of the semiconductor, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and an oxide semiconductor. And transition metals other than the main components thereof, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, oxygen vacancies may be formed, for example, by the addition of impurities. Further, when the semiconductor is silicon, examples of the impurity that changes the characteristics of the semiconductor include oxygen, a group 1 element excluding hydrogen, a group 2 element, a group 13 element, and a group 15 element.

  In this specification and the like, the silicon oxynitride film is a film having a higher oxygen content than nitrogen as the composition. For example, preferably, oxygen is 55 atomic% or more and 65 atomic% or less, nitrogen is 1 atomic% or more and 20 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, hydrogen is 0.1 atomic% or more and 10 atomic% or less It refers to what is included in the concentration range. In addition, the silicon nitride oxide film has a nitrogen content higher than that of oxygen as its composition. For example, preferably, nitrogen is 55 atomic percent or more and 65 atomic percent or less, oxygen is 1 atomic percent or more and 20 atomic percent or less, silicon is 25 atomic percent or more and 35 atomic percent or less, and hydrogen is 0.1 atomic percent or more and 10 atomic percent or less It refers to what is included in the concentration range.

  In the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

  Further, in this specification and the like, the term "insulator" can be reworded as an insulating film or an insulating layer. Further, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be reworded as a semiconductor film or a semiconductor layer.

  In addition, transistors shown in the present specification and the like are field effect transistors except when explicitly stated. In addition, transistors shown in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the threshold voltage (also referred to as "Vth") is assumed to be larger than 0 V except when explicitly stated.

  Moreover, in this specification etc., the "parallel" means the state by which two straight lines are arrange | positioned by the angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Moreover, "substantially parallel" means the state by which two straight lines are arrange | positioned by the angle of -30 degrees or more and 30 degrees or less. Also, "vertical" means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Further, “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

  In the present specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  In this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen and oxygen, and in the case where the barrier film has conductivity, it is called a conductive barrier film. There is.

  In the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like. For example, in the case where a metal oxide is used for the active layer of the transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET, the transistor can be put in another way as a transistor having an oxide or an oxide semiconductor.

Embodiment 1
Hereinafter, the structure and characteristics of a semiconductor device according to one embodiment of the present invention will be described.

  FIG. 1A is a cross-sectional view of part of the transistor 10, which is a semiconductor device according to one embodiment of the present invention.

  As illustrated in FIG. 1A, the transistor 10 includes a conductor 21, an insulator 22 disposed on the conductor 21, and an oxide disposed on the insulator 22 so as to overlap with the conductor 21. , An insulator 25 disposed on the oxide 23, and a conductor 26 disposed on the insulator 25 so as to overlap with the conductor 21 and the oxide 23. The conductor 21 is preferably arranged to be embedded in the insulator 24.

  In FIG. 1A, the conductor 21, the insulator 24, the insulator 22, the oxide 23, the insulator 25, and the conductor 26 are each illustrated as having a single-layer structure, but the semiconductor described in this embodiment can be used. The device is not limited to this. Each of the conductor 21, the insulator 24, the insulator 22, the oxide 23, the insulator 25, and the conductor 26 may have a single-layer structure or a stacked structure of two or more layers.

The oxide 23 preferably has a channel formation region in a region overlapping the conductor 26 and a source region and a drain region in a region not overlapping the conductor 26 with the channel formation region interposed therebetween. The broken lines in FIG. 1 indicate the boundary between the source region and the channel formation region, and the boundary between the drain region and the channel formation region. FIG. 1 shows an example in which the boundary between the source region and the channel formation region and the boundary between the drain region and the channel formation region substantially coincide with the side surface of the conductor 26. However, without limitation thereto, a part of the source region on the channel formation region side and / or a part of the drain region on the channel formation region side may overlap with the conductor 26. Alternatively, the boundary between the source region and the channel formation region and / or the boundary between the drain region and the channel formation region may be provided outside the conductor 26.

  Here, in the transistor 10, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used as the oxide 23. For example, as a metal oxide to be the oxide 23, one having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used. Thus, by using a metal oxide with a wide energy gap, the off-state current of the transistor can be reduced.

  For example, In-M-Zn oxide as the oxide 23 (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium It is preferable to use a metal oxide such as one or more selected from neodymium, hafnium, tantalum, tungsten, or magnesium. Alternatively, an In-Ga oxide or an In-Zn oxide may be used as the oxide 23.

  The transistor 10 including an oxide semiconductor has extremely low leak current (off current) in a non-conductive state, so that a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device.

  On the other hand, in the transistor including an oxide semiconductor, the electrical characteristics of the transistor which is easily changed due to impurities and oxygen vacancies in the oxide semiconductor may be deteriorated in reliability. Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. Thus, a transistor including an oxide semiconductor which contains oxygen vacancies is likely to be normally on. Thus, oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.

  In particular, when oxygen vacancies are present at the interface between the channel formation region in the oxide 23 where the channel is formed and the insulator 25 functioning as a gate insulating film, fluctuations in electrical characteristics are likely to occur, and the reliability is degraded. There is a case.

  Here, oxygen vacancies formed in the channel formation region in the oxide 23 can be reduced by supplying oxygen. In order to supply oxygen to the channel formation region, an insulator 25 containing oxygen may be provided in contact with the oxide 23, for example. Preferably, the insulator 25 may contain more oxygen (hereinafter also referred to as excess oxygen) than oxygen having a stoichiometric composition. That is, oxygen excess in the insulator 25 diffuses to the oxide 23, whereby oxygen vacancies in the oxide 23 can be reduced.

For example, as an insulator having an excess oxygen region that can be used for the insulator 25, it is preferable to use an oxide material from which part of oxygen is released by heating. The oxide from which oxygen is released by heating means that the amount of released oxygen in terms of molecular oxygen is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably TDS (Thermal Desorption Spectroscopy) analysis. It is an oxide film which is 1.0 × 10 ¹⁹ atoms / cm ³ or more, preferably 2.0 × 10 ¹⁹ atoms / cm ³ , more preferably 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C.

  Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

  The conductor 26 functions as a first gate (also referred to as a top gate) electrode, and the conductor 21 functions as a second gate (also referred to as a bottom gate) electrode. The threshold voltage of the transistor 10 can be controlled by independently changing the potential applied to the conductor 21 without interlocking with the potential applied to the conductor 26. In particular, by applying a negative potential to the conductor 21, the threshold voltage of the transistor 10 can be made larger than 0 V, and the drain current when the voltage applied to the conductor 26 is 0 V (hereinafter referred to as Icut). ) Can be made smaller.

In the transistor 10, in a state where the voltage V _BG [V] is applied to the bottom gate, when a voltage larger than the voltage V _th [V] is applied to the top gate, a channel starts to be formed in the oxide 23 or nearby I assume. The voltage V _th at this time can be referred to as the threshold voltage of the transistor 10.

The voltage V _th has a top gate voltage V _g [V] on the horizontal axis, and a drain current square root I I _d [A] plotted on the vertical axis on the linear scale on the V _g −√ I _d curve. can be the tangent at the point slope of the maximum, the top gate voltage V _g at the intersection of the Vg axis.

However, the method of obtaining the voltage V _th is not limited to the above. For example, in the V _g -I _d curve in which the top gate voltage V _g [V] is plotted on the horizontal axis and the logarithm of the drain current I _d [A] is plotted on the vertical axis, the voltage V _th has a maximum slope on the curve. The top gate voltage V _g may be a cross point of a tangent at a certain point and a straight line of I _d = 1.0 × 10 ⁻¹² [A].

As described above, in the semiconductor device described in this embodiment, by applying the voltage V _BG to the conductor 21, the voltage V _th can be increased and Icut of the transistor 10 can be sufficiently reduced. In other words, the transistor 10 can be provided with normally-off electrical characteristics.

For example, the transistor 10 having normally-off electrical characteristics can be used as a switching transistor of a memory cell of a memory device. Here, the switching transistor is a transistor connected to a node (hereinafter, may be referred to as a storage node) which holds a charge corresponding to data. As described above, since the transistor 10 has extremely low off-state current, the amount of charge released from the storage node can be extremely reduced, and the data retention time of the storage device can be extended. Further, since the transistor 10 has a large voltage V _{th and a} small Icut, data can be held without applying a potential with a large absolute value to the top gate of the transistor 10, and power consumption of the storage device is reduced. Can. As described above, by using the transistor 10 as a switching transistor of a memory cell of a memory device, data holding time of the memory device can be extended and power consumption can be reduced.

Next, controllability of the voltage V _th by the voltage V _BG of the transistor 10 will be described with reference to FIG. FIG. 1B is a graph obtained by measuring and plotting the voltage V _th with respect to the voltage V _BG in a sample having a structure similar to that of the transistor 10. In the graph shown in FIG. 1B, the vertical axis represents voltage V _th [V], and the horizontal axis represents voltage V _BG [V]. However, the horizontal axis is reversed in positive and negative directions.

As shown in FIG. 1B, the plots of the voltage V _BG and the voltage V _th are approximated by a straight line having a constant slope k. The slope k of this straight line can be expressed by −∂V _th / ∂V _BG . Here, as the value of −∂V _th / ∂V _BG is larger, the variation of the threshold voltage V _th per unit voltage applied to the bottom gate is larger. That is, it can be said that the controllability of the voltage V _th by the voltage V _BG of the transistor 10 is better as the value of −∂V _th / ∂V _BG is larger. Thus, in the transistor 10, −∂V _th / ∂V _BG can be treated as an index of controllability of the voltage V _th by the voltage V _BG .

In the transistor 10,-好 ま し い V _th / ∂V _BG is preferably as large as possible. On the other hand, when the voltage V _th is precisely controlled, if -∂V _th / ∂V _BG is excessively large, control of the voltage V _th may be difficult. Therefore, for example, in the transistor 10, the voltage V _BG and the voltage V _th preferably satisfy the following Expression (8), and more preferably the following Expression (9).

In the transistor 10 in which -∂V _th / ∂V _BG takes the above range, the voltage V _th can be increased at a voltage V _BG with a small absolute value, and Icut of the transistor 10 can be sufficiently reduced. Thus, the transistor 10 can be provided which operates at the voltage V _BG having a small absolute value and has normally-off electrical characteristics.

  For example, by using such a transistor 10 as a switching transistor of a memory cell of a memory device, data can be held without applying a potential with a large absolute value to the top gate and the bottom gate of the transistor 10; The power consumption of the device can be further reduced. As described above, by using the transistor 10 as a switching transistor of a memory cell of a memory device, data holding time of the memory device can be extended and power consumption can be reduced.

Although the structure in which the threshold voltage of the transistor 10 is increased has been described above, the semiconductor device described in this embodiment is not limited to this. As shown in FIG. 1B,-、 V _th / ∂V _BG has a constant value even in a region where the voltage V _BG takes a positive value. For example, if the threshold voltage of the transistor when the bottom gate voltage is 0 V is excessively large, the threshold voltage can be shifted to near 0 V by increasing the voltage V _BG .

The −∂V _th / ∂V _BG of the transistor 10 can be approximately obtained from the structure of the transistor 10. A method of obtaining −∂V _th / ∂V _BG from the structure of the transistor 10 will be described with reference to FIG. FIG. 2A is a schematic view showing a model between the top gate and the bottom gate of the transistor 10, and FIG. 2B is an equivalent circuit diagram corresponding to the model shown in FIG. 2A.

In the model of the transistor 10 shown in FIG. 2A, the conductor 21 has a function as a bottom gate, the insulator 22 has a function as a bottom gate gate insulator, and the oxide 23 is a channel formation region The conductor 26 has a function as a top gate, and the insulator 25 has a function as a gate insulator for the top gate. Here, the electrostatic capacitance of the insulator 22 and _{C BGI,} the capacitance of the oxide 23 and _{C S,} the electrostatic capacitance of the insulator 25 and _{C TGI,} model of the transistor 10, FIG. 2 (B It represents with the equivalent circuit diagram shown to. Note that in the case where the insulator 22, the oxide 23, and the insulator 25 are each formed of a stacked film, C _BGI , C _S , and C _TGI may each be a combined capacitance of series of stacked films.

In the transistor 10 shown in FIG. 2A, when the voltage V _TH is applied to the conductor 26 in the state where the voltage V _BG is applied to the conductor 21, a channel is formed in the vicinity of the interface between the oxide 23 and the insulator 25. Start being done. Hereinafter, in the transistor 10, a region where a channel is formed is referred to as a region P.

The voltage between the conductor 21 and the region P is V _B and the combined capacitance is C _B. Here, the combined capacitance _{C B is} the combined capacitance of _{C BGI} and _{C S.} Further, the voltage between the conductor 26 and the region P is V _T and the combined capacitance is C _T. Here, the combined capacitance _{C T is} equal to the _{C TGI.}

When a threshold voltage is applied to the conductor 26 and a channel starts to be formed in the region P, the amount of charge held in the region P can be regarded as zero. Therefore, the amount of charge held in the combined capacitance C _B, the charge amount is equal to be held in the combined capacitance C _T, following equation holds (10). Here, fixed charges and impurities are not considered as a model. Also in the case where these are taken into consideration, in the following calculation, the terms relating to the fixed charge and the charge of the impurity become 0, so the obtained expressions are the same.

The voltage V _T can be expressed by the following equation (11) using the voltage V _th , the elementary charge e, the work function φ _mT of the conductor 26, and the electron affinity χ _S of the oxide 23.

The voltage V _B can be expressed by the following equation (12) using the voltage V _BG , the elementary charge e, the work function φ _mB of the conductor 21, and the electron affinity χ _S of the oxide 23.

By solving equation (10) using equations (11) and (12), the following equation (13) is obtained. In equation (13), the constant not related to V _BG is constant K.

When V _th in equation (13) is partially differentiated with respect to V _BG , the following equation (14) is obtained.

Thus, -∂V _th / ∂V _BG can be obtained from the combined capacitance of the insulator 22 and the oxide 23 and the capacitance of the insulator 25. Thus, for example, in the transistor 10, the combined capacitance _{C B} combined capacity _{C T} is preferably satisfies the formula (15) below, it is more preferred to satisfy the equation (16) below.

In the transistor 10 in which C _B / C _T takes the above range, the voltage V _th can be increased and the Icut of the transistor 10 can be sufficiently reduced by the voltage V _BG having a small absolute value. Thus, the transistor 10 can be provided which operates at a voltage with a small absolute value and has normally-off electrical characteristics. Furthermore, by using such a transistor 10 as a switching transistor of a memory cell of a memory device, data retention time of the memory device can be extended and power consumption can be reduced.

Also, when the film to form a combined capacitance _{C B} combined capacity _{C T} is flat type, the equation (14), the equivalent oxide thickness (EOT: Equivalent oxide thickness) can also be represented using. In the present specification, the equivalent oxide thickness means a value obtained by converting the physical thickness to an electrical thickness equivalent to silicon oxide or silicon oxynitride.

In the transistor 10, between the conductor 21 and the region P, and EOT and EOT _B. Here, EOT _B is the sum of EOT of insulator 22 and oxide 23. Further, between the conductor 26 and the region P, and EOT and EOT _T. Here, EOT _T is the EOT of the insulator 25. Since EOT is proportional to the reciprocal of capacitance, equation (17) below holds from equation (14).

  Although the case where the region P is formed in the vicinity of the interface between the oxide 23 and the insulator 25 has been described above, the semiconductor device described in this embodiment is not limited to this. As shown in FIGS. 2C and 2D, the oxide 23 has a laminated structure of the oxide 23a, the oxide 23b, and the oxide 23c, and the region P is formed in the vicinity of the interface between the oxide 23b and the oxide 23c. May be configured. FIG. 2C is a schematic view showing a model between the top gate and the bottom gate of the transistor 10 in which the oxide 23 has a stacked structure, and FIG. 2D corresponds to the model shown in FIG. 2C. It is an equivalent circuit schematic.

  In the model illustrated in FIG. 2C, the oxide 23 includes an oxide 23a, an oxide 23b over the oxide 23a, and an oxide 23c over the oxide 23b. By including the oxide 23 b on the oxide 23 a, diffusion of impurities from the structure formed below the oxide 23 a to the oxide 23 b can be suppressed. In addition, by including the oxide 23 b under the oxide 23 c, diffusion of impurities to the oxide 23 b can be suppressed from a structure formed above the oxide 23 c.

  Moreover, it is preferable that the oxide 23 has a laminated structure by the oxide from which the atomic ratio of each metal atom differs. Specifically, in the metal oxide used for the oxide 23a, the atomic ratio of the element M in the constituent elements is larger than the atomic ratio of the element M in the constituent elements of the metal oxide used for the oxide 23b. Is preferred. In the metal oxide used for the oxide 23a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 23b. In the metal oxide used for the oxide 23b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 23a. As the oxide 23c, a metal oxide which can be used for the oxide 23a or the oxide 23b can be used.

  Further, it is preferable that the energy of the conduction band lower end of the oxide 23a and the oxide 23c be higher than the energy of the conduction band lower end of the oxide 23b. In other words, it is preferable that the electron affinity of the oxide 23a and the oxide 23c be smaller than the electron affinity of the oxide 23b.

  Here, in the oxide 23a, the oxide 23b, and the oxide 23c, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it changes continuously or joins continuously. In order to do this, it is preferable to lower the density of defect states in the mixed layer formed at the interface between the oxide 23a and the oxide 23b and at the interface between the oxide 23b and the oxide 23c.

  Specifically, the oxide layer 23a and the oxide layer 23b, and the oxide layer 23b and the oxide layer 23c have a common element other than oxygen (which is a main component), whereby a mixed layer with low density of defect states is formed. be able to. For example, in the case where the oxide 23 b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like may be used as the oxide 23 a and the oxide 23 c.

  At this time, the main path of the carrier is at or near the oxide 23b, for example, the interface between the oxide 23b and the oxide 23a. Since the density of defect states at the interface between the oxide 23a and the oxide 23b and at the interface between the oxide 23b and the oxide 23c can be lowered, the influence of interface scattering on carrier conduction is small, and a high on current can be obtained. can get.

In the model of the transistor 10 shown in FIG. 2 (C), the capacitance of the oxide 23a and _{C S1,} the electrostatic capacitance of the oxide 23b and _{C S2,} when the capacitance of the oxide 23c and _{C S3,} The model of the transistor 10 shown in FIG. 2C is represented by an equivalent circuit diagram shown in FIG.

Combined capacitance _{C B} between the conductor 21 and the region P _is a combined capacitance of _{C BGI} and _{C S1} and _{C S2.} Further, the combined capacitance _{C T} between conductor 26 and region P _is a combined capacitance of _{C S3} and _{C TGI.} For combined capacitance _{C B} and a combined capacitance _{C T,} equation (14) holds. Even in the transistor 10 in which the oxide 23 has a stacked structure, the voltage V _th is increased at the voltage V _BG with a small absolute value by configuring the transistor 10 to satisfy the equation (15) or (16). Can be made small enough. Thus, the transistor 10 can be provided which operates at a voltage with a small absolute value and has normally-off electrical characteristics. Furthermore, by using such a transistor 10 as a switching transistor of a memory cell of a memory device, data retention time of the memory device can be extended and power consumption can be reduced.

  As described above, according to one embodiment of the present invention, a semiconductor device with a large threshold voltage can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device operating at a voltage with a small absolute value can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments.

Second Embodiment
Hereinafter, an example of a specific structure of the transistor described in the above embodiment will be described with reference to FIGS.

<Configuration Example of Semiconductor Device>
FIGS. 3A, 3B, and 3C are a top view and a cross-sectional view of a transistor 200, and a periphery of the transistor 200, according to one embodiment of the present invention.

  FIG. 3A is a top view of a semiconductor device including the transistor 200. FIG. 3B and 3C are cross-sectional views of the semiconductor device. Here, FIG. 3B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 3A, and is also a cross-sectional view in the channel length direction of the transistor 200. 3C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 3A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 3A, some elements are omitted for clarity of the drawing.

  The semiconductor device of one embodiment of the present invention includes the transistor 200, the insulator 210 functioning as an interlayer film, the insulator 212, and the insulator 280. In addition, the transistor 200 includes the conductor 203 (the conductor 203a and the conductor 203b) which is electrically connected to the transistor 200 and functions as a wiring, and the conductor 240 (the conductor 240a and the conductor 240b) which functions as a plug. .

  A conductor 203a is formed in contact with the inner wall of the opening of the insulator 212, and a conductor 203b is formed inside the conductor 203. Here, the height of the top surface of the conductor 203 and the height of the top surface of the insulator 212 can be approximately the same. Note that although the transistor 200 illustrates a structure in which the conductor 203a and the conductor 203b are stacked, the present invention is not limited to this. For example, only the conductor 203b may be provided.

  The conductor 240 is formed in contact with the inner wall of the opening of the insulator 280. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 280 can be approximately the same. Note that in the transistor 200, the structure in which the conductor 240 is a single layer is shown; however, the present invention is not limited to this. For example, the conductor 240 may have a stacked structure of two or more layers.

[Transistor 200]
As shown in FIG. 3, the transistor 200 includes an insulator 214 and an insulator 216 disposed on a substrate (not shown), and a conductor 205 disposed to be embedded in the insulator 214 and the insulator 216. An insulator 220 disposed on the insulator 216 and the conductor 205, an insulator 222 disposed on the insulator 220, an insulator 224 disposed on the insulator 222, and the insulator The oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) disposed on the 224, the insulator 250 disposed on the oxide 230, and the insulator disposed on the insulator 250 252, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 252, an insulator 270 disposed on the conductor 260, and at least the insulator 250, And has an insulator 272 which is arranged in contact with a side surface of the conductor 260, the oxide 230 insulator 274 and disposed in contact with the insulator 272, and.

  Note that although the transistor 200 illustrates the structure in which the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this. Alternatively, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of three or more layers may be provided. In the transistor 200, the conductor 260a and the conductor 260b are stacked; however, the present invention is not limited to this.

  Here, the conductor 205 corresponds to the conductor 21 of the transistor 10 described in the above embodiment. The insulator 214 and the insulator 216 correspond to the conductor 21 of the transistor 10 described in the above embodiment. The insulator 220, the insulator 222, and the insulator 224 correspond to the insulator 22 of the transistor 10 described in the above embodiment. The oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) corresponds to the oxide 23 (the oxide 23a, the oxide 23b, and the oxide 23c) of the transistor 10 described in the above embodiment. The insulator 250 and the insulator 252 correspond to the insulator 25 of the transistor 10 described in the above embodiment. The conductor 260 corresponds to the conductor 26 of the transistor 10 described in the above embodiment.

In the transistor 200, when a voltage higher than the voltage V _th [V] is applied to the conductor 260 in the state where the voltage V _BG [V] is applied to the conductor 205, the oxide 230 or near it (eg, oxidation) It is assumed that a channel starts to be formed at the interface between the object 230b and the oxide 230c). As shown in the above embodiment, it is preferable that -∂V _th / ∂V _BG be as large as possible, and for example, it is preferable to satisfy the above-mentioned formula (8) or formula (9).

In the case where the region P is formed at the interface between the oxide 230 _b and the oxide 230 c of the transistor 200, the combined capacitance CB between the conductor 205 and the region P is the insulator 220, the insulator 222, the insulator 224, and the oxide It becomes the synthetic capacity of 230a and oxide 230b. Further, the combined capacitance _{C T} between the conductor 260 and the region P will combined capacitance of the oxide 230c, insulators 250, and the insulator 252. Combined capacitance of the transistor 200 _{C B} and a combined capacitance _{C T} is, it is preferable to satisfy the above equation (14), further preferably satisfy the above formula (15) or formula (16).

By using such a transistor 200, the voltage V _th can be increased at a voltage V _BG with a small absolute value, and Icut of the transistor 200 can be sufficiently reduced. Thus, the transistor 200 can be provided which operates at a voltage with a small absolute value and has normally-off electrical characteristics. Further, by using such a transistor 200 as a switching transistor of a memory cell of a memory device, data holding time of the memory device can be extended and power consumption can be reduced.

  Further, FIG. 4 shows an enlarged view of a region 239 in the vicinity of the channel which is surrounded by a broken line in FIG. 3 (B).

  As illustrated in FIG. 4, the oxide 230 is a region 232 between the region 234 which functions as a channel formation region of the transistor 200 and the regions 231 (the regions 231 a and 231 b) which function as source and drain regions. (The region 232a and the region 232b) are included. The region 231 functioning as a source region or a drain region is a low-resistance region in which the carrier density is high. The region 234 functioning as a channel formation region is a region having a lower carrier density than the region 231 functioning as a source region or a drain region. The region 232 has a lower carrier density than the region 231 functioning as a source or drain region and a higher carrier density than the region 234 functioning as a channel formation region. That is, the region 232 functions as a junction region between the channel formation region and the source or drain region. Note that the region 232 may function as a so-called overlap region (also referred to as a Lov region) overlapping with the conductor 260 functioning as a gate electrode.

  By providing the junction region, a high resistance region is not formed between the region 231 functioning as a source or drain region and the region 234 functioning as a channel formation region, so that the on current of the transistor can be increased.

  Further, in order to efficiently supply the excess oxygen of the insulator 250 to the oxide 230, the insulator 252 preferably suppresses oxygen diffusion. By providing the insulator 252 which suppresses diffusion of oxygen, diffusion of excess oxygen into the conductor 260 is suppressed. That is, the decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductor 260 due to excess oxygen can be suppressed.

  In addition, the insulator 250 and the insulator 252 may have a function as part of a gate insulator. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, it is preferable that the insulator 252 be a metal oxide which is a high-k material having a high dielectric constant. With this laminated structure, a laminated structure stable to heat and having a high relative dielectric constant can be obtained. Therefore, it is possible to thin the gate insulator EOT while maintaining the physical film thickness.

  With the above-described stacked structure, the on current can be improved without weakening the influence of the electric field from the conductor 260. Further, the physical thickness of the insulator 250 and the insulator 252 can suppress leakage current by maintaining the distance between the conductor 260 and the oxide 230. In addition, by providing the layered structure of the insulator 250 and the insulator 252, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily obtained. Can be adjusted accordingly.

  Here, as the insulator 252, a film having low crystallinity (or less crystals) or a film including an amorphous structure may be used. An oxide film having low crystallinity or an amorphous structure can diffuse oxygen of the oxide film to a nearby insulator by heating. For example, when a film with low crystallinity or a film including an amorphous structure is used for the insulator 252, excess oxygen is added to the insulator 250 from the insulator 252 due to the thermal history of a later step, and the insulator 250 is excessive. An oxygen region can be easily formed. In addition, a film with low crystallinity or a film including an amorphous structure has high planarity, and the interface between the insulator 250 and the insulator 252 can be in a favorable state.

  Specifically, a metal oxide containing as the insulator 252 one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium etc. A thing can be used.

  In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step.

  For example, an insulating film whose root mean square surface roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 μm × 1 μm, as a film having high flatness It is good to use the body.

  For example, as a film with low crystallinity, it is preferable to use an insulator in which a region with high luminance is observed as a result of an electron beam diffraction pattern using an electron microscope draws a circle (in a ring shape).

  Further, the insulator 272 is preferably provided in contact with the insulator 250 and the insulator 252. For example, the insulator 272 may have a function of suppressing at least one diffusion of oxygen (eg, an oxygen atom, an oxygen molecule, and the like). Since the insulator 272 has a function of suppressing the diffusion of oxygen, oxygen in the excess oxygen region of the insulator 250 is efficiently supplied to the region 234 without being diffused to the insulator 274 side. Thus, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 can be suppressed, and the reliability of the transistor 200 can be improved.

  Thus, a semiconductor device including a transistor including an oxide semiconductor with large on current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off current can be provided. Alternatively, it is possible to provide a semiconductor device with stable electrical characteristics and improved reliability while suppressing fluctuations in the electrical characteristics.

  Hereinafter, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

  The conductor 203 is extended in the channel width direction as illustrated in FIGS. 3A and 3C, and functions as a wiring for applying a potential to the conductor 205. Note that the conductor 203 is preferably provided so as to be embedded in the insulator 214 and the insulator 216.

  The conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260. The conductor 205 may be provided on and in contact with the conductor 203.

  By providing the conductor 205 over the conductor 203, the distance between the conductor 260 having a function as the first gate electrode and a wiring and the conductor 203 can be appropriately designed. That is, the insulator 214, the insulator 216, and the like are provided between the conductor 203 and the conductor 260, parasitic capacitance between the conductor 203 and the conductor 260 can be reduced, and withstand voltage can be increased.

  In addition, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor can be improved and the transistor can have high frequency characteristics. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200 can be improved. Therefore, the thicknesses of the insulator 214 and the insulator 216 are preferably large. Note that the extension direction of the conductor 203 is not limited to this. For example, the conductor 203 may extend in the channel length direction of the transistor 200.

  Note that the conductor 205 is disposed so as to overlap with the oxide 230 and the conductor 260 as illustrated in FIG. In addition, the conductor 205 may be larger than the region 234 in the oxide 230. In particular, as shown in FIG. 3C, the conductor 205 extends also in the region outside the end portion of the region 234 of the oxide 230 which intersects the channel width direction (W length direction). preferable. That is, on the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other through an insulator.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, a closed circuit is formed by connecting the electric field generated from the conductor 260 and the electric field generated from the conductor 205, thereby forming an oxidized circuit. The channel formation region formed in the object 230 can be covered.

  That is, the channel formation region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode. . In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

  In addition, the conductor 205 is in contact with the inner wall of the opening of the insulator 214 and the insulator 216, the conductor 205a is formed, and the conductor 205b is formed further inside. Here, the heights of the top surfaces of the conductors 205a and 205b and the top surface of the insulator 216 can be approximately the same. Note that although the transistor 200 illustrates a structure in which the conductor 205a and the conductor 205b are stacked, the present invention is not limited to this. For example, only the conductor 205b may be provided.

Here, the conductor 205a and the conductor 203a can diffuse impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _{2 and the} like), copper atoms, and the like. It is preferable to use a conductive material having a suppressing function (it is difficult for the above-mentioned impurities to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like) (the above-described oxygen is difficult to permeate). Note that, in the present specification, the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the impurities or the oxygen.

  When the conductor 205a and the conductor 203a have a function of suppressing the diffusion of oxygen, the conductor 205b and the conductor 203b can be prevented from being oxidized and the conductivity being lowered. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used. Therefore, the conductive material may be formed as a single layer or a stack as the conductor 205a and the conductor 203a. Accordingly, diffusion of impurities such as hydrogen and water can be suppressed from the insulator 210 to the transistor 200 side through the conductor 203 and the conductor 205 from the substrate side.

  The conductor 205 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. Note that although the conductor 205 b is illustrated as a single layer, a layered structure may be used, and for example, titanium, titanium nitride, and the above conductive material may be stacked.

  In addition, since the conductor 203b functions as a wiring, it is preferable to use a conductor having higher conductivity than the conductor 205b. For example, a conductive material containing copper or aluminum as a main component can be used. The conductor 203b may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.

  In particular, copper is preferably used for the conductor 203. Copper is preferably used for wiring and the like because it has low resistance. On the other hand, copper is easily diffused and thus diffusion to the oxide 230 may deteriorate the characteristics of the transistor 200. Therefore, for example, by using a material such as aluminum oxide or hafnium oxide with low copper permeability for the insulator 214, copper diffusion can be suppressed.

The insulator 210 and the insulator 214 preferably function as a barrier insulating film which prevents impurities such as water or hydrogen from entering the transistor from the substrate side. Therefore, the insulator 210 and the insulator 214 suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), copper atoms, etc. It is preferable to use an insulating material having the following function (it is difficult for the above-mentioned impurities to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like) (the above oxygen is difficult to transmit).

  For example, aluminum oxide or the like is preferably used as the insulator 210, and silicon nitride or the like is preferably used as the insulator 214. Accordingly, diffusion of impurities such as hydrogen and water from the insulator 210 and the insulator 214 toward the transistor can be suppressed. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side more than the insulator 210 and the insulator 214.

  Further, by providing the conductor 205 over the conductor 203, the insulator 214 can be provided between the conductor 203 and the conductor 205. Here, even when a metal such as copper which easily diffuses is used for the conductor 203 b, the metal can be prevented from diffusing into a layer higher than the insulator 214 by providing silicon nitride or the like as the insulator 214.

  The insulator 212, the insulator 216, and the insulator 280 which function as interlayer films preferably have a lower dielectric constant than the insulator 210 or the insulator 214. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

For example, as the insulator 212, the insulator 216, and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), titanate An insulator such as strontium (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used in a single layer or a stack. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  The insulator 220, the insulator 222, and the insulator 224 function as gate insulators.

  Here, the insulator 224 in contact with the oxide 230 is preferably an oxide insulator which contains oxygen at a higher proportion than the stoichiometric composition. That is, it is preferable that an excess oxygen region be formed in the insulator 224. By providing an insulator containing such excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide from which oxygen is released by heating is a desorption amount of oxygen of at least 1.0 × 10 ¹⁸ atoms / cm ³ , preferably 1 in terms of oxygen atom in TDS (thermal desorption spectroscopy) analysis. It is an oxide film having a density of not less than 0 × 10 ¹⁹ atoms / cm ³ , more preferably not less than 2.0 × 10 ¹⁹ atoms / cm ³ , or not less than 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.

  In addition, in the case where the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing at least one diffusion of oxygen (eg, oxygen atom, oxygen molecule, and the like) (the above oxygen is difficult to transmit). Is preferred.

  With the insulator 222 having a function of suppressing the diffusion of oxygen, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without being diffused to the insulator 220 side. Further, the conductor 205 can be inhibited from reacting with oxygen in the excess oxygen region of the insulator 224.

The insulator 222 is, for example, a so-called high material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). It is preferable to use an insulator containing a -k material in a single layer or a stack. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, the physical thickness can be maintained and voltage can be reduced.

  In particular, it is preferable to use an insulator including an oxide of one or both of an impurity and an insulating material having a function of suppressing diffusion of oxygen and the like (the above-described oxygen is difficult to transmit). As an insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When formed using such a material, it functions as a layer that prevents the release of oxygen from the oxide 230 and the entry of an impurity such as hydrogen from the peripheral portion of the transistor 200.

  Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  Further, the insulator 220 is preferably thermally stable. For example, since silicon oxide and silicon oxynitride are thermally stable, the combination with an insulator of a high-k material 222 can provide a stacked structure with high thermal stability and high dielectric constant.

  In the above, although the structure which provides the insulator 220, the insulator 222, and the insulator 224 as a bottom gate insulating film was demonstrated, it is not restricted to this. For example, a single layer or two layers may be provided without any of the insulator 220, the insulator 222, and the insulator 224. Further, for example, the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.

For example, hafnium oxide (HfO _x ) and aluminum oxide (AlO _x ) may be used as the insulator 222 and sequentially stacked from HfO _x , AlO _x , HfO _x , AlO _x from the conductor 205 side. . At this time, the film thickness of each layer may be about 2 to 5 nm, and the film thickness of the insulator 222 may be about 10 to 20 nm. It is preferable to perform such film formation of the insulator 222 while switching the film formation gas for each layer using the ALD method. By forming the insulator 222 in such a film configuration, it is possible to prevent the generation of a leak current due to the crystallization of HfO _x . In addition, the insulator 222 may be configured to be stacked with SiO _x , HfO _x , SiO _x , HfO _x sequentially from the conductor 205 side using hafnium oxide (HfO _x ) and silicon oxide (SiO _x ). Good. Such an insulator 222 may be stacked between the insulator 220 and the insulator 224, or the insulator 220 and / or the insulator 224 may not be provided.

  In addition, the oxide 230 preferably includes a region 231, a region 232, and a region 234. Note that at least a part of the region 231 is in contact with the insulator 274, and it is preferable that the concentration of at least one of a metal element such as indium, hydrogen, and nitrogen be higher than that of the region 234. In addition, the region 232 preferably has a concentration of at least one of a metal element such as indium, hydrogen, and nitrogen higher than the region 234 and lower than the region 231.

  That is, the regions 231 and 232 are regions in which metal atoms such as indium and gallium or impurities are added to the metal oxide provided as the oxide 230. Note that the region 231 is higher in conductivity than the region 234. Note that, in order to add impurities to the region 231 and the region 232, for example, plasma treatment, an ion implantation method in which ionized source gas is separated by mass separation, or ionized source gas is added without mass separation A dopant which is at least one of a metal element such as indium and an impurity may be added using an ion doping method, a plasma immersion ion implantation method, or the like.

  For example, by forming the insulator 274 containing an element serving as an impurity in contact with the oxide 230, impurities can be added to the regions 231 and 232. Alternatively, by increasing the content of metal atoms such as indium in the oxide 230 in the region 231, electron mobility can be increased and resistance can be reduced.

  That is, the region 231 is reduced in resistance by the addition of an element which forms an oxygen vacancy or an element which is trapped in the oxygen vacancy. As such an element, typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas and the like can be mentioned. Further, helium, neon, argon, krypton, xenon and the like can be given as typical examples of the rare gas element. Thus, the region 231 may include one or more of the above elements.

  Note that in FIG. 3 and FIG. 4, the region 234, the region 231, and the region 232 are formed in the oxide 230b, but the present invention is not limited thereto. For example, these regions include the oxide 230a and an oxide The object 230c may also be formed. Further, in FIG. 3 and FIG. 4, the boundaries of the respective regions are displayed substantially perpendicular to the top surface of the oxide 230, but the present embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 in the vicinity of the surface of the oxide 230 b and may be recessed toward the conductor 240 a or the conductor 240 b in the vicinity of the lower surface of the oxide 230 a.

  In the transistor 200, in the case where the resistance of the region 232 is lowered, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; , And mobility can be increased. Further, by including the region 232, the source region and the drain region do not overlap with the gate in the channel length direction, so that formation of unnecessary capacitance can be suppressed. Further, by including the region 232, leakage current in non-conduction can be reduced.

  In addition, for example, in the case where gallium or the like is added to the region 232, reduction in the unintended effective channel length can be suppressed by suppressing lateral diffusion of an impurity such as hydrogen from the region 231 to the region 234.

  Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements according to the circuit design.

  Thus, when the transistor 200 is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least a part of the region 234 functions as a region in which a channel is formed. With the region 232 between the region 231 and the region 234, in the transistor 200, the on-state current can be increased and the leakage current (off-state current) can be reduced.

  In addition, a curved surface is provided between the side surface of the oxide 230 and the top surface of the oxide 230. That is, the end of the side surface and the end of the upper surface are preferably curved (hereinafter, also referred to as a round shape). The curved surface preferably has a curvature radius of 3 nm to 10 nm, preferably 5 nm to 6 nm, at an end portion of the oxide 230 b, for example.

  In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.

  A transistor including an oxide semiconductor has extremely low leak current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. Further, an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device.

The insulator 250 functions as a gate insulating film. The insulator 250 is preferably placed in contact with the top surface of the oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in temperature-programmed desorption gas analysis (TDS analysis), the desorption amount of oxygen in terms of molecular oxygen is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 1.0 × 10 ^19. It is an oxide film which is atoms / cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms / cm ³ or 3.0 × 10 ²⁰ atoms / cm ³ . The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C.

  Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

  By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

  Further, in order to efficiently supply the excess oxygen of the insulator 250 to the oxide 230, the insulator 252 preferably suppresses oxygen diffusion. By providing the insulator 252 which suppresses diffusion of oxygen, diffusion of excess oxygen into the conductor 260 is suppressed. That is, the decrease in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductor 260 due to excess oxygen can be suppressed.

  In addition, the insulator 250 and the insulator 252 may have a function as part of a gate insulator. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, it is preferable that the insulator 252 be a metal oxide which is a high-k material having a high dielectric constant. With this laminated structure, a laminated structure stable to heat and having a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness.

  With the above-described stacked structure, the on current can be improved without weakening the influence of the electric field from the conductor 260. Further, the physical thickness of the insulator 250 and the insulator 252 can suppress leakage current by maintaining the distance between the conductor 260 and the oxide 230. In addition, by providing the layered structure of the insulator 250 and the insulator 252, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily obtained. Can be adjusted accordingly.

  Here, as the insulator 252, a film having low crystallinity (or less crystals) or a film including an amorphous structure may be used. An oxide film having low crystallinity or an amorphous structure can diffuse oxygen of the oxide film to a nearby insulator by heating. For example, when a film with low crystallinity or a film including an amorphous structure is used for the insulator 252, excess oxygen is added to the insulator 250 from the insulator 252 due to the thermal history of a later step, and the insulator 250 is excessive. An oxygen region can be easily formed. In addition, a film with low crystallinity or a film including an amorphous structure has high planarity, and the interface between the insulator 250 and the insulator 252 can be in a favorable state.

  Specifically, a metal oxide containing as the insulator 252 one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium etc. A thing can be used.

  In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like, which is an insulator containing one or both oxides of aluminum and hafnium, is preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in a later step.

  For example, an insulating film whose root mean square surface roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 μm × 1 μm, as a film having high flatness It is good to use the body.

  For example, as a film with low crystallinity, it is preferable to use an insulator in which a region with high luminance is observed as a result of an electron beam diffraction pattern using an electron microscope draws a circle (in a ring shape).

  In the above, although the structure which provides the insulator 250 and the insulator 252 as a top gate insulating film was demonstrated, it is not restricted to this. For example, a single layer may be provided without any of the insulator 250 and the insulator 252. For example, the insulator 250 and the insulator 252 may have a stacked structure of two or more layers. In that case, the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.

For example, silicon oxide (SiO _x ) is used as the insulator 250, hafnium oxide (HfO _x ) is used as the insulator 252, and SiO _x , HfO _x , SiO _x , HfO _x are sequentially stacked from the oxide 230 side. It may be configured. At this time, the film thickness of each layer may be about 2 to 5 nm, and the total film thickness may be about 10 to 20 nm. It is preferable that such film formation of the insulator 250 and the insulator 252 be performed while switching the film formation gas for each layer using an ALD method. By forming the insulator 250 and the insulator 252 in such a film configuration, it is possible to prevent the generation of a leakage current due to the crystallization of HfO _x . In addition, aluminum oxide (AlO _x ) is used as the insulator 250, and hafnium oxide (HfO _x ) is used as the insulator 252, and these layers are stacked sequentially with AlO _x , HfO _x , AlO _x , HfO _x from the oxide 230 side. It may be configured.

A conductor 260 functioning as a first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a. The conductor 260a, like the conductor 205a, diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.), copper atoms, etc. It is preferable to use a conductive material having a suppressing function. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of at least one of oxygen (eg, oxygen atom, oxygen molecule, and the like).

  When the conductor 260a has a function of suppressing the diffusion of oxygen, excess oxygen of the insulator 250 and the insulator 252 can prevent the conductor 260b from being oxidized and the conductivity being lowered. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used.

  The conductor 260 b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. In addition, since the conductor 260 functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.

  Alternatively, for example, a conductive oxide can be used as the conductor 260a. For example, a metal oxide that can be used as the oxide 230 is preferably used. In particular, among the In—Ga—Zn-based oxides, the atomic ratio of metals having high conductivity is [In]: [Ga]: [Zn] = 4: 2: 3 and its neighboring values It is preferable to use one of By providing such a conductor 260a, transmission of oxygen to the conductor 260b can be suppressed, and an increase in the electrical resistance value of the conductor 260b due to oxidation can be prevented.

  Further, oxygen is supplied to the region 250 of the oxide 230 by adding oxygen to the insulator 250 and the insulator 252 by forming a film of such a conductive oxide by a sputtering method. Is possible. Thus, oxygen vacancies in the region 234 of the oxide 230 can be reduced.

  In the case of using the conductive oxide as the conductor 260a, it is preferable to use a conductor which can improve the conductivity of the conductor 260a by adding an impurity such as nitrogen to the conductor 260a. For example, as the conductor 260b, titanium nitride or the like is preferably used. Alternatively, the conductor 260b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereon.

  Further, as shown in FIG. 3C, in the case where the conductor 205 extends in a region outside the end portion of the oxide 230 which intersects the channel width direction, the conductor 260 in the region, It is preferable to overlap through the insulator 250. That is, in the outside of the side surface of the oxide 230, the conductor 205, the insulator 250, and the conductor 260 preferably form a stacked structure.

  With the above structure, when a potential is applied to the conductor 260 and the conductor 205, a closed circuit is formed by connecting the electric field generated from the conductor 260 and the electric field generated from the conductor 205, thereby forming an oxidized circuit. The channel formation region formed in the object 230 can be covered.

  That is, the channel formation region of the region 234 can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode. .

  In addition, an insulator 270 which functions as a hard mask may be provided over the conductor 260b. By providing the insulator 270, when processing the conductor 260, the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, the shape may be 80 degrees or more and 95 degrees or less. By processing the conductor into the shape, processing of the insulator 272 formed in a later step is facilitated.

  The insulator 272 functioning as a barrier film is provided in contact with side surfaces of the insulator 250, the insulator 252, the conductor 260, and the insulator 270.

  Here, as the insulator 272, an insulating material which has a function of suppressing permeation of impurities such as water or hydrogen and oxygen can be used. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxygen in the insulator 250 and the insulator 252 can be prevented from diffusing to the outside. Further, entry of impurities such as hydrogen and water into the oxide 230 from the insulator 250 and an end portion of the insulator 252 can be suppressed. Thus, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 can be suppressed, and the reliability of the transistor 200 can be improved.

  By providing the insulator 272, the top surface and the side surface of the conductor 260, the side surface of the insulator 250, and the side surface of the insulator 252 can be formed using an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. It can be covered. Thus, impurities such as water or hydrogen can be prevented from being mixed into the oxide 230 through the conductor 260, the insulator 250, and the insulator 252. Thus, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.

  In particular, when the transistor is miniaturized and the channel length is formed to be approximately 10 nm to 30 nm, the impurity element contained in the structure provided around the transistor 200 is diffused, and the region 231 a and the region 231 b are formed. There is a risk of electrical continuity. With the above structure, when the first gate voltage is 0 V, electrical conduction between the source region and the drain region can be prevented.

  The insulator 274 is provided to cover the insulator 270, the insulator 272, the oxide 230, and the insulator 224. Here, the insulator 274 is provided in contact with the top surfaces of the insulator 270 and the insulator 272 and in contact with the side surface of the insulator 272.

  In addition, as the insulator 274, an insulating material having a function of suppressing permeation of oxygen is preferably used. For example, as the insulator 274, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like is preferably used.

  Note that in the case where the regions 231 and 232 are provided by depositing the insulator 274, the insulator 274 preferably contains at least one of hydrogen and nitrogen. By using an insulator having an impurity such as hydrogen or nitrogen for the insulator 274, the impurity such as hydrogen or nitrogen is added to the oxide 230 to form the regions 231 and 232 in the oxide 230. Can.

  An insulator 280 which functions as an interlayer film is preferably provided over the insulator 274. The insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film, similarly to the insulator 224 and the like. Note that an insulator similar to the insulator 210 may be provided over the insulator 280.

  In the openings formed in the insulator 280 and the insulator 274, the conductor 240a and the conductor 240b are provided. The conductor 240 a and the conductor 240 b are provided opposite to each other with the conductor 260 interposed therebetween. Note that the heights of the top surfaces of the conductor 240 a and the conductor 240 b may be flush with the top surface of the insulator 280.

  The conductor 240a is in contact with the region 231a which functions as one of the source region and the drain region of the transistor 200, and the conductor 240b is in contact with the region 231b which functions as the other of the source region and the drain region of the transistor 200. Thus, the conductor 240a can function as one of a source electrode and a drain electrode, and the conductor 240b can function as the other of the source electrode and the drain electrode. Since the regions 231a and 231b have low resistance, the contact resistance between the conductor 240a and the region 231a and the contact resistance between the conductor 240b and the region 231b can be reduced and the on-state current of the transistor 200 can be increased.

  A conductor 240a is formed in contact with the inner wall of the opening of the insulator 280 and the insulator 274. The region 231a of the oxide 230 is positioned at least at part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240 b is formed in contact with the inner wall of the insulator 280 and the opening of the insulator 274. The region 231 b of the oxide 230 is positioned at least at part of the bottom of the opening, and the conductor 240 b is in contact with the region 231 b.

  Here, the conductor 240 a and the conductor 240 b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surface of the oxide 230. In particular, the conductor 240 a and the conductor 240 b are preferably in contact with both or one of the side surface on the A3 side and the side surface on the A4 side on the side surface of the oxide 230 intersecting with the channel width direction. The conductor 240 a and the conductor 240 b may be in contact with the side surface on the A1 side (A2 side) on the side surface of the oxide 230 which intersects the channel length direction. In this manner, the conductor 240 a and the conductor 240 b are in contact with the oxide 230 by forming the conductor 240 a and the conductor 240 b in contact with the side surface of the oxide 230 in addition to the top surface of the oxide 230. The contact area of the contact portion can be increased and the contact resistance between the conductor 240a and the conductor 240b and the oxide 230 can be reduced without increasing the upper area of the contact portion. Thus, the on current can be increased while the source electrode and the drain electrode of the transistor are miniaturized.

  It is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductors 240a and 240b. Although not shown, the conductor 240a and the conductor 240b may have a stacked structure, for example, titanium, titanium nitride, and the above conductive material.

  In the case where the conductor 240 has a stacked structure, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen for the insulator 274 and the conductor in contact with the insulator 280 similarly to the conductor 205a and the like It is preferable to use For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or ruthenium oxide is preferably used. In addition, a conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stack. By using the conductive material, impurities such as hydrogen and water from above the insulator 280 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

  Further, although not shown, a conductor that functions by being in contact with the top surface of the conductor 240a and the top surface of the conductor 240b may be disposed. It is preferable to use a conductive material whose main component is tungsten, copper, or aluminum as the conductor functioning as the wiring. In addition, the conductor may have a stacked structure, for example, a stack of titanium, titanium nitride, and the above conductive material. Note that as in the case of the conductor 203 or the like, the conductor may be formed so as to be embedded in an opening provided in an insulator.

<Material of semiconductor device>
Hereinafter, constituent materials which can be used for the semiconductor device will be described.

<< board >>
As a substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. The semiconductor substrate may be, for example, a single semiconductor substrate of silicon, germanium or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. As the conductive substrate, there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate and the like. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, or the like. Further, there are a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on the conductor substrate, and the like. Alternatively, those provided with elements on these substrates may be used. The elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.

  Alternatively, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor on a flexible substrate, there is a method in which the transistor is peeled off after being manufactured on a non-flexible substrate and transposed to the flexible substrate. In that case, a release layer may be provided between the non-flexible substrate and the transistor. In addition, the substrate may have stretchability. In addition, the substrate may have the property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have the property that it does not return to its original shape. The substrate has, for example, a region having a thickness of 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate is thinned, the weight of the semiconductor device including the transistor can be reduced. In addition, when the substrate is made thin, it may have elasticity even when using glass or the like, or may return to its original shape when bending or pulling is stopped. Therefore, an impact or the like applied to the semiconductor device on the substrate due to a drop or the like can be alleviated. That is, a robust semiconductor device can be provided.

As a substrate which is a flexible substrate, for example, a metal, an alloy, a resin or glass, or fibers thereof can be used. In addition, as the substrate, a sheet, a film, a foil or the like in which fibers are woven may be used. As the substrate which is a flexible substrate has a lower coefficient of linear expansion, deformation due to the environment is preferably suppressed. As a substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is suitable as a flexible substrate because it has a low coefficient of linear expansion.

<< insulator >>
The insulator includes, for example, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, and the like.

  For example, as the miniaturization and higher integration of transistors progress, the thinning of the gate insulator may cause problems such as leakage current. By using a high-k material for the insulator that functions as a gate insulator, the physical thickness can be maintained and voltage can be reduced. On the other hand, for an insulator functioning as an interlayer film, by using a material having a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

  In addition, as insulators with high dielectric constants, oxides of gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, oxynitrides of aluminum and hafnium, oxides of silicon and hafnium, silicon and hafnium can be used. There is an oxynitride or a nitride having silicon and hafnium.

  Further, as an insulator having a low relative dielectric constant, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, empty There are silicon oxide or resin having holes.

  Also, in particular, silicon oxide and silicon oxynitride are thermally stable. Therefore, for example, by combining with a resin, it is possible to obtain a laminated structure having a low thermal conductivity and a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator with high relative permittivity to form a stacked structure with high thermal stability and high relative permittivity.

  In addition, in the transistor including an oxide semiconductor, electrical characteristics of the transistor can be stabilized by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen.

  As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack. Specifically, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen. A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  For example, insulator 224 and insulator 250, which function as part of a gate insulator, are preferably insulators having excess oxygen regions. For example, with a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

  For example, for the insulator 224 and the insulator 252 which function as part of a gate insulator, an insulator containing one or more oxides of aluminum, hafnium, and gallium can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.

  Here, for the insulator 224 and the insulator 252, a film with low crystallinity (or less crystals) or a film including an amorphous structure may be used. An oxide film having low crystallinity or an amorphous structure can diffuse oxygen of the oxide film to a nearby insulator by heating. For example, by using a film with low crystallinity or a film including an amorphous structure for the insulator 224 and the insulator 252, the insulator 224 and the insulator 252 can be used as the insulator 224 and the insulator 252 due to the thermal history of later steps. Excess oxygen is added to 250, and an insulator 224 and an insulator 250 can easily form an excess oxygen region. A film with low crystallinity or a film including an amorphous structure has high planarity, and the interface between the insulator 250 and the insulator 252, the interface between the insulator 220 and the insulator 222, and the insulator 222 and the insulator 224. And the interface between them can be in a good state.

  For example, an insulating film whose root mean square surface roughness (RMS) measured using an atomic force microscope is 0.4 nm or less, preferably 0.3 nm or less in a measurement range of 1 μm × 1 μm, as a film having high flatness It is good to use the body.

  For example, as a film with low crystallinity, it is preferable to use an insulator in which a region with high luminance is observed as a result of an electron beam diffraction pattern using an electron microscope draws a circle (in a ring shape).

  For example, as the insulator 222, silicon oxide or silicon oxynitride which is stable against heat is preferably used. By using a stack that has a stable film against heat and a high dielectric constant as the gate insulator, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness. It becomes.

  With the above-described stacked structure, the on current can be improved without weakening the influence of the electric field from the gate electrode. In addition, the leakage current can be suppressed by maintaining the distance between the gate electrode and the region where the channel is formed by the physical thickness of the gate insulator.

  The insulator 212, the insulator 216, the insulator 271, and the insulator 280 preferably include an insulator with a low relative dielectric constant. For example, the insulator 212, the insulator 216, and the insulator 280 are formed by adding silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and nitrogen It is preferable to have silicon oxide, silicon oxide having pores, or a resin. Alternatively, the insulator 212, the insulator 216, and the insulator 280 are formed by adding silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen It is preferable to have a stacked structure of silicon oxide or silicon oxide having holes and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic.

  As the insulator 210, the insulator 214, the insulator 270, and the insulator 272, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used. As the insulator 270 and the insulator 272, for example, metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide Alternatively, silicon nitride or the like may be used.

<< Conductor >>
The conductor is a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium and the like A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity, typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  Alternatively, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used. Alternatively, a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used. Alternatively, a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.

  Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode. Is preferred. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen in the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

  In particular, as a conductor functioning as a gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in a metal oxide in which a channel is formed. Alternatively, it may be possible to capture hydrogen mixed from an outer insulator or the like.

  As the conductor 260, the conductor 203, the conductor 205, and the conductor 240, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium A material containing one or more metal elements selected from zirconium, beryllium, indium, ruthenium and the like can be used. Alternatively, a semiconductor with high electrical conductivity, typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

<< metal oxides >>
As the oxide 230, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

  The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium or tin is preferably contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

  Here, it is assumed that the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases.

  In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.

[Metal oxide composition]
Hereinafter, a configuration of a Cloud-Aligned Composite (CAC) -OS that can be used for the transistor disclosed in one embodiment of the present invention will be described.

  In this specification etc., it may describe as CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a structure of a material.

  The CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and functions as a semiconductor throughout the material. Note that in the case where CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is electrons serving as carriers. Is a function that does not A function of switching (function of turning on / off) can be imparted to the CAC-OS or the CAC-metal oxide by causing the conductive function and the insulating function to be complementary to each other. By separating the functions of CAC-OS or CAC-metal oxide, both functions can be maximized.

  In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed as connected in a cloud shape with a blurred periphery.

  In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from the insulating region and a component having a narrow gap resulting from the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having the narrow gap acts complementarily to the component having the wide gap, and the carrier also flows to the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the above-described CAC-OS or CAC-metal oxide is used for the channel region of a transistor, high current driving force, that is, high on current, and high field effect mobility can be obtained in the on state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite (matrix composite) or a metal matrix composite (metal matrix composite).

[Structure of metal oxide]
Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. As the non-single crystal oxide semiconductor, for example, c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), pseudo amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

  The CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure. Note that distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

  The nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon. In the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) can not be confirmed near the strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is thought that it is for.

  In addition, a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer. In addition, when indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.

  The CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, CAAC-OS can not confirm clear crystal grain boundaries, so that it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities, generation of defects, or the like, so that the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, the oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.

  The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

  Oxide semiconductors have various structures, and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with oxide semiconductor]
Subsequently, a case where the above oxide semiconductor is used for a transistor will be described.

  Note that by using the above oxide semiconductor for the transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

Further, an oxide semiconductor with low carrier density is preferably used for the transistor. In the case of reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In the present specification and the like, the low impurity concentration and the low density of defect level states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. It should be cm ³ or more.

  In addition, since the high purity intrinsic or the substantially high purity intrinsic oxide semiconductor film has a low density of defect states, the density of trap states may also be low.

  In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave like fixed charge. Therefore, in the transistor in which the channel region is formed in the oxide semiconductor with a high trap state density, the electrical characteristics may be unstable.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. The impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.

[impurities]
Here, the influence of each impurity in the oxide semiconductor is described.

In the oxide semiconductor, when silicon or carbon which is one of the group 14 elements is contained, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × ¹⁰ 18 atoms / cm ³ or less, preferably 2 × ¹⁰ 17 atoms / cm ³ or less.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state may be formed and a carrier may be generated. Therefore, a transistor including an oxide semiconductor which contains an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is contained in an oxide semiconductor, electrons which are carriers are generated, carrier density is increased, and n-type is easily formed. As a result, a transistor in which an oxide semiconductor containing nitrogen is used as a semiconductor is likely to be normally on. Therefore, in the oxide semiconductor, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ^{18 in} SIMS. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancies, electrons which are carriers may be generated. In addition, a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on. Thus, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, in an oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm. ^{It is} less than ³ and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  With the use of the oxide semiconductor in which the impurities are sufficiently reduced for the channel region of the transistor, stable electrical characteristics can be provided.

<Method for manufacturing semiconductor device>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to the present invention will be described with reference to FIGS. Moreover, in FIG. 5 to FIG. 13, (A) of each figure shows a top view. Further, (B) of each drawing is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line of A1-A2 shown in (A). Further, (C) of each drawing is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line of A3-A4 in (A).

  First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film formation of the insulator 210 can be performed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD (chemical vapor deposition). This can be performed using an atomic layer deposition method or the like.

  The CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: thermal CVD) method using heat, a photo CVD method using light, etc. . Furthermore, it can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.

  The plasma CVD method provides high quality films at relatively low temperatures. Further, the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (such as a transistor or a capacitor), or the like included in a semiconductor device may be charged up by receiving charge from plasma. At this time, wirings, electrodes, elements, and the like included in the semiconductor device may be broken by the stored charge. On the other hand, in the case of a thermal CVD method which does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

  In addition, the ALD method is also a film formation method capable of reducing plasma damage to an object to be processed. Also, in the ALD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

  The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed unlike a film forming method in which particles released from a target or the like are deposited. Therefore, the film forming method is less susceptible to the shape of the object to be processed, and has good step coverage. In particular, since the ALD method has excellent step coverage and uniformity of thickness, it is suitable for coating the surface of an opening with a high aspect ratio. However, since the deposition rate is relatively slow, the ALD method may be preferably used in combination with another deposition method such as a CVD method having a high deposition rate.

  The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having any composition can be formed depending on the flow rate ratio of the source gas. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time taken for film formation can be shortened by the time taken for conveyance and pressure adjustment as compared with the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be enhanced.

  In this embodiment mode, aluminum oxide is deposited as the insulator 210 by a sputtering method. In addition, the insulator 210 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed by an ALD method on the aluminum oxide film. Alternatively, aluminum oxide may be formed by an ALD method, and aluminum oxide may be formed by sputtering on the aluminum oxide.

  Next, the insulator 212 is formed over the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 212 by a CVD method.

  Next, an opening is formed in the insulator 212 and the insulator 210. The openings include, for example, grooves and slits. In addition, the region in which the opening is formed may be referred to as an opening. Although the formation of the opening may use wet etching, it is preferable to use dry etching for fine processing. Further, as the insulator 210, it is preferable to select an insulator that functions as an etching stopper film at the time of forming the groove by etching the insulator 212. For example, in the case where a silicon oxide film is used as the insulator 212 which forms a groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used as the insulator 210 which functions as an etching stopper film.

  After the opening is formed, a conductive film to be the conductor 203a is formed. The conductive film preferably includes a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. The film formation of the conductor to be the conductor 203a can be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment mode, a tantalum nitride film or a film in which titanium nitride is stacked over tantalum nitride is formed by sputtering as a conductive film to be the conductor 203a. By using such a metal nitride as the conductor 203a, even if a metal that easily diffuses such as copper is used as the conductor 203b described later, the metal can be prevented from diffusing out of the conductor 203a.

  Next, a conductive film to be the conductor 203b is formed over the conductive film to be the conductor 203a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film to be the conductor 203 b.

  Next, CMP treatment is performed to remove part of the conductive film to be the conductor 203 a and the conductive film to be the conductor 203 b, thereby exposing the insulator 212. As a result, the conductive film to be the conductor 203a and the conductive film to be the conductor 203b remain only in the opening. Accordingly, the conductor 203 including the conductor 203a and the conductor 203b whose top surface is flat can be formed (see FIG. 5). Note that part of the insulator 212 may be removed by the CMP treatment.

  Next, the insulator 214 is formed over the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon nitride is formed as the insulator 214 by a CVD method. In this manner, by using an insulator that is less likely to transmit copper such as silicon nitride as the insulator 214, even if a metal that easily diffuses copper such as copper is used for the conductor 203b, the metal is a layer higher than the insulator 214 Can be prevented from spreading.

  Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 216 by a CVD method.

  Next, an opening which reaches the conductor 203 is formed in the insulator 214 and the insulator 216. Although the formation of the opening may use wet etching, it is preferable to use dry etching for fine processing.

  After the opening is formed, a conductive film to be the conductor 205a is formed. The conductive film to be the conductor 205a preferably contains a conductive material having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. The conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment mode, tantalum nitride is formed by a sputtering method as a conductive film to be the conductor 205a.

  Next, a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment mode, titanium nitride is formed by a CVD method as a conductive film to be the conductor 205b, and tungsten is formed over the titanium nitride film by a CVD method.

  Next, CMP treatment is performed to remove part of the conductive film to be the conductor 205 a and the conductive film to be the conductor 205 b, thereby exposing the insulator 216. As a result, the conductive film to be the conductor 205a and the conductor 205b remains only in the opening. Thus, the conductor 205 including the conductor 205a and the conductor 205b with a flat top surface can be formed (see FIG. 5). Note that part of the insulator 212 may be removed by the CMP treatment.

  Next, the insulator 220 is formed over the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 212 by a CVD method.

  Next, the insulator 222 is formed over the insulator 220. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. The insulator 222 has a barrier property to hydrogen and water, whereby hydrogen contained in a structure provided in the periphery of the transistor 200 and water do not diffuse inside the transistor 200, and thus, the oxide 230 can contain the hydrogen and water. The generation of oxygen deficiency can be suppressed.

  The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, the insulator 222 is a film having low crystallinity (or referred to as having few crystals), or a film including an amorphous structure. An oxide film having low crystallinity or an amorphous structure can diffuse oxygen of the oxide film to a nearby insulator by heating. By using a film with low crystallinity or a film including an amorphous structure for the insulator 222, excess oxygen is added to the insulator 224 from the insulator 222 by a thermal history in a later step, and an excess oxygen region is added to the insulator 224. Can be easily formed. In addition, a film with low crystallinity or a film including an amorphous structure has high flatness, and the interface with another film to be stacked can be in a good state.

  The oxide film with low crystallinity which can be used for the insulator 222 or contains an amorphous structure has a deposition temperature of R.K. A film can be formed by a sputtering method in a mixed atmosphere containing T and 200 ° C. and oxygen. The film forming temperature is preferably 130 ° C. or less, more preferably R. It is preferable that T (RT: Room temperature. In this specification, RT means a temperature at which heating is not intentionally performed). Further, as a mixed atmosphere containing oxygen, a mixed gas of oxygen and a rare gas, or a mixed gas of oxygen and nitrogen can be used.

  The root mean square surface roughness (RMS) measured using an atomic force microscope by a sputtering method in a mixed atmosphere containing a film forming temperature of 200 ° C. or lower and oxygen in a measurement range of 1 μm × 1 μm: 0. An insulator 222 which is 4 nm or less, preferably 0.3 nm or less can be formed. In addition, the insulator 222 in which a region with high luminance can be observed (in a ring shape) can be formed as an electron diffraction pattern using an electron microscope draws a circle (in a ring shape).

  Next, the insulator 224 is formed over the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 5). In this embodiment mode, silicon oxide is deposited as the insulator 224 by a CVD method.

  Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere. .

  In this embodiment, as the heat treatment, after the insulator 224 is formed, treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.

  By the heat treatment, excess oxygen is added to the insulator 224 from the insulator 222, so that an excess oxygen region can be easily formed in the insulator 224. Further, impurities such as hydrogen and water contained in the insulator 224 can be removed.

  The heat treatment can also be performed at each timing after the insulator 220 is formed and after the insulator 222 is formed. Although the heat treatment conditions described above can be used for the heat treatment, it is preferable that the heat treatment after formation of the insulator 220 be performed in an atmosphere containing nitrogen.

  Here, in order to form an excess oxygen region in the insulator 224A, plasma treatment including oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, for example, a device having a power supply for generating high density plasma using microwaves is preferably used. Alternatively, the substrate side may have a power supply for applying an RF (Radio Frequency). The use of a high density plasma can generate high density oxygen radicals, and the application of RF to the substrate side can efficiently introduce oxygen radicals generated by the high density plasma into the insulator 224. Alternatively, after performing plasma treatment including an inert gas using this apparatus, plasma treatment including oxygen may be performed to compensate for the released oxygen. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, the heat treatment may not be performed.

  Next, on the insulator 224, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed (see FIG. 6). Note that the oxide film is preferably formed continuously without being exposed to the air environment. By forming the film without opening to the atmosphere, impurities or moisture from the air environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be It can be kept clean.

  The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, in the case where the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the above oxide film is formed by sputtering, the above In-M-Zn oxide target can be used.

  In particular, when the oxide film 230A is formed, part of oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

  In addition, in the case where the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor can be formed by deposition with the proportion of oxygen contained in the sputtering gas being 1% to 30%, preferably 5% to 20%. It is formed. A transistor including an oxygen-deficient oxide semiconductor can provide relatively high field-effect mobility.

  In this embodiment mode, the oxide film 230A is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. In addition, a film is formed as the oxide film 230B by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Note that each oxide film may be formed in accordance with the characteristics to be obtained for the oxide 230 by appropriately selecting deposition conditions and an atomic ratio.

  Next, heat treatment may be performed. For the heat treatment, the above-described heat treatment conditions can be used. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B can be removed. In this embodiment, after performing treatment for 1 hour at a temperature of 400 ° C. in a nitrogen atmosphere, treatment for 1 hour at a temperature of 400 ° C. in an oxygen atmosphere is continuously performed.

  Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIG. 7).

  Note that in the above steps, the insulator 224 may be processed into an island shape. In that case, the insulator 222 can be used as an etching stopper film.

  Here, the oxide 230 a and the oxide 230 b are formed so that at least part thereof overlaps with the conductor 205. The side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230 a and the oxide 230 b are substantially perpendicular to the top surface of the insulator 222, reduction in area and density can be achieved when the plurality of transistors 200 is provided. Note that the angle between the side surface of the oxide 230 a and the side surface of the oxide 230 b and the top surface of the insulator 222 may be acute. In that case, the larger the angle between the side surface of the oxide 230a and the side surface of the oxide 230b and the top surface of the insulator 222, the better.

  In addition, a curved surface is provided between the side surfaces of the oxide 230 a and the oxide 230 b and the top surface of the oxide 230 a. That is, the end of the side surface and the end of the upper surface are preferably curved (hereinafter, also referred to as a round shape). The curved surface preferably has a curvature radius of 3 nm to 10 nm, preferably 5 nm to 6 nm, at an end portion of the oxide 230 b, for example. By not having a corner at the end, the coverage of the film in the subsequent film formation process is improved.

  Note that the processing of the oxide film may be performed using a lithography method. Further, dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.

  In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled and exposed between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. In the case of using an electron beam or an ion beam, the mask is unnecessary. Note that for the removal of the resist mask, dry etching such as ashing can be performed, wet etching can be performed, wet etching can be performed after the dry etching, or dry etching can be performed after the wet etching.

  In addition, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the oxide film 230B, a resist mask is formed thereon, and a hard mask having a desired shape is formed by etching the hard mask material. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the etching of the oxide film. On the other hand, when the material of the hard mask does not affect the post-process or can be used in the post-process, it is not necessary to remove the hard mask.

  As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used. The capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes. Alternatively, a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency power supplies having different frequencies may be applied to the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high density plasma source.

  Further, by performing the process such as the above-described dry etching, an impurity due to an etching gas or the like may be attached or diffused to the surface or the inside of the oxide 230a, the oxide 230b, or the like. The impurities include, for example, fluorine or chlorine.

  Washing is performed to remove the above-mentioned impurities and the like. The cleaning method may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, or cleaning by heat treatment, and the above cleaning may be performed in combination as appropriate.

  As the wet cleaning, a cleaning process may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

  Subsequently, heat treatment may be performed. As the heat treatment conditions, the above-described heat treatment conditions can be used.

  Next, over the insulator 224, the oxide 230a, and the oxide 230b, an oxide film 230C, an insulating film 250A, an insulating film 252A, a conductive film 260A, a conductive film 260B, an insulating film 270A, and an insulating film 271A are sequentially formed. Membrane (see FIG. 8).

  The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed by a film formation method similar to that of the oxide film 230A or the oxide film 230B in accordance with the characteristics desired for the oxide 230c. In this embodiment mode, the oxide film 230C is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic number ratio].

  Next, the insulating film 250A is formed. The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film may be formed as the insulating film 250A by a CVD method. Note that the film formation temperature at the time of forming the insulating film 250A is preferably 350 ° C. or more and less than 450 ° C., particularly about 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator with few impurities can be formed.

  Note that oxygen is excited by microwaves to generate high-density oxygen plasma, and the insulating film 250A is exposed to the oxygen plasma to form oxygen in the insulating film 250A, the oxide 230a, the oxide 230b, and the oxide film 230C. Can be introduced.

  Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By the heat treatment, the water concentration and the hydrogen concentration of the insulating film 250A can be reduced.

  Next, the insulating film 252A is formed over the insulating film 250A. As the insulating film 252A, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. The insulator 222 has a barrier property to hydrogen and water, whereby hydrogen contained in a structure provided in the periphery of the transistor 200 and water do not diffuse inside the transistor 200, and thus, the oxide 230 can contain the hydrogen and water. The generation of oxygen deficiency can be suppressed.

  The insulating film 252A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, the insulating film 252A is a film having low crystallinity (or less crystals), or a film including an amorphous structure. An oxide film having low crystallinity or an amorphous structure can diffuse oxygen of the oxide film to a nearby insulator by heating. By using a film with low crystallinity or a film including an amorphous structure for the insulating film 252A, excess oxygen is added to the insulating film 250A from the insulating film 252A by a thermal history in a later step, and an excess oxygen region is added to the insulating film 250A. Can be easily formed. In addition, a film with low crystallinity or a film including an amorphous structure has high flatness, and the interface with another film to be stacked can be in a good state.

  The oxide film having low crystallinity or an amorphous structure that can be used for the insulating film 252A has a film forming temperature of R.V. A film can be formed by a sputtering method in a mixed atmosphere containing T and 200 ° C. and oxygen. The film forming temperature is preferably 130 ° C. or less, more preferably R. It is preferable that T (RT be a temperature at which heating is not intentionally performed). Further, as a mixed atmosphere containing oxygen, a mixed gas of oxygen and a rare gas, or a mixed gas of oxygen and nitrogen can be used.

  The root mean square surface roughness (RMS) measured using an atomic force microscope by a sputtering method in a mixed atmosphere containing a film forming temperature of 200 ° C. or lower and oxygen in a measurement range of 1 μm × 1 μm: 0. An insulator 222 which is 4 nm or less, preferably 0.3 nm or less can be formed. In addition, it is possible to form the insulating film 252A in which a region with high luminance is observed (in a ring shape) as a result of an electron beam diffraction pattern using an electron microscope draws a circle.

  Further, by forming a metal oxide film as the insulating film 252A by sputtering in an atmosphere containing oxygen, oxygen can be added to the insulating film 250A to form an excess oxygen region in the insulating film 250A. . The excess oxygen added to the insulating film 250A can compensate for oxygen vacancies by supplying oxygen to the oxide 230.

  Here, when forming the insulating film 252A by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power supply and given a potential E0. Further, the substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region of potential E2 between the target and the substrate. The magnitude relationship of each potential is E2> E1> E0.

  Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target to repel particles sputtered from the target. The sputtered particles adhere to and deposit on the film formation surface to form a film. Further, some ions are recoiled by the target, pass through the formed film through the film formed as recoil ions, and are taken into the insulating film 250A in contact with the deposition surface and the insulator 224. There is a case. Further, ions in the plasma are accelerated by the potential difference E2-E1 and strike the film formation surface. At this time, some ions reach the inside of the insulating film 250A and the insulator 224. By the ions being taken into the insulating film 250A and the insulator 224, regions into which the ions are taken are formed in the insulating film 250A and the insulator 224. That is, in the case where the ion is an ion containing oxygen, an excess oxygen region is formed in the insulating film 250A and the insulator 224.

  By introducing excess oxygen into the insulating film 250A and the insulator 224, an excess oxygen region can be formed. Excess oxygen in the insulating film 250A and the insulator 224 can be supplied to the oxide 230 so that oxygen vacancies in the oxide 230 can be compensated.

  Therefore, as a method for forming the insulating film 252A, oxygen is added to the insulating film 250A and the insulator 224 while forming the insulating film 252A by performing film formation under an oxygen gas atmosphere using a sputtering apparatus. It can be introduced. In particular, by using an oxide of one or both of aluminum and hafnium having a barrier property for the insulating film 252A, excess oxygen introduced into the insulator 250 can be effectively contained.

  Subsequently, the conductive film 260A and the conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, titanium nitride is formed by a CVD method as the conductive film 260A, and tungsten is formed by a CVD method as the conductive film 205B.

  Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. Note that heat treatment may not be performed in some cases. By this heat treatment, excess oxygen is added to the insulator 250 and the insulator 224 from the insulator 252, so that an excess oxygen region can be easily formed in the insulator 250 and the insulator 224.

  The insulating film 270A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 270A functions as a barrier film and thus uses an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Thereby, the oxidation of the conductor 260 can be prevented. Further, impurities such as water or hydrogen can be prevented from being mixed into the oxide 230 through the conductor 260 and the insulator 250. In this embodiment mode, aluminum oxide is deposited as the insulating film 270A by an ALD method.

  The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the thickness of the insulating film 271A is preferably larger than that of the insulating film 272A which is to be formed in a later step. Thus, when the insulator 272 is formed in a later step, the insulator 271 can be easily left over the conductor 260. In this embodiment, a silicon oxide film is formed as the insulating film 271A by a CVD method.

  Next, the insulating film 271A is etched to form an insulator 271. Here, the insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the insulator 250, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 can be formed substantially perpendicular to the substrate.

  With the insulator 271 as a mask, the insulating film 250A, the insulating film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) insulator 250, an insulator 252, a conductor 260 (conductors 260a and 260b), and an insulator 270 are formed (see FIG. 9). The insulator 250, the insulator 252, the conductor 260a, the conductor 260b, the insulator 270, and the insulator 271 are formed so as to at least partially overlap with the conductor 205 and the oxide 230.

  The side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are preferably in the same plane.

  Preferably, the side surface of the insulator 250, the side surface of the insulator 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the same surface shared by the side surface of the insulator 270 are substantially perpendicular to the substrate. . That is, in the cross-sectional shape, the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, and the insulator 270 preferably have larger acute angles with respect to the top surface of the oxide 230. Note that in the cross-sectional shape, an angle between the side surface of the insulator 250, the insulator 252, the conductor 260a, the conductor 260b, and the insulator 270 and the top surface of the oxide 230 may be acute. In that case, the larger the angle between the side surfaces of the insulator 250, the conductor 260a, the conductor 260b, and the insulator 270, and the top surface of the oxide 230, the better.

  Note that, even after the above processing, the post-process may be advanced without removing the hard mask (insulator 271). In that case, the insulator 271 can function as a hard mask also in the addition of a dopant performed in a later step.

  In addition, the upper portion of the region which does not overlap with the insulator 250 in the oxide 230 b may be etched by the above etching. In this case, the thickness of a region of the oxide 230 b overlapping with the insulator 250 may be larger than the thickness of a region not overlapping with the insulator 250.

  Next, an insulating film 272A is formed to cover the oxide 230c, the insulator 250, the insulator 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 10). It is preferable that the insulating film 272A be formed by an ALD method excellent in coverage. By using the ALD method, the insulating film 272A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 also in the stepped portion formed by the conductor 260 or the like. be able to.

  Next, the insulating film 272A is anisotropically etched to form the insulator 272 in contact with the insulator 250, the conductor 260, and the side surface of the insulator 270 (see FIG. 11). As the anisotropic etching treatment, dry etching treatment is preferably performed. Thus, the insulator 272 can be formed in a self-aligned manner by removing the insulating film formed on a surface substantially parallel to the substrate surface.

  Here, by forming the insulator 271 on the insulator 270, the insulator 270 can be left even if the insulating film 272A on the top of the insulator 270 is removed. Further, oxidation is performed by setting the height of the structure including the insulator 250, the conductor 260, the insulator 270, and the insulator 271 higher than the height of the oxide 230a, the oxide 230b, and the oxide film 230C. The insulating film 272A on the side surface of the oxide 230a and the oxide 230b through the film 230C can be removed. Further, when the end portions of the oxide 230a and the oxide 230b are rounded, it is possible to remove the insulating film 272A formed on the side surfaces of the oxide 230a and the oxide 230b via the oxide film 230C. Can be shortened and the insulator 272 can be formed more easily.

  Although not shown, the insulating film 272A may remain on the side surface of the oxide 230. In that case, the film formability of an interlayer film or the like to be formed in a later step can be enhanced. In addition, by the insulator remaining on the side surface of the oxide 230, impurities such as water or hydrogen mixed in the oxide 230 can be reduced, and the outward diffusion of oxygen from the oxide 230 can be prevented. is there.

  Further, a structure in which the insulating film 272A is left is formed in contact with the side surface of the oxide 230, so that an insulator 274 containing an element to be an impurity is formed in a later step. In the case where the region 231 a and the region 231 b are formed, the interface region between the insulator 224 and the oxide 230 is not reduced in resistance; therefore, generation of a leakage current can be suppressed. Alternatively, when indium is added to the oxide 230, even when a dopant is added to have a concentration peak in the oxide 230a, the generation of leakage current through the oxide 230a can be suppressed.

  The anisotropic etching may be performed after the addition of a dopant described later. In this case, the dopant is added to the oxide 230 through the insulating film 272A.

  Subsequently, in the oxide 230, a region 231, a region 232, and a region 234 are formed. The regions 231 and 232 are regions in which metal atoms such as indium and gallium or impurities are added to a metal oxide provided as the oxide 230. Note that the region 231 is higher in conductivity than at least the oxide 230 b in the region 234.

  In order to add an impurity to the regions 231 and 232, for example, a metal element such as indium or gallium and a dopant which is at least one of the impurities may be added. Note that as the dopant, an element that forms the above-described oxygen vacancy, an element that is captured by the oxygen vacancy, or the like may be used. For example, as the element, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas and the like can be mentioned. Further, helium, neon, argon, krypton, xenon and the like can be given as typical examples of the rare gas element.

  For example, in order to add an impurity to the region 231 and the region 232, a film containing a dopant may be formed as the insulator 274 in contact with the region 231. As the insulator 274, an insulating film containing one or more of the above elements is preferably used (see FIG. 12).

  Specifically, an insulator 274 containing an element serving as an impurity such as nitrogen may be formed in contact with the oxide 230. An insulator including an element which is an impurity such as nitrogen may extract and absorb oxygen contained in the oxide 230. When oxygen is extracted from the oxide 230, oxygen vacancies in the regions 231 and 232 are generated. In the oxygen vacancies, an impurity element such as hydrogen or nitrogen contained in a deposition atmosphere of the insulator 274 is captured by deposition of the insulator 274 or heat treatment after deposition, and the regions 231 and 232 have low resistance. Turn That is, in the oxide 230, an oxygen vacancy is formed by the added impurity element mainly in a region in contact with the insulator 274, and the impurity element further enters the oxygen vacancy, so that the carrier density becomes high and resistance is reduced. Be done. At that time, it is considered that the resistance is reduced by the diffusion of the impurity also into the region 232 which is not in contact with the insulator 274.

  Therefore, by formation of the insulator 274, the source and drain regions can be formed in a self-aligned manner. Therefore, a miniaturized or highly integrated semiconductor device can also be manufactured with high yield.

  Here, by covering the top surfaces and the side surfaces of the conductor 260, the insulator 252, and the insulator 250 with the insulator 270 and the insulator 272, an impurity element such as nitrogen or hydrogen can be contained in the conductor 260 and the insulator 252. And the insulator 250 can be prevented. Accordingly, impurity elements such as nitrogen or hydrogen can be prevented from entering the region 234 which functions as a channel formation region of the transistor 200 through the conductor 260, the insulator 252, and the insulator 250. Thus, the transistor 200 having favorable electrical characteristics can be provided.

  For example, as the insulator 274, silicon nitride, silicon nitride oxide, or silicon oxynitride which is formed by a CVD method can be used. In this embodiment, silicon nitride oxide is used as the insulator 274.

  In the case where silicon nitride oxide is used as the insulator 274, the concentration of at least one of hydrogen and nitrogen is preferably higher in the regions 231a and 231b than in the region 234. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like. Here, as the concentration of hydrogen or nitrogen in the region 234, the vicinity of the center of the region of the oxide 230b overlapping with the insulator 250 (for example, the distances from both sides in the channel length direction of the insulator 250 of the oxide 230b are approximately equal The concentration of hydrogen or nitrogen in part) may be measured.

  Note that although the region 231, the region 232, and the region 234 are formed by using the reduction in resistance of the oxide 230 by film formation of the insulator 274 in the above description, this embodiment is not limited to this. .

  Other dopant addition methods include an ion implantation method in which the ionized source gas is separated by mass separation, an ion doping method in which the ionized source gas is added without mass separation, and a plasma immersion ion implantation method. It can be used. When mass separation is performed, the added ion species and its concentration can be strictly controlled. On the other hand, when mass separation is not performed, high concentration ions can be added in a short time. Alternatively, an ion doping method may be used which generates and ionizes clusters of atoms or molecules. Note that the dopant may be rephrased as an ion, a donor, an acceptor, an impurity, an element, or the like.

  The dopant may also be added by plasma treatment. In this case, the plasma treatment can be performed using a plasma CVD apparatus, a dry etching apparatus, and an ashing apparatus, and a dopant can be added to the region 231 and the region 232. Note that each region or the like may be formed by combining a plurality of the above-described processes.

  For example, in the region 231, the carrier density can be increased and resistance can be reduced by increasing the content of the element forming the above-described oxygen vacancy and the element trapped in the oxygen vacancy. Alternatively, for example, by adding a metal source such as indium in the region 231 and increasing the content of metal atoms such as indium in the oxide 230, electron mobility can be increased and resistance can be reduced. . Note that in the case where indium is added, the atomic ratio of indium to the element M in at least the region 231 is larger than the atomic ratio of indium to the element M in the region 234.

  Further, for example, by increasing the gallium content in the region 232, the reduction of the unintended execution channel length can be suppressed by suppressing the diffusion of the impurity such as hydrogen added to the region 231.

  Alternatively, for example, the oxide 230 may be subjected to plasma treatment using the insulator 250, the insulator 252, the conductor 260, the insulator 272, the insulator 270, and the insulator 271 as masks. The plasma treatment may be performed in an atmosphere containing the above-described element that forms oxygen vacancies, or an element captured by oxygen vacancies. For example, plasma treatment may be performed using argon gas and nitrogen gas.

  Alternatively, for example, after the insulating film 272A is formed, a dopant may be added by an ion doping method through the insulating film 272A. The insulating film 272A is provided to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 270. Therefore, in the direction perpendicular to the top surface of the oxide 230, the film thickness of the insulating film 272A is different in the insulator 250, the conductor 260, the periphery of the insulator 270, and the other regions. That is, the film thickness of the insulating film 272A is larger in the periphery of the insulator 250, the conductor 260, and the insulator 270 than in the other regions. That is, by adding a dopant through the insulating film 272A, the regions 231 and 232 can be provided in a self-aligned manner even in a transistor whose channel length is miniaturized to about 10 nm to 30 nm. Further, the region 232 may be formed by diffusion of the dopant in the region 231 in a step such as heat treatment performed in a later step.

  In the transistor 200 and the provision of the region 232, a high resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 where a channel is formed; You can increase the degree. Further, with the region 232, since the source region and the drain region do not overlap with the gate in the channel length direction, formation of unnecessary capacitance can be suppressed. Further, by including the region 232, leakage current in non-conduction can be reduced.

  Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements according to the circuit design.

  Subsequently, heat treatment can be performed. The heat treatment conditions described above can be used for the heat treatment. By heat treatment, the added dopant can be diffused into the region 232 of the oxide 230 and the on-state current can be increased.

  Next, the insulator 280 is formed over the insulator 274. The insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an inkjet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, a curtain coater method, or the like can be used. In this embodiment mode, silicon oxynitride is used as the insulating film.

  Next, part of the insulator 280 is removed. The insulator 280 is preferably formed to have a flat top surface. For example, the top surface of the insulator 280 may have flatness immediately after being deposited as an insulating film to be the insulator 280. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the top surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such processing is called planarization processing. The planarization process includes a CMP process, a dry etching process, and the like. In this embodiment, a CMP process is used as the planarization process. However, the upper surface of the insulator 280 may not necessarily have flatness.

  Next, in the insulator 280 and the insulator 274, an opening reaching the region 231a of the oxide 230 and an opening reaching the region 231b of the oxide 230 are formed. The formation of the opening may be performed using a lithography method. Note that the opening is formed so as to expose the side surface of the oxide 230 in the opening reaching the oxide 230 so that the conductor 240 a and the conductor 240 b are provided in contact with the side surface of the oxide 230.

  Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, CMP treatment is performed to remove part of the conductive film to be the conductor 240 a and the conductor 240 b, thereby exposing the insulator 280. As a result, since the conductive film remains only in the opening, the conductor 240a and the conductor 240b whose top surface is flat can be formed (see FIG. 13).

  Through the above steps, a semiconductor device including the transistor 200 can be manufactured. As illustrated in FIGS. 5 to 13, the transistor 200 can be formed by using the method for manufacturing a semiconductor device described in this embodiment.

  According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off current can be provided. Alternatively, according to one embodiment of the present invention, a transistor with large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

<Modification Example of Semiconductor Device>
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described with reference to FIGS. 14, 15, and 16.

  14A, 15A, and 16A are top views of a semiconductor device including the transistor 200. FIG. 14B, 14C, 15B, 15C, 16B, and 16C are cross-sectional views of the semiconductor device. Here, FIG. 14 (B), FIG. 15 (B), or FIG. 16 (B) is indicated by an alternate long and short dash line A1-A2 in FIG. 14 (A), FIG. 15 (A), or FIG. FIG. 16 is a cross-sectional view of a portion, and also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 14C, FIG. 15C, or FIG. 16C is a portion shown by an alternate long and short dash line of A3-A4 in FIG. 14A, FIG. 15A, or FIG. And a cross-sectional view of the transistor 200 in the channel width direction. In the top views of FIG. 14A, FIG. 15A, and FIG. 16A, some elements are omitted for the sake of clarity of the figure.

  In the semiconductor devices shown in FIGS. 14, 15A and 16A, the same reference numerals are applied to the structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note.

  Hereinafter, the structure of the transistor 200 is described with reference to FIGS. 14, 15A, and 16A. Note that also in this item, as a constituent material of the transistor 200, any of the materials described in detail in <Configuration Example of Semiconductor Device> can be used.

[Modification 1 of Semiconductor Device]
As illustrated in FIG. 14, the transistor 200 is different from the semiconductor device described in <Structural Example 1 of Semiconductor Device> in that at least the insulator 273 is included.

  Specifically, as illustrated in FIG. 14, the insulator 273 is provided between the insulator 224, the oxide 230, the insulator 272, and the insulator 271, and the insulator 274.

  By providing the insulator 273 between the insulator 274 and the oxide 230 as shown in FIG. 14, the amount of dopant diffused when the insulator 274 is formed can be adjusted. Therefore, the thickness and material of the insulator 273 may be designed as appropriate depending on the desired performance of the transistor.

  For example, as the insulator 273, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen can be used. For example, aluminum oxide or hafnium oxide is preferably used. Thus, the thickness of the insulator 273 can be reduced. Specifically, the thickness of the insulator 273 is preferably 0.5 nm or more and 1.2 nm or less.

  Note that the insulator 273 may be formed by an ALD method. By using the ALD method, the insulator 273 with high filmability can be formed.

  In addition, by providing the insulator 273, the barrier property of the insulator 272 is enhanced by covering the side surface of the insulator 272 with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. be able to. Thus, impurities such as water or hydrogen can be prevented from being mixed into the oxide 230 through the conductor 260, the insulator 250, and the insulator 252. Therefore, the insulator 273 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulating film.

[Modification 2 of Semiconductor Device]
As illustrated in FIG. 15, the transistor 200 is different from the semiconductor device described in <Structural Example 1 of Semiconductor Device> in at least the shape of the oxide 230c.

  Specifically, as shown in FIG. 15, the oxide 230c is provided to cover the oxide 230a and the oxide 230b. That is, the oxide 230b is surrounded by the oxide 230a and the oxide 230c. With this structure, in the region 234, entry of impurities into the oxide 230b in which a channel is formed can be suppressed.

  The side surfaces of the oxide 230 a and the side surfaces of the oxide 230 b are preferably provided so as to be on the same plane. In addition, the oxide 230c is preferably formed to cover the oxide 230a and the oxide 230b. For example, the oxide 230c is formed in contact with the side surface of the oxide 230a, the top and side surfaces of the oxide 230b, and part of the top surface of the insulator 224. Here, when the oxide 230c is viewed from the top, the side surfaces of the oxide 230c are located outside the side surfaces of the oxide 230a and the oxide 230b. With this structure, in the case where the transistor 200 is electrically connected to the conductor 240, electrical conduction is also performed over the insulator 224 through the oxide 230c; thus, ohmic contact is favorable.

[Modification 3 of Semiconductor Device]
As shown in FIG. 16, in the transistor 200, the semiconductor device shown in <Modified Example 1 of Semiconductor Device>, the insulator 275 is provided, and a part of the film thickness of the insulator 273 is thin. The point differs in that the insulator 272 is not provided and the region 236 is provided.

  Specifically, as shown in FIG. 16, the insulator 275 is disposed on the side surface of the conductor 260 via the insulator 273. As the insulator 275, an insulating material which can be used for the insulator 271 may be used. By providing the insulator 274 as a film containing hydrogen, nitrogen, or the like through the insulator 275, addition of hydrogen and nitrogen is suppressed in a region (the region 234) overlapping with the insulator 275. In addition, the region 232 is determined by the shape, the film thickness, the width, and the like of the insulator 275. Therefore, by appropriately designing the insulator 275, the region 232 in which hydrogen and nitrogen are diffused can be controlled, and the characteristics of the transistor 200 can be obtained.

  The insulator 273 may also function as a side barrier that protects the side surfaces of the gate electrode and the gate insulator. The film thickness for preventing the diffusion of impurities as a side barrier may differ from the film thickness for diffusing an impurity in an amount to reduce resistance of at least the region 231 as a buffer layer. That is, the insulator 273 may have different thicknesses in the region functioning as a side barrier and the region functioning as a buffer layer. Therefore, the thickness of the insulator 273 in the region in contact with the insulator 273 is preferably larger than the thicknesses of the side surfaces of the conductor 260, the side surfaces of the insulator 250, and the side surfaces of the insulator 252.

  In the case where the insulator 273 and the insulator 275 are provided as described above, the insulator 272 may not be provided.

  Alternatively, as shown in FIG. 15, the insulator 224 may be formed into an island shape, and the insulator 273 may be in contact with the insulator 222 in a region which does not overlap with the insulator 224. When the insulator 222 and the insulator 273 are in contact with each other, the oxide 230 has a structure sealed with a film which suppresses diffusion of hydrogen or nitrogen. Thus, excessive impurities can be prevented from entering the oxide 230 from structures other than the insulator 274.

  The oxide 230 b may also have a region 236 (a region 236 a and a region 236 b) overlapping with the conductor 240. The region 236 is a low-resistance region in which the carrier density is higher than that of the source region 231 which functions as a drain region. As the transistor is miniaturized, the contact area between the oxide 230 and the conductor 240 also decreases. By reducing the resistance of the region 236, sufficient ohmic contact between the oxide 230 and the conductor 240 can be secured.

  In the region 236, the carrier density can be increased and resistance can be reduced by increasing the content of the element that forms the above-described oxygen vacancy and the element trapped in the oxygen vacancy. Further, by adding a metal element such as indium and increasing the content of metal atoms such as indium in the region 236, electron mobility can be increased and resistance can be reduced. Note that in the case where indium is added, the atomic ratio of indium to the element M in at least the region 236 is larger than the atomic ratio of indium to the element M in the region 234.

  In order to reduce the resistance of the region 236, an opening through which the oxide 230 is exposed is provided in the insulator 280, the insulator 274, and the insulator 273, and the insulator 280, the insulator 274, and the insulator 273 are used as masks. An impurity or a metal element may be added.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments.

Third Embodiment
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

<Configuration Example of Semiconductor Device>
17A, 17B, and 17C are top views and cross-sectional views of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that in this specification, a memory device including one capacitor and at least one transistor is referred to as a cell.

  FIG. 17A is a top view of a cell 600 including the transistor 200 and the capacitor 100. FIG. 17B and 17C are cross-sectional views of the cell 600. Here, FIG. 17B is a cross-sectional view of a portion indicated by an alternate long and short dash line A1-A2 in FIG. 17A, and is also a cross-sectional view of the transistor 200 in the channel length direction. 17C is a cross-sectional view of a portion indicated by an alternate long and short dash line A3-A4 in FIG. 17A, and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 17A, some elements are omitted for clarity of the drawing.

[Cell 600]
The semiconductor device of one embodiment of the present invention includes the transistor 200, the capacitor 100, and the insulator 280 which functions as an interlayer film. In addition, the transistor 200 includes the conductor 240 (the conductor 240a, the conductor 240b, the conductor 240c, and the conductor 240d) which is electrically connected to the transistor 200 and functions as a plug.

  In the cell 600 illustrated in FIG. 17, part of the structure included in the transistor 200 is used in combination with part of the structure included in the capacitor 100 by providing the transistor 200 and the capacitor 100 in the same layer. be able to. That is, part of the structure of the transistor 200 may function as part of the structure of the capacitor 100.

  In addition, by overlapping part or whole of the capacitor 100 with the transistor 200, the total area of the projection area of the transistor 200 and the projection area of the capacitor 100 can be reduced.

  The lower portion of the region where the capacitor 100 and the transistor 200 overlap with each other is a plug electrically connected to the transistor 200 or a conductor 240 b functioning as a wiring and the conductor 207 (the conductor 207 a and the conductor 207 b). By providing them, the miniaturization or high integration of the cell 600 is facilitated. In addition, since the conductor 207 can be formed in the same step as the conductor 205 which is a structure of the transistor 200, the process can be shortened.

  Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on the required capacitance value.

  For example, the area of the capacitor 100 is determined by the area where the region 231 b of the oxide 230 and the conductor 120 overlap with the insulator 130 interposed therebetween. Therefore, when the capacitance value required for the cell 600 can not be obtained with the capacitor 100 shown in FIGS. 17A and 17B, the width in the direction A3-A4 in the region 231b of the oxide 230a and the oxide 230b Can be made larger than the width in the direction A3-A4 in the region 234 of the oxide 230a and the oxide 230b, the capacitance value can be increased.

  Further, for example, the length in the A1-A2 direction in the region 231b of the oxide 230 may be longer than the length in the A1-A2 direction of the conductor 120. In that case, the conductor 240 b can be embedded in the insulator 280. That is, the region 231 b of the oxide 230 and the conductor 240 b may be provided in contact with each other in a region where the region 231 b of the oxide 230 and the conductor 120 do not overlap. Therefore, the steps can be shortened by forming the conductor 240a, the conductor 240b, and the conductor 240c in the same step.

  With the above structure, miniaturization or high integration is possible. Also, the degree of freedom in design can be increased. Further, the transistor 200 and the capacitor 100 are formed in the same step. Therefore, since the process can be shortened, the productivity can be improved.

[Transistor 200]
The structure of the transistor 200 may be a transistor included in the semiconductor device described in the above embodiment. The transistor 200 illustrated in FIG. 17 is an example, and is not limited to the structure. An appropriate transistor may be used according to the circuit configuration and the driving method.

[Capacitance element 100]
As illustrated in FIG. 17, the capacitor 100 has a structure common to that of the transistor 200. In this embodiment, the region 231 b provided in the oxide 230 of the transistor 200 is described as an example of the capacitor 100 functioning as one of the electrodes of the capacitor 100.

  The capacitor 100 includes the insulator 130 over the region 231 b of the oxide 230 and the region 231, and the conductor 120 over the insulator 130. Furthermore, the conductor 120 is preferably disposed over the insulator 130 so that at least a portion of the conductor 130 overlaps with the region 231 b of the oxide 230.

  The region 231 b of the oxide 230 functions as one of the electrodes of the capacitor 100, and the conductor 120 functions as the other of the electrodes of the capacitor 100. The insulator 130 functions as a dielectric of the capacitor 100. The region 231 b of the oxide 230 is low in resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100.

  Note that the insulator 130 may be provided by processing the insulator 274. The insulator 130 (insulator 274) may be left in contact with the transistor 200 and the insulator 224.

  Alternatively, a dopant may be added to the region 231 of the oxide 230 by an ion doping method, plasma treatment, or the like to separately provide the insulator 130 as a dielectric without providing the insulator 274. For the insulator 130, for example, aluminum oxide or silicon oxynitride may be used in a single layer or stacked layers.

  The conductor 120 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Although not shown, the conductor 120 may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.

<Structure of Cell Array>
Here, an example of a cell array according to the present embodiment is shown in FIGS. 18 and 19. For example, a cell array can be formed by arranging the transistor 200 illustrated in FIG. 17 and the cell 600 including the capacitor 100 in a matrix or matrix.

  FIG. 18A is a circuit diagram showing one form in which the cells 600 shown in FIG. 17 are arranged in a matrix. In FIG. 18A, one of the source and the drain of the transistor included in the cell 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). In addition, the BL is also electrically connected to one of the source and the drain of a transistor included in a cell in the column direction. On the other hand, first gates of the transistors included in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, the second gate BG may be provided in a transistor included in each cell 600. The potential applied to BG can control the threshold of the transistor. In addition, a first electrode of a capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be part of a structure that constitutes a transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to PL.

  18B shows a circuit 620 including the cell 600a electrically connected to WL04 and BL02 as part of a row, and the cell 600b electrically connected to WL03 and BL02 in FIG. 18A. FIG. FIG. 18B shows a cross-sectional view of the cell 600a and the cell 600b.

  The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600 b includes the transistor 200 b and the capacitor 100 b.

  One of the source and the drain of the transistor 200a and one of the source and the drain of the transistor 200b are both electrically connected to BL02.

  From the above configuration, by sharing the wiring electrically connected to one of the source and the drain, the occupied area of the cell array can be further reduced.

  FIG. 19A is a circuit diagram showing a mode different from FIG. 18A in a circuit in which the cells 600 shown in FIG. 17 are arranged in a matrix. In FIG. 19A, the first gates of the transistors included in the cells 600 arranged in the row direction are electrically connected to the common WL (WL01, WL02, and WL03). In addition, one of the source and the drain of a transistor included in a cell in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, the second gate BG may be provided in a transistor included in each cell 600. The potential applied to BG can control the threshold of the transistor. In addition, a first electrode of a capacitor included in the cell 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be part of a structure that constitutes a transistor. In addition, the second electrode of the capacitor included in the cell 600 is electrically connected to PL.

  FIG. 19B shows a circuit 610 including the cell 600 a electrically connected to WL 02 and BL 03 as part of a row, and the cell 600 b electrically connected to WL 02 and BL 04 in FIG. 19A. FIG. FIG. 19B is a cross-sectional view of the cell 600a and the cell 600b.

  The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600 b includes the transistor 200 b and the capacitor 100 b.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments.

Embodiment 4
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

<Storage device 1>
The memory device illustrated in FIGS. 20, 21, and 22 includes the transistor 300, the transistor 200, and the capacitor 100. 20 and 22 are cross-sectional views in the channel length direction of the transistor 200 and the transistor 300. FIG. 21 shows a cross-sectional view of the transistor 300 in the channel width direction in the vicinity of the transistor 300. FIG.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor for the memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.

  In the memory device illustrated in FIGS. 20 and 22, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. There is. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The memory device illustrated in FIGS. 20 and 22 has a characteristic that the potential of the gate of the transistor 300 can be held, whereby information can be written, held, and read as described below.

  The writing and holding of information will be described. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, whereby the transistor 200 is turned on. Thus, the potential of the wiring 1003 is applied to the node SN electrically connected to the gate of the transistor 300 and one of the electrodes of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of charges (hereinafter referred to as low level charge and high level charge) giving two different potential levels is given. After that, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off, whereby the transistor 200 is turned off, whereby charge is held at the node SN (holding).

  When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is supplied to the wiring 1001, the wiring 1002 takes a potential corresponding to the amount of charge held at the node SN. This is because, if the transistor 300 is an n-channel type, the apparent threshold voltage V th — _H when the high level charge is given to the gate of the transistor 300 is given the low level charge to the gate of the transistor 300. This is because the threshold voltage V _{th_L} is lower than the apparent threshold voltage V _{th_L} . Here, the apparent threshold voltage refers to the potential of the wiring 1005 which is required to turn on the transistor 300. Therefore, by _setting the potential of the wiring 1005 to the potential V ₀ between V _{th — H} and V th — _L , the charge given to the node SN can be determined. For example, in the case where a high level charge is given to the node SN in writing, the transistor 300 is turned “on” when the potential of the wiring 1005 is V ₀ (> V th — _H ). On the other hand, in the case where low level charge is applied to the node SN, the transistor 300 remains in the “non-conductive state” even if the potential of the wiring 1005 becomes V ₀ (<V th — _L ). Therefore, the information held in the node SN can be read by determining the potential of the wiring 1002.

<Structure of Storage Device 1>
The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. Have.

  As shown in FIG. 21, in the transistor 300, the top surface of the semiconductor region 313 and the side surface in the channel width direction are covered with the conductor 316 with the insulator 315 interposed therebetween. As described above, by setting the transistor 300 to a Fin type, the on-characteristic of the transistor 300 can be improved by increasing the effective channel width. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

  The transistor 300 may be either p-channel or n-channel.

  A semiconductor such as a silicon-based semiconductor is preferably included in a region where the channel of the semiconductor region 313 is to be formed, a region in the vicinity thereof, a low resistance region 314a to be a source or drain region, a low resistance region 314b, and the like. Preferably, crystalline silicon is included. Alternatively, it may be formed using a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide) or the like. It is also possible to use silicon whose effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.

  The low-resistance region 314a and the low-resistance region 314b impart p-type conductivity such as an element imparting n-type conductivity such as arsenic or phosphorus or p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313 Containing elements.

  The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, an alloy Materials or conductive materials such as metal oxide materials can be used.

  Note that the threshold voltage can be adjusted by defining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

  Note that the transistor 300 illustrated in FIG. 20 is an example, and is not limited to the structure. An appropriate transistor may be used according to the circuit configuration and the driving method.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked over the transistor 300.

  For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used as the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Just do it.

  The insulator 322 may have a function as a planarization film which planarizes a step difference generated by the transistor 300 and the like provided below the insulator. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.

  Further, as the insulator 324, a film having a barrier property to prevent diffusion of hydrogen or an impurity from the substrate 311, the transistor 300, or the like to the region where the transistor 200 is provided is preferably used.

  As an example of a film having a barrier property to hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, the characteristics of the semiconductor element may be reduced. Therefore, it is preferable to use a film which suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

The desorption amount of hydrogen can be analyzed, for example, using a thermal desorption gas analysis method (TDS) or the like. For example, in the TDS analysis, the desorption amount of hydrogen in the insulator 324 is 10 × 10 5 in the range of 50 ° C. to 500 ° C. when the desorption amount in terms of hydrogen atoms is converted per area of the insulator 324. ¹⁵ atom / cm ² or less, and may be preferably 5 × ¹⁰ 15 atom / cm ² or less.

  Note that the insulator 326 preferably has a dielectric constant lower than that of the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the dielectric constant of the insulator 324 is preferably 0.7 times or less of the dielectric constant of the insulator 326, and more preferably 0.6 times or less. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

  In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, the conductor 328 electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 have a function as a plug or a wiring. Moreover, the conductor which has a function as a plug or wiring may put several structure together, and may provide the same code | symbol. In the present specification and the like, the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and a wiring (conductor 328 and conductor 330 and the like), a single layer or a stack of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material It can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 350, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 350 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  As a conductor having a barrier property to hydrogen, for example, tantalum nitride or the like may be used. Further, by stacking tantalum nitride and tungsten with high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, the tantalum nitride layer having a barrier property to hydrogen preferably has a structure in contact with the insulator 350 having a barrier property to hydrogen.

  A wiring layer may be provided over the insulator 350 and the conductor 356. For example, in FIG. 20, an insulator 360, an insulator 362, and an insulator 364 are sequentially stacked and provided. In the insulator 360, the insulator 362, and the insulator 364, a conductor 366 is formed. The conductor 366 functions as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 360, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 360 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 20, an insulator 370, an insulator 372, and an insulator 374 are sequentially stacked. In the insulator 370, the insulator 372, and the insulator 374, a conductor 376 is formed. The conductor 376 functions as a plug or a wiring. Note that the conductor 376 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that, for example, for the insulator 370, similarly to the insulator 324, an insulator having a barrier property to hydrogen is preferably used. The conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening portion of the insulator 370 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 20, an insulator 380, an insulator 382, and an insulator 384 are sequentially stacked. A conductor 386 is formed in the insulator 380, the insulator 382, and the insulator 384. The conductor 386 functions as a plug or a wiring. Note that the conductor 386 can be provided using a material similar to the conductor 328 and the conductor 330.

  Note that for example, for the insulator 380, as in the case of the insulator 324, it is preferable to use an insulator having a barrier property to hydrogen. The conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, a conductor having a barrier to hydrogen is formed in an opening of the insulator 380 having a barrier to hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

  Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above, the memory device according to this embodiment It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

  An insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked over the insulator 384. For any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, a material having a barrier property to oxygen or hydrogen is preferably used.

  For example, for the insulator 210 and the insulator 214, for example, a film having a barrier property to prevent diffusion of hydrogen and impurities from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 200 is provided Is preferred. Therefore, the same material as the insulator 324 can be used.

  As an example of a film having a barrier property to hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, the characteristics of the semiconductor element may be reduced. Therefore, it is preferable to use a film which suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of desorption of hydrogen.

  Further, as the film having a barrier property to hydrogen, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used for the insulator 210 and the insulator 214.

  In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

  For example, for the insulator 212 and the insulator 216, the same material as the insulator 320 can be used. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 212 and the insulator 216.

  In the insulator 210, the insulator 212, the insulator 214, and the insulator 216, the conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded. Note that the conductor 218 has a function as a plug electrically connected to the capacitor 100 or the transistor 300, or a wiring. The conductor 218 can be provided using a material similar to the conductor 328 and the conductor 330.

  In particular, the conductor 218 in a region in contact with the insulator 210 and the insulator 214 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. According to this structure, the transistor 300 and the transistor 200 can be completely separated in a layer having a barrier property to oxygen, hydrogen, and water, and can suppress diffusion of hydrogen from the transistor 300 to the transistor 200. .

  The transistor 200 is provided above the insulator 216. Note that the structure of the transistor 200 may be a transistor included in the semiconductor device described in the above embodiment. The transistor 200 illustrated in FIG. 20 is an example, and is not limited to the structure. An appropriate transistor may be used according to the circuit configuration and the driving method.

  An insulator 280 is provided above the transistor 200.

  An insulator 282 is provided on the insulator 280. For the insulator 282, a substance having a barrier property to oxygen or hydrogen is preferably used. Therefore, for the insulator 282, the same material as the insulator 214 can be used. For example, for the insulator 282, metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

  In particular, aluminum oxide has a high blocking effect of preventing permeation of the film against both oxygen and impurities such as hydrogen and moisture which cause fluctuation of the electrical characteristics of the transistor. Thus, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed in the transistor 200 during and after the manufacturing process of the transistor. Further, release of oxygen from the oxide of the transistor 200 can be suppressed. Therefore, it is suitable to be used as a protective film for the transistor 200.

  In addition, an insulator 286 is provided over the insulator 282. The insulator 286 can be made of the same material as the insulator 320. In addition, by using a material having a relatively low dielectric constant as the interlayer film for the insulating film, parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286.

  In the insulator 220, the insulator 222, the insulator 280, the insulator 282, and the insulator 286, the conductor 246, the conductor 248, and the like are embedded.

  The conductor 246 and the conductor 248 each function as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 246 and the conductor 248 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  Subsequently, a capacitor 100 is provided above the transistor 200. The capacitive element 100 includes a conductor 110, a conductor 120, and an insulator 130.

  The conductor 112 may be provided over the conductor 246 and the conductor 248. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 functions as an electrode of the capacitor 100. Note that the conductor 112 and the conductor 110 can be formed at the same time.

  For the conductor 112 and the conductor 110, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film containing the above-described element as a component (Tantalum nitride, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Or indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide can also be applied.

  Although the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 20, the present invention is not limited to this structure, and may have a stacked structure of two or more layers. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.

  In addition, the insulator 130 is provided over the conductor 112 and the conductor 110 as a dielectric of the capacitor 100. The insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium oxide, etc. It may be used, and it can be provided in a stack or a single layer.

  For example, for the insulator 130, a material such as silicon oxynitride with high dielectric strength may be used. With this configuration, the capacitor 100 can improve the dielectric strength and can suppress electrostatic breakdown of the capacitor 100 by including the insulator 130.

  The conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. Note that as the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper) or Al (aluminum) or the like which is a low resistance metal material may be used.

  An insulator 150 is provided over the conductor 120 and the insulator 130. The insulator 150 can be provided using a material similar to that of the insulator 320. Moreover, the insulator 150 may function as a planarizing film which covers the uneven shape below it.

  With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification of Storage Device 1>
Hereinafter, an example of a memory device according to one embodiment of the present invention will be described with reference to FIG.

  FIG. 22 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. Note that in the memory device shown in FIG. 22, the same reference numerals are attached to the structure having the same function as the semiconductor device shown in the above embodiment and <structure of memory device 1> and the structure of the memory device. Do.

  As shown in FIG. 22, the transistor 200 is different from the semiconductor device shown in <Configuration Example of Memory Device 1> in that the cell 600 described in the above embodiment is provided. Note that the configuration of the transistor 200 illustrated in FIG. 22 is a configuration illustrated in [Modification 3 of semiconductor device].

  Specifically, as shown in FIG. 22, instead of the capacitor 100 and the transistor 200, a cell 600 sharing a part of the configuration of the capacitor 100 and a part of the configuration of the transistor 200 is included.

  With the above structure, the total of the projected area of the memory device can be reduced by overlapping part or all of the cell 600 and the transistor 300. Therefore, miniaturization or high integration of the cell 600 is facilitated. In addition, the process can be shortened.

<Storage device 2>
The semiconductor device illustrated in FIG. 23 is a memory device including the transistor 400, the transistor 200, and the capacitor 100. One mode of the storage device will be described below with reference to FIG.

  FIG. 23A is a circuit diagram illustrating an example of a connection relation of the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. A cross-sectional view of a semiconductor device in which the wirings 1004 to the wirings 1010 and the like illustrated in FIG. 23A correspond to each other is illustrated in FIG.

  The transistors 200 and 400 formed on a substrate (not shown) have different configurations. For example, the transistor 400 may have a smaller drain current Icut when the bottom gate voltage and the top gate voltage are 0 V as compared to the transistor 200. The potential of the bottom gate of the transistor 200 can be controlled by using the transistor 400 as a switching element. Thus, after the node connected to the bottom gate of the transistor 200 is set to a desired potential, the transistor 400 is turned off to suppress dissipation of the charge of the node connected to the bottom gate of the transistor 200. it can.

  As illustrated in FIG. 23, in the transistor 200, the gate is electrically connected to the wiring 1004, one of the source and the drain is connected to the wiring 1003, and the other of the source and the drain is electrically connected to one of the electrodes of the capacitor 100. The other of the electrodes of the capacitor 100 is electrically connected to the wiring 1005. In addition, the drain of the transistor 400 is electrically connected to the wiring 1010. In addition, as illustrated in FIG. 23B, the bottom gate of the transistor 200 and the source, top gate, and bottom gate of the transistor 400 are electrically connected to each other through the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009. Connected

  Here, by application of a potential to the wiring 1004, the on / off state of the transistor 200 can be controlled. When the transistor 200 is turned on and a potential is applied to the wiring 1003, charge can be supplied to the capacitor 100 through the transistor 200. At this time, by turning off the transistor 200, the charge supplied to the capacitor 100 can be held. The wiring 1005 can control the potential of the connection portion of the transistor 200 and the capacitor 100 by capacitive coupling by applying an arbitrary potential. For example, when a ground potential is applied to the wiring 1005, the charge can be easily held. In addition, by applying a negative potential to the wiring 1010, a negative potential is applied to the bottom gate of the transistor 200 through the transistor 400, the threshold voltage of the transistor 200 is larger than 0 V, and off current is reduced. , Icut can be very small.

As described in the above embodiment, the transistor 200 can increase the voltage V _th and reduce Icut sufficiently with the voltage V _BG having a small absolute value. Therefore, the absolute value of the negative voltage applied to the wiring 1010 can be reduced. Thus, a negative voltage can be applied to the wiring 1010 without providing an excessive step-down circuit or the like.

  Note that although 3.3 V is selected as a voltage corresponding to the wiring 1003 in an example described later, the storage device according to the present embodiment is not limited to this. The voltage may be less than 3.3V or greater than 3.3V. For example, in the storage device according to this embodiment, in the case of storing multilevel data, the margin for reading multilevel data can be increased by increasing the voltage that can be applied to the wiring 1003.

  The bottom gate voltage of the transistor 200 can be controlled by the wiring 1010 by connecting the top gate and the bottom gate of the transistor 400 with the source and connecting the source of the transistor 400 and the bottom gate of the transistor 200. . When the negative potential of the bottom gate of the transistor 200 is held, the voltage between the top gate and the source of the transistor 400 and the voltage between the bottom gate and the source are 0 V. Since Icut of the transistor 400 is very small and the threshold voltage is larger than that of the transistor 200, this structure maintains negative potential of the bottom gate of the transistor 200 for a long time without supplying power to the transistor 400. be able to.

  Further, by holding the negative potential of the bottom gate of the transistor 200, Icut of the transistor 200 can be extremely reduced without supplying power to the transistor 200. That is, charge can be held in the capacitor 100 for a long time without supplying power to the transistors 200 and 400. For example, by using such a semiconductor device as a memory element, memory can be held for a long time without power supply. Thus, a memory device in which the frequency of the refresh operation is low or which does not require the refresh operation can be provided.

Further, as described in the above embodiment, the transistor 200 can increase the voltage V _th and reduce Icut sufficiently at the voltage V _BG with a small absolute value. Therefore, the withstand voltage required of the transistor 400 is relatively low, so that the degree of freedom in design of the transistor 400 can be increased.

  Note that the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 is not limited to those illustrated in FIGS. The connection relationship can be appropriately changed according to the required circuit configuration.

<Structure of Storage Device 2>
FIG. 23B is a cross-sectional view of the memory device including the capacitor 100, the transistor 200, and the transistor 400. Note that in the memory device shown in FIG. 23, the same reference numerals are appended to the structure having the same function as the semiconductor device shown in the above embodiment and <structure of memory device 1> and the structure of the memory device. Do.

  The memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided in the same layer, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  Note that for the capacitor 100 and the transistor 200, the capacitor and the transistor included in any of the semiconductor devices and memory devices described in the above embodiments and FIGS. 20 and 22 may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 23 are merely examples, and the present invention is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

  The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductor 460a and a conductor 460b) functioning as a top gate electrode, a conductor 405 (conductor 405a and a conductor 405b) functioning as a bottom gate electrode, and a conductor 460. An insulator 470 and an insulator 472 which are in contact with each other, an insulator 220 which functions as a gate insulating layer, an insulator 222, an insulator 224, and an insulator 450, an oxide 430c having a region where a channel is formed, a source or An oxide 431 a and an oxide 431 b which function as one of drains and an oxide 432 a and an oxide 432 b which function as the other of the source and the drain are included. Further, the conductor 405 functioning as a bottom gate electrode is electrically connected to the conductor 403 (conductor 403a and conductor 403b) functioning as a wiring.

  In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The insulator 452 is the same layer as the insulator 252. The conductor 460 is the same layer as the conductor 260. In addition, the insulator 470 is the same layer as the insulator 270. The insulator 472 is the same layer as the insulator 272.

  In the oxide 430 c which functions as an active layer of the transistor 400, oxygen vacancies are reduced and impurities such as hydrogen or water are reduced as in the case of the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 400 can be greater than 0 V, the off-state current can be reduced, and the drain current when the bottom gate voltage and the top gate voltage are 0 V can be extremely small.

  With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor including an oxide semiconductor. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage device 3>
The semiconductor device illustrated in FIG. 24 is a memory device including the transistor 300, the transistor 200, and the capacitor 100. One mode of the storage device is described below with reference to FIG.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in the above embodiment can be formed with high yield even when miniaturized; therefore, the transistor 200 can be miniaturized. When such a transistor is used for a memory device, the memory device can be miniaturized or highly integrated. The off-state current of the transistor described in the above embodiment is small; thus, when used for a memory device, stored data can be held for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.

  In FIG. 24, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. There is. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

  In FIG. 24, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. . The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is a drain of the transistor 400 And are electrically connected. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

  The semiconductor device illustrated in FIG. 24 has a characteristic that the potential of the gate of the transistor 300 can be held, whereby information can be written, held, and read as described below.

  The writing and holding of information will be described. First, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned on, whereby the transistor 200 is turned on. Thus, the potential of the third wiring 1003 is applied to the node SN electrically connected to the gate of the transistor 300 and one of the electrodes of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of charges (hereinafter referred to as low level charge and high level charge) giving two different potential levels is given. After that, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned off, and the transistor 200 is turned off, whereby charge is held at the node SN (holding).

  When the off-state current of the transistor 200 is small, the charge of the node SN is held for a long time.

Next, reading of information will be described. When an appropriate potential (readout potential) is applied to the fifth wiring 1005 in a state where the first wiring 1001 is applied with a predetermined potential (constant potential), the second wiring 1002 generates the charge held at the node SN. Take the potential according to the amount. This is because, if the transistor 300 is an n-channel type, the apparent threshold voltage V th — _H when the high level charge is given to the gate of the transistor 300 is given the low level charge to the gate of the transistor 300. This is because the threshold voltage V _{th_L} is lower than the apparent threshold voltage V _{th_L} . Here, the apparent threshold voltage refers to the potential of the fifth wiring 1005 which is necessary to turn on the transistor 300. Therefore, by _setting the potential of the fifth wiring 1005 to the potential V ₀ between V _{th — H} and V th — _L , the charge given to the node SN can be determined. For example, in the case where a high level charge is given to the node SN in writing, the transistor 300 is turned “on” if the potential of the fifth wiring 1005 is V ₀ (> V th — _H ). On the other hand, when low level charge is applied to the node SN, the transistor 300 remains in the “non-conductive state” even if the potential of the fifth wiring 1005 becomes V ₀ (<V th — _L ). Therefore, by determining the potential of the second wiring 1002, the information held in the node SN can be read.

<Structure of Storage Device 3>

  FIG. 24 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, the transistor 300, and the transistor 400. In the memory device shown in FIG. 24, the semiconductor device shown in the above embodiment, <structure of memory device 1>, and <structure of memory device 2>, and the structure having the same function as that of the memory device are included. The same symbols are attached to the structures that are possessed.

  The memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistor 200 and the transistor 400 are provided above the transistor 300, and the capacitor 100 is provided above the transistor 300, the transistor 200, and the transistor 400.

  Note that for the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitor and the transistor included in the semiconductor device described in the above embodiment and FIGS. 20 to 23, and the memory device may be used. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 24 are merely examples, and the present invention is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

  With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor including an oxide semiconductor. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of Memory Cell Array>

  An example of the memory cell array of the present embodiment is shown in FIG. A memory cell array can be formed by arranging the transistors 200 as memory cells in a matrix.

  The memory device shown in FIG. 25 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 20 and 24 in a matrix. Note that one transistor 400 can control the back gate voltage of the plurality of transistors 200. Therefore, the number of transistors 400 may be smaller than that of the transistors 200.

  Therefore, the transistor 400 shown in FIG. 24 is omitted in FIG. FIG. 25 is a cross-sectional view of a part of a row in the case where the memory devices shown in FIGS. 20 and 24 are arranged in a matrix.

  Further, the configuration of the transistor 300 is different from that in FIG. In the transistor 300 illustrated in FIG. 25, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. In addition, the conductor 316 is provided to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. Note that the conductor 316 may use a material for adjusting a work function. Such a transistor 300 is also referred to as a Fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator which functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Further, here, the case where the convex portion is formed by processing a part of the semiconductor substrate is described; however, a semiconductor film having a convex shape may be formed by processing the SOI substrate.

  In the memory device shown in FIG. 25, memory cell 650a and memory cell 650b are arranged adjacent to each other. The memory cell 650a and the memory cell 650b each include the transistor 300, the transistor 200, and the capacitor 100, and are electrically connected to the wiring 1001, the wiring 1002, the wiring 1003, the wiring 1004, the wiring 1005, and the wiring 1006. Similarly, in each of the memory cells 650 a and 650 b, a node at which the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is referred to as a node SN. Note that the wiring 1002 is a wiring common to the memory cell 650a and the memory cell 650b which are adjacent to each other.

In the case of arranging memory cells in an array, it is necessary to read information of a desired memory cell at the time of reading. For example, in the case where the memory cell array has a NOR configuration, only information of a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is in the “non-conductive state” regardless of the charge applied to the node SN, that is, a potential lower than V th — _H is applied to the wiring 1005 connected to the memory cell which does not read data. Just do it. Alternatively, for example, in the case where the memory cell array has a NAND configuration, only information of a desired memory cell can be read by turning on the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned “on” regardless of the charge applied to the node SN, that is, a potential higher than V th — _L is applied to the wiring 1005 connected to the memory cell which does not read data. Good.

  With this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, power consumption can be reduced in a semiconductor device using a transistor including an oxide semiconductor. Alternatively, in a semiconductor device using a transistor including an oxide semiconductor, miniaturization or high integration can be achieved. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments.

Fifth Embodiment
In this embodiment, a transistor using an oxide as a semiconductor (hereinafter, referred to as an OS transistor) and a memory element to which a capacitor is applied according to one embodiment of the present invention with reference to FIGS. 26 to 29. A NOSRAM will be described as an example of the device. NOSRAM (registered trademark) is an abbreviation of "nonvolatile oxide semiconductor RAM" and refers to a RAM having memory cells of gain cell type (2T type, 3T type). In the following, a memory device using an OS transistor such as a NOSRAM may be referred to as an OS memory.

  In the NOSRAM, a memory device (hereinafter referred to as “OS memory”) in which an OS transistor is used for a memory cell is applied. The OS memory is a memory that has at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor is a transistor with extremely small off current, the OS memory has excellent retention characteristics and can function as a non-volatile memory.

<< NOSRAM >>
FIG. 26 shows a configuration example of the NOSRAM. The NOSRAM 1600 shown in FIG. 26 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. The NOSRAM 1600 is a multivalued NOSRAM that stores multivalued data in one memory cell.

  The memory cell array 1610 has a plurality of memory cells 1611, a plurality of word lines WWL and RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In the NOSRAM 1600, 3-bit (eight-valued) data is stored in one memory cell 1611.

  The controller 1640 controls the entire NOSRAM 1600 in a centralized manner, writes the data WDA [31: 0], and reads the data RDA [31: 0]. The controller 1640 processes external command signals (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for the row driver 1650, the column driver 1660 and the output driver 1670.

  The row driver 1650 has a function of selecting a row to access. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

  Column driver 1660 drives source line SL and bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

  The DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts 32-bit data WDA [31: 0] into analog voltages every three bits.

  The write driver 1662 has a function of precharging the source line SL, a function of electrically floating the source line SL, a function of selecting the source line SL, and an input of the write voltage generated by the DAC 1663 to the selected source line SL. Have a function of precharging the bit line BL, a function of electrically floating the bit line BL, and the like.

  The output driver 1670 includes a selector 1671, an ADC (analog-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed, and transmits the voltage of the selected source line SL to the ADC 1672. The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.

  The configurations of the row driver 1650, the column driver 1660, and the output driver 1670 described in this embodiment are not limited to the above. Arrangements of these drivers and wirings connected to the drivers may be changed according to the configuration or driving method of the memory cell array 1610 or the like, or functions of the drivers and wirings connected to the drivers are changed Or you may add. For example, part of the functions of the source line SL may be provided to the bit line BL.

  Although the amount of information held in each memory cell 1611 is 3 bits in the above description, the configuration of the storage device described in this embodiment is not limited to this. The amount of information held by each memory cell 1611 may be 2 bits or less, or 4 bits or more. For example, when the amount of information held in each memory cell 1611 is 1 bit, the DAC 1663 and the ADC 1672 may not be provided.

<Memory cell>
FIG. 27A is a circuit diagram showing a configuration example of the memory cell 1611. The memory cell 1611 is a 2T-type gain cell, and the memory cell 1611 is electrically connected to the word lines WWL and RWL, the bit line BL, the source line SL, and the wiring BGL. The memory cell 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitive element C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor, and is formed of, for example, a p-channel Si transistor. The capacitive element C61 is a holding capacitance for holding the voltage of the node SN. The node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

  Since the write transistor of the memory cell 1611 is configured by the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

  In the example of FIG. 27A, the bit line is a common bit line for writing and reading, but as shown in FIG. 27B, the bit line WBL functioning as a writing bit line and the reading bit line And the bit line RBL may be provided.

  FIGS. 27C-27E show other configuration examples of the memory cell. FIGS. 27C-27E show an example in which the write bit line WBL and the read bit line RBL are provided. However, as shown in FIG. Bit lines may be provided.

  A memory cell 1612 shown in FIG. 27C is a modified example of the memory cell 1611, and the read transistor is changed to an n-channel transistor (MN 61). The transistor MN61 may be an OS transistor or a Si transistor.

  In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a back gate.

  The memory cell 1613 shown in FIG. 27D is a 3T-type gain cell, and is electrically connected to the word lines WWL and RWL, the bit lines WBL and RBL, the source line SL, and the wirings BGL and PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a read transistor, and the transistor MP63 is a selection transistor.

  A memory cell 1614 shown in FIG. 27E is a modification of the memory cell 1613, in which the read transistor and the select transistor are changed to n-channel transistors (MN62 and MN63). The transistors MN62 and MN63 may be OS transistors or Si transistors.

  The OS transistors provided in the memory cells 1611-1614 may be transistors without back gates or may be transistors with back gates.

  In the above, a so-called NOR type memory device in which memory cells 1611 and the like are connected in parallel is described, but the memory device described in this embodiment is not limited to this. For example, a so-called NAND memory device in which memory cells 1615 as shown below are connected in series may be used.

  FIG. 28 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. Referring to FIG. The memory cell array 1610 illustrated in FIG. 28 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitive element C63. Here, the transistor MN64 is formed of, for example, an n-channel Si transistor. The transistor MN 64 may be a p-channel Si transistor or an OS transistor.

  Hereinafter, the memory cell 1615a and the memory cell 1615b illustrated in FIG. 28 will be described as an example. Here, reference numerals of a wiring or a circuit element connected to either the memory cell 1615 a or the memory cell 1615 b are denoted by a or b.

  In the memory cell 1615a, the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitive element C63a are electrically connected. Further, the bit line WBL and the other of the source and the drain of the OS transistor MO63a are electrically connected. In addition, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the back gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other of the electrodes of the capacitive element C 63 a are electrically connected.

  The memory cell 1615 b can be provided symmetrically with the memory cell 1615 a with the contact portion with the bit line WBL as an axis of symmetry. Accordingly, the circuit element included in the memory cell 1615 b is also connected to the wiring in the same manner as the memory cell 1615 a.

  Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a included in the memory cell 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory cells 1615. As described above, in the NAND-type memory cell array 1610, the plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

  Here, FIG. 29 shows a cross-sectional view corresponding to the memory cell 1615a and the memory cell 1615b. Memory cell 1615a and memory cell 1615b have the same structure as the memory device shown in FIG. That is, capacitive element C63a and capacitive element C63b have the same structure as capacitive element 100, OS transistor MO63a and OS transistor MO63b have the same structure as transistor 200, and transistor MN64a and transistor MN64b are similar to transistor 300. It has a structure. However, in the memory cell 1615a and the memory cell 1615b described in this embodiment, the conductor 256 is provided over the insulator 280 and the conductor 240a. Further, in FIG. 22, the portion where the film thickness of the insulator 273 is thin is removed. The description can be referred to for the configuration shown in FIG. 29 that is given the same reference numeral as the configuration shown in FIG.

  In memory cell 1615a, conductor 120 is extended to function as word line RWLa, conductor 260 is extended to function as word line WWLa, and conductor 205 is extended to be wiring It functions as BGLa. Similarly, the word line RWLb, the word line WWLb, and the wiring BGLb are provided in the memory cell 1615b.

  The low resistance region 314b illustrated in FIG. 29 functions as a source of the transistor MN64a and a drain of the transistor MN64b. In addition, the low resistance region 314a functioning as the drain of the transistor MN64a is electrically connected to the bit line RBL through the conductor 328 and the conductor 330. The source of the transistor MN64b is electrically connected to the source line SL through the transistor MN64, the conductor 328, and the conductor 330 included in the plurality of memory cells 1615.

  In addition, the conductor 256 is extended and provided to function as a bit line WBL. Here, the conductor 240a functions as a contact portion of the word line WBL, and is used in common by the OS transistor MO63a and the OS transistor MO63b. Thus, the memory cell 1615a and the memory cell 1615b share the contact portion of the bit line WBL, thereby reducing the number of contact portions of the bit line WBL and reducing the occupied area of the memory cell 1615 in a top view. Can. Accordingly, the storage device according to the present embodiment can be further highly integrated, and the storage capacity per unit area can be increased.

  In the memory device having the memory cell array 1610 shown in FIG. 28, write operation and read operation are performed for each of a plurality of memory cells (hereinafter referred to as a memory cell column) connected to the same word line WWL (or word line RWL). Do. For example, the write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column to be written, and the OS transistor MO63 of the memory cell column to be written is turned on. Thereby, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the designated memory cell column and the electrode of the capacitive element C63, and a predetermined charge is applied to the gate. Then, when the OS transistor MO63 of the memory cell column is turned off, the predetermined charge given to the gate can be held. Thus, data can be written to the memory cell 1615 of the specified memory cell column.

  Also, for example, the read operation can be performed as follows. First, to a word line RWL not connected to a memory cell column to be read, a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64 is applied to read a memory cell column The other transistors MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read by the charge of the gate of the transistor MN64 so that the on state or the off state of the transistor MN64 is selected. Then, a constant potential is applied to the source line SL, and the reading circuit connected to the bit line RBL is brought into an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are in the on state except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is for reading It is determined by the state (on state or off state) of the transistor MN64 of the memory cell column. The conductance of the transistor differs depending on the charge of the gate of the transistor MN64 in the memory cell column to be read, and accordingly, the potential of the bit line RBL takes a different value. Information can be read out from the memory cell 1615 of the specified memory cell column by reading out the potential of the bit line RBL by the reading circuit.

  In the memory cell array 1610 shown in FIG. 28, the configuration in which the plurality of OS transistors MO63 are connected in parallel to the bit line WBL is shown, but the storage device shown in this embodiment is not limited to this. For example, as shown in FIG. 30, a plurality of OS transistors MO63 may be connected in series to bit line WBL. Note that the description related to FIG. 28 may be referred to for circuit elements, wirings, and the like illustrated in FIG.

  In the memory cell 1615 shown in FIG. 30, one of the source and the drain of the OS transistor MO63 is connected to the other of the source and the drain of the OS transistor MO63 of the adjacent memory cell. That is, the node SN functions as one of the source and drain of the OS transistor MO63 of the same memory cell, and also functions as the other of the source and drain of the OS transistor MO63 of the adjacent memory cell. In the memory cell 1615 at the end of the plurality of memory cells 1615 connected in series, the other of the source and the drain of the OS transistor MO63 is electrically connected to the bit line WBL.

  Here, FIG. 31 shows a cross-sectional view corresponding to the memory cell 1615 connected to the bit line WBL and the memory cell 1615 adjacent thereto. As shown in FIG. 31, in the memory cell array 1610 shown in FIG. 30, a plurality of OS transistors MO 63 connected in series are formed in one island-shaped oxide 230. A conductor 256 functioning as a bit line WBL is connected to the other of the source and the drain of the OS transistor MO63 at the end of the plurality of OS transistors MO63 connected in series via the conductor 240a. The description can be referred to for the configuration shown in FIG. 29 that is given the same reference numeral as the configuration shown in FIG.

  The write operation and the read operation of the memory cell array 1610 shown in FIG. 30 can basically refer to the write operation and the read operation of the memory cell array 1610 shown in FIG. However, in the memory cell array 1610 shown in FIG. 30, the node SN of each memory cell 1615 is connected to the OS transistor MO63 of the same memory cell and the OS transistor MO63 of the adjacent memory cell. Therefore, when one of the OS transistors MO63 is turned on, the charge held at the node SN is released, and the written data is erased.

  Therefore, in the write operation of memory cell array 1610 shown in FIG. 30, first, the write operation is performed with the memory cell column farthest from bit line WBL. Next, the write operation is performed on the memory cell column adjacent to the memory cell column in which the data is written. Thereafter, the write operation is performed in order up to the memory cell column connected to the bit line WBL. Thus, the OS transistor MO63 connected to the written node SN is obtained by sequentially performing the write operation from the memory cell column farthest from the bit line WBL to the memory cell column connected to the bit line WBL. The write operation can be performed without being turned on. Thus, it is possible to prevent data from being erased during the write operation of memory cell array 1610 shown in FIG.

  Since data is rewritten by charging / discharging of the capacitive element C61, the capacitive element C62, or the capacitive element C63, the number of times of rewriting is in principle not limited, and data can be written and read with low energy. In addition, since it is possible to hold data for a long time, the refresh frequency can be reduced.

  When the semiconductor device described in the above embodiment is used for the memory cells 1611, 1612, 1613, 1614, and 1615, the transistor 200 is used as the OS transistors MO61, MO62, and MO63, and the capacitor 100 is used as the capacitors C61, C62, and C63. The transistor 300 can be used as the transistors MP61, MP62, MP63, MN61, MN62, MN63, and MN64. Thus, the area occupied by the pair of the transistor and the capacitor in top view can be reduced, so that the memory device according to this embodiment can be further highly integrated. Therefore, the storage capacity per unit area of the storage device according to the present embodiment can be increased.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Sixth Embodiment
In this embodiment, a DOSRAM will be described as an example of a memory device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention with reference to FIGS. 32 and 33. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM", and refers to a RAM having memory cells of 1T (transistor) 1C (capacitance) type. OS memory is applied to the DOSRAM as well as the NOSRAM.

<< DOSRAM1400 >>
FIG. 32 shows a configuration example of the DOSRAM. As shown in FIG. 32, the DOSRAM 1400 has a controller 1405, a row circuit 1410, a column circuit 1415, a memory cell and a sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

  The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier driver circuit 1414. The column circuit 1415 has a global sense amplifier array 1416 and an input / output circuit 1417. The global sense amplifier array 1416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, and global bit lines GBLL and GBLR.

(MC-SA array 1420)
The MC-SA array 1420 has a stacked structure in which the memory cell array 1422 is stacked on the sense amplifier array 1423. Global bit lines GBLL and GBLR are stacked on memory cell array 1422. In the DOSRAM 1400, a hierarchical bit line structure hierarchized by local bit lines and global bit lines is adopted as the structure of bit lines.

  Memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N−1>. A configuration example of the local memory cell array 1425 is shown in FIG. The local memory cell array 1425 has a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 33A, the structure of the local memory cell array 1425 is an open bit line type, but may be a folded bit line type.

  An example of a circuit configuration of the memory cell 1445 is shown in FIG. The memory cell 1445 includes a transistor MW1, a capacitor CS1, and terminals B1 and B2. The transistor MW1 has a function of controlling charging and discharging of the capacitive element CS1. The gate of the transistor MW1 is electrically connected to the word line, the first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the first terminal of the capacitive element. The second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant voltage (for example, low power supply voltage) is input to the terminal B2.

  In the case of using the semiconductor device described in the above embodiment for the memory cell 1445, the transistor 200 can be used as the transistor MW1 and the capacitor 100 can be used as the capacitor CS1. Thus, the area occupied by the pair of the transistor and the capacitor in top view can be reduced, so that the memory device according to this embodiment can be highly integrated. Therefore, the storage capacity per unit area of the storage device according to the present embodiment can be increased.

  The transistor MW1 has a back gate, and the back gate is electrically connected to the terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the voltage of the terminal B1. For example, the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOS RAM 1400.

  The back gate of the transistor MW1 may be electrically connected to the gate, the source, or the drain of the transistor MW1. Alternatively, the transistor MW1 may not be provided with a back gate.

  Sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> -1426 <N-1>. The local sense amplifier array 1426 includes one switch array 1444 and a plurality of sense amplifiers 1446. A bit line pair is electrically connected to sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying a voltage difference between the bit line pair, and a function of holding the voltage difference. Switch array 1444 has a function of selecting a bit line pair and electrically connecting the selected bit line pair and the global bit line pair.

  Here, the bit line pair means two bit lines which are simultaneously compared by the sense amplifier. The global bit line pair refers to two global bit lines which are simultaneously compared by the global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form a pair of bit lines. Global bit line GBLL and global bit line GBLR form a pair of global bit lines. Hereinafter, the term “bit line pair (BLL, BLR)” and “global bit line pair (BLL, BLR)” are also used.

(Controller 1405)
The controller 1405 has a function of controlling the overall operation of the DOS RAM 1400. The controller 1405 performs a logical operation on an externally input command signal to determine an operation mode, and generates a control signal for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. And a function of holding an address signal input from the outside, and a function of generating an internal address signal.

(Row circuit 1410)
The row circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL in the access target row.

  The column selector 1413 and the sense amplifier driver circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting a bit line of the access target column. The selection signal of column selector 1413 controls switch array 1444 of each local sense amplifier array 1426. The control signals of the sense amplifier driver circuit 1414 drive the plurality of local sense amplifier arrays 1426 independently.

(Column circuit 1415)
Column circuit 1415 has a function of controlling an input of data signal WDA [31: 0] and a function of controlling an output of data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

  Global sense amplifier 1447 is electrically connected to global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between the global bit line pair (GBLL, GBLR) and a function of holding this voltage difference. Writing and reading of data to the global bit line pair (GBLL, GBLR) are performed by the input / output circuit 1417.

  An outline of the write operation of the DOSRAM 1400 will be described. Data is written to the global bit line pair by input / output circuit 1417. Data of the global bit line pair is held by the global sense amplifier array 1416. The data of the global bit line pair is written to the bit line pair of the target column by the switch array 1444 of the local sense amplifier array 1426 designated by the address. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the row circuit 1410 selects the word line WL of the target row, and the data held by the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

  An outline of the read operation of the DOSRAM 1400 will be described. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL in the target row is selected, and the data of the memory cell 1445 is written to the bit line. The local sense amplifier array 1426 detects and holds the voltage difference of the bit line pair of each column as data. Among the data held in local sense amplifier array 1426, data in the column designated by the address is written to the global bit line pair by switch array 1444. Global sense amplifier array 1416 detects and holds data of global bit line pairs. The held data of the global sense amplifier array 1416 is output to the input / output circuit 1417. Thus, the read operation is completed.

  Since the data is rewritten by the charge and discharge of the capacitive element CS1, the number of times of rewriting is not limited in principle in the DOSRAM 1400, and data can be written and read with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, the capacity can be easily increased.

  The transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, charge leakage from the capacitive element CS1 can be suppressed. Therefore, the retention time of the DOS RAM 1400 is very long compared to the DRAM. Therefore, since the frequency of refresh can be reduced, the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites a large amount of data with high frequency, for example, a frame memory used for image processing.

  Since MC-SA array 1420 has a stacked structure, bit lines can be shortened to a length approximately equal to the length of local sense amplifier array 1426. By shortening the bit line, the bit line capacitance can be reduced and the storage capacitance of the memory cell 1445 can be reduced. Further, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. From the above reasons, the load driven at the time of access to the DOS RAM 1400 is reduced, and power consumption can be reduced.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Seventh Embodiment
In this embodiment, as an example of a semiconductor device to which an OS transistor and a capacitor are applied according to one embodiment of the present invention, referring to FIGS. 34 to 37, an FPGA (field programmable gate array) is used. explain. In the FPGA of this embodiment, an OS memory is applied to a configuration memory and a register. Here, such an FPGA is called "OS-FPGA".

<< OS-FPGA >>
FIG. 34A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 34A is capable of context switching with a multi-context structure, fine-grained power gating, and NOFF (normally off) computing. The OS-FPGA 3110 includes a controller 3111, a word driver 3112, a data driver 3113, and a programmable area 3115.

  The programmable area 3115 has two input / output blocks (IOBs) 3117 and a core 3119. The IOB 3117 has a plurality of programmable input / output circuits. The core 3119 includes a plurality of logic array blocks (LABs) 3120 and a plurality of switch array blocks (SABs) 3130. The LAB 3120 has a plurality of PLEs 3121. FIG. 34B shows an example in which LAB 3120 is configured of five PLEs 3121. As shown in FIG. 34C, the SAB 3130 has a plurality of switch blocks (SB) 3131 arranged in an array. The LAB 3120 is connected to its own input terminal and the LAB 3120 in four (upper, lower, left, and right) directions via the SAB 3130.

  The SB 3131 will be described with reference to FIGS. 35 (A) to 35 (C). Data and datab, and signals context [1: 0] and word [1: 0] are input to the SB 3131 shown in FIG. data and datab are configuration data, and data and datab are in a complementary relationship with each other. The number of contexts of the OS-FPGA 3110 is 2, and the signals context [1: 0] are context selection signals. The signal word [1: 0] is a word line selection signal, and the wiring to which the signal word [1: 0] is input is a word line.

  The SB 3131 includes PRS (programmable routing switches) 3133 [0] and 3133 [1]. The PRS 3133 [0] and 3133 [1] have a configuration memory (CM) that can store complementary data. When the PRS 3133 [0] and the PRS 3133 [1] are not distinguished, they are referred to as the PRS 3133. The same applies to the other elements.

  FIG. 35B shows a circuit configuration example of PRS3133 [0]. The PRS3133 [0] and the PRS3133 [1] have the same circuit configuration. The PRS 3133 [0] and the PRS 3133 [1] are different in the context selection signal and the word line selection signal that are input. Signals context [0] and word [0] are input to PRS 3133 [0], and signals context [1] and word [1] are input to PRS 3133 [1]. For example, in SB 3131, PRS 3133 [0] becomes active when the signal context [0] becomes “H”.

  The PRS 3133 [0] has a CM 3135 and a Si transistor M31. The Si transistor M31 is a pass transistor controlled by the CM 3135. The CM 3135 has memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 includes a capacitor C31 and OS transistors MO31 and MO32. The memory circuit 3137B includes a capacitive element CB31, an OS transistor MOB31, and an MOB32.

  In the case of using the semiconductor device described in the above embodiment for the SAB 3130, the transistor 200 can be used as the OS transistors MO31 and MOB31, and the capacitor 100 can be used as the capacitors C31 and CB31. Thus, the area occupied by the pair of transistor and capacitive element in top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

  The OS transistors MO31, MO32, MOB31, and MOB32 have back gates, and these back gates are electrically connected to power supply lines supplying fixed voltages.

  The gate of the Si transistor M31 is a node N31, the gate of the OS transistor MO32 is a node N32, and the gate of the OS transistor MOB32 is a node NB32. The nodes N32 and NB32 are charge holding nodes of the CM 3135. The OS transistor MO32 controls conduction between the node N31 and the signal line for the signal context [0]. The OS transistor MOB32 controls the conduction between the node N31 and the low potential power supply line VSS.

  The data held by the memory circuits 3137 and 3137B are in a complementary relationship. Therefore, either one of the OS transistor MO32 or MOB 32 conducts.

  An operation example of the PRS 3133 [0] will be described with reference to FIG. Configuration data has already been written to the PRS 3133 [0], the node N 32 of the PRS 3133 [0] is “H”, and the node NB 32 is “L”.

  While the signal contex [0] is "L", the PRS 3133 [0] is inactive. During this period, even if the input terminal of the PRS 3133 [0] changes to “H”, the gate of the Si transistor M31 is maintained at “L”, and the output terminal of the PRS 3133 [0] is also maintained “L”.

  While the signal contex [0] is "H", the PRS 3133 [0] is active. When the signal contex [0] transitions to “H”, the gate of the Si transistor M31 transitions to “H” according to the configuration data stored in the CM 3135.

  When the input terminal changes to "H" while PRS 3133 [0] is active, the gate voltage of the Si transistor M31 is increased by boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. As a result, the OS transistor MO32 of the memory circuit 3137 loses the driving capability, and the gate of the Si transistor M31 is in a floating state.

  In the PRS 3133 with multi-context capability, the CM 3135 combines the functionality of a multiplexer.

  FIG. 36 shows a configuration example of PLE 3121. The PLE 3121 has a LUT (look-up table) block 3123, a register block 3124, a selector 3125, and a CM 3126. The LUT block 3123 is configured to multiplex the output of the internal 16-bit CM pair according to the input inA-inD. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration stored in the CM 3126.

  The PLE 3121 is electrically connected to the power supply line for the voltage VDD through the power switch 3127. The on / off of the power switch 3127 is set by configuration data stored in the CM 3128. By providing the power switch 3127 in each PLE 3121, fine grained power gating is possible. The fine-grained power gating function allows power gating of PLE 3121 which is not used after context switching, so standby power can be effectively reduced.

  In order to implement NOFF computing, the register block 3124 is configured with non-volatile registers. The non-volatile register in PLE 3121 is a flip flop (hereinafter referred to as [OS-FF]) including an OS memory.

  The register block 3124 has an OS-FF 3140 [1] 3140 [2]. The signals user_res, load, and store are input to the OS-FFs 3140 [1] and 3140 [2]. The clock signal CLK1 is input to the OS-FF 3140 [1], and the clock signal CLK2 is input to the OS-FF 3140 [2]. FIG. 37A shows a configuration example of the OS-FF 3140.

  The OS-FF 3140 has an FF 3141 and a shadow register 3142. The FF 3141 has nodes CK, R, D, Q, and QB. The clock signal is input to the node CK. The signal user_res is input to the node R. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. The logic of the node Q and the node QB are complementary to each other.

  The shadow register 3142 functions as a backup circuit of the FF 3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes the backed up data back to the nodes Q and QB according to the signal load.

  The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143 B have the same circuit configuration as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitive element C36 and OS transistors MO35 and MO36. The memory circuit 3143B includes a capacitive element CB36, an OS transistor MOB35, and an OS transistor MOB36. Nodes N36 and NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, respectively, and are charge holding nodes, respectively. Nodes N37 and NB37 are gates of the Si transistors M37 and MB37.

  In the case of using the semiconductor device described in the above embodiment for the LAB 3120, the transistor 200 can be used as the OS transistors MO35 and MOB 35, and the capacitor 100 can be used as the capacitors C36 and CB36. Thus, the area occupied by the pair of transistor and capacitive element in top view can be reduced, so that the semiconductor device according to this embodiment can be highly integrated.

  The OS transistors MO35, MO36, MOB35, and MOB36 each have a back gate, which is electrically connected to a power supply line supplying a fixed voltage.

  An operation method example of the OS-FF 3140 will be described with reference to FIG.

(backup)
When the signal store of “H” is input to the OS-FF 3140, the shadow register 3142 backs up the data of the FF 3141. The node N36 becomes "L" by writing the data of the node Q, and the node NB36 becomes "H" by writing the data of the node QB. After that, power gating is performed to turn off the power switch 3127. Although the data of the nodes Q and QB of the FF 3141 disappears, the shadow register 3142 holds the backed up data even if the power is off.

(recovery)
The power switch 3127 is turned on to supply power to the PLE 3121. Thereafter, when the signal “load” of “H” is input to the OS-FF 3140, the shadow register 3142 writes back the data being backed up to the FF 3141. Since the node N36 is at "L", the node N37 is maintained at "L" and the node NB36 is at "H", so the node NB37 becomes "H". Therefore, the node Q becomes "H" and the node QB becomes "L". That is, the OS-FF 3140 returns to the state at the time of backup operation.

  The power consumption of the OS-FPGA 3110 can be effectively reduced by combining the fine-grained power gating and the backup / recovery operation of the OS-FF 3140.

  Errors that may occur in memory circuits include soft errors due to the incidence of radiation. A soft error is a secondary space generated by nuclear reaction between alpha rays emitted from materials that make up memories and packages, etc., and primary cosmic rays that enter the atmosphere from space with atomic nuclei of atoms present in the atmosphere. This is a phenomenon in which erroneous operation such as inversion of data held in the memory occurs when electron neutron and the like are irradiated to the transistor and electron-hole pairs are generated. An OS memory using an OS transistor is highly resistant to soft errors. Therefore, by mounting the OS memory, a highly reliable OS-FPGA 3110 can be provided.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Eighth Embodiment
In this embodiment mode, an AI system to which the semiconductor device described in the above embodiment mode is applied will be described with reference to FIG.

  FIG. 38 is a block diagram showing a configuration example of an AI system 4041. As shown in FIG. The AI system 4041 includes an operation unit 4010, a control unit 4020, and an input / output unit 4030.

  The operation unit 4010 includes an analog operation circuit 4011, a DOSRAM 4012, a NOSRAM 4013, and an FPGA 4014. As the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014, the DOSRAM 1400, the NOSRAM 1600, and the OS-FPGA 3110 described in the above embodiment can be used.

  The control unit 4020 includes a central processing unit (CPU) 4021, a graphics processing unit (GPU) 4022, a phase locked loop (PLL) 4023, a static random access memory (SRAM) 4024, and a programmable read only memory (PROM) 4025. , A memory controller 4026, a power supply circuit 4027, and a PMU (Power Management Unit) 4028.

  The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general purpose input / output module 4034, and a communication module 4035.

  The operation unit 4010 can execute learning or inference by a neural network.

  The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.

  The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog operation circuit 4011 using the OS transistor has an analog memory, and can perform the product-sum operation necessary for learning or inference with low power consumption.

  The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory for temporarily storing digital data sent from the CPU 4021. The DOSRAM 4012 has a memory cell including an OS transistor and a read out circuit unit including an Si transistor. Since the memory cell and the read out circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the entire circuit area.

  Calculations using neural networks may have more than 1000 input data. When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so the input data can not but be divided and stored. The DOSRAM 4012 can arrange memory cells in a highly integrated manner even with a limited circuit area, and has a larger storage capacity than an SRAM. Therefore, the DOS RAM 4012 can store the input data efficiently.

  The NOSRAM 4013 is a non-volatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data as compared to other non-volatile memories such as flash memory, ReRAM (Resistive Random Access Memory) and MRAM (Magnetoresistive Random Access Memory). In addition, unlike the flash memory and the ReRAM, there is no deterioration of the element when writing data, and there is no limit to the number of times data can be written.

  Further, the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. The NOSRAM 4013 can reduce the memory cell area per bit by storing multi-value data.

  In addition to digital data, the NOSRAM 4013 can store analog data. Therefore, the analog operation circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, no D / A conversion circuit or A / D conversion circuit is required. Therefore, the NOSRAM 4013 can reduce the area of peripheral circuits. In the present specification, analog data refers to data having a resolution of 3 bits (eight values) or more. The above-mentioned multi-value data may be included in the analog data.

  Data and parameters used for neural network calculations can be temporarily stored in the NOSRAM 4013. The above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021. However, the NOSRAM 4013 provided inside has higher speed and lower power consumption than the data and parameters. Can be stored. Further, since the NOSRAM 4013 can make the bit line longer than the DOS RAM 4012, the storage capacity can be increased.

  The FPGA 4014 is an FPGA using an OS transistor. The AI system 4041 uses the FPGA 4014 to perform deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), self-coder, deep Boltzmann machine (DBM), which will be described later in hardware. It is possible to configure connections of neural networks, such as Deep Belief Networks (DBNs). The connection of the above neural network can be implemented at higher speed by configuring it with hardware.

  The FPGA 4014 is an FPGA having an OS transistor. The OS-FPGA can have a smaller memory area than an FPGA configured with SRAM. Therefore, even if the context switching function is added, the area increase is small. The OS-FPGA can also transmit data and parameters at high speed by boosting.

  The AI system 4041 can provide the analog operation circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and low power consumption. Further, the analog arithmetic circuit 4011, the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

  Note that the arithmetic unit 4010 need not have all the DOS RAM 4012, the NOSRAM 4013, and the FPGA 4014. One or more of the DOSRAM 4012, the NOSRAM 4013, and the FPGA 4014 may be selected and provided in accordance with the problem that the AI system 4041 wants to solve.

  The AI system 4041 can perform deep neural network (DNN), convolutional neural network (CNN), recursive neural network (RNN), self-coder, deep Boltzmann machine (DBM), deep belief network ( Operations such as DBN) can be performed. The PROM 4025 can store programs for executing these operations. Also, part or all of these programs may be stored in the NOSRAM 4013.

  Many existing programs that exist as libraries are based on GPU processing. Therefore, the AI system 4041 preferably includes a GPU 4022. Among the product-sum operations used in learning and inference, the AI system 4041 can execute the product-sum operation that is rate-limiting in the operation unit 4010 and can execute the other product-sum operations in the GPU 4022. By doing so, learning and inference can be performed at high speed.

  The power supply circuit 4027 not only generates a low voltage potential for the logic circuit, but also performs potential generation for analog operation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.

  The PMU 4028 has a function of temporarily turning off the power supply of the AI system 4041.

  The CPU 4021 and the GPU 4022 preferably have OS memory as a register. By having the OS memory, the CPU 4021 and the GPU 4022 can keep data (logical value) in the OS memory even when the power supply is turned off. As a result, the AI system 4041 can save power.

  The PLL 4023 has a function of generating a clock. The AI system 4041 operates based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. The PLL 4023 having an OS memory can hold an analog potential for controlling the oscillation cycle of the clock.

  The AI system 4041 may store data in an external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. By doing so, it is possible to exchange data at high speed.

  Part or all of the circuits illustrated in the control unit 4020 can be formed over the same die as the computing unit 4010. By doing so, the AI system 4041 can perform neural network calculations at high speed and low power consumption.

  Data used for neural network calculations are often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.

  Since learning and inference using neural networks often deal with voice and video, the AI system 4041 includes a voice codec 4032 and a video codec 4033. The audio codec 4032 encodes (decodes) and decodes (decodes) audio data, and the video codec 4033 encodes and decodes video data.

  The AI system 4041 can perform learning or inference using data obtained from an external sensor. Therefore, the AI system 4041 has a general purpose input / output module 4034. The general-purpose input / output module 4034 includes, for example, Universal Serial Bus (USB), Inter-Integrated Circuit (I2C), and the like.

  The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 4035.

  The analog operation circuit 4011 may use a multi-level flash memory as an analog memory. However, the flash memory is limited in the number of rewrites. In addition, it is very difficult to form multilevel flash memory by embedding (forming the arithmetic circuit and the memory on the same die).

  In addition, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM is limited in the number of times of rewriting, and there is a problem in storage accuracy. Furthermore, since the element has two terminals, the circuit design that separates writing and reading of data becomes complicated.

  The analog operation circuit 4011 may use an MRAM as an analog memory. However, the MRAM has a low rate of change in resistance, and has problems in storage accuracy.

  In view of the above, it is preferable that the analog arithmetic circuit 4011 use the OS memory as an analog memory.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 9)
<Example of application of AI system>
In this embodiment, an application example of the AI system described in the above embodiment will be described with reference to FIG.

  FIG. 39A shows an AI system 4041A in which the AI systems 4041 described with reference to FIG. 38 are arranged in parallel to enable transmission and reception of signals between the systems via a bus line.

  An AI system 4041A illustrated in FIG. 39A includes a plurality of AI systems 4041_1 to AI systems 4041 — n (n is a natural number). The AI systems 4041_1 to AI systems 4041 — n are connected to one another via a bus line 4098.

  Also, FIG. 39B is an AI system 4041B in which the AI systems 4041 described in FIG. 38 are arranged in parallel in the same manner as FIG. 39A to enable transmission and reception of signals between systems via a network. is there.

  An AI system 4041B illustrated in FIG. 39B includes a plurality of AI systems 4041_1 to AI systems 4041 — n. The AI systems 4041_1 to AI systems 4041 — n are connected to one another via a network 4099.

  The network 4099 may be provided with a communication module for each of the AI systems 4041_1 to 4041_n to perform communication by wireless or wired communication. The communication module can communicate via the antenna. For example, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area), which is the foundation of the World Wide Web (WWW). Communication can be performed by connecting each electronic device to a computer network such as Network) or GAN (Global Area Network). When performing wireless communication, as a communication protocol or communication technology, LTE (Long Term Evolution), GSM (Global System for Mobile Communication (registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000) A communication standard such as W-CDMA (registered trademark) or a specification standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark) can be used.

  With the configurations shown in FIGS. 39A and 39B, analog signals obtained by an external sensor or the like can be processed by different AI systems. For example, as in biological information, information such as brain waves, pulse, blood pressure, and body temperature may be acquired by various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors, and analog signals may be processed by separate AI systems. it can. By processing or learning signals in each of the separate AI systems, it is possible to reduce the amount of information processing per AI system. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be enhanced. From information obtained by each AI system, it can be expected that changes in complexly changing biological information can be grasped in an integrated manner in an instant.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Tenth Embodiment
This embodiment shows an example of an IC in which the AI system described in the above embodiment is incorporated.

  The AI system described in the above embodiment integrates a digital processing circuit consisting of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, an OS memory such as an OS-FPGA and DOSRAM, NOSRAM, etc. into one die. be able to.

  FIG. 40 shows an example of an IC incorporating an AI system. The AI system IC 7000 shown in FIG. 40 has a lead 7001 and a circuit portion 7003. In the circuit portion 7003, the various circuits described in the above embodiment are provided in one die. The circuit portion 7003 has a stacked structure, as shown in FIG. 10 in the above embodiment, and is roughly classified into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the AI system IC 7000 can be easily miniaturized.

  In FIG. 40, the QFP (Quad Flat Package) is applied to the package of the AI system IC 7000, but the aspect of the package is not limited to this.

  A digital processing circuit such as a CPU, an analog operation circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM or NOSRAM may be formed in the Si transistor layer 7031, the wiring layer 7032 and the OS transistor layer 7033 it can. That is, the elements constituting the above AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment does not need to increase the manufacturing process even if the number of elements is increased, and the above-mentioned AI system can be incorporated at low cost.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 11)
<Electronic equipment>
The semiconductor device according to one embodiment of the present invention can be used for various electronic devices. FIG. 41 illustrates a specific example of an electronic device using the semiconductor device according to one embodiment of the present invention.

  FIG. 41A is an external view showing an example of a car. The automobile 2980 has a car body 2981, wheels 2982, a dashboard 2983, lights 2984 and the like. In addition, the automobile 2980 includes an antenna, a battery, and the like.

  An information terminal 2910 illustrated in FIG. 41B includes a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like in a housing 2911. The display portion 2912 includes a display panel and a touch screen in which a flexible substrate is used. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book reader, or the like.

  A laptop personal computer 2920 illustrated in FIG. 41C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. In addition, the notebook personal computer 2920 includes an antenna, a battery, and the like inside a housing 2921.

  A video camera 2940 illustrated in FIG. 41D includes a housing 2941, a housing 2942, a display portion 2943, an operation switch 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display portion 2943 is provided in the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside a housing 2941. The housing 2941 and the housing 2942 are connected by the connection portion 2946, and the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the direction of the image displayed on the display portion 2943 can be changed and the display / non-display of the image can be switched.

  FIG. 41E shows an example of a bangle type information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. The display portion 2952 is provided with a display panel using a flexible substrate, so that the information terminal 2950 which is flexible, lightweight, and easy to use can be provided.

  FIG. 41F shows an example of a watch-type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, electronic mail, text browsing and creation, music reproduction, Internet communication, computer games, and the like.

  The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. In addition, the display portion 2962 is provided with a touch sensor, and can be operated by touching the screen with a finger, a stylus, or the like. For example, by touching an icon 2967 displayed on the display portion 2962, an application can be activated. The operation switch 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution / cancellation, power saving mode execution / cancellation, etc. besides time setting. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

  In addition, the information terminal 2960 can perform near-field wireless communication according to the communication standard. For example, it is possible to make a hands-free call by intercommunicating with a wireless communicable headset. In addition, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with another information terminal via a connector. In addition, charging can be performed through the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

  For example, a memory device using the semiconductor device of one embodiment of the present invention can hold control information of the electronic device described above, a control program, and the like for a long time. By using the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  This embodiment can be implemented in appropriate combination with the structures described in the other embodiments, examples, and the like.

In this example, a sample 200A having a structure similar to that of the transistor 200 described in the above embodiment is manufactured, and a result of comparison between an actual measurement value of -∂V _th / ∂V _BG and a prediction value is described. The sample 200A according to this example has the same structure as the transistor 200 shown in FIG. 3 in the above embodiment.

  As shown in FIG. 42A, the sample 200A is disposed so as to be embedded in the insulator 214 and the insulator 216 disposed on a substrate (not shown) and the insulator 214 and the insulator 216. A conductor 205 (a conductor 205a and a conductor 205b), an insulator 220 disposed on the insulator 216 and the conductor 205, an insulator 222 disposed on the insulator 220, and an insulator 222 An insulator 230 disposed on the upper surface, an oxide 230 (an oxide 230a, an oxide 230b, and an oxide 230c) disposed on the insulator 224, and an insulator disposed on the oxide 230 250, an insulator 252 disposed on the insulator 250, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 252, and An insulator 270, an insulator 271 disposed on the insulator 270, an insulator 272 disposed in contact with at least the insulator 250 and a side surface of the conductor 260, an oxide 230, and an insulator 272 And an insulator 274 disposed in contact with each other.

  The insulator 214 is aluminum oxide having a thickness of 40 nm which is deposited by RF sputtering. The insulator 216 is a silicon oxynitride film deposited using a PECVD method. The conductor 205a is tantalum nitride having a thickness of 40 nm which is deposited by sputtering. The conductor 205 b is titanium nitride having a film thickness of 5 nm formed using the ALD method, and tungsten formed on the titanium nitride using the metal CVD method.

  The insulator 220 is a 10-nm-thick silicon oxynitride film deposited using a PECVD method. The insulator 222 is hafnium oxide with a film thickness of 20 nm formed by using the ALD method. The insulator 224 is a 30-nm-thick silicon oxynitride film deposited using a PECVD method.

  The oxide 230 a is an In—Ga—Zn oxide which is deposited to a thickness of 5 nm by DC sputtering. Note that an In: Ga: Zn = 1: 3: 4 [atomic number ratio] target is used for film formation of the oxide 230 a, and 45 sccm of oxygen gas is used as a film formation gas, and the film formation pressure is 0.7 Pa (Canon The film forming power was 500 W, the substrate temperature was 200 ° C., and the target-substrate distance was 60 mm.

  The oxide 230 b is a 15 nm thick In—Ga—Zn oxide film-formed using a DC sputtering method. Note that an In: Ga: Zn = 4: 2: 4.1 atomic number ratio target is used for film formation of the oxide 230 b, and 40 sccm of argon gas and 5 sccm of oxygen gas are used as a film formation gas, and a film formation pressure is used. Of 0.7 Pa (measured with a miniature gauge MG-2 manufactured by Canon Anelva), a deposition power of 500 W, a substrate temperature of 130 ° C., and a target-substrate distance of 60 mm.

  The oxide 230 c is an In—Ga—Zn oxide which is deposited to a thickness of 5 nm by DC sputtering. The oxide 230c was formed under the same conditions as the oxide 230a.

  The insulator 250 is silicon oxynitride having a film thickness of 10 nm which is deposited using a PECVD method. The insulator 214 is aluminum oxide having a thickness of 5 nm which is deposited by RF sputtering.

  The conductor 260a is titanium nitride having a film thickness of 10 nm formed by sputtering. The conductor 260 b is tungsten having a film thickness of 30 nm formed by sputtering.

  The insulator 270 is aluminum oxide with a film thickness of 7 nm formed using the ALD method. The insulator 271 is a silicon oxynitride film deposited using a PECVD method. The insulator 272 is a 5-nm-thick aluminum oxide film formed using an ALD method. The insulator 274 is a silicon oxynitride film with a thickness of 20 nm formed by PECVD.

In the sample 200A having the above-described configuration, the electrical characteristics were measured when the voltage V _BG was 0 V, −3 V, and −6 V, and the voltage V _th was calculated. Measurements of the electrical properties of the sample 200A are a drain voltage _{V d} and + 3.3V, was performed while sweeping every 0.1V top gate voltage _{V g} from -3.3V to + 3.3V. In the calculation of the voltage V _th , the slope on the V _g- I _d curve is plotted with the top gate voltage V _g [V] on the horizontal axis and the logarithm of the drain current I _d [A] on the vertical axis. The top gate voltage V _g was taken as the intersection of the tangent at the maximum point and the straight line of I _d = 1.0 × 10 ⁻¹² [A].

FIG. 42B shows the measurement results of the voltage V _th with respect to the voltage V _BG of the sample 200A. In the graph shown in FIG. 42B, the vertical axis represents shift amount [V] of voltage V _th , and the horizontal axis represents voltage V _BG [V]. However, the horizontal axis is reversed in positive and negative directions. Note that the shift amount of the voltage _{V th,} when the voltage _{V th} when the _V BG = 0V and _0V, which is the difference between the voltage _{V th} when the V BG = -3 V, and -6 V.

As shown in FIG. 42 (B), the plot of the voltage V _th of the sample 200A is approximated by a straight line having a constant slope of 0.26. Therefore, in the sample 200A, the actual measurement value of −∂V _th / ∂V _BG was 0.26. This satisfies Equations (8) and (9) described above. From this, it is shown that the controllability of the voltage V _th by the voltage V _BG is good in the configuration of the sample 200A according to the present example.

Next, from the model of the sample 200A shown in FIG. 43, the predicted value of −∂V _th / ∂V _BG was calculated using Expression (17). FIG. 43 is a schematic view showing a model between the top gate and the bottom gate of the sample 200A.

As shown in FIG. 43, in the sample 200A, a region P is formed at the interface between the oxide 230b and the oxide 230c. Therefore, from EOT _B between the conductor 205 and the region P and EOT _T between the conductor 260 and the region P, a predicted value of − 予 測 V _th / ∂V _BG can be obtained.

EOT _B can be calculated from the film thickness and relative permittivity of the insulator 220, the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b. Further, EOT _T is oxide 230c, can be calculated from the thickness and dielectric constant of the insulator 250, and the insulator 252.

  The relative dielectric constants of the structures shown in FIG. 43 are the dielectric constant of silicon oxynitride used for the insulator 220, the insulator 224, and the insulator 250 is 4.1, and the hafnium oxide used for the insulator 222 is 16.4. The In-Ga-Zn oxide used for the oxide 230a, the oxide 230b, and the oxide 230c is 15, and the aluminum oxide used for the insulator 252 is 8.3.

From the above, EOT _B was 50.5 nm and EOT _T was 13.8 nm. In the present embodiment, EOT _B and EOT _T is converted to a silicon oxynitride equivalent electrical thickness. The values of these EOT _B and EOT _T, when used in equation (17), the predicted value of -∂V _th / ∂V _BG became 0.27. Thus, in the sample 200A, the predicted value and the measured value of -∂V _th / ∂V _BG were in good agreement.

Therefore, the configuration of the sample 200A according to this embodiment has good controllability of the voltage _{V th} by voltage _{V BG,} it has been shown to be predictive of actual measurement values of -∂V _th / ∂V _BG The

10 Transistor 21 Conductor 22 Insulator 23 Oxide 23a Oxide 23b Oxide 23c Oxide 24 Insulator 25 Insulator 26 Conductor 100 Capacitive Element 100a Capacitive Element 100a Capacitive Element 100b Capacitive Element 110 Conductor 112 Conductor 120 Conductor 130 Insulator 150 insulator 200 transistor 200a transistor 200A sample 200b transistor 203 conductor 203a conductor 203b conductor 205 conductor 205a conductor 205b conductor 205b conductor film 207 conductor 207a conductor 207b conductor 210 insulator 212 insulator 214 insulator 216 insulator 218 conductor 220 insulator 222 insulator 224 insulator 224A insulator 230 oxide 230a oxide 230A oxide film 230b oxide 230B oxide film 230c oxide 230C oxide film 231 Region 231a Region 231b Region 232 Region 232a Region 232b Region 234 Region 240 Conductor 240a Conductor 240b Conductor 240c Conductor 240d Conductor 246 Conductor 250 Conductor 250 Insulator 250A Insulating Film 252 Insulating 252A Insulating Film 256 Conducting Body 260 conductor 260a conductor 260A conductive film 260b conductor 260B conductive film 270 insulator 270A insulating film 271 insulator 271A insulating film 272 insulator 272A insulating film 273 insulator 274 insulator 280 insulator 282 insulator 286 insulator 300 Transistor 311 substrate 313 semiconductor region 314 a low resistance region 314 b low resistance region 315 insulator 316 conductor 320 insulator 322 insulator 324 insulator 326 insulator 328 conductor 330 conductor 350 insulator 3 52 insulator 354 insulator 356 conductor 360 insulator 362 insulator 364 insulator 366 conductor 370 insulator 372 insulator 376 insulator 376 conductor 382 insulator 384 insulator 386 conductor 400 transistor 403 conductor 403a conductor 403b conductor 405 conductor 405a conductor 405b conductor 430c oxide 431a oxide 431b oxide 432a oxide 432b oxide 450 insulator 452 insulator 460 conductor 460a conductor 460b conductor 470 insulator 472 insulation Body 600 cell 600 a cell 600 b cell 610 circuit 620 circuit 650 a memory cell 650 b memory cell 1001 wiring 1002 wiring 1003 wiring 1003 wiring 1005 wiring 1005 wiring 1007 wiring 1008 wiring 1009 wiring 010 wiring 1400 DOSRAM
1405 controller 1410 row circuit 1411 decoder 1412 word line driver circuit 1413 column selector 1414 sense amplifier driver circuit 1415 column circuit 1416 global sense amplifier array 1417 input / output circuit 1420 MC-SA array 1422 memory cell array 1423 sense amplifier array 1425 local memory cell array 1426 local Sense amplifier array 1444 Switch array 1445 Memory cell 1446 Sense amplifier 1447 Global sense amplifier 1600 NOSRAM
1610 memory cell array 1611 memory cell 1612 memory cell 1613 memory cell 1614 memory cell 1615 memory cell 1615 a memory cell 1615 b memory cell 1640 controller 1650 row driver 1651 row decoder 1652 word line driver 1660 column driver 1661 column decoder 1661 driver 1663 DAC
1670 output driver 1671 selector 1672 ADC
1673 Output buffer 2000 CDMA
2910 information terminal 2911 housing 2912 display portion 2913 camera 2914 speaker portion 2915 operation switch 2916 external connection portion 2917 microphone 2920 laptop personal computer 2921 housing 2922 display portion 2923 keyboard 2924 pointing device 2940 video camera 2941 housing 2942 housing 2942 display Section 2944 Operation switch 2945 Lens 2946 Connection section 2950 Information terminal 2951 Display section 2960 Information terminal 2961 Display section 2961 Display section 2963 Band 2964 Buckle 2965 Operation switch 2966 Input and output terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3110 OS-FPGA
3111 controller 3112 word driver 3113 data driver 3115 programmable area 3117 IOB
3119 core 3120 LAB
3121 PLE
3123 block 3124 register block 3125 selector 3126 CM
3127 power switch 3128 CM
3130 SAB
3131 SB
3133 PRS
3135 CM
3137 memory circuit 3137 B memory circuit 3140 OS-FF
3141 FF
3142 shadow register 3143 memory circuit 3143 B memory circuit 3188 inverter circuit 3189 inverter circuit 4010 arithmetic unit 4011 analog arithmetic circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 control unit 4021 CPU
4022 GPU
4023 PLL
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 I / O unit 4031 external storage control circuit 4032 audio codec 4033 video codec 4034 general purpose input / output module 4035 communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 bus line 4099 network 7000 AI system IC
7001 lead 7003 circuit portion 7031 Si transistor layer 7032 wiring layer 7033 OS transistor layer

Claims (9)

A semiconductor device having a transistor,
The transistor is
A first conductor,
A first insulator disposed on the first conductor;
An oxide disposed on the first insulator so as to overlap the first conductor;
A second insulator disposed over the oxide;
And a second conductor disposed on the second insulator so as to overlap the first conductor and the oxide,
When a voltage greater than the voltage V _th is applied to the second conductor in a state where the voltage V _BG is applied to the first conductor, a channel is formed in the oxide,
The voltage V _th and the voltage V _BG satisfy the following equation (1):

A semiconductor device characterized by In claim 1,
Furthermore, the voltage V _th and the voltage V _BG satisfy the following equation (2):

A semiconductor device characterized by In claim 1 or claim 2,
A combined capacitance C _B of the first insulator and the oxide, the capacitor C _T of the first insulator, satisfies the equation (3) below,

A semiconductor device characterized by In claim 1 or claim 2,
The oxide is a laminated structure of a first oxide, a second oxide on the first oxide, and a third oxide on the second oxide,
The energy at the bottom of the conduction band of the first oxide and the third oxide is greater than the energy at the bottom of the conduction band of the second oxide,
Said first insulator, said first oxide, and a combined capacitance C _B of the second oxide, the combined capacitance C _T of the third oxide and said first insulator, the following Satisfy equation (4),

A semiconductor device characterized by In any one of claims 1 to 4,
The oxide is
A channel formation region in a region overlapping with the second conductor;
In a region not overlapping the second conductor, a source region and a drain region are provided across the channel formation region,
A semiconductor device characterized by A semiconductor device having a first transistor and a second transistor, the semiconductor device comprising:
The first transistor is
A first conductor,
A first insulator disposed on the first conductor;
A first oxide disposed on the first insulator so as to overlap the first conductor;
A second oxide disposed on the first oxide so as to overlap the first conductor;
A third oxide disposed on the second oxide so as to overlap the first conductor;
A second insulator disposed on the third oxide;
A second conductive material disposed on the second insulator so as to overlap the first conductor, the first oxide, the second oxide, and the third oxide. Have a body,
The energy at the bottom of the conduction band of the first oxide and the third oxide is greater than the energy at the bottom of the conduction band of the second oxide,
When a voltage greater than the voltage V _th is applied to the second conductor in a state where the voltage V _BG is applied to the first conductor, a channel is formed in the second oxide,
The voltage V _th and the voltage V _BG satisfy the following equation (5):

The second transistor is
A fourth oxide formed of the same material as the third oxide,
One of the source and the drain of the second transistor and the gate of the second transistor are electrically connected to the first conductor.
A semiconductor device characterized by In claim 6,
Furthermore, the voltage V _th and the voltage V _BG satisfy the following equation (6):

A semiconductor device characterized by In claim 6 or claim 7,
Said first insulator, said first oxide, and a combined capacitance C _B of the second oxide, the combined capacitance C _T of the third oxide and said first insulator, the following Satisfy equation (7),

A semiconductor device characterized by In any one of claims 6 to 8,
The second oxide is
A channel formation region in a region overlapping with the second conductor;
In a region not overlapping the second conductor, a source region and a drain region are provided across the channel formation region,
A semiconductor device characterized by