JP2003023161A - Semiconductor device and method for manufacturing the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving the characteristics of a TFT, and realizing the structure of the TFT optimal for the driving conditions of a pixel section and a driving circuit by using a small number of photomasks. SOLUTION: This semiconductor integrated device is provided with a semiconductor film, a first electrode, and a first insulating film put between the semiconductor film and the first electrode. Also, this is provided with a second electrode and a second insulating film put between the semiconductor film and the second electrode. Then, the first electrode and the second electrode are overlapped with each other with the channel formation region of the semiconductor film put between the first electrode and the second electrode, and a constant voltage is always applied to the first electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a thin film transistor (hereinafter referred to as TFT) using a semiconductor film having a crystal structure formed on a substrate and a method for manufacturing the same. Note that in this specification, a semiconductor device refers to all devices which function by utilizing semiconductor characteristics, and a semiconductor device manufactured by the present invention is a display device typified by a liquid crystal display device including a TFT.
The semiconductor integrated circuit (microprocessor, signal processing circuit, high-frequency circuit, or the like) is included in the category.

[0002]

2. Description of the Related Art In various semiconductor devices including semiconductor elements such as a television receiver, a personal computer, and a mobile phone, a display for displaying characters and images becomes an indispensable means for humans to recognize information. ing. Particularly in recent years, a flat panel display (flat panel display) represented by a liquid crystal display device utilizing the electro-optical characteristics of liquid crystal has been actively used.

As one form of a flat panel display, an active matrix drive system is known in which a TFT is provided for each pixel and a data signal is sequentially written to display an image. The TFT is an essential element for realizing the active matrix driving method.

Most of TFTs are manufactured by using amorphous silicon, but the field effect mobility is low,
Since it was impossible to operate at a frequency necessary for processing a video signal, it was used exclusively as a switching element provided for each pixel. The data line side driving circuit that outputs a video signal to the data line and the scanning line side driving circuit that outputs a scanning signal to the scanning line are TAB (Tape Automa
It was covered by an external IC (driver IC) mounted by ted bonding) or COG (Chip on Glass).

However, since the pixel pitch becomes narrower as the pixel density increases, it is considered that the method of mounting the driver IC has a limit. For example, in the case of UXGA (1200 × 1600 pixels), the RGB color system requires 6000 connection terminals even if simply estimated. An increase in the number of connecting terminals causes an increase in the probability of contact failure. In addition, the area (frame area) in the peripheral portion of the pixel portion is increased, which becomes a factor of impairing the miniaturization and external design of a semiconductor device using this as a display. From this background, the need for a display device integrated with a drive circuit has become clear. By integrally forming the pixel portion and the scanning line side and data line side driving circuits on the same substrate, the number of connection terminals can be drastically reduced and the area of the frame region can be reduced.

As a means for realizing this, a method of forming a TFT with a polycrystalline silicon film has been proposed. However, even if a TFT is formed by using polycrystalline silicon, the electrical characteristics of the TFT will be limited to the MO formed on the single crystal silicon substrate.
It was not comparable to the characteristics of the S-transistor. For example, the field effect mobility is 1/10 or less that of single crystal silicon. In addition, there is a problem that off-state current becomes high due to defects formed at crystal grain boundaries.

Nevertheless, the data line side driving circuit is required to have high driving ability (ON current, I _on ), and to prevent deterioration due to the hot carrier effect to improve reliability, while the pixel section has low OFF current ( I _off ) is required.

As a TFT structure for reducing the off current value, a lightly doped drain (LDD) is used.
n) The structure is known. In this structure, an LDD region added with an impurity element at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. Further, as an effective structure for preventing the deterioration of the on-current value due to hot carriers, an LD in which a part of the LDD region overlaps the gate electrode
The D structure (hereinafter, Gate-drain Overlapped LDD is abbreviated as GOLD) is known.

[0009]

A TFT is manufactured by laminating a semiconductor film, an insulating film, or a conductive film while etching into a predetermined shape using a photomask. However, if the structure of the TFT is optimized in order to obtain the characteristics required for the pixel portion and each drive circuit, the number of photomasks increases, the manufacturing process becomes complicated, and the number of processes inevitably increases.

Another object of the present invention is to provide a technique for improving the characteristics of the TFT and realizing a TFT having a structure optimal for the driving conditions of the pixel portion and the driving circuit with a small number of photomasks.

[0011]

In order to solve the above problems, a thin film transistor included in a semiconductor device of the present invention is sandwiched between a semiconductor film, a first electrode, and the semiconductor film and the first electrode. And a first insulating film,
It has a second electrode and a second insulating film sandwiched between the semiconductor film and the second electrode. And the first electrode and the second
The electrodes of are overlapped with each other with the channel formation region of the semiconductor film interposed therebetween.

In the present invention, the reduction of the off-current is more important than the increase of the on-current. For example, in the case of a TFT formed as a switching element in the pixel portion of a semiconductor device, the first electrode is always constant. Apply voltage (common voltage). The constant voltage is smaller than the threshold in the case of the n-channel TFT and larger than the threshold in the case of the p-channel TFT.

By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold value and to suppress the off-current as compared with the case where the number of electrodes is one.

In the present invention, the increase of the on-current is more important than the reduction of the off-current. For example, in the case of a TFT included in a buffer of a drive circuit of a semiconductor device, the first electrode and the second electrode are Apply the same voltage.

In this specification, the drive circuit is a circuit for generating a signal for displaying an image in the pixel portion, and includes a data line drive circuit and a scanning line drive circuit.

By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the thickness of the semiconductor film is made thin, so that the subthreshold coefficient (S value) is increased. ) Can be reduced, and the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Also,
Since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved. In addition, interface scattering can be suppressed and transconductance (gm) can be increased.

A circuit diagram of the thin film transistor of the present invention will be described with reference to FIG. Here, only the p-channel TFT is shown as a representative. In the case of the n-channel TFT, the arrow direction is opposite to that in the case of the p-channel TFT. FIG. 31A is a circuit diagram of a general thin film transistor having only one electrode. FIG. 31B is a circuit diagram of a thin film transistor of the invention which has two electrodes sandwiching a semiconductor film and a constant voltage (here, a ground voltage) is applied to one electrode. is there. Figure 3
1 (C) has two electrodes sandwiching a semiconductor film,
Furthermore, the two electrodes are electrically connected to each other,
It is a circuit diagram of a thin film transistor of the present invention. In the following description of the present invention, the circuit diagram shown in FIG. 31 is used.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. In FIG. 1A, a first electrode 11 is formed on a substrate 10 having an insulating surface.
The first electrode 11 may be made of a conductive material. Typically, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta),
It can be formed of an alloy or compound composed of one or more selected from titanium (Ti). Alternatively, a stack of several conductive films may be used as the first electrode. The first electrode 11 has a thickness of 150 to 400 nm.

A first insulating film 12 is formed so as to cover the first electrode 11. Note that in this embodiment mode, two layers of insulating films (a first insulating film A 12a and a first insulating film B 12) are used.
A laminate of b) is used as the first insulating film 12. In FIG. 1, the first insulating film A 12a is formed of a silicon oxynitride film or a silicon nitride film with a thickness of 10 to 50 nm. The first insulating film B 12b is a silicon oxynitride film or a silicon oxide film and is formed to a thickness of 0.5 to 1 μm. When a silicon oxynitride film is used, a film formed by a plasma CVD method from a mixed gas of SiH ₄ , NH ₃ , and N ₂ O and containing 20 to 40 atomic% of nitrogen is used. By using a nitrogen-containing insulating film such as a silicon oxynitride film or a silicon nitride film, diffusion of impurities such as alkali metal from the substrate 10 side can be prevented.

The surface of the first insulating film 12 may have irregularities due to the first electrode 11 previously formed. The unevenness is flattened by polishing the surface.
Chemical-mechanical polishing (Chemical-Mecha
nical Polishing: hereinafter referred to as CMP). As the CMP polishing agent (slurry) for the first insulating film 12, for example, fumed silica particles obtained by thermally decomposing silicon chloride gas are dispersed in a KOH-added aqueous solution. The first insulating film is removed by CMP to the extent of 0.1 to 0.5 μm to planarize the surface.
Note that the surface of the first insulating film does not necessarily need to be polished. The level difference of the unevenness on the surface of the planarized first insulating film is preferably 5 nm or less, and more preferably 1 nm or less. The improved flatness makes it possible to reduce the thickness of the first insulating film used as a gate insulating film to be formed later.
The mobility of can be improved. Further, since the flatness is improved, off current can be reduced when a TFT is manufactured.

A semiconductor film 13 is formed on the first insulating film 12 whose surface is flattened. The semiconductor film 13 has a channel forming region 18 and an impurity region 19 sandwiching the channel forming region 18. Then, the semiconductor film 1
A second insulating film 14 is formed on the semiconductor film 3, and the second electrode 1 is formed on the semiconductor film 13 with the second insulating film 14 interposed therebetween.
5 is formed.

The first electrode 11 and the second electrode 15 overlap each other with the channel forming region 18 interposed therebetween.

In addition, the third insulating film 16 and the wiring 17 are provided as needed.

The first electrode 11 and the second electrode 15 may be electrically connected, or a common voltage may be applied to either one of the electrodes.

In FIG. 1A, AA 'when the first electrode 11 and the second electrode 15 are directly connected.
A cross-sectional view of is shown in FIG.

As shown in FIG. 1B, the first electrode 11
The second electrode 15 and the second electrode 15 are connected to each other outside the semiconductor film 13 via a contact hole 21 formed in the first insulating film 12b and the second insulating film 14.

In FIG. 1A, the first electrode 11 and the second electrode 11
1C is a cross-sectional view taken along the line AA ′ in the case where the electrode 15 is connected by a wiring 24 formed of the same conductive film as the wiring 17.

As shown in FIG. 1C, the first electrode 11
And the wiring 24 are the first insulating film 12b and the second insulating film 1
4 and the third insulating film 16 through the contact holes 23 formed. Further, the second electrode 15 and the wiring 24 are connected via the contact hole 22 formed in the third insulating film 16.

The method of electrically connecting the first electrode 11 and the second electrode 15 is not limited to the configuration shown in FIGS. 1 (B) and 1 (C).

The film thickness to be removed by CMP is determined in consideration of the thickness of the first insulating film 12, its dielectric constant and the thickness of the second insulating film 14. The film remaining here substantially functions as a gate insulating film. Therefore, when the first insulating film is formed by laminating a plurality of insulating films, the first electrode 11
Only the uppermost insulating film may be polished above, or the lower insulating film may be exposed.

For example, the first insulating film A 12a and the first insulating film A 12a
The insulating film B 12b is formed of a silicon oxynitride film and has a dielectric constant of 7.5, and when the second insulating film 14 is formed of a silicon oxide film, the dielectric constant is 3.9, which is different. In that case, the finished dimensions after CMP are preferably such that the thickness of the first insulating film 12 is 150 nm and the thickness of the second insulating film 14 is 110 nm.

By applying the common voltage to the first electrode, it is possible to suppress the variation in threshold value and to suppress the off-current as compared with the case where there is one electrode.

The TFT is a top gate type (planar type) depending on the arrangement of the semiconductor film, the gate insulating film and the gate electrode.
And bottom gate type (inverted stagger type) are known.
In any case, it is necessary to reduce the thickness of the semiconductor film in order to reduce the subthreshold coefficient. When a semiconductor film obtained by crystallizing an amorphous semiconductor film is used as in a TFT, the amorphous semiconductor film becomes thin and its crystallinity deteriorates, and the effect of purely reducing the film thickness is obtained. I can't. However, the thickness of the semiconductor film is substantially reduced by electrically connecting the first electrode and the second electrode and overlapping the two electrodes above and below the semiconductor film as shown in FIG. Similarly to the above, it is possible to deplete quickly with the application of voltage, reduce the field effect mobility and the subthreshold coefficient, and increase the on-current.

When the first electrode 11 and the second electrode 15 are electrically connected, the closer the dielectric constants of the first insulating film 12 and the second insulating film 14 are, the closer the electric field is. The on-current can be increased by decreasing the effect mobility and the subthreshold coefficient.

Further, in the portion where the first electrode 11 and the channel forming region overlap, the film thickness of the first insulating film 12 when the film is uniform, the second electrode 15 and the channel. In the portion where the formation area overlaps, the second
When the thickness of the insulating film 14 is uniform, the closer it is, the smaller the field effect mobility and the subthreshold coefficient and the larger the on-current.
If the film thickness of the first insulating film in the portion overlapping the first electrode 11 is d1 and the film thickness of the second insulating film in the portion overlapping the second electrode 15 is d2, | d1-d2 | / d1 ≦
0.1, and | d1-d2 | / d2 ≦ 0.
It is desirable to satisfy 1. More preferably, | d1-d
2 | /d1≦0.05, and | d1-d2
It is preferable to satisfy | /d2≦0.05.

Most preferably, the first electrode 11 and the second electrode
Of the thin film transistor when the ground voltage is applied to the first electrode 11 and the thin film transistor when the ground voltage is applied to the second electrode 15 in a state where the ground voltage is not electrically connected to the first electrode 11. That is, the first electrode 11 and the second electrode 15 are electrically connected after the thresholds are set to be approximately the same. By doing so, the field effect mobility and the subthreshold coefficient can be further reduced, and the on-current can be further increased.

With such a structure, channels (dual channels) can be formed above and below the semiconductor film,
The characteristics of the TFT can be improved.

Further, wiring for transmitting various signals or electric power can be formed simultaneously with the first electrode 11. Also,
When combined with the planarization treatment by CMP, it does not affect the semiconductor film or the like formed thereover.
In addition, the wiring density can be increased by the multilayer wiring. Hereinafter, a specific example applied to a display device driven by an active matrix will be described by way of examples.

[0039]

EXAMPLE 1 A process for manufacturing a semiconductor device of the present invention will be described. Here, the pixel portion on the same substrate,
A method of simultaneously manufacturing TFTs (n-channel TFTs and p-channel TFTs) of a driver circuit provided near the pixel portion will be described in detail. In this embodiment, the common voltage is applied to the first electrode of all the TFTs formed in the pixel portion, and the first electrode and the second electrode are connected to the TFT formed in the driving circuit. An example is shown. 2 to 6 used in this embodiment are cross-sectional views illustrating the manufacturing process thereof, and FIGS. 7 to 9 are top views corresponding to the manufacturing processes, and the same reference numerals are used for convenience of description.

In FIG. 2A, the substrate 101 can be made of any material as long as it has an insulating surface and can withstand a processing temperature in a later step. Typically, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

A first wiring 102 and first electrodes 103 to 107 are formed on the insulating surface of the substrate 101. The first wiring and the first electrode are formed of a conductive material including one kind or a plurality of kinds selected from Al, W, Mo, Ti, and Ta. Although W is used in this embodiment, a stack of W on TaN may be used as the first wiring and the first electrode.

FIG. 7 (A) shows a top view of the pixel portion in FIG. 2 (A). First electrodes 105, 106, 1
Reference numeral 07 is a part of the common wiring 180.

First wiring 102 and first electrodes 103 to 1
After forming 07, the first insulating film 110 is formed. In this embodiment, the first insulating film 110 is composed of two insulating films (first insulating film A 110a and first insulating film B 110b).
Are formed by stacking. First insulating film A 1
10a is a silicon oxynitride film and is formed to a thickness of 10 to 50 nm. The first insulating film B 110b is formed using a silicon oxide film or a silicon oxynitride film with a thickness of 0.5 to 1 μm.

The surface of the first insulating film 110 may have unevenness due to the first wiring and the first electrode formed previously. Preferably, it is desirable to flatten these irregularities. CMP is used as a flattening method. CMP polishing agent (slurry) for the first insulating film 110
For example, fumed silica particles obtained by thermally decomposing silicon chloride gas may be dispersed in a KOH-added aqueous solution. The first insulating film is made 0.1 by CMP.
The surface is flattened by removing about 0.5 μm.

Thus, the flattened first insulating film 112 is formed as shown in FIG. 2B, and the semiconductor layer is formed thereon. The semiconductor layer 113 is formed using a semiconductor having a crystal structure. This is obtained by crystallizing the amorphous semiconductor layer formed over the first insulating film 112. After the amorphous semiconductor layer is deposited, it is crystallized by heat treatment or irradiation with laser light. The material of the amorphous semiconductor layer is not limited, but is preferably silicon or silicon germanium (Si _x G
e _1-x ; 0 <x <1, typically x = 0.001
0.05) It is formed of an alloy or the like.

After that, the semiconductor layer 113 is divided into islands by etching, and the semiconductor film 11 is formed as shown in FIG.
4 to 117 are formed.

FIG. 7B shows a top view of FIG. 2C. The first electrodes 105 and 106 are the semiconductor film 11
6 and the first insulating film 112 are interposed therebetween. In addition, the first electrode 107 overlaps with the semiconductor film 116 and the first insulating film 112 therebetween. The semiconductor film 18
Reference numeral 1 denotes a semiconductor film for forming a capacitor, which is overlapped with the first electrode 107 and the first insulating film 112 sandwiched therebetween.

Next, as shown in FIG. 3A, a second insulating film 118 is formed to cover the semiconductor films 114 to 117 and 181. The second insulating film 118 is formed of an insulator containing silicon by a plasma CVD method or a sputtering method. Its thickness is 40 to 150 nm.

A conductive film is formed over the second insulating film 118 to form a second gate electrode and a second wiring. In the present invention, the second gate electrode is formed by stacking two or more conductive films. The first conductive film 119 formed over the second insulating film 118 is formed of a nitride of a refractory metal such as molybdenum or tungsten, and the second conductive film 120 formed thereover is formed of a refractory metal, aluminum, or the like. It is formed of a low resistance metal such as copper or polysilicon.
Specifically, as the first conductive film, W, Mo, Ta, Ti
One or more kinds of nitrides selected from the above are selected, and one or more kinds of alloys selected from W, Mo, Ta, Ti, Al, Cu, or n-type polycrystalline silicon is used as the second conductive film. For example, the first conductive film 119 may be formed of TaN and the second conductive film 120 may be formed of W. In addition, when the second gate electrode and the second wiring are formed of a three-layer conductive film, the first layer may be Mo, the second layer may be Al, and the third layer may be TiN. Further, the first layer may be W, the second layer may be Al, and the third layer may be TiN. By forming the wiring in multiple layers, the thickness of the wiring itself is increased, so that the wiring resistance can be suppressed.

Next, the first conductive film 119 and the second conductive film 120 are etched using the mask 190,
A second wiring and a second electrode are formed.

As shown in FIG. 3B, first etching treatment is performed to form first shape electrodes 121 to 125 having tapered ends (first conductive films 121a to 121a).
25a and the second conductive films 121b to 125b). The second insulating film 118 is formed of the first shape electrodes 121 to 125.
In the portion not covered with, the surface is thinned by etching by about 20 to 50 nm. Here, in order to distinguish between before etching and after etching, the second insulating film 130 is shown after etching.

The first doping process is performed by an ion implantation method or an ion doping method in which ions are implanted without mass separation. The doping is the first shape electrodes 121 to 1
25 is used as a mask to form the first concentration one conductivity type impurity regions 126 to 129 in the semiconductor films 114 to 117. The first concentration is 1 × 10 ^{20 to} 1.5 × 10 ²¹ / cm ³ .

Next, a second etching process is performed as shown in FIG. 4A without removing the resist mask. In this etching process, the second conductive film is anisotropically etched to form second shape electrodes 131 to 135 (first conductive film 131a to 135a and second conductive film 1).
31b-135b). Second shape electrodes 131 to
The width of 135 is reduced by this etching process, and its end portion has the first concentration of one conductivity type impurity regions 126 to 129.
It is formed so as to be located inside the (second impurity region). As shown in the next step, the length of the LDD is determined by this receding width. The second shape electrodes 131 to 135 are second
Function as an electrode.

FIG. 8 (A) shows a top view of FIG. 4 (A).
The second shape electrodes 133 and 134 are a part of the gate wiring 182. The second shape electrodes 133 and 134 overlap with the semiconductor film 116, and the second shape electrode 135 overlaps with the semiconductor film 117 with the second insulating film 130 interposed therebetween.
Further, the second shape electrodes 133 and 134 and the first electrodes 105 and 106 overlap with each other with the semiconductor film 116 and the second insulating film interposed therebetween. The second shape electrode 1
A part of 35 overlaps with the semiconductor film 181 with the second insulating film 130 interposed therebetween.

Further, the second shape electrodes 131 and 132,
The first electrodes 103 and 104 are the semiconductor films 114 and 11
5 and the second insulating film 130 are sandwiched therebetween and overlap each other.

Then, in this state, impurities of one conductivity type are
2 doping treatment is performed to remove impurities of one conductivity type into a semiconductor film.
114-117. Formed by this doping process
Second conductivity type impurity region (first impurity region)
Area) 195 to 198 are the second shape electrodes 131 to 135.
Partially overlaps with the first conductive films 131a to 135a forming
Is formed in a self-aligned manner. By ion doping
The added impurities are the first conductive films 131a to 135a.
The ions that reach the semiconductor film are
The numbers decrease and inevitably result in low concentrations. Its concentration is 1 × 1
0¹⁷~ 1 x 10 ¹⁹/cm³Becomes

Next, as shown in FIG. 4B, resist masks 139 and 140 are formed and a third doping process is performed. By this third doping process, impurity regions 141 and 142 having a conductivity type opposite to the one conductivity type of the third concentration are formed in the semiconductor films 115 and 117. An impurity region of a conductivity type opposite to the third concentration of one conductivity type is formed in a region overlapping with the second shape electrodes 132 and 134, and has a concentration of 1.5 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. The impurity element is added in the concentration range of.

Through the steps up to this point, the regions to which impurities have been added for the purpose of controlling valence electrons are formed in the respective semiconductor films. First electrodes 103-107 and second shaped electrode 1
31 to 135 function as gate electrodes at positions intersecting with the semiconductor film.

After that, a step of activating the impurity element added to each semiconductor film is performed. This activation is performed using a gas heating type instant thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 400 to 700 ° C., typically 450 to 500 ° C. In addition to this, a laser annealing method using the second harmonic (532 nm) of a YAG laser can be applied. The second harmonic of the YAG laser (532 nm) is used for activation by irradiation with laser light.
Is used to irradiate the semiconductor film with this light. Of course, the same applies not only to the laser light but also to the RTA method using a lamp light source,
The semiconductor film is heated by radiation from a lamp light source from both sides or one side of the substrate.

Thereafter, as shown in FIG. 5A, a passivation film 143 made of silicon nitride is formed to a thickness of 50 to 100 nm by a plasma CVD method, and heat treatment is performed at 410 ° C. in a clean oven to perform nitriding. Hydrogen released from the silicon film hydrogenates the semiconductor film.

Next, a third insulating film 144 made of an organic insulating material is formed on the passivation film 143.
The reason for using the organic insulating material is to flatten the surface of the third insulating film 144. In order to obtain a more complete flat surface, it is desirable that this surface be flattened by the CMP method. When using the CMP method together,
Oxide film formed by plasma CVD method, SOG (Spin on Glass) or PS formed by coating method
G or the like can also be used. Note that the passivation film 143 may be regarded as part of the third insulating film 144.

The third insulating film 144 thus flattened
A transparent conductive film 145 containing indium tin oxide as a main component is formed on the surface of the film with a thickness of 60 to 120 nm. Since fine irregularities are also formed on this surface, it is desirable to polish and flatten by a CMP method using aluminum oxide as an abrasive.

FIG. 8B shows a top view of FIG. 5A.

Then, the transparent conductive film 145 is etched to form a pixel electrode (third electrode) 146. Then, the second insulating film 130, the passivation film 143,
Contact holes are formed in the third insulating film 144 and wirings 147 to 153 are formed. This wiring is formed by laminating a titanium film and an aluminum film.

The wiring 147 includes the first wiring 102 and the second wiring 102.
Is connected to the electrode 131 of the shape. Further, the first wiring 102 and the first electrode 103 are electrically connected.

The wiring 148 is connected to the impurity region 126 and the impurity region 141. The wiring 149 is connected to the impurity region 141. The wiring 150 is connected to the impurity region 128 and functions as a source wiring. The wiring 151 is connected to the impurity region 128 and the second shape electrode 135. The wiring 152 is connected to the impurity region 142. The wiring 153 is connected to the impurity region 142 and the pixel electrode 146 and functions as a power supply line.

In the above steps, assuming that the impurity region of one conductivity type is n type and the impurity region opposite to the one conductivity type is p type, a drive circuit having the n channel type TFT 202 and the p channel type TFT 203 on the same substrate. 200, a pixel portion 201 having an n-channel TFT 204 and a p-channel TFT 205 is formed.

In the drive circuit 200, an n-channel type T
In the FT 202, the pair of gate electrodes 131 and 103 overlap with each other with the channel formation region 160 interposed therebetween. The second concentration one conductivity type impurity region 195 is LDD,
The first concentration one conductivity type impurity region 126 functions as a source or drain region. In the drive circuit 200, the pair of gate electrodes 13 in the p-channel TFT 203 is used.
Reference numerals 2 and 104 are overlapped with each other with the channel formation region 161 interposed therebetween. Impurity region 1 opposite to third conductivity type
41 functions as a source or drain region. LDD
The length in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. The structure of such an LDD is mainly intended to prevent the deterioration of the TFT due to the hot carrier effect. A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like can be formed by the n-channel TFT and the p-channel TFT. In particular, the structure of the first n-channel TFT 201 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.

In the pixel portion 201, the n-channel TF
At T204, the pair of gate electrodes 133 and 105 are
The channel forming regions 162 are overlapped with each other with the channel forming region 162 interposed therebetween. In the n-channel TFT 204, the pair of gate electrodes 134 and 106 are overlapped with each other with the channel formation region 163 interposed therebetween. Second concentration one conductivity type impurity region 1
Reference numeral 96 functions as an LDD, and the first-concentration one conductivity type impurity region 128 functions as a source or drain region. The n-channel TFT 204 has a form in which two TFTs are connected in series with an impurity region of one conductivity type having a first concentration inserted. In the p-channel TFT 205, the pair of gate electrodes 135 and 107 are overlapped with each other with the channel formation region 164 interposed therebetween. The impurity region 142 opposite to the third concentration of one conductivity type functions as a source or drain region.

In this embodiment, a constant voltage (common voltage) is always applied to the common wiring to apply the common voltage to the first electrode. This constant voltage is smaller than the threshold value in the case of an n-channel TFT,
In the case of FT, it is set larger than the threshold value. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one. In the TFT formed as the switching element in the pixel portion of the semiconductor device, the reduction of the off current is more important than the increase of the on current, and thus the above configuration is useful.

Further, in this embodiment, in the TFT included in the drive circuit of the semiconductor device, the semiconductor film is inserted to form a pair of electrically connected gate electrodes, so that the thickness of the semiconductor film is substantially reduced. When the gate voltage is applied, depletion is accelerated, the field effect mobility is increased, and the subthreshold coefficient can be reduced. As a result, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. Further, the current driving capability is improved, and the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

The pixel portion 201 has a structure which can be applied to an active matrix driving type light emitting device, and FIG. 6A shows a state in which a light emitting element is formed over the third insulating film 144. A partition layer 170 that covers the n-channel TFT 204 and the p-channel TFT 205 is formed over the third insulating film 144. Wet the organic compound layer and cathode (processing such as etching with chemicals and washing with water)
Therefore, the partition layer 170 formed of a photosensitive resin material is provided over the fourth insulating film in accordance with the pixel electrode 146. The partition layer 170 is formed using an organic resin material such as polyimide, polyamide, polyimide amide, or acrylic. The partition layer 170 is formed so as to cover the end portion of the pixel electrode. In addition, the end portion of the partition layer 170 is 45
It is formed to have a taper angle of -60 degrees.

FIG. 9 shows a top view of the pixel portion in this state. The partition layer 170 is formed in a region surrounded by a dotted line in FIG.

The active matrix driving type light emitting device shown here is configured by arranging organic light emitting elements in a matrix. The organic light emitting device 174 includes an anode, a cathode, and an organic compound layer formed between them. The pixel electrode 146 becomes an anode when formed of a transparent conductive film. The organic compound layer is formed by combining a hole transporting material having a relatively high hole mobility, an electron transporting material having the opposite property, a light emitting material, and the like. They may be formed in layers or may be mixed and formed.

The organic compound material is formed as a thin film layer having a total thickness of about 100 nm. Therefore, it is necessary to improve the flatness of the surface of ITO formed as the anode. If the flatness is poor, at worst the short-circuit with the cathode formed on the organic compound layer will occur. As another means for preventing this, a method of forming an insulating film having a thickness of 1 to 5 nm can be adopted. As the insulating film, polyimide, polyimide amide, polyamide, acrylic, or the like can be used.
The counter electrode (fourth electrode) 172 can be used as a cathode by being formed using a material such as an alkali metal or an alkaline earth metal such as MgAg or LiF.

For the counter electrode 172, a material containing magnesium (Mg), lithium (Li) or calcium (Ca) having a small work function is used. Preferably MgAg
(Material in which Mg and Ag are mixed at Mg: Ag = 10: 1)
The electrode consisting of Besides, MgAgAl electrode,
Examples thereof include LiAl electrodes and LiFAl electrodes. Further, an insulating film 173 made of silicon nitride or a DLC film is formed on the upper layer thereof with a thickness of 2 to 30 nm, preferably 5 to 10 nm. The DLC film can be formed by a plasma CVD method, and even when formed at a temperature of 100 ° C. or lower, the DLC film can be formed with good coverage with covering the end portion of the partition layer 622.
The internal stress of the DLC film can be relaxed by mixing a slight amount of argon, and it can be used as a protective film. The DLC film contains oxygen and C
Since it has a high gas barrier property against O, CO ₂ , H ₂ O, etc., it is suitable as the insulating film 173 used as a barrier film.

FIG. 6 is a sectional view taken along line BB ′ of FIG.
It shows in (B). A capacitor is formed in a portion where the first electrode, the first insulating film 112, and the semiconductor film 181 overlap with each other. Further, a capacitor is formed in a portion where the second shape electrode 135, the second insulating film 130, and the semiconductor film 181 overlap with each other.

In the present embodiment, the first electrode and the second electrode are connected by the wiring formed at the same time as the source wiring, but the first electrode and the second electrode are directly connected. May be. However, in the case where the first electrode and the second electrode are connected by a wiring formed at the same time as the source wiring as in this embodiment, it is not necessary to increase the number of steps and the number of masks can be suppressed.

When the airtightness is improved by a process such as packaging, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or a circuit formed on the substrate and an external signal terminal is attached. Completed as a product.

(Embodiment 2) In this embodiment, a configuration of a pixel of a light emitting device, which is one of the semiconductor devices of the present invention, different from that of Embodiment 1 will be described.

FIG. 10 shows a top view of a pixel of the light emitting device of this embodiment. FIG. 11 shows a cross-sectional view taken along the line AA ′ in FIG.

Reference numeral 501 denotes an n-channel TFT,
2 is a p-channel TFT. n-channel type TFT5
01 includes a semiconductor film 503, a first insulating film 520, first electrodes 504 and 505, a second insulating film 521, and second electrodes 506 and 507. Then, the semiconductor film 503 has a first concentration one conductivity type impurity region 508.
And a second-concentration one conductivity type impurity region 509 and channel formation regions 510 and 511.

The first electrodes 504 and 505 and the channel forming regions 510 and 511 are respectively formed of the first insulating film 520.
They are overlapped with each other. In addition, the second electrode 506,
The channel formation regions 510 and 511 overlap with each other with the second insulating film 521 interposed therebetween.

The p-channel TFT 502 is composed of the semiconductor film 5
30, a first insulating film 520, a first electrode 532,
It has a second insulating film 521 and a second electrode 531. Then, the semiconductor film 530 has a third-concentration one-conductivity-type impurity region 533 and a channel formation region 534.

First electrode 532 and channel formation region 53
4 overlap with each other with the first insulating film 520 interposed therebetween. Second electrode 531 and channel formation region 534
Are overlapped with each other with the second insulating film 521 interposed therebetween.

Then, the first electrode 532 and the second electrode 5
31 are electrically connected to each other via a wiring 540.

In this embodiment, even in the TFT in the same pixel,
A common voltage is applied to the first electrode of the TFT (n-channel TFT 501 in this embodiment) used as a switching element. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

TF used as a switching element
In the TFT (p-channel type TFT 502 in this embodiment) which allows a current larger than T to flow, the first electrode and the second electrode are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the semiconductor film is made thinner, so that the subthreshold coefficient can be made smaller. Further, the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced.
Therefore, the integration density can be improved.

[Embodiment 3] In this embodiment, an example in which a flip-flop circuit used for a shift register of a driver circuit is formed using a TFT in which a first electrode and a second electrode are electrically connected is described. To do.

FIG. 12 shows a circuit diagram of the flip-flop circuit of this embodiment. Note that the flip-flop circuit included in the semiconductor device of the present invention is not limited to the structure shown in FIG. Further, the flip-flop circuit is given as an example of circuits included in the driver circuit, and the semiconductor device of the present invention does not necessarily have to include the flip-flop circuit. The TFT of the present invention can also be used in circuits other than flip-flops.

The flip-flop circuit shown in FIG. 12A includes clocked inverters 1201 and 1202,
It has an inverter 1203. FIG. 12B is a circuit diagram showing each circuit element of the flip-flop circuit shown in FIG. 12A more specifically.

The clocked inverter of this embodiment has p
It has two channel type TFTs and two n channel type TFTs. A first voltage (VDD) is applied to the source of the first p-channel TFT and the drain is connected to the source of the second p-channel TFT. The drain of the second p-channel TFT is connected to the drain of the second n-channel TFT. The source of the second n-channel type TFT is connected to the drain of the first n-channel type TFT, and the second voltage (GND) is applied to the source of the first n-channel type TFT. Note that the first voltage is higher than the second voltage.

The clock signal (CK) is input to the gate electrode of the first n-channel TFT, and the clock signal (CK) is input to the gate electrode of the first p-channel TFT.
The inverted clock signal (CK
b) has been entered.

The clocked inverter is synchronized with the clock signal (CK) and the inverted clock signal (CKb),
Second p-channel TFT and second n-channel TFT
The output signal (OUT) is output by inverting the polarity of the signal (IN) input to the gate electrode of the.

In this embodiment, all the TFTs included in the clocked inverter shown in FIG. 12B have a first electrode and a second electrode which are electrically connected.

FIG. 13 shows a top view of the clocked inverter shown in FIG. Reference numerals 1201 and 1202 are clocked inverters and 1203 is an inverter. Clock signal (CK), inverted clock signal (CK
b) and the input signal (IN) are the wirings 1210 and 1 respectively.
211 and 1212. Output signal (OU
T) is output from the wiring 1213. Further, the first voltage (VDD) and the second voltage (GND) are applied to the wirings 1214 and 1215, respectively.

FIG. 14 is a sectional view taken along line AA 'in FIG.
FIG. 14B shows a cross-sectional view taken along line BB ′ in FIG.

1220 is a clocked inverter 12
The first p-channel TFT included in 02, 122
1 is the second p of the clocked inverter 1202
It is a channel type TFT.

The first p-channel TFT 1220 has a first electrode 1230 and a second electrode 1231.
The first electrode 1230 and the second electrode 1231 overlap with each other with the channel formation region 1233 included in the semiconductor film 1232 interposed therebetween.

The second p-channel TFT 1221 has a first electrode 1234 and a second electrode 1235.
The first electrode 1234 and the second electrode 1235 overlap with each other with the channel formation region 1236 included in the semiconductor film 1232 interposed therebetween.

Then, the first p-channel TFT 122
The source region 1240 included in the semiconductor film 1232 of 0 is connected to the wiring 1214. In addition, the drain region 1241 included in the semiconductor film 1232 of the second p-channel TFT 1221 is connected to the wiring 1215.

First electrode 1230 and second electrode 1231
Are connected to the wiring 1211 to which the inverted clock signal (CKb) is input. Therefore, the first electrode 123
0 and the second electrode 1231 are electrically connected. Although not shown, the first electrode 1234 and the second electrode 12
35 is also electrically connected.

Although the first electrode and the second electrode are electrically connected to each other by another wiring in this embodiment, the first electrode and the second electrode may be directly connected to each other. good. However, in the case where the first electrode and the second electrode are electrically connected to each other by a wiring, the wiring can be formed at the same time as another wiring, so that the number of masks can be suppressed.

Wirings 1210, 1211, 1214
And 1215 can be formed by stacking a plurality of conductive films. The wiring resistance can be reduced by making the wiring into a multi-layered wiring and the length of the wiring can be shortened, and the drive circuit can be highly integrated.

Further, as shown in this embodiment, each TFT
It is not necessary to connect the first electrode and the second electrode of each TFT, and in the plurality of TFTs included in the circuit,
When either the first electrode or the second electrode is connected to each other, the first
It suffices that the above electrode and the second electrode are connected.

This embodiment can be implemented by freely combining with Embodiment 1 or Embodiment 2.

(Embodiment 4) Another embodiment of the present invention will be described with reference to the drawings. Here, an example of a pixel structure and a driver circuit configuration suitable for a liquid crystal display device will be described. FIGS. 15, 16 and 17 used in this embodiment are cross-sectional views illustrating the manufacturing process thereof, and FIGS. 18 and 19 are top views corresponding thereto, and are described using common reference numerals for convenience of description. To do.

In FIG. 15A, the first wiring 302 and the first electrodes 303 to 306 are formed on the substrate 301 in Example 1.
It is formed in the same manner as. Then, the first insulating film 307 is formed. In this embodiment, a three-layer insulating film (first insulating film A
307a, first insulating film B307b, first insulating film C
307c) are stacked and used as the first insulating film 307. First insulating film A formed of silicon oxynitride film
307a is formed to a thickness of 50 nm, and a first insulating film B 307b is formed.
1μm using a silicon oxide film formed of TEOS
To have a three-layer structure in which a silicon oxynitride film is formed as the first insulating film C 307c after the surface is planarized by CMP. Of course, the insulating film of FIG. 15 is not limited to this structure, and may have the same structure as that of the first embodiment. The semiconductor films 310 to 312 divided into islands are formed in the same manner as in the first embodiment.

FIG. 18 is a top view of FIG.
It shows in (A). A cross-sectional view taken along line AA ′ of FIG. 18A corresponds to FIG. First electrode 305 and first
The electrode 306 is included in a part of the common wiring 380.

Next, as shown in FIG. 15B, a second insulating film 350 which covers the semiconductor films 310 to 312 is formed. The second insulating film 350 is formed of an insulator containing silicon by a plasma CVD method or a sputtering method. Its thickness is 4
It is set to 0 to 150 nm.

Second electrodes 313 to 317 are formed thereon. The material for forming the second wiring is not limited, but the first layer formed of a nitride of a refractory metal such as molybdenum or tungsten and the refractory metal or a low resistance metal such as aluminum or copper formed thereon. Alternatively, it is formed of polysilicon or the like. Specifically, the first layer is W, Mo, T
a or Ti selected from one or more kinds of nitrides,
The second layer is made of one or more alloys selected from W, Mo, Ta, Ti, Al and Cu, or n-type polycrystalline silicon.

FIG. 18 is a top view of FIG.
It shows in (B). The second electrode 315 and the second electrode 316 are
It is included in a part of the gate wiring 381. Then, the second electrode 315 and the second electrode 316 are respectively formed in the first insulating film 3
07, the semiconductor film 312, and the second insulating film 350 are sandwiched therebetween, and overlap with the first electrodes 305 and 306.

After that, an impurity region is formed in each semiconductor film by the ion doping method as in the first embodiment. Further, heat treatment for activation or hydrogenation is performed. In this heat treatment,
It is preferable to use a gas heating type RTA method.

A passivation film 318 made of a silicon nitride film and a third insulating film 319 made of an organic resin material selected from acryl, polyimide, polyamide and polyimideamide are formed. The passivation film 318 may be regarded as a part of the third insulating film 319. The surface of the third insulating film is preferably flattened by CMP. After that, openings are formed and wirings 320 to 323 and pixel electrodes 324 are formed.

Thus, the n-channel TF is formed on the same substrate.
A driver circuit 400 including a T402 and a p-channel TFT 403, and a pixel portion 401 including an n-channel TFT 404 and a capacitor portion 405 are formed.

In the drive circuit 400, the n-channel TFT is used.
In 402, the semiconductor film 310 is the channel formation region 33.
Has 0. Then, the channel formation region 330 and the first electrode 303 overlap with each other with the first insulating film 307 interposed therebetween. In addition, the channel formation region 330 and the second electrode 313 overlap with each other with the second insulating film 350 interposed therebetween. Further, although not shown, the first wiring 3
02 and the first electrode 303 are connected to each other, and the wiring 320
Is connected to the first wiring 302 and the second electrode 313. In addition, the second concentration one conductivity type impurity region 334 is L
As DD, the first-concentration one-conductivity-type impurity region 335 functions as a source or drain region. The length of the LDD in the channel length direction is 0.5 to 2.5 μm, preferably 1.5 μm. The structure of such an LDD is mainly intended to prevent the deterioration of the TFT due to the hot carrier effect.

In the p-channel TFT 403, the semiconductor film 311 has a channel forming region 331. Then, the channel formation region 331 and the first electrode 304 are
The first insulating film 307 is sandwiched between them to overlap. Also,
The channel formation region 331 and the second electrode 314 overlap with each other with the second insulating film 350 interposed therebetween. The impurity region 336 opposite to one conductivity type of the third concentration functions as a source or drain region.

A shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit and the like can be formed by these n-channel TFT 402 and p-channel TFT 403. In particular, the structure of the first n-channel TFT 402 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.

Even if the CMOS structure is not used, the NMO
The present invention can be similarly applied to a circuit based on S or PMOS.

In the pixel portion 401, the n-channel TFT 4
In 04, the semiconductor film 312 is the channel formation region 33.
2, 340. The first electrode 305 and the second electrode 315 overlap with each other with the channel formation region 332 interposed therebetween. In addition, the first electrode 306 and the second electrode 316
Overlap with the channel formation region 340 in between. The second concentration one conductivity type impurity region 337 functions as an LDD, and the first concentration one conductivity type impurity region 338 functions as a source or drain region. This n-channel type T
The FT 404 has a form in which two TFTs are connected in series with an impurity region of one conductivity type having a first concentration inserted.

Further, the capacitor portion connected to the n-channel TFT 404 in the pixel portion 401 is formed by the semiconductor film 312, the second insulating film 350, and the second electrode 317.

FIG. 19 is a top view of the pixel portion in FIG. 16A, and the line AA 'corresponds to FIG. 16A. The line BB ′ corresponds to FIG. 16 (B).

As described above, according to the present invention, by forming the pair of gate electrodes by inserting the semiconductor film, the thickness of the semiconductor film is substantially halved, and depletion progresses rapidly with the application of the gate voltage. Thus, it becomes possible to increase the field effect mobility and decrease the subthreshold coefficient.

After forming up to FIG. 16A, an alignment film 453 is formed as shown in FIG. 17, and rubbing treatment is performed.
Although not shown, before forming the alignment film 453, a columnar spacer for holding the substrate distance may be formed at a desired position by patterning an organic resin film such as an acrylic resin film. . Further, spherical spacers may be dispersed over the entire surface of the substrate instead of the columnar spacers.

Then, the counter electrode 45 is formed on the counter substrate 450.
1 is formed, an alignment film 452 is formed thereon, and rubbing treatment is performed. The counter electrode 451 is made of ITO. Then, the counter substrate 450 on which the seal pattern 454 is formed
Stick together. After that, a liquid crystal material 455 is placed between both substrates.
And then completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix driving liquid crystal display device shown in FIG. 17 is completed.

This embodiment can be implemented by freely combining it with the third embodiment.

Example 5 In this example, an example of manufacturing a semiconductor film by a method different from that of Example 1 will be described.

In FIG. 20A, reference numeral 100 is a substrate having an insulating surface. In FIG. 20A, the substrate 10
For 0, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this step may be used.

First, as shown in FIG. 20A, the substrate 1
00, the first electrodes 102a and 102b are formed. The first electrodes 102a and 102b may be formed of a conductive material. Typically, aluminum (Al), tungsten (W), molybdenum (M
o), tantalum (Ta), titanium (Ti), or an alloy or compound composed of one or more selected from them. Alternatively, a stack of several conductive films may be used as the first electrode.

Then, a first insulating film 101 is formed on the insulating surface so as to cover the first electrodes 102a and 102b. The first insulating film 101 is formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiO _x N _y ), or the like. A typical example is 2 as the first insulating film 101.
The first silicon oxynitride film, which has a layered structure and is formed by using SiH ₄ , NH ₃ , and N ₂ O as reaction gases, has a thickness of 50 to 1
A structure is employed in which a second silicon oxynitride film formed by using 00 nm, SiH ₄ , and N ₂ O as reaction gases is laminated to a thickness of 100 to 150 nm. In addition, as one layer of the first insulating film 101, a silicon nitride film (SiN film) having a film thickness of 10 nm or less, or a second silicon oxynitride film (Si
It is preferable to use an N _x O _y film (X >> Y). At the time of gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, it is extremely effective to use a silicon nitride film as the first insulating film in contact with the semiconductor film. Also,
A three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

Next, a first semiconductor layer 103 having an amorphous structure is formed on the first insulating film. For the first semiconductor layer 103, a semiconductor material containing silicon as its main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied and is formed with a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor layer having a high-quality crystal structure by the subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor layer 103 having an amorphous structure is 5 × 10 ¹⁸ / cm ³ (Secondary ion mass spectrometry (SIMS)
It is recommended to reduce the atomic concentration to less than or equal to (atomic concentration measured in).
These impurities become a factor that hinders later crystallization, and also becomes a factor that increases the density of trap centers and recombination centers even after crystallization. Therefore, it is desirable to use not only a high-purity material gas but also an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electrolytic polishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.

Next, as a technique for crystallizing the first semiconductor layer 103 having an amorphous structure, here, Japanese Patent Application Laid-Open No. 8-
Crystallization is performed using the technique described in Japanese Patent No. 78329. The technique described in the publication is a crystal structure that expands from an added region as a starting point by selectively adding a metal element that promotes crystallization to an amorphous silicon film (also called an amorphous silicon film) and performing heat treatment. To form a semiconductor layer having First, on the surface of the first semiconductor layer 103 having an amorphous structure, a metal element having a catalytic action for promoting crystallization (here, nickel) is converted into a weight of 1 to 100.
A nickel acetate salt solution containing ppm is applied by a spinner to form the nickel-containing layer 104. (FIG. 20B) As a means other than the method for forming the nickel-containing layer 104 by coating, a sputtering method, a vapor deposition method, or a means for forming an extremely thin film by plasma treatment may be used. In addition, although the example of coating the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Next, heat treatment is performed to perform crystallization.
In this case, in crystallization, silicide is formed in a portion of the semiconductor layer in contact with a metal element that promotes crystallization of a semiconductor, and crystallization proceeds with the silicide as a nucleus. Thus, FIG. 20 (C)
The first semiconductor layer 105 having the crystal structure shown in is formed. Note that the concentration of oxygen contained in the first semiconductor layer 105 after crystallization is preferably 5 × 10 ¹⁸ / cm ³ or less. Here, the heat treatment for dehydrogenation (450
C., 1 hour) and then heat treatment for crystallization (550.degree.
650 ° C. for 4 to 24 hours). Further, when crystallization is performed by irradiation with intense light, any one of infrared light, visible light, or ultraviolet light or a combination thereof can be used, but typically, a halogen lamp, a metal halide, or the like. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source is 1 to 60
Second, preferably 30 to 60 seconds, and turn it on once to 1
Repeated 0 times, the semiconductor layer momentarily 600 ~ 1000 ℃
It may be heated to a certain degree. Note that, if necessary, the first semiconductor layer 10 having an amorphous structure before being irradiated with strong light.
A heat treatment for releasing hydrogen contained in 5 may be performed.
Further, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. Considering the productivity, it is desirable to perform crystallization by irradiating strong light.

First semiconductor layer 1 thus obtained
In 05, a metal element (here, nickel) remains. It is not evenly distributed in the membrane,
If the average concentration is exceeded, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ . Of course, even in such a state, it is possible to form various semiconductor elements including the TFT, but the element is removed by the method described below.

Next, in order to increase the crystallization rate (ratio of crystal components in the total volume of the film) and repair defects left in the crystal grains, laser light is applied to the first semiconductor layer 105 having a crystal structure. Irradiation with (first laser light) in the air or an oxygen atmosphere. Laser light (first laser light)
Irradiation results in the formation of irregularities on the surface and the formation of a thin oxide film 106. (FIG. 20 (D)) As this laser light (first laser light), excimer laser light having a wavelength of 400 nm or less, and second and third harmonics of YAG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light.

Further, an oxide film (called chemical oxide) is formed from an ozone-containing aqueous solution (typically ozone water) to form a barrier layer 1 composed of an oxide film having a total thickness of 1 to 10 nm.
07 is formed, and the second semiconductor layer 108 containing a rare gas element is formed over this barrier layer 107 (FIG. 20E).
Note that here, the first semiconductor layer 10 having a crystal structure is used.
The oxide film 106 formed by irradiating the laser beam with respect to No. 5 is also regarded as a part of the barrier layer. The barrier layer 107 functions as an etching stopper when only the second semiconductor layer 108 is selectively removed in a later step. Further, instead of the ozone-containing aqueous solution, the chemical oxide can be similarly formed by treating with an aqueous solution in which sulfuric acid, hydrochloric acid, nitric acid and the like are mixed with hydrogen peroxide solution. Further, as another method of forming the barrier layer 107, ozone may be generated by irradiation of ultraviolet rays in an oxygen atmosphere to oxidize the surface of the semiconductor layer having the crystal structure. As another method for forming the barrier layer 107, an oxide film having a thickness of about 1 to 10 nm may be deposited as a barrier layer by a plasma CVD method, a sputtering method, an evaporation method, or the like. As another method for forming the barrier layer 107, a clean oven may be used and heated to about 200 to 350 ° C. to form a thin oxide film. Note that the barrier layer 107 is not particularly limited as long as it is formed by any one of the above methods or a combination of these methods; however, nickel in the first semiconductor layer may be included in the first semiconductor layer due to subsequent gettering. It is necessary to have a film quality or film thickness that can be transferred to the second semiconductor layer.

Here, the second semiconductor layer 108 containing a rare gas element is formed by a sputtering method to form a gettering site. (FIG. 20E) Note that it is desirable to appropriately adjust the sputtering conditions so that a rare gas element is not added to the first semiconductor layer. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used. Of these, argon (Ar), which is an inexpensive gas, is preferable. Here, the second semiconductor layer is formed using a target made of silicon in an atmosphere containing a rare gas element. There are two meanings of containing the rare gas element ion, which is an inert gas, in the film. One is to form dangling bonds to give strain to the semiconductor layer, and the other is to give strain to the lattice of the semiconductor layer. In order to give strain between the lattices of the semiconductor layer, it is remarkably obtained when an element having an atomic radius larger than that of silicon such as argon (Ar), krypton (Kr), and xenon (Xe) is used. Further, by containing a rare gas element in the film, not only lattice strain but also dangling bonds are formed, which contributes to the gettering action.

When the second semiconductor layer is formed using a target containing phosphorus, which is an impurity element of one conductivity type, in addition to gettering by the rare gas element, gettering is performed by utilizing the Coulomb force of phosphorus. It can be carried out.

Further, during gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, the oxygen concentration contained in the second semiconductor layer 108 is higher than the oxygen concentration contained in the first semiconductor layer. High concentration, eg 5 × 10 ¹⁸ /
It is desirable to set it to cm ³ or more.

Next, heat treatment is performed to perform gettering for reducing or removing the concentration of the metal element (nickel) in the first semiconductor layer. As the heat treatment for performing gettering, treatment for irradiating strong light or heat treatment may be performed. By this gettering,
The metal element moves in the direction of the arrow in FIG. 20F (that is, the direction from the substrate side to the surface of the second semiconductor layer), and the metal contained in the first semiconductor layer 105 covered with the barrier layer 107. The element is removed or the concentration of the metal element is reduced. The distance that the metal element moves during gettering may be at least the thickness of the first semiconductor layer, and gettering can be completed in a relatively short time. Here, all of nickel is moved to the second semiconductor layer 108 so that nickel is not segregated in the first semiconductor layer 105.
Sufficiently gettering is performed so that nickel contained in the semiconductor layer 105 is almost absent, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less.

Depending on the heat treatment conditions for gettering, the crystallinity of the first semiconductor layer is increased at the same time as gettering to repair defects left in the crystal grains, that is, improve the crystallinity. be able to.

In this specification, gettering means that the metal element in the gettered region (here, the first semiconductor layer) is released by thermal energy and moves to the gettering site by diffusion. . Therefore,
Gettering depends on the processing temperature, and the higher the temperature, the shorter the gettering.

When a process of irradiating strong light is used as the heat treatment for gettering, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and it is turned on 1 to 10 times. It is preferably repeated 2 to 6 times. The light emission intensity of the lamp light source is arbitrary, but is instantaneously 60
The semiconductor layer is heated to 0 to 1000 ° C., preferably 700 to 750 ° C.

When heat treatment is performed, heat treatment may be performed in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example at 550 ° C. for 14 hours. In addition to the heat treatment, strong light may be irradiated.

Next, using the barrier layer 107 as an etching stopper, only the second semiconductor layer indicated by 106 is selectively removed, and then the barrier layer 107 made of an oxide film is removed. As a method of selectively etching only the second semiconductor layer, dry etching without using plasma with ClF ₃ , hydrazine, or tetraethylammonium hydroxide (chemical formula (CH ₃ ) ₄ NO
It can be performed by wet etching with an alkaline solution such as an aqueous solution containing H). In addition, after removing the second semiconductor layer, when the nickel concentration was measured on the surface of the barrier layer by TXRF, nickel was detected at a high concentration.
The barrier layer is preferably removed, and may be removed with an etchant containing hydrofluoric acid.

Next, the first semiconductor layer having a crystal structure is irradiated with laser light (second laser light) in a nitrogen atmosphere or vacuum. When the laser light (second laser light) is applied, the height difference of the unevenness formed by the irradiation of the first laser light (PV value: Peak to Valley, the difference between the maximum value and the minimum value of the height) Is reduced, that is, flattened. (FIG. 20 (G)) Here, the PV value of the unevenness is AF
It may be observed by M (atomic force microscope). Specifically, the uneven P formed by the irradiation of the first laser beam
-The surface with a V value of about 10 to 30 nm is the second
By irradiating the laser light of, the PV value of the unevenness on the surface can be made 5 nm or less, and depending on the condition, it can be 1.5.
can be less than or equal to nm. As the laser light (second laser light), excimer laser light having a wavelength of 400 nm or less, and the second and third harmonics of a YAG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light.

The energy density of the second laser light is made higher than that of the first laser light, preferably 30 to 60 mJ / cm ² . However, the second
If the energy density of the laser light is higher than that of the first laser light by 90 mJ / cm ² or more, the surface roughness will increase, and the crystallinity will be further lowered or microcrystallized. Is becoming worse.

The irradiation of the second laser light is higher than the energy density of the first laser light, but the crystallinity hardly changes before and after the irradiation. In addition, the crystal state such as grain size hardly changes. That is, it is considered that only flattening is performed by the irradiation of the second laser light.

The advantage that the semiconductor layer having a crystal structure is flattened by the irradiation of the second laser light is very large. For example, the improved flatness makes it possible to reduce the thickness of the second insulating film used as a gate insulating film to be formed later and improve the mobility of the TFT. In addition, since the flatness is improved, TF
When T is manufactured, off current can be reduced.

When the gettering site is added to the first semiconductor layer by irradiating it with the second laser light, the rare gas element in the semiconductor layer having a crystalline structure is removed. The effect of removing or reducing is also obtained.

Next, the planarized first semiconductor layer 10
9 is used to form a semiconductor film having a desired shape by using a known patterning technique.

This embodiment can be implemented by freely combining with Embodiments 1 to 4.

(Embodiment 6) In this embodiment, an example of forming a semiconductor film by a thermal crystallization method using a catalytic element is shown.

When a catalyst element is used, it is disclosed in JP-A-7-130.
It is desirable to use the techniques disclosed in Japanese Patent No. 652 and Japanese Patent Laid-Open No. 8-78329.

Here, an example in which the technique disclosed in Japanese Laid-Open Patent Publication No. 7-130652 is applied to the present invention is shown in FIG.
Shown in 1. First, the first electrode 1252 is formed over the substrate 1251. Then, so as to cover the first electrode 1252,
A first insulating film 1253 was formed on the substrate 1251, and an amorphous silicon film 1254 was formed thereon. Further, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1255. (Figure 21 (A))

Next, after a dehydrogenation step at 500 ° C. for 1 hour, at 500 to 650 ° C. for 4 to 12 hours, for example, 550.
The crystalline silicon film 1256 is subjected to heat treatment at 8 ° C. for 8 hours.
Was formed. The crystalline silicon film 125 thus obtained
6 had a very good crystalline quality. (Figure 21 (B))

Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. FIG. 2 shows the case where the same technology is applied to the present invention.
It will be explained in 2.

First, the first electrode 1302 is formed on the glass substrate 1301. Then, a first insulating film 1303 was provided over the substrate 1301 so as to cover the first electrode 1302, and an amorphous silicon film 1304 was formed thereover. Then, a silicon oxide film 1305 was continuously formed over the amorphous silicon film 1304. At this time, the thickness of the silicon oxide film 1305 was set to 150 nm.

Next, the silicon oxide film 1305 is patterned to form contact holes 1306 selectively,
Then, a nickel acetate salt solution containing 10 ppm by weight of nickel was applied. As a result, the nickel-containing layer 1307 is formed, and the nickel-containing layer 1307 is formed only on the bottom of the contact hole 1306.
Contacted 04. (Figure 22 (A))

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment was performed at 570 ° C. for 14 hours to form a crystalline silicon film 1308. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and then the crystallization proceeds in the lateral direction. The crystalline silicon film 1308 thus formed is composed of rod-shaped or needle-shaped crystals aggregated, and the respective crystals grow macroscopically with a certain directionality, so that the crystallinity is uniform. There is an advantage. (Figure 22 (B))

The catalyst elements that can be used in the above two techniques are not only nickel (Ni) but also germanium (Ge), iron (Fe), palladium (Pd), tin (S).
n), lead (Pb), cobalt (Co), platinum (Pt),
Elements such as copper (Cu) and gold (Au) may be used.

A crystalline semiconductor film (including a crystalline silicon film, a crystalline silicon germanium film, etc.) is formed by using the technique as described above, and patterning is performed to obtain a crystalline T film.
A semiconductor layer of FT can be formed. A TFT manufactured from a crystalline semiconductor film using the technique of this embodiment is
Excellent characteristics were obtained, but high reliability was required for that reason. However, by adopting the TFT structure of the present invention, a TFT that makes the most of the technique of this embodiment
It has become possible to fabricate.

Next, an example in which a step of removing the catalytic element from the crystalline semiconductor film is performed after the crystalline semiconductor film is formed by using the above-mentioned catalytic element with the amorphous semiconductor film as an initial film, 23. In this example, as the method, the technique described in JP-A-10-135468 or JP-A-10-135469 was used.

The technique described in the publication is a technique for removing the catalytic element used for crystallization of the amorphous semiconductor film after the crystallization by using the gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 1.
It can be reduced to 0 ¹⁷ atms / cm ³ or less, preferably 1 × 10 ¹⁶ atms / cm ³ .

Here, an alkali-free glass substrate typified by Corning's 1737 substrate was used. FIG. 23 (A)
Then, the first electrode 1402 is formed over the substrate 1401. Then, the substrate 14 is formed so as to cover the first electrode 1402.
01, a first insulating film 1403 was provided, and a crystalline silicon film 1404 was formed thereon.

Then, a silicon oxide film 1405 for a mask is formed to a thickness of 150 nm on the surface of the crystalline silicon film 1404, a contact hole is provided by patterning, and a region where the crystalline silicon film is partially exposed is provided. There is. Then, the step of adding phosphorus was performed to provide a region (gettering region) 1406 in which phosphorus was added to the crystalline silicon film.

In this state, 550 to 80 in a nitrogen atmosphere.
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example at 600 ° C. for 12 hours, the region 1406 in which phosphorus is added to the crystalline silicon film acts as a gettering site, and the catalyst left in the crystalline silicon film 1404. The element could be segregated in the gettering region 1406 to which phosphorus was added.

Then, the silicon oxide film 140 for the mask is used.
5 and the phosphorus-added region 1406 are removed by etching, so that the concentration of the catalytic element used in the crystallization process is reduced to 1 × 10 ¹⁷ atms / cm ³ or less. I was able to get This crystalline silicon film could be used as it is as a semiconductor layer of the TFT of the present invention.

This embodiment can be implemented in combination with Embodiments 1 to 4.

(Embodiment 7) In this embodiment, a structure of a semiconductor device of the present invention will be described.

FIG. 24 shows a block diagram of a light emitting device which is one of the semiconductor devices of the present invention. The light emitting device is an OLED (Organic Light Emitting Devic) formed on a substrate.
e) corresponds to an OLED panel enclosed between the substrate and the cover material. An OLED module in which an IC including a controller is mounted on the OLED panel may be called a light emitting device.

The OLED has a layer containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field (hereinafter, referred to as an organic light emitting layer), an anode layer and a cathode layer. is doing. Luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission when returning to a ground state from a triplet excited state (phosphorescence). One of the above-mentioned light emissions may be used, or both of the light emissions may be used.

In the present specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers.
The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, an OLED has a structure in which an anode, a light emitting layer, and a cathode are laminated in this order, and in addition to this structure, an anode / hole injection layer /
It may have a structure in which a light emitting layer / cathode or an anode / hole injection layer / light emitting layer / electron transport layer / cathode are laminated in this order.

In FIG. 24, a drive circuit of a light emitting device for displaying an image using a digital video signal will be described as an example. The light emitting device shown in FIG. 24 has a data line driving circuit 80.
0, a scan line driver circuit 801, and a pixel portion 802.

In the pixel portion 802, a plurality of source wirings,
A plurality of gate wirings and a plurality of power supply lines are formed,
A region surrounded by the source wiring, the gate wiring, and the power supply line corresponds to a pixel. Note that in FIG. 24, one of a plurality of pixels
One source wiring 807, one gate wiring 809,
Only a pixel having one power supply line 808 is shown as a representative. Each pixel is a switching T that serves as a switching element.
FT 803, driving TFT 804, storage capacitor 805
And an OLED 806.

The gate electrode of the switching TFT 803 is connected to the gate wiring 809. One of a source region and a drain region of the switching TFT 803 is a source wiring 807 and the other is a driving TFT 80.
4 gate electrodes.

One of the source region and the drain region of the driving TFT 804 is the power source line 808 and the other is the OLED.
It is connected to 806. Then, the driving TFT 804
A storage capacitor 805 is formed by the gate electrode and the power supply line 808. Note that the storage capacitor 805 does not necessarily have to be formed.

The data line driving circuit 800 has a shift register 810, a first latch 811, and a second latch 812. The shift register 810 is supplied with a clock signal (S-CLK) and a start pulse signal (S-SP) for the data line driver circuit. The first latch 811 has a latch signal (Latch) that determines the latch timing.
signals) and a video signal (Video signal)
als) is given.

A clock signal (S
-CLK) and the start pulse signal (S-SP) are input, a sampling signal that determines the sampling timing of the video signal is generated and input to the first latch 811.

Note that the sampling signal from the shift register 810 is buffered and amplified by a buffer or the like, and then
It may be input to the first latch 811. Since many circuits or circuit elements are connected to the wiring to which the sampling signal is input, load capacitance (parasitic capacitance)
Is big. This buffer is effective in order to prevent "dullness" of the rising or falling of the timing signal caused by the large load capacitance.

The first latch 811 has a plurality of stages of latches. The first latch 811 samples the input video signal in synchronization with the input sampling signal, and sequentially stores the sampled video signal in the latch of each stage.

The time until the writing of the video signal to the latches of all the stages of the first latch 811 is completed is called a line period. In practice, the line period may include a period in which a horizontal blanking period is added to the line period.

When one line period ends, the second latch 8
A latch signal is input to 12. At this moment, the video signal written and held in the first latch 811 is
The signals are sent to the latch 812 all at once, written in and held in the latches of all stages of the second latch 812.

The video signal is sequentially written in the first latch 811 which has finished sending the video signal to the second latch 812, based on the sampling signal from the shift register 810.

During the second one-line period, the video signal written and held in the second latch 812 is input to the source line.

On the other hand, the scan line driver circuit has a shift register 821 and a buffer 822. The shift register 821 has a clock signal (G-C) for the scanning line driver circuit.
LK) and the start pulse signal (G-SP) are given.

A clock signal (G
-CLK) and the start pulse signal (G-SP) are input, a selection signal that determines the timing of selecting the gate wiring is generated and input to the buffer 822. The selection signal input to the buffer 822 is buffer-amplified and input to the gate wiring 809.

When the gate wiring 809 is selected, the switching TFT 803 having the gate electrode connected to the selected gate wiring 809 is turned on. Then, the video signal input to the source wiring is input to the gate electrode of the driving TFT 804 via the switching TFT 803 which is turned on.

The switching of the driving TFT 804 is controlled based on the information of 1 or 0 contained in the video signal input to the gate electrode. Driving TFT 80
When 4 is on, the potential of the power supply line is applied to the pixel electrode of the OLED 806, and the OLED 806 emits light. When the driving TFT 804 is off, the potential of the power supply line is OLED8.
The OLED 806 does not emit light without being applied to the pixel electrode of 06.

In the circuit included in the data line driver circuit 800 and the scan line driver circuit 801, in the light emitting device shown in FIG. 24, the first electrode and the second electrode of the TFT are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the semiconductor film is made thinner, so that the subthreshold coefficient can be made smaller. Further, the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, the drive voltage can be reduced. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

Also, in the pixel portion 802, the switching TFT 80 used as a switching element.
A common voltage is applied to one of the first electrode and the second electrode of No. 3. As a result, it is possible to suppress variations in the threshold and to suppress the off-current as compared with the case where there is one electrode.

A driving TFT 804 for supplying a current to the OLED 806 electrically connects the first electrode and the second electrode. As a result, the on-current can be increased as compared with the case where the number of electrodes is one. In addition,
The driving TFT is not limited to this configuration, and a common voltage may be applied to either one of the first electrode and the second electrode without electrically connecting the first electrode and the second electrode. May be. Further, a thin film transistor having a general structure having only one electrode may be included.

Next, FIG. 25 shows the structure of a general liquid crystal display device. The element substrate shown in FIG. 25 includes a data line driver circuit 700, a scan line driver circuit 701, and a pixel portion 702.

A plurality of source wirings and a plurality of gate wirings are formed in the pixel portion 702, and a region surrounded by the source wirings and the gate wirings corresponds to a pixel. Note that, in FIG. 25, only a pixel having one source wiring 703 and one gate wiring 704 is representatively shown among a plurality of pixels. Each pixel has a pixel TFT serving as a switching element and a liquid crystal cell 706.

The liquid crystal cell 706 has a pixel electrode, a counter electrode, and liquid crystal provided between the pixel electrode and the counter electrode.

The gate electrode of the pixel TFT 705 is connected to the gate wiring 704. One of a source region and a drain region of the pixel TFT 705 is a source wiring 703.
The other is connected to the pixel electrode of the liquid crystal cell 706.

The data line driving circuit 700 includes a shift register 710, a level shifter 711 and an analog switch 71.
Have two. The shift register 710 is supplied with a clock signal (S-CLK) for the data line driver circuit and a start pulse signal (S-SP). The analog switch 712 has a video signal (Video signal).
s) is given.

A clock signal (S
-CLK) and the start pulse signal (S-SP) are input, a sampling signal that determines the sampling timing of the video signal is generated, and the level shifter 711 is generated.
Entered in. The sampling signal is the level shifter 71.
At 1, the amplitude of the voltage is increased and the voltage is input to the analog switch 712. The analog switch 712 samples the input video signal in synchronization with the input sampling signal and inputs the sampled video signal to the source wiring 703.

On the other hand, the scan line driver circuit has a shift register 721 and a buffer 722. The shift register 721 includes a clock signal (G-C) for the scan line driver circuit.
LK) and the start pulse signal (G-SP) are given.

A clock signal (G
-CLK) and the start pulse signal (G-SP) are input, a selection signal that determines the timing of selecting the gate wiring is generated and input to the buffer 722. The selection signal input to the buffer 722 is buffer-amplified and input to the gate wiring 704.

When the gate wiring 704 is selected, the pixel T in which the gate electrode is connected to the selected gate wiring 704.
The FT705 turns on. Then, the sampled video signal input to the source wiring is input to the pixel electrode of the liquid crystal cell 706 via the pixel TFT 705 that is turned on. Then, the liquid crystal is driven according to the potential of the video signal, and an image is displayed.

In the circuit included in the data line driver circuit 700 and the scan line driver circuit 701 in the liquid crystal display device shown in FIG. 25, the first electrode and the second electrode of the TFT are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the semiconductor film is made thinner, so that the subthreshold coefficient can be made smaller. Further, the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, the drive voltage can be reduced. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

In the pixel portion 702, the first pixel of the pixel TFT 705 used as a switching element is
A common voltage is applied to either one of the electrode and the second electrode. As a result, it is possible to suppress variations in the threshold and to suppress the off-current as compared with the case where there is one electrode.

This embodiment can be carried out in combination with the first to sixth embodiments.

(Embodiment 8) In this embodiment, an external view of a light emitting device according to the present invention will be described.

FIG. 26A is a top view of the light emitting device.
26B is a cross-sectional view taken along the line AA ′ of FIG. 26A, and FIG. 26C is a cross-sectional view taken along the line BB ′ of FIG.

Pixel portion 400 provided on the substrate 4001
2, the data line driving circuit 4003, and the first and second scanning line driving circuits 4004a and 4004b are provided so as to surround the sealing material 4009. In addition, the pixel portion 4002
, The data line driving circuit 4003, and the sealing material 400 on the first and second scanning line driving circuits 4004a and 4004b.
8 are provided. Therefore, the pixel portion 4002, the data line driver circuit 4003, the first and second scan line driver circuits 4004a and 4004b, the substrate 4001 and the sealant 4009.
And a sealing material 4008, which is sealed with a filling material 4210.

The pixel portion 4 provided on the substrate 4001
002, the data line driving circuit 4003, the first and second
The scan line driver circuits 4004a and 4004b each include a plurality of TFTs. In FIG. 26B, the base film 401 is typically used.
The CMOS 4201 included in the data line driver circuit 4003 and the driving TFT (TFT that controls the current to the OLED) 420 included in the pixel portion 4002, which are formed on the 0.
2 is illustrated.

In this embodiment, a p-channel TFT or an n-channel TFT having an electrically connected first electrode and a second electrode of the present invention is used for the CMOS 4201, and the driving TFT 4202 is used. Is a p-channel TFT having an electrically connected first electrode and second electrode. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.

CMOS 4201 and driving TFT 420
A third insulating film 4301 is formed on the second electrode 2, and a pixel electrode (anode) 4203 electrically connected to the drain of the driving TFT 4202 is formed thereon. Pixel electrode 4203
For this, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide or indium oxide can be used.
Moreover, you may use what added gallium to the said transparent conductive film.

A fourth insulating film 4302 is formed on the pixel electrode 4203, and an opening is formed on the pixel electrode 4203 in the fourth insulating film 4302. In this opening, the organic light emitting layer 4 is formed on the pixel electrode 4203.
204 is formed. As the organic light emitting layer 4204, a known organic light emitting material or an inorganic organic light emitting material can be used. The organic light emitting material includes a low molecular weight (monomer) material and a high molecular weight (polymer) material, and either of them may be used.

As a method of forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. Further, the structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer or the electron injection layer.

A cathode 4205 made of a conductive film having a light-shielding property (typically, a conductive film containing aluminum, copper or silver as a main component or a laminated film of these and another conductive film) is formed on the organic light emitting layer 4204. Is formed. Also, the cathode 4
It is desirable to exclude water and oxygen existing at the interface between 205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise the organic light emitting layer 4204 in a nitrogen or rare gas atmosphere and to form the cathode 4205 without exposing it to oxygen or moisture. In the present embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film forming apparatus. And the cathode 4205
Is given a predetermined voltage.

As described above, the pixel electrode (anode) 42
03, an organic light emitting layer 4204 and a cathode 4205
The LED 4303 is formed. And OLED4303
A protective film 4209 is formed over the insulating film 4302 so as to cover the insulating film 4302. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the OLED 4303.

Reference numeral 4005a is a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005a passes between the sealing material 4009 and the substrate 4001, and the FPC 4006 has the FPC 4006 with the anisotropic conductive film 4300 interposed therebetween.
It is electrically connected to the wiring 4301.

As the sealing material 4008, a glass material, a metal material (typically a stainless material), a ceramic material, a plastic material (including a plastic film) can be used. As a plastic material, FRP
(Fiberglass-Reinforced Pl
astics) plate, PVF (polyvinyl fluoride)
A film, mylar film, polyester film or acrylic resin film can be used. Alternatively, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can be used.

However, when the emission direction of light from the OLED is toward the cover material side, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

Further, as the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone can be used. Resin, PVB (polyvinyl butyral) or E
VA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, the substrate 400 of the sealing material 4008 is used.
A concave portion 4007 is provided on the surface on the first side, and a hygroscopic substance or a substance 4207 capable of adsorbing oxygen is arranged. The hygroscopic substance or the substance 4207 capable of adsorbing oxygen is held by the recessed cover material 4208 in the recess 4007 so that the hygroscopic substance or the substance 4207 capable of adsorbing oxygen does not scatter. Note that the recess cover material 4208 has a fine mesh shape and has a structure in which air and moisture can pass through and a hygroscopic substance or a substance that can adsorb oxygen 4207 cannot pass through. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the OLED 4303 can be suppressed.

As shown in FIG. 26C, the pixel electrode 42
At the same time that 03 is formed, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a.

The anisotropic conductive film 4300 has a conductive filler 4300a. Substrate 4001 and F
By thermocompression bonding with PC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

This embodiment can be implemented by being freely combined with Embodiment 1, 2, 3, 6 or 7.

(Embodiment 9) The semiconductor device of the present invention can be used in various electronic devices.

Electronic equipment using the present invention include video cameras, digital cameras, goggle type displays (head mount displays), navigation systems,
Sound reproduction devices (car audio, audio components, etc.), notebook personal computers, game machines,
A portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), an image reproducing device provided with a recording medium (specifically, a digital video disc (DV)
D) and other recording media, and a device equipped with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

FIG. 27A shows a display device, which is a housing 20.
01, support base 2002, display unit 2003, speaker unit 2004, video input terminal 2005 and the like. The display device of the present invention is completed by using the present invention for the display portion 2003 and other circuits. Display device is for PC, TV
It includes all display devices for displaying information such as broadcast reception and advertisement display.

FIG. 27B shows a digital still camera including a main body 2101, a display portion 2102, an image receiving portion 2103,
An operation key 2104, an external connection port 2105, a shutter 2106 and the like are included. The digital still camera of the present invention is completed by using the present invention in the display portion 2102 and other circuits.

FIG. 27C shows a laptop personal computer, which has a main body 2201, a housing 2202, and a display section 2.
203, keyboard 2204, external connection port 220
5, including a pointing mouse 2206 and the like. The notebook personal computer of the present invention is completed by using the present invention for the display portion 2203 and other circuits.

FIG. 27D shows a mobile computer, which has a main body 2301, a display portion 2302, and a switch 230.
3, an operation key 2304, an infrared port 2305 and the like. The mobile computer of the present invention is completed by applying the present invention to the display portion 2302 and other circuits.

FIG. 27E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a casing 2402, a display portion A2403, a display portion B2404, a recording medium ( DVD, etc.) reading unit 240
5, an operation key 2406, a speaker portion 2407, and the like. The display unit A2403 mainly displays image information, and the display unit B2404 mainly displays character information. The image reproducing apparatus of the present invention is completed by using the present invention in the display portions A, B 2403, 2404 and other circuits. In addition,
The image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 27F shows a goggle type display (head mounted display), which is a main body 250.
1, a display portion 2502 and an arm portion 2503 are included. By using the present invention in the display portion 2502 and other circuits, the goggle type display of the present invention is completed.

FIG. 27G shows a video camera, which has a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, and an image receiving portion 260.
6, a battery 2607, a voice input unit 2608, operation keys 2609, and the like. The video camera of the present invention is completed by using the present invention in the display portion 2602 and other circuits.

[0232] Here, FIG. 27H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, a voice input portion 2704, a voice output portion 2705, operation keys 2706,
An external connection port 2707, an antenna 2708, and the like are included.
The mobile phone of the present invention is completed by using the present invention for the display portion 2703 and other circuits.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. In addition, this embodiment can be implemented by freely combining with Embodiments 1 to 8.

Example 10 In this example, the T of the present invention was used.
In the FT, the characteristics of the TFT when the first electrode and the second electrode are electrically connected will be described.

FIG. 28A shows a sectional view of a TFT in which the first electrode and the second electrode of the present invention are electrically connected.
For comparison, a cross-sectional view of a TFT having only one electrode is shown in FIG. In addition, FIG.
FIG. 29 shows the relationship between the gate voltage and the drain current obtained by simulation in the TFT shown in FIG.

The TFT shown in FIG. 28A has a first electrode 2801, a first insulating film 2802 in contact with the first electrode 2801, a semiconductor film 2808 in contact with the first insulating film 2802, and a semiconductor The second insulating film 2 in contact with the film 2808
806 and a second electrode 2807 which is in contact with the second insulating film. The semiconductor film 2808 is provided in the channel formation region 2
803, a first impurity region 2804 in contact with the channel formation region 2803, and a second impurity region 2805 in contact with the first impurity region 2804.

[0237] The first electrode 2801 and the second electrode 2807
Overlap with each other with the channel formation region 2803 sandwiched therebetween. Then, the first electrode 2801 and the second electrode 28
The same voltage is applied to 07.

The first insulating film 2802 and the second insulating film 2
806 is formed of silicon oxide. Also the first electrode,
The second electrode 2807 is made of Al. The channel length is 7 μm, the channel width is 4 μm, the thickness of the first insulating film at the portion where the first gate electrode and the channel forming region overlap is 110 μm, and the portion where the second gate electrode and the channel forming region overlap. The second insulating film has a thickness of 110 μm. The thickness of the channel formation region is 50 nm, and the length of the first impurity region in the channel length direction is 1.5 μm.

Then, 1 is formed in the channel formation region 2803.
An impurity imparting p-type of × 10 ¹⁷ / cm ³ is doped, and the first impurity region has an n of 3 × 10 ¹⁷ / cm ³ .
The impurity imparting type is doped, and the second impurity region is doped with the impurity imparting n-type of 5 × 10 ¹⁹ / cm ³ .

The TFT shown in FIG. 28B has a first insulating film 2902, a second insulating film 2906 in contact with the first insulating film 2902, and a second electrode 2 in contact with the second insulating film.
907. The semiconductor film 2908 includes a channel formation region 2903, a first impurity region 2904 in contact with the channel formation region 2903, and a first impurity region 290.
4 has a second impurity region 2905 which is in contact with 4.

The second electrode 2907 overlaps with the channel formation region 2903.

First insulating film 2902 and second insulating film 2
906 is formed of silicon oxide. The second electrode 2
907 is formed of Al. Channel length is 7 μm,
The channel width is 4 μm, and the thickness of the second insulating film in the portion where the second gate electrode and the channel formation region overlap is 110 μm. The thickness of the channel formation region is 50
nm, and the length of the first impurity region in the channel length direction is 1.5 μm.

Then, 1 is formed in the channel formation region 2903.
An impurity imparting p-type of × 10 ¹⁷ / cm ³ is doped, and the first impurity region has an n of 3 × 10 ¹⁷ / cm ³ .
The impurity imparting type is doped, and the second impurity region is doped with the impurity imparting n-type of 5 × 10 ¹⁹ / cm ³ .

In FIG. 29, the horizontal axis represents the gate voltage and the vertical axis represents the drain current. FIG. 28 (A)
The value of drain current with respect to the gate voltage of the TFT of No. 2 is shown by a solid line, and the value of drain current with respect to the gate voltage of the TFT of FIG.

From FIG. 29 to FIG. 28A, the TFT
Mobility of 139 cm ² / V · s, S value of 0.118 V / d
ec was obtained. Further, in FIG. 28B, the TFT mobility is 86.3 cm ² / V · s and the S value is 0.160 V / d.
ec was obtained. From this, when the first electrode and the second electrode are provided and the second electrode is electrically connected, the mobility is higher than that when only one electrode is provided, and S
The value becomes smaller.

(Embodiment 11) In this embodiment, an example of manufacturing a semiconductor film by a method different from that of Embodiment 1 will be described.

In FIG. 30A, reference numeral 600 is a substrate having an insulating surface. In FIG. 30A, the substrate 60
For 0, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature of this step may be used.

First, as shown in FIG. 30A, the substrate 6
00, the first electrodes 602a and 602b are formed. The first electrodes 602a and 602b may be formed of a conductive material. Typically, aluminum (Al), tungsten (W), molybdenum (M
o), tantalum (Ta), titanium (Ti), or an alloy or compound composed of one or more selected from them. Alternatively, a stack of several conductive films may be used as the first electrode.

Then, a first insulating film 601 is formed on the insulating surface so as to cover the first electrodes 602a and 602b. The first insulating film 601 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiO _x N _y ), or the like. A typical example is 2 as the first insulating film 601.
The first silicon oxynitride film, which has a layered structure and is formed by using SiH ₄ , NH ₃ , and N ₂ O as reaction gases, has a thickness of 50 to 1
A structure is employed in which a second silicon oxynitride film formed by using 00 nm, SiH ₄ , and N ₂ O as reaction gases is laminated to a thickness of 100 to 150 nm. Further, as a layer of the first insulating film 601, a silicon nitride film (SiN film) having a film thickness of 10 nm or less, or a second silicon oxynitride film (Si
It is preferable to use an N _x O _y film (X >> Y). At the time of gettering, nickel tends to move to a region having a high oxygen concentration. Therefore, it is extremely effective to use a silicon nitride film as the first insulating film which is in contact with the semiconductor film. Also,
A three-layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

Next, a first semiconductor layer 603 having an amorphous structure is formed on the first insulating film. For the first semiconductor layer 603, a semiconductor material containing silicon as its main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied and is formed with a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor layer having a high-quality crystal structure by the subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the film of the first semiconductor layer 603 having an amorphous structure is 5 × 10 ¹⁸ / cm ³ (Secondary ion mass spectrometry (SIMS)
It is recommended to reduce the atomic concentration to less than or equal to (atomic concentration measured in).
These impurities become a factor that hinders later crystallization, and also becomes a factor that increases the density of trap centers and recombination centers even after crystallization. For this reason, it is desirable to use not only a high-purity material gas but also a CVD apparatus for mirror surface treatment (electrolytic polishing treatment) in the reaction chamber and an ultra-high vacuum compatible system equipped with an oil-free vacuum exhaust system.

Next, as shown in FIG. 30B, the semiconductor layer 603 is crystallized by a laser crystallization method to form a second semiconductor layer 605 having crystallinity. Here, after heat treatment for dehydrogenation (450 ° C., 1 hour), the semiconductor layer 603 was crystallized by a laser crystallization method. The laser irradiation was performed in the air or an oxygen atmosphere. A pulse oscillation type or continuous emission type excimer laser having a wavelength of 400 nm or less, or a YAG laser can be used.
Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated onto the semiconductor layer. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 4
00 mJ / cm ² (typically 200-300 mJ / cm
² ) When the YAG laser is used, the second harmonic wave and the third harmonic wave thereof are used, and the pulse oscillation frequency 30
~ 300 kHz, laser energy density 300
~ 600 mJ / cm ² (typically 350-500 mJ /
cm ² ) is good. And a width of 100 to 1000 μm,
For example, a laser beam converged linearly at 400 μm may be irradiated over the entire surface of the substrate, and the overlapping ratio (overlap ratio) of the linear laser lights at this time may be set to 50 to 90%.

When laser light (first laser light) is applied, unevenness is formed on the surface of the second semiconductor layer and a thin oxide film 606 is formed. (Figure 30 (B))

Next, the oxide film 606 is removed by an etchant containing hydrofluoric acid.

Next, the second semiconductor layer having a crystal structure is irradiated with laser light (second laser light) in a nitrogen atmosphere or vacuum. When the laser light (second laser light) is applied, the height difference of the unevenness formed by the irradiation of the first laser light (PV value: Peak to Valley, the difference between the maximum value and the minimum value of the height) Is reduced, that is, flattened, and the third semiconductor layer 607 is formed. (Fig. 30
(C)) Here, the PV value of the unevenness may be observed by an AFM (atomic force microscope). Specifically, the PV value of the unevenness formed by the irradiation of the first laser light is 10
A surface having a size of about 30 nm to 30 nm can have a PV value of unevenness of 5 nm or less by the irradiation of the second laser beam. This laser light (second laser light) is an excimer laser light with a wavelength of 400 nm or less, or Y
The second and third harmonics of the AG laser are used. Further, light emitted from an ultraviolet lamp may be used instead of the excimer laser light.

The energy density of the second laser light is made higher than that of the first laser light, preferably 30 to 60 mJ / cm ² . However, the second
If the energy density of the laser light is higher than that of the first laser light by 90 mJ / cm ² or more, the surface roughness will increase, and the crystallinity will be further lowered or microcrystallized. Is becoming worse.

The irradiation of the second laser light is higher than the energy density of the first laser light, but the crystallinity hardly changes before and after the irradiation. In addition, the crystal state such as grain size hardly changes. That is, it is considered that only flattening is performed by the irradiation of the second laser light.

[0257] The semiconductor layer having a crystal structure is flattened by the irradiation with the second laser light, which is very advantageous. For example, the improved flatness makes it possible to reduce the thickness of the second insulating film used as a gate insulating film to be formed later and improve the mobility of the TFT. In addition, since the flatness is improved, TF
When T is manufactured, off current can be reduced.

Next, a semiconductor film having a desired shape is formed on the third semiconductor layer 607 by using a known patterning technique.

This embodiment can be implemented by freely combining with Embodiments 1 to 10.

(Embodiment 12) In this embodiment, a configuration of a pixel of a light emitting device which is one of the semiconductor devices of the present invention, which is different from that of Embodiment 1, will be described.

FIG. 32 shows a top view of a pixel of the light emitting device of this embodiment.

Reference numeral 901 denotes an n-channel TFT,
2 is a p-channel TFT. Further, 903 is a source wiring, 904 is a power supply line, 905 is a gate wiring, 906 is a common wiring, and 911 is a semiconductor film for capacitance.

In this embodiment, the power supply line 904 and the gate wiring 905 are simultaneously formed from the same conductive film. In other words, the power supply line 904 and the gate wiring 905 are formed in the same layer. The gate wirings 905 included in the adjacent pixels are connected to each other through the connection wiring 907 formed in the same layer as the common wiring 906.

A part of the gate wiring 905 functions as the second electrode of the n-channel TFT 901. Also,
Part of the common wiring 906 is an n-channel TFT 901.
Functioning as the first electrode of. N channel type T
One of a source region and a drain region of the FT 901 is a source wiring 903, and the other is a p-channel TF via a connection wiring 908 formed in the same layer as the source wiring 903.
It is connected to the first electrode 909 and the second electrode 910 of T902.

One of the source region and the drain region of the p-channel TFT 902 is formed in the power supply line 904 through the connection wiring 912 which is formed in the same layer as the source wiring 903, and the other is formed in the same layer as the source wiring 903. It is connected to the pixel electrode 914 through the connected connection wire 913.

The first electrode 909 overlaps with the capacitor wiring 911 with a first insulating film (not shown) interposed therebetween. The capacitor wiring 911 is connected to the power supply line 904.

In this embodiment, since the source wiring and the power supply line are formed in different layers, they can be overlapped with each other, and as a result, the aperture ratio can be increased. Note that the present invention is not limited to this structure, and the power supply line may be formed in a layer above the source wiring. Further, either the source wiring or the power supply wiring may be formed in the same layer as the common wiring.

In this embodiment, even TFTs in the same pixel,
A common voltage is applied to the first electrode of the TFT (n-channel TFT 901 in this embodiment) used as a switching element. By applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

TF used as a switching element
In a TFT (p-channel TFT 902 in this embodiment) that allows a current larger than T to flow, the first electrode and the second electrode are electrically connected. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the semiconductor film is made thinner, so that the subthreshold coefficient can be made smaller. Further, the field effect mobility can be further improved. Therefore, the on-current can be increased as compared with the case where the number of electrodes is one. Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced.
Therefore, the integration density can be improved.

(Embodiment 13) In this embodiment, an embodiment of a thin film transistor included in the semiconductor device of the present invention will be described with reference to FIG.

FIG. 33 is a sectional view of the thin film transistor of this example. The thin film transistor shown in FIG.
Electrode 3001, a first insulating film 3002 in contact with the first electrode 3001, a semiconductor film 3008 in contact with the first insulating film 3002, a second insulating film 3006 in contact with the semiconductor film 3008, and a second insulating film Second electrode 300 in contact with the membrane
Have 7. The semiconductor film 3008 includes a channel formation region 3003 and a first formation region which is in contact with the channel formation region 3003.
Impurity region 3004 and a second impurity region 3005 in contact with the first impurity region 3004.

The concentration of one conductivity type impurity added to the first impurity region 3004 is the same as that of the second impurity region 300.
The concentration is lower than the concentration of one conductivity type impurity added to No. 5.

[0273] The first electrode 3001 and the second electrode 3007
Overlap with each other with the channel formation region 3003 interposed therebetween. Then, the first electrode 3001 and the second electrode 30
The same voltage is applied to 07.

In the thin film transistor of this embodiment, the tapered portion of the first electrode 3001 overlaps the first impurity region 3004. And the first electrode 30
01 is substantially flat in the portion overlapping with the channel formation region 3003. With the above configuration, the first
The electrode and the channel forming region overlap with each other at a substantially constant interval. In this state, the film thickness of the first insulating film in the portion where the first electrode and the channel formation region overlap and the thickness of the second insulating film in the portion where the second electrode and the channel formation region overlap If the film thickness is made substantially the same, the S value can be made smaller.

This embodiment can be implemented in combination with Embodiments 1 to 12.

(Embodiment 14) In this embodiment, the second aspect of the present invention will be described.
In a TFT having one electrode, the measured value of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region will be described. In addition, the actual measurement value was calculated | required in each case when the 1st electrode was set to GND and when the 1st electrode and the 2nd electrode were electrically connected. Further, for comparison, a measured value of the drain current Id with respect to the gate voltage of the TFT without the first electrode was also obtained.

FIG. 37 shows a specific structure of the TFT used in this example. A top view of a TFT having two electrodes of the present invention is shown in FIG. 37A, and a cross-sectional view taken along the line AA ′ of FIG. 37A is shown in FIG. In addition, FIG. 37 (C)
A top view of a TFT having only a second electrode for comparison is shown in FIG. 37, and a cross-sectional view taken along line BB ′ of FIG. 37C is shown in FIG.
7 (D).

In the TFT shown in FIGS. 37A and 37B, a base film 901 using a SiNO film is formed with a thickness of 50 nm on a glass substrate 900, and the base film 901 has a thickness of 1 nm.
W of 00 nm is formed as the first electrode 902. Then, the base film 90 is formed so as to cover the first electrode 902.
First insulating film 903 which functions as a gate insulating film on
Is deposited. Note that the first insulating film 903 is formed of 110
nm SiNO film.

Then, a semiconductor film 904 having a thickness of 54 nm is formed on the first insulating film 903. Next, SiN
A 115-nm-thick second insulating film 905 was formed using an O film. Then, a second electrode 906 including two conductive films 906a and 906b is formed over the second insulating film 905. In this example, TaN of 50 nm and 370 nm
A second electrode 906 was formed by stacking W and W. Further, impurities are added to the semiconductor film 904, and the semiconductor film 90
Reference numeral 4 has a channel formation region 907 and an impurity region 908 sandwiching the channel formation region.

The TFT shown in FIGS. 37C and 37D is different from that shown in FIG. 37 only in that it does not have the first electrode 902.
This is different from the TFTs shown in (A) and (B).

The voltage difference between the second electrode and the source region (gate voltage Vgs) of the TFT shown in FIGS. 37C and 37D.
FIG. 34 shows the measured values of the drain current Id with respect to. In the TFT shown in FIGS. 37A and 37B, the first
35 shows measured values of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the second electrode and the source region when the electrode 902 of FIG. In addition, FIG.
In the TFTs shown in (A) and (B), the first electrode 90
2 when the second electrode 906 and the second electrode 906 are electrically connected
FIG. 35 shows measured values of the drain current Id with respect to the voltage difference (gate voltage Vgs) between the electrode and the source region. In each graph, the solid line shows the drain current Id and the broken line shows the mobility.

From the comparison between FIG. 34 and FIGS. 35 and 36,
It can be seen that the threshold value is closer to 0 and the S value is improved when the first electrode is provided, as compared with the case where the first electrode is not provided. Further, from the comparison between FIG. 35 and FIG. 36, the on-current is higher in the case where the first electrode and the second electrode are electrically connected than in the case where the first electrode is grounded. You can see it getting higher.

[0283]

According to the present invention, by applying the common voltage to the first electrode, it is possible to suppress the variation in the threshold and to suppress the off-current as compared with the case where the number of the electrodes is one.

Further, by applying the same voltage to the first electrode and the second electrode, the depletion layer spreads quickly in the same manner as when the thickness of the semiconductor film is made thin, so that the subthreshold coefficient is It is possible to reduce the size and further improve the field effect mobility. Therefore, the number of electrodes is 1.
The on-current can be increased as compared with the two cases.
Therefore, by using the TFT having this structure in the drive circuit, the drive voltage can be lowered. Further, since the on-current can be increased, the size of the TFT (particularly the channel width) can be reduced. Therefore, the integration density can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a TFT of the present invention.

2A to 2C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a light emitting device.

3A to 3C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a light emitting device.

4A to 4C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a light emitting device.

5A to 5C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a light emitting device.

6A to 6C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a light-emitting device.

FIG. 7 is a top view illustrating a manufacturing process of a pixel portion of a light emitting device.

FIG. 8 is a top view illustrating a manufacturing process of a pixel portion of a light emitting device.

FIG. 9 is a top view illustrating a structure of a pixel portion of a light emitting device.

FIG. 10 is a top view illustrating a structure of a pixel portion of a light emitting device.

FIG. 11 is a cross-sectional view illustrating a structure of a pixel portion of a light emitting device.

FIG. 12 is a circuit diagram of a flip-flop circuit.

FIG. 13 is a top view of a flip-flop circuit.

FIG. 14 is a cross-sectional view of a flip-flop circuit.

15A to 15C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a liquid crystal display device.

16A to 16C are cross-sectional views illustrating a manufacturing process of a driver circuit and a pixel portion in a liquid crystal display device.

FIG. 17 is a cross-sectional view illustrating the structure of a liquid crystal display device.

FIG. 18 is a top view illustrating a manufacturing process of a pixel portion in a liquid crystal display device.

FIG. 19 is a top view illustrating a structure of a pixel portion of a liquid crystal display device.

FIG. 20 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 21 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 22 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 23 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 24 is a block diagram showing a structure of a light emitting device.

FIG. 25 is a block diagram showing a configuration of a liquid crystal display device.

26A and 26B are an external view and a cross-sectional view of a light-emitting device.

27A to 27C are diagrams of electronic devices each including a semiconductor device of the present invention.

FIG. 28 is a diagram showing a structure of a TFT used for simulation.

FIG. 29 is a diagram showing characteristics of TFTs obtained by simulation.

FIG. 30 is a diagram showing a step of crystallizing a semiconductor layer.

FIG. 31 is a diagram showing a circuit diagram of a general thin film transistor and a circuit diagram of a thin film transistor of the present invention.

FIG. 32 is a top view illustrating a structure of a pixel portion of a light emitting device.

FIG. 33 is a cross-sectional view of a thin film transistor of the invention.

FIG. 34 shows measured values of Id-Vgs characteristics of a general TFT.

FIG. 35 is a measured value of Id-Vgs characteristics of the TFT of the present invention.

FIG. 36 is an actual measurement value of Id-Vgs characteristics of the TFT of the present invention.

37A and 37B are a top view and a cross-sectional view of a TFT whose measured values are obtained.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H05B 33/14 A 21/8238 H01L 29/78 617N 27/08 331 612B 27/092 627A H05B 33/14 617S 27/08 321D (72) Inventor Mai Akiba 398 Hase, Atsugi City, Kanagawa Prefecture F-term in Semiconductor Energy Research Institute Co., Ltd. (reference) 2H092 GA59 JA24 JA35 JA36 JA40 KA04 KA07 KA12 KA18 MA05 MA08 MA13 MA17 MA29 MA30 NA22 NA27 PA06 3K007 AB05 AB18 BA06 BB07 DB03 GA04 5C094 AA22 AA24 BA03 BA27 BA43 CA19 DA15 EA04 EA07 5F048 AA09 AB10 AC04 BA16 BB01 BB02 BB04 BB09 BB11 BB12EE06 DD06EE06 DD06 EE02 BB02 DD06 BB02 DD02 BB02 BB02 BB07 BB02 EE23 EE28 EE30 EE38 FF02 FF03 FF04 FF10 FF28 FF29 FF30 FF36 GG01 GG02 GG13 GG25 GG34 GG43 GG45 GG47 HJ04 HJ12 HJ13 HJ23 HL03 HL04 HL11 HM15 NN03 NN04 NN23 NN24 NN25 NN27 NN35 NN36 NN72 NN73 PP01 PP02 PP03 PP04 PP29 PP34 PP35 QQ03 QQ11 QQ19 QQ23 QQ28

Claims (41)

[Claims] 1. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. A semiconductor device, wherein the electrodes are overlapped with each other with a channel formation region of the semiconductor film interposed therebetween. 2. A semiconductor device having a thin film transistor and a liquid crystal cell, wherein the thin film transistor has a first electrode, a first insulating film formed in contact with the first electrode, and the first electrode. A semiconductor film formed in contact with the insulation film, a second insulation film formed in contact with the semiconductor film, and a second electrode formed in contact with the second insulation film, The first electrode and the second electrode overlap with each other with a channel forming region of the semiconductor film interposed therebetween, and the liquid crystal cell includes a pixel electrode, a counter electrode, the pixel electrode and the counter electrode. A liquid crystal provided between the pixel electrodes, and the thin film transistor controls input of a video signal to the pixel electrode. 3. The semiconductor device according to claim 1, wherein when the thin film transistor is an n-channel TFT, the constant voltage is lower than a threshold voltage of the thin film transistor. 4. The semiconductor device according to claim 1, wherein when the thin film transistor is a p-channel TFT, the constant voltage is higher than a threshold voltage of the thin film transistor. 5. A semiconductor device having a first thin film transistor, a second thin film transistor, and an OLED, wherein the first and second thin film transistors are in contact with the first electrode and the first electrode. A first insulating film formed by: and a semiconductor film formed in contact with the first insulating film,
A second insulating film formed in contact with the semiconductor film and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are: The semiconductor films overlap with each other with a channel formation region interposed therebetween, and the OLED is provided between a third electrode, a fourth electrode, and the third electrode and the fourth electrode. An organic light emitting layer, and the first thin film transistor controls input of a video signal to the second electrode of the second thin film transistor, and the video signal input to the second electrode The drain current of the second thin film transistor is controlled by, and the drain current is input to the third electrode. 6. A semiconductor device having a first thin film transistor, a second thin film transistor, and an OLED, wherein the first and second thin film transistors are in contact with the first electrode and the first electrode. A first insulating film formed by: and a semiconductor film formed in contact with the first insulating film,
A second insulating film formed in contact with the semiconductor film and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are: The semiconductor films overlap with each other with a channel formation region interposed therebetween, and the OLED is provided between a third electrode, a fourth electrode, and the third electrode and the fourth electrode. An organic light emitting layer, and the first thin film transistor controls input of a video signal to the second electrode of the second thin film transistor, and the video signal input to the second electrode The drain current of the second thin film transistor is controlled by, the drain current is input to the third electrode, the first electrode and the second electrode of the second thin film transistor, Electricity to each other Wherein a connected to. 7. A semiconductor device comprising a first thin film transistor and a second thin film transistor, wherein the first and second thin film transistors include a first electrode,
A first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a second insulating film formed in contact with the semiconductor film, A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. The semiconductor device is overlapped, and the first electrode and the second electrode of the second thin film transistor are electrically connected to each other. 8. A semiconductor device having a first thin film transistor and a second thin film transistor, wherein the first and second thin film transistors include a first electrode,
A first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a second insulating film formed in contact with the semiconductor film, A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. The first electrode and the second electrode of the second thin film transistor, which are overlapped with each other, are connected to each other through a contact hole formed in the first insulating film and the second insulating film. A semiconductor device characterized by the above. 9. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. First and second thin film transistors each having a second insulating film formed by: and a second electrode formed in contact with the second insulating film; covering the second electrode; A semiconductor device comprising: a third insulating film formed on a second insulating film; and a wiring formed on the third insulating film, wherein the first electrode and the second electrode Are overlapped with each other with a channel formation region of the semiconductor film sandwiched therebetween, and the wiring is formed through the second contact hole formed in the first and second insulating films, and the second wiring is formed. In contact with the first electrode of the thin film transistor, and
The second thin film transistor has the second thin film transistor through the first contact hole formed in the third insulating film.
A semiconductor device, which is in contact with the electrode of. 10. A semiconductor device including a pixel portion having a first thin film transistor and a liquid crystal cell, and a drive circuit having a second thin film transistor, wherein the first and second thin film transistors have a first electrode. ,
A first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a second insulating film formed in contact with the semiconductor film, A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. The liquid crystal cell is overlapped and has a pixel electrode, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode, and is generated in the drive circuit by the first thin film transistor. Input of a video signal to the pixel electrode is controlled, and the first electrode and the second electrode of the second thin film transistor are electrically connected to each other. . 11. A semiconductor device including a pixel portion having a first thin film transistor and a liquid crystal cell, and a drive circuit having a second thin film transistor, wherein the first and second thin film transistors have a first electrode. ,
A first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a second insulating film formed in contact with the semiconductor film, A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. The liquid crystal cell is overlapped and has a pixel electrode, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode, and is generated in the drive circuit by the first thin film transistor. Input of a video signal to the pixel electrode is controlled, and the first electrode and the second electrode included in the second thin film transistor are formed in the first insulating film and the second insulating film. Through the contact holes provided A semiconductor device characterized by being provided. 12. A semiconductor device including a pixel portion having a first thin film transistor, a second thin film transistor and an OLED, and a drive circuit having a third thin film transistor, wherein the first, second and third thin film transistors are provided. Is formed in contact with the first electrode, the first insulating film formed in contact with the first electrode, the semiconductor film formed in contact with the first insulating film, and the semiconductor film. A second insulating film,
A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. Overlapping, the OLED includes a third electrode, a fourth electrode, and an organic light emitting layer provided between the third electrode and the fourth electrode, and the first thin film transistor Controls the input of a video signal to the second electrode of the second thin film transistor, and controls the drain current of the second thin film transistor by the video signal input to the second electrode. The drain current is input to the third electrode, and the first and second drain electrodes are included in the first and second thin film transistors.
The semiconductor device, wherein the electrode and the second electrode are electrically connected to each other. 13. A semiconductor device including a pixel portion having a first thin film transistor, a second thin film transistor and an OLED, and a drive circuit having a third thin film transistor, wherein the first, second and third thin film transistors are provided. Is formed in contact with the first electrode, the first insulating film formed in contact with the first electrode, the semiconductor film formed in contact with the first insulating film, and the semiconductor film. A second insulating film,
A second electrode formed in contact with the second insulating film, and the first electrode and the second electrode sandwich a channel formation region of the semiconductor film therebetween. Overlapping, the OLED includes a third electrode, a fourth electrode, and an organic light emitting layer provided between the third electrode and the fourth electrode, and the first thin film transistor Controls the input of a video signal to the second electrode of the second thin film transistor, and controls the drain current of the second thin film transistor by the video signal input to the second electrode. The drain current is input to the third electrode, and the first and second drain electrodes are included in the first and second thin film transistors.
The semiconductor device is characterized in that the electrode and the second electrode are connected via a contact hole formed in the first insulating film and the second insulating film. 14. The method according to claim 12 or 13, wherein in the third thin film transistor, when the first electrode and the second electrode are electrically separated from each other, the first electrode is grounded. A semiconductor device, wherein the threshold value of the third thin film transistor when a voltage is applied and the threshold value of the third thin film transistor when a ground voltage is applied to the second electrode are substantially the same. 15. The first thin film transistor according to claim 5, wherein the first electrode and the second electrode are electrically separated from each other in the second thin film transistor. The threshold value of the second thin film transistor when a ground voltage is applied to the electrode and the threshold value of the second thin film transistor when a ground voltage is applied to the second electrode are substantially the same. Semiconductor device. 16. The method according to claim 5, wherein when the first thin film transistor is an n-channel TFT, the first electrode of the first thin film transistor is provided on the first electrode of the first thin film transistor. A semiconductor device, wherein a constant voltage lower than a threshold voltage is applied. 17. The method according to claim 5, wherein when the first thin film transistor is a p-channel TFT, the first electrode of the first thin film transistor has a first electrode of the first thin film transistor. A semiconductor device, wherein a constant voltage higher than a threshold voltage is applied. 18. The semiconductor device according to claim 5, wherein the semiconductor film has an impurity region formed with a channel formation region interposed therebetween. 19. The semiconductor film according to claim 5, wherein the semiconductor film has a first impurity region in contact with a channel formation region and a second impurity region in contact with the first impurity region. And the impurity concentration in the first impurity region is
The semiconductor device is characterized in that the impurity concentration is lower than the impurity concentration in the impurity region. 20. The dielectric constant according to claim 1, wherein the first insulating film and the second insulating film have substantially the same dielectric constant, and the first insulating film has the same dielectric constant. 1. A semiconductor device, wherein a film thickness in a portion overlapping with the first electrode and a film thickness in a portion overlapping with the second electrode of the second insulating film are substantially the same. 21. The film thickness of the first insulating film in a portion where the channel formation region and the first electrode overlap with each other, according to any one of claims 1 to 19, wherein: If the film thickness of the second insulating film in the portion where the channel forming region and the second electrode overlap is d2,
| D1-d2 | /d1≦0.1, and | d1-d2 | /
A semiconductor device characterized by satisfying d2 ≦ 0.1. 22. The film thickness of the first insulating film in a portion where the channel forming region and the first electrode overlap with each other, according to any one of claims 1 to 19, wherein: If the film thickness of the second insulating film in the portion where the channel forming region and the second electrode overlap is d2,
| D1-d2 | /d1≦0.05, and | d1-d2 |
A semiconductor device satisfying /d2≦0.05. 23. The semiconductor device according to claim 1, wherein the first insulating film is planarized by chemical mechanical polishing. 24. The semiconductor device according to claim 23, wherein the flattened first insulating film has a height difference of unevenness of 5 nm or less on the surface. 25. The semiconductor device according to claim 23, wherein the flattened first insulating film has a height difference of unevenness of 1 nm or less on the surface. 26. Any one of claims 23 to 25.
In the paragraph, the film thickness of the planarized first insulating film in a portion where the channel formation region and the first electrode overlap each other is set to d1, and the channel formation region and the second electrode overlap each other. The film thickness of the second insulating film in the area where
2, then | d1-d2 | /d1≦0.1, and | d
A semiconductor device characterized by satisfying 1-d2 | /d2≦0.1. 27. Any one of claims 23 to 25.
In the paragraph, the film thickness of the planarized first insulating film in a portion where the channel formation region and the first electrode overlap each other is set to d1, and the channel formation region and the second electrode overlap each other. The film thickness of the second insulating film in the area where
2, then | d1-d2 | /d1≦0.05, and |
A semiconductor device characterized by satisfying d1-d2 | /d2≦0.05. 28. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The display device is characterized in that the electrodes are overlapped with each other with a channel formation region of the semiconductor film interposed therebetween. 29. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. A digital still camera, wherein the electrodes are overlapped with each other with a channel forming region of the semiconductor film interposed therebetween. 30. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The notebook personal computer, wherein the electrodes are overlapped with each other with a channel forming region of the semiconductor film interposed therebetween. 31. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The mobile computer is characterized in that the electrodes are overlapped with each other with a channel formation region of the semiconductor film interposed therebetween. 32. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The image reproducing device is characterized in that the electrodes are overlapped with each other with a channel forming region of the semiconductor film interposed therebetween. 33. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The goggle type display is characterized in that the electrodes are overlapped with each other with a channel forming region of the semiconductor film interposed therebetween. 34. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The video camera is characterized in that the electrodes are overlapped with each other with a channel forming region of the semiconductor film interposed therebetween. 35. A first electrode, a first insulating film formed in contact with the first electrode, a semiconductor film formed in contact with the first insulating film, and a semiconductor film formed in contact with the semiconductor film. A semiconductor device using a thin film transistor having a second insulating film formed by: and a second electrode formed in contact with the second insulating film, wherein the first electrode and the second electrode are formed. The mobile phone is characterized in that the electrodes are overlapped with each other with the channel formation region of the semiconductor film interposed therebetween. 36. A step of forming a first electrode and a second electrode on an insulating surface; a step of forming a first insulating film in contact with the first electrode and the second electrode; Forming a first semiconductor film and a second semiconductor film in contact with the first insulating film, a step of forming a second insulating film in contact with the first and second semiconductor films, and Etching the insulating film and the second insulating film to expose a part of the first electrode; and a third step of contacting the second insulating film and contacting a part of the first electrode. And a fourth electrode in contact with the second insulating film, the first electrode and the third electrode sandwich the first semiconductor film between them. And the second electrode and the fourth electrode are overlapped with each other with the second semiconductor film interposed therebetween. A method for manufacturing a semiconductor device, characterized in that they are in conflict with each other. 37. A step of forming a first electrode and a second electrode on an insulating surface; a step of forming a first insulating film in contact with the first electrode and the second electrode; Planarizing the insulating film by chemical mechanical polishing to form a first semiconductor film and a second semiconductor film in contact with the planarized first insulating film, and the first semiconductor film and the second semiconductor film. Forming a second insulating film in contact with the semiconductor film, and etching the planarized first insulating film and the second insulating film to expose a part of the first electrode. Forming a third electrode in contact with the second insulating film and in contact with a portion of the first electrode, and a fourth electrode in contact with the second insulating film, The first electrode and the third electrode are overlapped with each other with the first semiconductor film interposed therebetween. The method for manufacturing a semiconductor device, wherein the second electrode and the fourth electrode are overlapped with each other with the second semiconductor film interposed therebetween. 38. A step of forming a first electrode and a second electrode on an insulating surface; a step of forming a first insulating film in contact with the first electrode and the second electrode; Forming a first semiconductor film and a second semiconductor film in contact with the insulating film, and forming a second insulating film in contact with the first semiconductor film and the second semiconductor film; Forming a third electrode and a fourth electrode in contact with the insulating film, and forming a third insulating film in contact with the second insulating film, covering the third electrode and the fourth electrode. And a step of etching the first insulating film, the second insulating film, and the third insulating film to expose a part of the first electrode and a part of the third electrode, Forming a wiring in contact with a part of the first electrode and a part of the third electrode, And the third electrode sandwich and overlap the first semiconductor film, and the second electrode and the fourth electrode sandwich the second semiconductor film. A method for manufacturing a semiconductor device, wherein: 39. A step of forming a first electrode and a second electrode on an insulating surface; a step of forming a first insulating film in contact with the first electrode and the second electrode; Planarizing the insulating film by chemical mechanical polishing, forming a first semiconductor film and a second semiconductor film in contact with the planarized first insulating film, and the first semiconductor film And a step of forming a second insulating film in contact with the second semiconductor film, a step of forming a third electrode and a fourth electrode in contact with the second insulating film, the third electrode and the fourth electrode Forming a third insulating film in contact with the second insulating film so as to cover the electrode, and forming the flattened first insulating film, the second insulating film, and the third insulating film. Etching to expose a portion of the first electrode and a portion of the third electrode; Forming a wiring in contact with a part of the electrode and a part of the third electrode, the first electrode and the third electrode sandwich the first semiconductor film between them. 2. The method for manufacturing a semiconductor device, wherein the second electrode and the fourth electrode are overlapped with each other with the second semiconductor film interposed therebetween. 40. Any one of claims 36 to 39.
In the paragraph 1, the first semiconductor film has a channel formation region and an impurity region sandwiching the channel formation region, and the first electrode and the third electrode have the channel formation region. A method for manufacturing a semiconductor device, characterized in that 41. Any one of claims 36 to 40.
In the paragraph, the second semiconductor film has a channel formation region and an impurity region sandwiching the channel formation region, and the second electrode and the fourth electrode are the channel formation region. A method for manufacturing a semiconductor device, characterized in that