KR101786222B1 - Interconnect structure having an etch stop layer over conductive lines - Google Patents

Abstract

A multilayer interconnect structure for an integrated circuit includes a first dielectric layer on the substrate and a conductive line partially exposed over the first dielectric layer. Such a structure further comprises an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and etch stop layer provide via holes that partially expose the conductive lines. Such a structure further includes vias disposed in the via holes, and other conductive lines disposed over the vias and coupled to the conductive lines through the vias. A method of forming a multilayer interconnect structure is also disclosed. The etch stop layer reduces the lateral and vertical etch of the first and second dielectric layers when via holes are misaligned due to overlay errors.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an interconnect structure having an etch stop layer on a conductive line. ≪ Desc / Clms Page number 1 >

The present disclosure relates to an interconnect structure having an etch stop layer over a conductive line.

The semiconductor integrated circuit (IC) industry is experiencing rapid growth. Technological advances in IC materials and design have created generations of ICs, each with smaller and more complex circuits than previous generations. During the course of IC innovation, while the functional density (i. E., The number of interconnected devices per chip area) is generally increased, the geometric shape size (i. E., The smallest component ) Was decreased. This scaling down process generally offers advantages by increasing production efficiency and reducing associated costs. Such reduction has also increased the complexity of the processing and manufacturing of the IC and requires similar development in IC processing and fabrication to achieve this advancement.

For example, an IC is formed by connecting several devices (transistors, resistors, capacitors, etc.) using multilayer interconnects. In a typical multi-layer interconnect structure, a conductive line (e.g., copper wire) is placed in a stacked dielectric layer and is connected from one layer to another via a via. Typically, copper wires and vias are fabricated using a single or dual damascene process. In such a process, the underlying dielectric layer is patterned to form trenches, then the trenches are overfilled with copper, and the excess copper is removed using chemical-mechanical planarization (CMP) To form a copper wire in the trench. Subsequently, another dielectric layer is formed on the underlying dielectric layer and the process described above is repeated to form vias and top level copper wires. The multilayer dielectric layer is patterned by a lithographic (or photolithographic) process. Often, overlay errors between lithographic processes may result in via misalignment for the target copper wire. Misaligned vias can cause nearby copper wires and accidental bridges (shorts), creating IC defects; May cause excessive etching of the underlying dielectric layer, creating IC reliability problems. Such via-wire misalignment is becoming increasingly problematic as IC miniaturization continues.

In one exemplary aspect, the present disclosure is directed to a device. Such an element comprises a substrate, a first dielectric layer on the substrate, and a conductive line partially embedded in the first dielectric layer. A first portion of the conductive line is disposed within the first dielectric layer and a second portion of the conductive line is disposed over the first dielectric layer. The device further comprises an etch stop layer on top of both the first dielectric layer and the conductive line. The device further comprises a second dielectric layer over the etch stop layer. The etch stop layer includes a dielectric material that is different from the material of the first and second dielectric layers. The second dielectric layer and etch stop layer provide openings that partially expose the conductive lines. The device further includes a via disposed in the opening and coupled to the conductive line.

In another illustrative aspect, this disclosure is directed to a method for fabricating a multilayer interconnect structure for an integrated circuit. The method includes providing a device comprising a substrate, a first dielectric layer over the substrate, and a conductive line that lies within the first dielectric layer, wherein the upper surface of the conductive line and the upper surface of the first dielectric layer are coplanar . The method further includes recessing the upper surface of the first dielectric layer such that a first portion of the conductive line is above the first dielectric layer. The method further includes depositing an etch stop layer over both the first dielectric layer and the first portion of the conductive line. The method further comprises depositing a second dielectric layer over the etch stop layer. The method further comprises performing an etch process for the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive lines, wherein the etch rate of the etch stop layer in such an etch process is Is slower than the etch rate of the second dielectric layer in the etching process. The method further includes forming a via in the via hole.

In another illustrative aspect, this disclosure is directed to a method for fabricating a multilayer interconnect structure for an integrated circuit. The method includes providing a device comprising a substrate, a first dielectric layer over the substrate, and a conductive line that lies within the first dielectric layer, wherein the upper surface of the conductive line and the upper surface of the first dielectric layer are coplanar . The method further includes the step of recessing the upper surface of the first dielectric layer such that a first portion of the conductive line is exposed above the upper surface of the first dielectric layer. The method further comprises forming an etch stop layer over the first portion of the first dielectric layer and the conductive line, such etch stop layer having a conformal cross-sectional profile. The method further comprises depositing a second dielectric layer over the etch stop layer, wherein the first and second dielectric layers are made of the same material. The method further includes etching the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive line, wherein the etch stop layer is etched to a level lower than the etch rate of the second dielectric layer . The method further includes forming a via in the via hole.

BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be best understood from the following detailed description when considered in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, for clarity, the dimensions of various features can be arbitrarily enlarged or reduced.
1A and 1B are a top view and a cross-sectional view of a multi-layer interconnect of an IC constructed in accordance with various aspects of the present disclosure.
Figures 2a and 2b are top and cross-sectional views illustrating multilayer interconnects of an IC with via-wire misalignment to illustrate aspects of the present disclosure.
Figure 3 shows a flow diagram of a method of manufacturing an IC having multilayer interconnects of Figures 1A and 1B, in accordance with some embodiments.
Figures 4, 5, 6, 7, 8, 8a, 9, and 10 are cross-sectional views of forming a multilayer interconnect for an IC according to the method of Figure 3, in accordance with some embodiments.
11 shows a flow diagram of another method of manufacturing an IC having multilayer interconnects, in accordance with some embodiments.
12A, 12B, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B are cross-sectional views of forming a multilayer interconnect for an IC according to the method of FIG. 11, in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, for implementing different features of the claimed subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, such specific examples are merely illustrative and not restrictive. For example, in the following description, forming the first feature on or on the second feature may include embodiments in which the first and second features are formed in direct contact, May be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations disclosed.

Also, for ease of description to describe a relationship to one element or feature (s) or feature (s) of a feature, as shown in the Figures, the terms " Spatially relative terms such as " stomach ", "upper ", etc. may be used herein. Such spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientations shown in the figures It will be possible for the device to be oriented differently (rotated 90 degrees or in other orientations) and the spatially relative description used herein may be similarly interpreted accordingly.

The present disclosure relates generally to semiconductor devices. More particularly, this disclosure relates to a multi-layer interconnect structure for an integrated circuit (IC). It is an object of the present disclosure to provide a protective layer over a conductive line in a multilayer interconnect. In the case of via-wire misalignment due to lithography overlay errors when forming via holes, the protective layer minimizes lateral and vertical over-etching of the underlying dielectric layer. This effectively prevents the vias from accidentally short-circuiting with nearby wires. It also improves device reliability by limiting electron migration (EM) and time-dependent dielectric breakdown (TDDB) associated with diffusion of the metal into underlying dielectric layers.

FIG. 1A shows a top view of a semiconductor device 100, and FIG. 1B shows a cross-sectional view of a semiconductor device 100 along the line "1-1" of FIG. 1A. 1A and 1B, a semiconductor device 100 includes a substrate 102 and a multi-layer interconnect structure 103 constructed in accordance with the present disclosure. For simplicity, interconnect structure 103 is shown having two layers of conductive lines. The first layer includes conductive lines 106A and 106B (collectively, 106A / B), and the second layer includes conductive lines 116A. The two layers are interconnected via vias 112A. It should be noted that, in various embodiments, the interconnect structure 103 may include more than two layers of conductive lines, such as five, seven, or more layers in a complex IC. In addition, the interconnect structure 103 may include one or more layers of conductive lines below the 106A / B layer and / or above the 116A layer.

In an embodiment, the substrate 102 comprises a silicon substrate (e.g., a wafer). Alternatively, substrate 102 may comprise another elemental semiconductor such as germanium; A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium paraben, and / or indium antimonide; An alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or a combination thereof. In yet another alternative, the substrate 102 is a semiconductor on insulator (SOI). The substrate 102 may be a p-type field effect transistor (PFET), an n-type FET (NFET), a metal-oxide semiconductor field effect transistor (MOSFET), a complementary metal- Transistors, bipolar transistors, high voltage transistors, and active devices such as high frequency transistors. The transistor may be a planar transistor or a multi-gate transistor such as a FinFET. The substrate 102 may further include passive components such as resistors, capacitors, and inductors.

An interconnect structure 103 is built on the substrate 102 and connects various active and / or passive components within the substrate 102 to form an IC. In the illustrated embodiment, the interconnect structure 103 comprises a first dielectric layer 104, which may be a low dielectric constant (low-K) dielectric material such as tetraethylorthosilicate (TEOS) oxide, Or a doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / Dielectric material.

The interconnect structure 103 further includes conductive lines 106A and 106B that are partially within the dielectric layer 104 and partially over the dielectric layer 104. [ Although not shown, a conductive line 106A / B may be formed through a layer of another lower portion of the interconnect structure 103 or through a layer of active and / or passive elements (e.g., source, drain, and gate contact) Or passive elements within the substrate 102. The active and / In an embodiment, each of the conductive lines 106A and 106B includes an electrically conductive metal-diffusion barrier layer as an outer layer and a metal conductor as an inner layer. For example, the barrier layer may comprise tantalum (Ta) or tantalum nitride (TaN) and the metal conductor may comprise copper (Cu), aluminum (Al), tungsten (W), cobalt Lt; / RTI > In an embodiment, the barrier layer comprises a layer of one or more materials.

The interconnect structure 103 further includes an etch stop layer 108 and a second dielectric layer 110. An etch stop layer 108 is formed over the first dielectric layer 104 and the conductive lines 106A / B and has a conformal cross-sectional profile in this embodiment. A dielectric layer 110 is formed over the etch stop layer 108. In various embodiments, the dielectric layer 110 may be a low dielectric constant dielectric material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or borophosphosilicate glass (BPSG), fused silica glass (FSG) , Phosphosilicate glass (PSG), doped silicon oxide such as boron doped silicon glass (BSG), and / or other suitable dielectric materials. The dielectric layers 104 and 110 may comprise the same or different dielectric material (s). The etch stop layer 108 comprises a dielectric material having a higher density than the materials in the dielectric layers 110 and 104. For example, it will have the etching stop layer 108 may comprise a material selected from the group consisting of SiCN, SiCO, SiO _2, SiN, and AlON. Other suitable materials for etch stop layer 108 are included in this disclosure.

Dielectric layer 110 and etch stop layer 108 together provide an opening in which vias 112A are located. The interconnect structure 103 further includes a third dielectric layer 114 on which a conductive line 116A is placed. In an embodiment, the dielectric layers 114 and 110 may comprise the same or different materials. Vias 112A and conductive lines 116A each include an electrically conductive metal-diffusion barrier layer surrounding the metal conductor, as described above for conductive lines 106A / B, although different materials may be used .

In an embodiment, the conductive lines 106A / B and the vias 112A are formed in separate damascene processes, and each damascene process includes lithographic patterning of each dielectric layer 104 and 110. As a result, a lithography overlay error between the via 112A and the conductive line 106A must be taken into account during the fabrication of the device 100. [

As shown in FIGS. 1A and 1B, the vias 112A are properly aligned with the conductive lines 106A, that is, the vias are overlapped with the center lines of the conductive lines in a top view, Lt; RTI ID = 0.0 > 106A. ≪ / RTI > This is an ideal case for manufacturing. However, as it is virtually impossible to eliminate lithographic overlay errors, misalignment between the via and the underlying conductive lines occurs in some ICs or in some portions of the ICs. This is illustrated in FIGS. 2A and 2B, wherein FIG. 2A is a top view of the device 200, and FIG. 2B is a cross-sectional view of the semiconductor device 200 along the line "2-2" of FIG. 2A. The device 200 is similar in many respects to the device 100. However, during fabrication of device 200, an overlay error (E), defined as a misalignment between the respective center lines of the via and the conductive line, is generated between the via 112A and the conductive line 106A. Overlay error E may be caused by variations in lithography and etching processes such as lithographic light sources, resist materials, resist development processes, etch processes, and the like. The overlay error E may be within the process variation window, but may cause quality and / or reliability problems for the device 200 if not properly handled. In a typical multi-layer interconnect structure, there is no etch stop layer 108. Instead, the conductive lines 106A and 106B may be completely embedded in the dielectric layer 104. Misaligned via holes on the conductive lines 106A may cause excessive etching of the underlying dielectric layer 104 and the etching rate of such dielectric layer 104 is typically large ). As a result, the lateral distance D between the via 112A and the adjacent conductive line (e. G., Conductive line 106B) can be very small and can cause bridging therebetween will be.

In this embodiment, the thickness TH of the etch stop layer 108 is formed to be larger than the overlay error E. This effectively limits the etching of the via holes to occur in the sidewalls of the etch stop layer 108. In addition, the etch stop layer 108 has an etch rate lower than the dielectric layers 110 and 104. For example, during the via hole etching process, the etch of the etch stop layer 108 may be three times slower than the etch of the dielectric layers 110 and 104. This effectively limits the lateral and vertical etch of the dielectric layers 110 and 104 when the via holes are substantially misaligned with the conductive lines 106A, as shown in FIG. 2B. As a result, the lateral distance D between the via 112A and the neighboring conductive line 106B is advantageously greater in this embodiment than a conventional interconnect structure, for the same amount of overlay error. In addition, the etch stop layer 108 serves as an additional diffusion barrier layer over the metal material in the conductive lines 106A / B, which reduces electron migration (EM) and time-dependent dielectric breakdown (TDDB) Thereby improving device reliability. A method of manufacturing the interconnect structure 103 will be described below.

3 illustrates a flow diagram of a method 300 of forming a semiconductor device having a multi-layer interconnect structure, such as semiconductor device 100 having a multi-layer interconnect structure 103, according to various aspects of the present disclosure. do. The method 300 is illustrative only and is not intended to limit the present disclosure beyond what is explicitly recited in a claim. For additional embodiments of the method, it is contemplated that additional processes may be provided before, during, and after method 300, and that some of the processes described may be replaced, removed, or moved have. The method 300 will now be described in conjunction with FIGS. 4-12, which are cross-sectional views of the semiconductor device 100 at various stages of the manufacturing process.

At step 302, the method 300 (FIG. 3) receives the element 100 as shown in FIG. The device 100 (FIG. 4) includes a substrate 102, a dielectric layer 104, and a conductive line 106A / B embedded in the dielectric layer 104. The composition of the substrate 102, the dielectric layer 104, and the conductive lines 106A / B has been described above with reference to Figs. 1A and 1B. Dielectric layer 104 and conductive lines 106A / B may be formed on substrate 102 by a variety of processes including deposition, lithography, etching, and CMP processes, as described below .

In an embodiment, dielectric layer 104 includes a low dielectric constant dielectric material and is chemically stable, such as low pressure CVD (LPCVD), plasma enhanced chemical vapor deposition (PECVD), flowable CVD (FCVD) Is deposited on the substrate 102 by vapor deposition (CVD) techniques. For example, the FCVD process may include depositing a flowable material (e.g., a liquid compound) over the substrate 102 to fill the various trenches at the top, and depositing the flowable material < RTI ID = 0.0 > Into a solid material. The dielectric layer 104 is then planarized or otherwise recessed by a CMP process to have a planar top surface.

Subsequently, the dielectric layer 104 is patterned with one or more lithographic and etch processes to form trenches therein. The lithographic process may include forming a photoresist (or resist) layer overlying the dielectric layer 104, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to include a resist To form a masking element. The trenches are then etched into the dielectric layer 104 using masking elements. The etching process may include dry etching, wet etching, and / or other suitable processes.

Thereafter, an electrically conductive barrier / adhesive layer and a metal (e.g., copper) conductor layer are deposited over the patterned dielectric layer 104 by one or more of techniques such as sputtering, CVD, and electrolytic or electroless plating Lt; / RTI > The barrier and metal conductor layers overfill the trenches in the dielectric layer 104. Thereafter, a CMP process is performed to planarize the top surface of the device 100, thereby removing the excess barrier and metal material on the dielectric layer 104. Barriers and metal materials remain in the trenches, forming conductive lines 106A / B. As a result of the CMP process, the top surface 104 'of the dielectric layer 104 and the top surface 106' of the conductive lines 106A / B are coplanar.

At step 304, the method 300 (FIG. 3) recesses the dielectric layer 104 to partially expose the conductive lines 106A / B. Referring to FIG. 5, dielectric layer 104 is recessed and exposed such that a first portion of conductive line 106A / B has a height H above the top surface 104 'in the "z" direction. The remaining portion of the conductive line 106A / B is still embedded in the dielectric layer 104. [ In an embodiment, the conductive lines 106A / B comprise copper and the process 304 comprises a reactive ion etching (RIE) process adapted for the recessing of the dielectric layer 104. The conductive lines 106A / B remain substantially unchanged in the RIE process. However, the edge of the conductive line 106A / B between the top surface of the conductive line and the sidewall surface begins to be rounded during the etching process. The height H is one of the factors that determine how large the vertical protection etch stop layer 108 (FIG. 2B) will provide. If the height H is too low, misaligned via holes will penetrate the etch stop layer 108 and reach into the dielectric layer 104. By controlling the etch time and etch rate of the dielectric layer 104 in the RIE process, the desired height H can be obtained. In an embodiment, the height H is controlled to be within a range of about 1 nanometer (nm) to about 7 nm.

At step 306, the method 300 (FIG. 3) deposits the etch stop layer 108 over the dielectric layer 104 and exposes the conductive lines 106A / B. Referring to Figure 6, in this embodiment, the etch stop layer 108 is deposited to have a conformal cross-sectional profile in the " xz "plane and both the top and sidewall surfaces of the conductive lines 106A / do. In this embodiment, the rounded edges of the conductive lines 106A / B help conformal deposition of the etch stop layer 108. In an embodiment, an etch stop layer 108 is deposited using atomic layer deposition (ALD) techniques. Also, the etching stop layer 108 is formed so as to have a sidewall thickness TH. The sidewall thickness TH is controlled to be thicker than the maximum lithography overlay error allowed by the manufacturing process. This effectively prevents misaligned via holes from being excessively etched laterally (in the "x" direction). In the example, the thickness (TH) ranges from about 1 nm to about 7 nm. In an alternative embodiment, the etch stop layer 108 does not have a conformal cross-sectional profile in the "xz" plane, but its sidewall thickness TH is still thicker than the maximum lithographic overlay error allowed by the manufacturing process . In various embodiments, the etch stop layer 108 comprises a material having a higher density than the dielectric layer 104. In one example, the dielectric layer 104 comprises porous carbon-doped silicon dioxide and the etch stop layer 108 comprises undoped silicon dioxide. In various embodiments, there will be a etch stop layer 108 may comprise a material such as SiCN, SiCO, SiO _2, SiN, and AlON.

At step 308, a method 300 (FIG. 3) deposits a second dielectric layer 110 over the etch stop layer 108. Referring to FIG. 7, the dielectric layer 110 may use the same material as the dielectric layer 104. Alternatively, the dielectric layer 110 may utilize different low dielectric constant materials. In various embodiments, the dielectric layer 110 may be formed from a dielectric material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or borophosphosilicate glass (BPSG), fused silica glass (FSG) Doped silicon oxide such as for example polysilicon glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The dielectric layer 110 may be formed using chemical vapor deposition (CVD), such as LPCVD, PECVD, and FCVD. The upper surface of the dielectric layer 110 is planarized.

At step 310, the method 300 (FIG. 3) etches the via hole 111 through at least the dielectric layer 110 and the etch stop layer 108 to partially expose the conductive line 106A. In an embodiment, the via hole 111 is formed as part of a single damascene process (shown in Figures 8 to 10) or a dual damascene process (shown in Figures 11 to 16b), which will be described separately hereinbelow Etched.

Referring to FIG. 8, there is shown a device 100 having a via hole 111 etched through a dielectric layer 110 and an etch stop layer 108. The via hole 111 exposes a part of the upper surface of the conductive line 106A, but does not expose the side wall surface of the conductive line 106A. In this embodiment, the via hole 111 is formed by one or more lithography and etching processes. The lithographic process may include forming a resist layer overlying the dielectric layer 110, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a masking element comprising the resist . The trenches are then etched into the dielectric layer 110 and etch stop layer 108 using a masking element until the conductive lines 106 are exposed. The etching process may include dry etching, wet etching, and / or other suitable processes.

In an embodiment, a lithographic process for patterning the dielectric layer 104 and a lithographic process for patterning the dielectric layer 110 use two separate masks (or photomasks). The conductive line 106A is represented as a trench in one mask used by a previous process and the via hole 111 is represented as another trench in another mask used by a subsequent process. Due to process variations, a specific misalignment (or overlay error) may exist between the via hole 111 and the conductive line 106A. As shown in Fig. 8A, the via hole 111A is not properly aligned with the conductive line 106A due to the overlay error E. As a result, the via hole 111A not only exposes the upper surface of the conductive line 106A, but also exposes a part of the side wall surface of the conductive line 106A. In the absence of the etch stop layer 108, such misalignment may create at least two negative effects. One negative effect is that the etch process can excessively etch the dielectric layer 110 laterally (along the "x" direction) due to its large etch rate. This can undesirably reduce the distance D between the via to be formed and the neighboring conductive line 106B, thereby causing cross-linking defects (electrical shorts). Another negative effect is that the etch process can over-etch the dielectric layer 104 in the vertical direction (along the "z" direction) due to its large etch rate. This may cause metal diffusion into the dielectric layer 104, resulting in a long-term reliability problem for the IC. In this embodiment, the etch stop layer 108 has a lower etch rate than the dielectric layers 110 and 104, which reduces the lateral and vertical etch of the via hole 111A. Also, the sidewall thickness TH of the etch stop layer 108 is formed to be larger than the overlay error E. This ensures that the bottom portion of the via hole 111A is confined within the etch stop layer 108 and the conductive line 106A. In addition, the etch stop layer 108 over the conductive lines 106A / B serves as an additional protection against cross-linking, EM, and TDDB defects. In summary, the presence of the etch stop layer 108 prevents defects and reliability problems associated with a certain amount of overlay error between the via and underlying conductive lines. This is one of the advantages provided by the present disclosure, which is superior to conventional multilayer interconnect structures.

At step 312, the method 300 (FIG. 3) forms a via 112A in the via hole 111 of FIG. Referring to FIG. 9, vias 112A include at least one barrier layer and a metal conductor layer. In one example, the barrier layer (s) may comprise tantalum (Ta) or tantalum nitride (TaN) and the metal conductor may comprise copper (Cu), aluminum (Al), tungsten (W), cobalt Or other suitable metals. The barrier layer may be formed by CVD, physical vapor deposition (PVD), or ALD techniques, and metal conductors may be formed by sputtering, CVD, or electroplating techniques. The barrier layer and the metal conductor over fill the via hole 111 using the above-described film forming method. Subsequently, a CMP process is performed to remove excess material on the top surface of dielectric layer 110, thereby leaving the remaining barrier layer and metal conductor as vias 112A.

At step 314, the method 300 (FIG. 3) forms another conductive line, or conductive line 116A, coupled to the conductive line 106A through the via 112A. 10, a dielectric layer 114 is formed over the dielectric layer 110 and a conductive line 116A is placed in the dielectric layer 114 and electrically coupled to the conductive line 106A through the via 112A. . The dielectric layer 114 may comprise dielectric materials that are the same or different than the dielectric layers 110 and 104. In various embodiments, the composition of the conductive line 116A is substantially the same as the conductive line 106A. In an embodiment, process 314 includes depositing a low dielectric constant dielectric layer 114 over the dielectric layer 110, etching the dielectric layer 114 to form a trench therein, depositing the trench in an electrically conductive barrier / Overfilling the adhesive layer and the metal conductor, and planarizing the upper surface of the device 100 to remove the excess barrier layer and the metal conductor. The method 300 may proceed to an additional step for completing the fabrication of the device 100, for example, by fabricating an additional conductive layer of the interconnect structure 103.

Figures 11 to 16B illustrate the formation of vias 112A and conductive lines 116A using a dual damascene process. Referring to Figure 11, a method 400 of forming a semiconductor device having a multi-layer interconnect structure, such as semiconductor device 100 having a multi-layer interconnect structure 103, according to various aspects of the present disclosure, . The method 400 may be viewed as an embodiment of the method 300 (FIG. 3), and the method 400 proceeds from the process 308 and in the dual damascene process, the via 112A and the conductive line 116A ). The method 400 is briefly described below in conjunction with Figures 12A-16B. 12a, 13a, 14a, 15a, and 16a illustrate a cross-sectional view of semiconductor device 100 during various fabrication steps, while Figures 12b, 13b, 14b, 15b, 200). ≪ / RTI > Devices 100 and 200 may be different portions of the same IC or portions of different ICs. The devices are arranged side by side for purposes of illustration.

In step 402, the method 400 etches a track trench 113 in the second dielectric layer 110. [ 12A and 12B, the track trench 113 is a placeholder for the conductive line 116A.

At step 404, the method 400 performs a lithography process to form a via trench 111 over the track trench 113. [ Referring to Figures 13A and 13B, an exemplary lithographic process using a layer of three materials (three-layer lithography) is shown. Three layers are: a bottom layer (BL) 118, an intermediate layer (ML) 120, and a resist 122. The ML 120 is formed over the BL 118 and the resist 122 is formed over the ML 120 and the photolithography process is completed To provide a via trench 111 therein. 13A, in the fabrication of the device 100, the via trench 111 is properly aligned with the conductive line 106A. 13B, due to the lithographic overlay error E, in the fabrication of the device 200, the via trench 111 is misaligned with the conductive line 106A.

In step 406, which is an embodiment of process 310, the method 400 performs one or more etch processes to extend the via trench 111 into the various underlying layers. 14A and 14B, the BL 118, the second dielectric layer 110, and the etch stop layer 108 are etched to partially expose the conductive line 106A. The resist 122 and the ML 120 of Figs. 13A and 13B have been removed.

At step 408, the method 400 removes the BL 118 to expose the track trench 113. 15A and 15B, a track trench 113 and a via hole 111 are formed, and a conductive line 106A is partially exposed at each of the elements 100 and 200. As shown in FIG. In the device 100, the via hole 111 is properly aligned with the conductive line 106A, and only a part of the upper surface of the conductive line 106A is exposed. In the device 200, the via hole 111 is misaligned with the conductive line 106A, and consequently, a part of the upper surface of the conductive line 106A and a part of the side wall surface are exposed. Due to the presence of the etch stop layer 108, the bottom portion of the via hole 111A is advantageously defined within the etch stop layer 108 and the conductive line 106A.

16A and 16B, the method 400 is completed by filling the via hole 111 and the track trench 113 with the appropriate material (s) to form a via 112A and a conductive line (s) 116A. Subsequently, a CMP process is performed to remove excess material (s) and planarize the top surface of devices 100 and 200. Process 410 may be viewed as a combination of processes 312 and 314.

The method 400 may proceed to an additional step for completing the fabrication of the devices 100 and 200, for example, by making additional conductive layers of the interconnect structure 103.

Although not intending to be limiting, one or more embodiments of the present disclosure provide many advantages over semiconductor devices and methods of forming them. For example, an embodiment of the present disclosure provides an etch stop layer as a passivation layer over a conductive line in a multilayer interconnect structure. The etch stop layer limits the negative lateral and vertical etch of the underlying dielectric layer when there is via-wire misalignment due to overlay errors. In an embodiment, the sidewall thickness of the etch stop layer is formed to be thicker than the maximum overlay error tolerated by the fabrication process. This effectively eliminates bridging connection defects and EM / TDDB problems associated with via-wire misalignment.

In one exemplary aspect, the present disclosure is directed to a device. Such an element comprises a substrate, a first dielectric layer on the substrate, and a conductive line partially embedded in the first dielectric layer. A first portion of the conductive line is disposed within the first dielectric layer and a second portion of the conductive line is disposed over the first dielectric layer. The device further comprises an etch stop layer on top of both the first dielectric layer and the conductive line. The device further comprises a second dielectric layer over the etch stop layer. The etch stop layer includes a dielectric material that is different from the material of the first and second dielectric layers. The second dielectric layer and etch stop layer provide openings that partially expose the conductive lines. The device further includes a via disposed in the opening and coupled to the conductive line.

In another illustrative aspect, this disclosure is directed to a method for fabricating a multilayer interconnect structure for an integrated circuit. The method includes providing a device comprising a substrate, a first dielectric layer over the substrate, and a conductive line that lies within the first dielectric layer, wherein the upper surface of the conductive line and the upper surface of the first dielectric layer are coplanar . The method further includes the step of recessing the upper surface of the first dielectric layer such that a first portion of the conductive line is above the first dielectric layer. The method further includes depositing an etch stop layer over both the first dielectric layer and the first portion of the conductive line. The method further comprises depositing a second dielectric layer over the etch stop layer. The method further comprises performing an etch process for the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive lines, wherein the etch rate of the etch stop layer in such an etch process is Is slower than the etch rate of the second dielectric layer in the etching process. The method further includes forming a via in the via hole.

In another illustrative aspect, this disclosure is directed to a method for fabricating a multilayer interconnect structure for an integrated circuit. The method includes providing a device comprising a substrate, a first dielectric layer over the substrate, and a conductive line that lies within the first dielectric layer, wherein the upper surface of the conductive line and the upper surface of the first dielectric layer are coplanar . The method further includes the step of recessing the upper surface of the first dielectric layer such that a first portion of the conductive line is exposed above the upper surface of the first dielectric layer. The method further comprises forming an etch stop layer over the first portion of the first dielectric layer and the conductive line, such etch stop layer having a conformal cross-sectional profile. The method further comprises depositing a second dielectric layer over the etch stop layer, wherein the first and second dielectric layers are made of the same material. The method further includes etching the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive line, wherein the etch stop layer is etched to a level lower than the etch rate of the second dielectric layer . The method further includes forming a via in the via hole.

In order that those skilled in the art will be better able to understand aspects of the disclosure, the foregoing has outlined features of some embodiments. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or to achieve the same advantages as the embodiments disclosed herein do. It will also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure and that those skilled in the art will be able to make various alterations, permutations, and alternatives without departing from the spirit and scope of the disclosure do.

Claims (10)

As a device,
Board;
A first dielectric layer over the substrate;
A conductive line in which a first portion of the conductive line is disposed within a first dielectric layer and a second portion of the conductive line is disposed over a first dielectric layer;
An etch stop layer over both the first dielectric layer and the conductive line;
Wherein the etch stop layer comprises a dielectric material that is different from the material of the first dielectric layer and the second dielectric layer and wherein the second dielectric layer and the etch stop layer comprise a conductive line partially The second dielectric layer providing an opening for exposing the second dielectric layer to the second dielectric layer; And
A via disposed in the opening and coupled to the conductive line,
Wherein the thickness of the etch stop layer is greater than an overlay error that is a distance between a centerline of the conductive line and a centerline of the via. 2. The device of claim 1, wherein the via is disposed on an upper surface of the conductive line or on both the upper surface and the sidewall surface of the conductive line. 2. The device of claim 1, further comprising another conductive line disposed over the vias and coupled to the conductive lines through the vias. 2. The device of claim 1, wherein the second portion of the conductive line has a rounded edge between the top surface of the conductive line and the sidewall surface. 2. The device of claim 1, wherein the first dielectric layer and the second dielectric layer comprise the same low dielectric constant (low-K) dielectric material. 2. The device of claim 1 wherein the etch stop layer has a higher density both in the first dielectric layer and the second dielectric layer. Article of claim 1, wherein each of the first dielectric layer and second dielectric layer is the etch stop layer, and includes a low dielectric constant dielectric material comprises a material selected from the SiCN, SiCO, SiO _2, SiN, and AlON device. 2. The device of claim 1, wherein the etch stop layer has a conformal cross-sectional profile. A method for fabricating a multilayer interconnect structure for an integrated circuit,
Board; A first dielectric layer over the substrate; And providing a conductive line within the first dielectric layer, the conductive line having an upper surface of the conductive line and a top surface of the first dielectric layer being coplanar;
Recessing an upper surface of the first dielectric layer such that a first portion of the conductive line is positioned over the first dielectric layer;
Depositing an etch stop layer over both the first dielectric layer and the first portion of the conductive line;
Depositing a second dielectric layer over the etch stop layer;
Applying an etch process to the second dielectric layer and the etch stop layer to form via holes that partially expose the conductive lines, wherein the etch rate of the etch stop layer in the etch process is greater than the etch rate of the etch stop layer in the etch process. Performing an etching process that is lower than an etch rate of the second dielectric layer; And
And forming a via in the via hole,
Wherein the thickness of the etch stop layer is greater than an overlay error that is a distance between a centerline of the conductive line and a centerline of the via.
A method for fabricating a multilayer interconnect structure for an integrated circuit. A method for fabricating a multilayer interconnect structure for an integrated circuit,
Board; A first dielectric layer over the substrate; And providing a conductive line within the first dielectric layer, the conductive line having an upper surface of the conductive line and a top surface of the first dielectric layer being coplanar;
Recessing an upper surface of the first dielectric layer such that a first portion of the conductive line is exposed above the upper surface of the first dielectric layer;
Forming an etch stop layer having a conformal cross-sectional profile over the first portion of the first dielectric layer and the conductive line;
Depositing on the etch stop layer a second dielectric layer of the same material as the first dielectric layer;
Etching the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive line, wherein the etch stop layer has an etch rate that is lower than an etch rate of the second dielectric layer, Etching the second dielectric layer and the etch stop layer; And
And forming a via in the via hole,
Wherein the thickness of the etch stop layer is greater than an overlay error that is a distance between a centerline of the conductive line and a centerline of the via.
A method for fabricating a multilayer interconnect structure for an integrated circuit.

Images