TWI680557B - Semiconductor package structure and method for preparing the same - Google Patents

Abstract

The present disclosure provides a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure includes a first substrate, a second substrate, an interconnect structure disposed between the first substrate and the second substrate, and a plurality of through structures that penetrate the first substrate and a portion of the interconnect structure. A first TSV conductor and a plurality of second TSV conductors penetrating the first substrate and a portion of the interconnect structure. The interconnect structure includes a dielectric structure, a plurality of first connection layers, and a plurality of ring-shaped second connection layers disposed in the dielectric structure. At least one of the plurality of first TSVs is in contact with one of the first connection layers. At least one of the plurality of through-silicon via conductors is in contact with one of the ring-shaped second connection layer and the other of the first connection layer.

Description

Semiconductor packaging structure and preparation method thereof

This application claims the priority and benefits of U.S. Provisional Application No. 62 / 770,942 filed on 11/23/2018 and U.S. Formal Application No. 16 / 244,794 filed on 10/01/2019. The contents of the official US application are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor packaging structure and a manufacturing method thereof, and more particularly, to a semiconductor packaging structure including a through silicon via (TSV) and a manufacturing method thereof.

Semiconductor components are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor components has become smaller and smaller, with more functions and a larger number of integrated circuits. Due to the miniaturization of semiconductor elements, chip-on-chip technology is widely used in the manufacture of semiconductor packages.

In one method, a stack of at least two wafers (or dies) is used to form, for example, a memory element in a three-dimensional (3D) package. In this way, compared with other semiconductor integrated circuits, it is possible to produce a device having two Products with double memory capacity. In addition to increasing memory capacity, stacked packages also provide improved mounting density and utilization of the mounting area. Because these excellent At the same time, research and development of stacked packaging technology has been accelerated.

A stacked package using a through silicon via (TSV) is disclosed in the art. Stacked packages using TSVs have a structure that has TSVs in them, so the chips are electrically connected to each other through TSVs. Generally speaking, TSVs are formed by etching vertical vias through the substrate and filling the vias with a conductive material such as copper (Cu). Generally, the vertical through holes formed through the substrate have the same depth and are aligned with the pads formed in the wafer. In addition, specific wiring lines are designed and formed, and formed as end points where TSVs are located. However, this particular wiring will complicate circuit design, especially in dual-die stacked designs.

The above description of the "prior art" is only for providing background technology. It does not recognize that the above description of the "prior technology" reveals the subject matter of this disclosure, does not constitute the prior technology of this disclosure, and any description of the "prior technology" above. Neither shall be part of this case.

The disclosure provides a semiconductor package structure including a first substrate, a second substrate, an interconnection structure, a plurality of first TSV conductors, and a plurality of second TSV conductors. The first substrate has a first front surface and a first back surface opposite to the first front surface. The second substrate has a second front surface and a second back surface opposite to the second front surface. The interconnection structure is disposed between the first front surface of the first substrate and the second front surface of the second substrate. The plurality of first TSV conductors penetrate the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; the plurality of second TSV conductors pass from the first substrate The first back surface of a substrate penetrates the first substrate and a portion of the interconnect structure. The interconnect structure includes a dielectric structure, a plurality of first connection layers are disposed in the dielectric structure, and a plurality of ring-shaped second connection layers are disposed in the dielectric structure. In some embodiments, the plurality of first wears At least one of the TSV conductors is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of second TSV conductors is in contact with one of the plurality of annular second connection layers and the other of the plurality of first connection layers.

In some embodiments, the semiconductor package structure further includes a first etch stop layer disposed above the first connection layer, and a second etch stop layer disposed above the second connection layer.

In some embodiments, the first etch stop layer is disposed above a surface of the first connection layer facing the first substrate, and the second etch stop layer is disposed on a surface of the second connection layer facing the first substrate. Above the surface.

In some embodiments, the surface of the first connection layer is separated from the dielectric structure by the first etch stop layer, and the surface of the second connection layer is separated from the dielectric structure by the second etch stop layer.

In some embodiments, at least one of the plurality of first TSV conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to the first connection layer.

In some embodiments, at least one of the plurality of through-silicon via conductors includes a first portion and a second portion coupled to the first portion.

In some embodiments, the first portion of the second TSV conductor passes through a portion of the dielectric structure and the second etch stop layer. In some embodiments, the second portion of the second TSV conductor passes through the ring-shaped second connection layer, a portion of the dielectric structure, and the first etch stop layer.

In some embodiments, a width of the first portion is greater than a width of the second portion.

In some embodiments, the interconnection structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers. In some embodiments, the plurality of third connection layers are separated from the plurality of first TSV conductors and the plurality of second TSV conductors.

In some embodiments, an interface is formed within the interconnect structure.

In some embodiments, at least one of the plurality of first TSV conductors passes through the interface.

In some embodiments, at least one of the plurality of second TSV conductors passes through the interface.

The disclosure further provides a method for manufacturing a semiconductor structure, which includes the following steps. A first substrate is provided. The first substrate has a first front surface, a first back surface opposite to the first front surface, and a first interconnection structure disposed above the first front surface. A second substrate is provided. The second substrate has a second front surface, a second back surface opposite to the second front surface, and a second interconnection structure disposed above the second front surface. Joining the first interconnect structure and the second interconnect structure to form a third interconnect structure, the third interconnect structure is disposed on the first front surface of the first substrate and the second substrate of the second substrate Between the front surfaces. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers. A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etch stop layers provided above the plurality of ring-shaped second connection layers. A first etch is performed to form a first via opening and a second via opening penetrating the first substrate and a portion of the third interconnect structure. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first through hole opening. The second through-hole opening includes a first portion and a second portion coupled to each other. In some embodiments, the first connection layer The upper first etch stop layer is exposed through a bottom of the second portion of the second through hole opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through the bottom of the first via opening and the bottom of the second portion of the second via opening. A first TSV conductor is formed in the first via opening, and a second TSV conductor is formed in the second via opening.

In some embodiments, the dielectric structure is exposed through a sidewall of the first via opening by performing the first etching, and the dielectric structure is exposed through the sidewall of the first via opening by performing the second etching. The first etch stop layer.

In some embodiments, the dielectric structure is exposed through a sidewall of the first portion of the second via opening by performing the first etching. In some embodiments, by performing the first etching, a ring-shaped second etch stop layer, the ring-shaped second connection layer, and the interposer are exposed through a sidewall of the second portion of the second through-hole opening. Electric structure.

In some embodiments, by performing the second etching, the dielectric structure and the annular second etch stop layer are exposed through the sidewall of the first portion of the second via opening. In some embodiments, by performing the second etching, the dielectric structure and the first etch stop layer are exposed through the sidewall of the second portion of the second via opening.

In some embodiments, a width of the second portion of the second through-hole opening is smaller than a width of the first portion of the second through-hole opening.

In some embodiments, the first etch stop layer is disposed above the first connection layer and above a surface facing the first substrate, and the ring-shaped second etch stop layer is disposed on the ring-shaped second connection layer. Above, facing above a surface of the first substrate.

In some embodiments, the third interconnect structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected to the first TSV conductor and the second via. The TSV conductors are separated.

In some embodiments, an interface is formed between the first interconnect structure and the second interconnect structure.

The disclosure further provides a method for manufacturing a semiconductor package structure. According to the manufacturing method, the connection layer is designed to provide electrical connection with the first and the second TSV conductors, and is divided into two types: the first connection layer and the ring-shaped second connection layer. The first etch stop layer is formed over the first connection layer, and the second etch stop layer is formed in a ring shape over the second connection layer in a ring shape. Therefore, the first etch will stop at the first etch stop layer, but the first etch will continue to etch the dielectric structure through the ring-shaped second etch stop layer and the ring-shaped second connection layer, and finally stop at the The first etch stop layer.

Therefore, a first through-hole opening is formed, wherein the dielectric structure is exposed through the sidewall of the first through-hole opening, and the first etch stop layer is exposed through the bottom of the first through-hole opening. Unlike the first through-hole opening, the second through-hole opening includes the first portion and the second portion connected to each other. In addition, due to the annular configuration of the second etch stop layer and the second connection layer, the first portion and the second portion are self-aligned when formed. The dielectric structure is exposed through the side wall of the first portion of the second through-hole opening, and the dielectric structure, the ring-shaped second etch stop layer, and the ring-shaped connection layer pass through the second through-hole opening. A portion of the sidewall is exposed, and the first etch stop layer is exposed through a bottom of the second portion of the second through-hole opening. The first etch stop layer is then removed to expose the first connection layer. Therefore, the dielectric structure and the first etch stop layer are exposed through the sidewall of the first through-hole opening at this time, and the first connection layer is exposed through the bottom of the first through-hole opening. Unlike the first through-hole opening, the dielectric structure and the ring-shaped second etch stop layer are now exposed through the sidewall of the first portion of the second through-hole opening, and the ring-shaped second connection layer, the dielectric The electrical structure and the first etch stop layer pass through the The side wall of the second portion of the second through-hole opening is exposed, and the first connection layer is exposed through the bottom of the second portion of the second through-hole opening.

In this disclosure, the first TSV conductor formed in the first via opening is in contact with the first connection layer, and the second TSV conductor formed in the second via opening is in contact with the first connection layer. The ring-shaped second connection layer is in contact with the first connection layer. It should be noted that by providing the first connection layer and the ring-shaped second connection layer, a vertical electrical connection between different layers in the interconnect structure can be easily constructed. Therefore, it is easy to construct an electrical connection between the two substrates. Therefore, no extra wiring is needed to place the conductors at the same height.

In contrast, compared to the application method without the ring-shaped second etch stop layer and the ring-shaped second connection layer, additional wiring is required to place conductors having the same height to form an electrical connection. Such extra wiring complicates circuit design, especially in dual-die stacks.

The technical features and advantages of this disclosure have been outlined quite extensively above, so that the detailed description of this disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application of this disclosure will be described below. Those with ordinary knowledge in the technical field to which this disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as this disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent constructions cannot be separated from the spirit and scope of this disclosure as defined by the scope of the attached patent application.

10‧‧‧Preparation method

50‧‧‧Semiconductor package structure

101‧‧‧ steps

102‧‧‧step

104‧‧‧step

106‧‧‧step

108‧‧‧ steps

110‧‧‧step

200‧‧‧ substrate

202B‧‧‧Back surface

202F‧‧‧Front surface

210‧‧‧Interconnection Structure

212‧‧‧Dielectric structure

214a‧‧‧Connection layer

214b‧‧‧Connection layer

214c‧‧‧Connection layer

216a‧‧‧etch stop layer

216b‧‧‧etch stop layer

300‧‧‧ substrate

302B‧‧‧Back surface

302F‧‧‧Front surface

310‧‧‧Interconnection Structure

312‧‧‧dielectric structure

314a‧‧‧Connection layer

314b‧‧‧ Connection layer

314c‧‧‧Connection layer

316a‧‧‧etch stop layer

316b‧‧‧etch stop layer

400‧‧‧ interconnect structure

402‧‧‧dielectric structure

404‧‧‧ interface

410‧‧‧First through hole opening

412‧‧‧Second through hole opening

414a‧‧‧Part I

414b‧‧‧Part II

420‧‧‧Barrier and glue layer

422‧‧‧Conductive material

430‧‧‧The first through-silicon via conductor

432‧‧‧Second through-silicon via conductor

434a‧‧‧Part I

434b‧‧‧Part II

M1‧‧‧First floor

M2‧‧‧The second floor

M3‧‧‧Third floor

When referring to the drawings combined with the embodiments and the scope of the patent application, the disclosure in this application can be understood more fully. The same component symbols in the drawings refer to the same components.

FIG. 1 is a flowchart illustrating a method for preparing a semiconductor package structure in some embodiments of the present disclosure. law.

2 and 3 are schematic diagrams illustrating manufacturing stages of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure.

FIG. 4A is a partial cross-sectional view of FIGS. 2 and 3.

FIG. 4B is a schematic top view (or a schematic bottom view) of FIG. 4.

Fig. 4C is a view opposite to the view shown in Fig. 4B.

5 to 9 are schematic diagrams illustrating various manufacturing stages of a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure.

The following description of this disclosure is accompanied by drawings that form a part of the description to illustrate the embodiment of the disclosure, but the disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment.

"One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment.

In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application.

FIG. 1 is a flowchart illustrating a method 10 for fabricating a semiconductor structure in some embodiments of the present disclosure. The manufacturing method 10 includes step 101, providing a first substrate having a first front surface, a first back surface opposite to the first front surface, and a first interconnection structure disposed above the first front surface. . The manufacturing method 10 further includes step 102, providing a second substrate having a second front surface, a second back surface opposite to the second front surface, and a second interconnect disposed above the second front surface. structure. According to this embodiment, step 101 may be performed before, after, or at the same time as step 102. The manufacturing method 10 further includes step 104, joining the first interconnect structure and the second interconnect structure to form a first front surface of the first substrate and a second front surface of the second substrate. A third interconnect structure. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers. A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etch stop layers provided above the plurality of ring-shaped second connection layers. The manufacturing method 10 further includes step 106, performing a first etching to form a first through-hole opening and a second through-hole opening penetrating the first substrate and a portion of the third interconnect structure. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first through hole opening. In some embodiments, the second through-hole opening includes a first portion and a second portion coupled to each other, and the first etch stop layer above the first connection layer passes through the first through-hole of the second through-hole opening. One bottom of the two parts is exposed. The manufacturing method 10 further includes step 108, performing a second etching to remove a portion of the first etch stop layer and exposing the bottom through the bottom of the first through hole opening and the bottom of the second portion of the second through hole opening. First connection layer. The manufacturing method 10 further includes step 110, forming a first first TSV conductor in the first via opening, and forming a second TSV conductor in the second via opening. According to one or more embodiments, it will be further described 10. Preparation method 10 of this semiconductor structure.

2 and 3 are schematic diagrams illustrating manufacturing stages of a method for manufacturing a semiconductor package structure according to some embodiments of the present disclosure. Referring to FIG. 2, a substrate 200 is provided according to step 101. In some embodiments, the substrate 200 includes silicon (Si). In other embodiments, the substrate 200 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon, silicon germanium (SiGe), silicon carbide (SiC), diamond, An epitaxy layer or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 200 may include a silicon-on-insulator (SOI) substrate, but the disclosure is not limited thereto. The substrate 200 has a front surface 202F and a back surface 202B opposite to the front surface 202F, as shown in FIG. 2. In some embodiments, a circuit layer (not shown) is formed on or in the substrate 200 of the front surface 202F. The circuit layer may include a circuit pattern or a circuit element, such as a transistor, a capacitor, and an or diode, but the present disclosure is not limited thereto. Therefore, the front surface 202F may be referred to as an active surface, but the present disclosure is not limited thereto.

The substrate 200 further includes an interconnection structure 210 disposed above the front surface 202F. The interconnect structure 210 includes a dielectric structure 212 formed by a plurality of dielectric layers, and a plurality of connection layers are formed in the plurality of dielectric layers. The dielectric structure 212 for isolating the connection layer is also referred to as an inter-metal dielectric (IMD) layer. The dielectric structure 212 may include, but is not limited to, for example, silicon oxide (SiO), tetraethoxysilane (TEOS), phosphosilicate glass (PSG), or boro-phosphosilicate glass (BPSG). The connection layers in different dielectric layers are generally described as being in different layers, and the first to nth layers are referred to as M1 to Mn. For example, the interconnect structure 210 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in FIG. 2. However, those skilled in the art should easily understand that the number of layers is not limited to three. A circuit layer and an interconnect structure 210 are disposed above the substrate 200. The substrate 200 may be a semiconductor wafer or a die used for 3D wafer packaging, wafer level packaging (WLP), or wafer bonding processes.

Still referring to FIG. 2, in this embodiment, the connection layers in the interconnect structure 210 are formed according to different purposes. For example, the connection layers 214a and 214b are designated to be electrically connected to the via-hole conductor, and the connection layer 214c is designated to be an internal connection layer without contacting the via-hole conductor. In some embodiments, the connection layers 214a, 214b, and 214c may be formed by a conventional process, such as, but not limited to, a dual damascene process. The connection layers 214a and 214b are different from the connection layer 214c. As shown in FIG. 2, the etch stop layer 216 a is disposed above one surface of the connection layer 214 a facing the substrate 200, and the etch stop layer 216 b is disposed above one surface of the connection layer 214 b facing the substrate 200. Unlike the connection layers 214a and 214b, the connection layer 214c does not have any etch stop layer on any surface thereof, as shown in FIG. In some embodiments, the connection layers 214a, 214a, and 214c may include a conductive material such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co) , But this disclosure is not limited to this.

It is important that the connection layers 214a and 214b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 214a is used as an end point of the vertical electrical connection, so it is designed to include a flat plate structure, wherein the surface of the connection layer 214a covered by the etch stop layer 216a also has a flat plate structure. Therefore, a sufficient contact area of a via-hole conductor is provided through the connection layer 214a. The connection layers 214c are electrically connected to each other and / or to the connection layer 214a.

4A is a partial cross-sectional view of FIGS. 2 and 3, FIG. 4B is a schematic plan view (or a bottom view) of FIG. 4A, and FIG. 4C is a view opposite to the view shown in FIG. 4B. 4A to 4C, in some embodiments, the connection layer 214b is used as a part of the vertical connection. Therefore, the connection layer 214b is designed to include a ring configuration, and the etch stop layer 216b covering the surface of the connection layer 214b is also designed to include a ring configuration. 2 and 4B, in a top view of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b, the dielectric structure 212 can be observed from a center of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b. Refer to Figure 2 and Figure 4C. In the bottom view of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b, the ring-shaped etch stop layer 216b completely covers the surface of the connection layer 214b to provide protection.

It is worth noting that the etch stop layer 216a and the ring-shaped etch stop layer 216b include materials that are different or sufficiently different in composition so that the etch stop layer 216a and the ring-shaped etch stop layer 216b can use appropriate etching with respect to the dielectric structure 112 Chemicals to selectively remove. In some embodiments, the etch stop layer 216a and the ring-shaped etch stop layer 216b may include the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), but the disclosure is not limited thereto.

Referring to FIG. 3, a substrate 300 is provided according to step 102. As described above, according to the embodiment, step 101 may be performed before, after, or at the same time as step 102. In some embodiments, the substrate 300 includes silicon (Si). In other embodiments, the substrate 300 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon, silicon germanium (SiGe), silicon carbide (SiC), diamond, An epitaxy layer or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 300 may include a silicon-on-insulator (SOI) substrate, but the disclosure is not limited thereto. The substrate 300 has a front surface 302F and a back surface 302B opposite to the front surface 302F, as shown in FIG. 3. In some embodiments, a circuit layer (not shown) is formed on or in the substrate 300 of the front surface 302F. The circuit layer may include a circuit pattern or a circuit element, such as a transistor, a capacitor, and an or diode, but the present disclosure is not limited thereto. Therefore, the front surface 302F may be referred to as an active surface, but the present disclosure is not limited thereto.

The substrate 300 further includes an interconnection structure 310 disposed above the front surface 302F. The interconnect structure 310 includes a dielectric structure 312 formed by a plurality of dielectric layers, wherein a plurality of connection layers are formed in the plurality of dielectric layers. The dielectric structure 312 used to isolate the connection layer is also referred to as an intermetal dielectric (IMD) layer. The dielectric structure 312 may include, but is not limited to, for example, silicon oxide (SiO), Tetraethoxysilane (TEOS), phosphosilicate glass (PSG) or boro-phosphosilicate glass (BPSG). The connection layers in different dielectric layers are generally described as being in different layers, and the first to nth layers are referred to as M1 to Mn. For example, the interconnect structure 310 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in FIG. 3. However, those skilled in the art should easily understand that the number of layers is not limited to three. A circuit layer and an interconnect structure 310 are disposed above the substrate 300. The substrate 300 may be a semiconductor wafer or a die used for 3D wafer packaging, wafer level packaging (WLP), or wafer bonding processes.

Still referring to FIG. 3, in this embodiment, the connection layers in the interconnect structure 310 are formed according to different purposes. For example, the connection layers 314a and 314b are designated to be electrically connected to the via-hole conductor, and the connection layer 314c is designated to be an internal connection layer without contacting the via-hole conductor. In some embodiments, the connection layers 314a, 314b, and 314c may be formed by a conventional process, such as, but not limited to, a dual damascene process. The connection layers 314a and 314b are different from the connection layer 314c. As shown in FIG. 3, the etch stop layer 316 a is disposed above one surface of the connection layer 314 a facing the substrate 300, and the etch stop layer 316 b is disposed above one surface of the connection layer 314 b facing the substrate 300. Unlike the connection layers 314a and 314b, the connection layer 314c does not have any etch stop layer on any surface thereof, as shown in FIG. In some embodiments, the connection layers 314a, 314a, and 314c may include a conductive material such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co) , But this disclosure is not limited to this.

It is important that the connection layers 314a and 314b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 314a is used as an end point of the vertical electrical connection, and therefore is designed to include a flat plate structure, wherein the surface of the connection layer 314a covered by the etch stop layer 316a also has a flat plate structure. Therefore, a sufficient contact area of a via-hole conductor is provided through the connection layer 314a. Further, the connection layers 314c are electrically connected to each other and / or to the connection layer 314a.

4A to 4C, in some embodiments, the connection layer 314b is used as a part of the vertical connection. Therefore, the connection layer 314b is designed to include a ring configuration, and the etch stop layer 316b covering the surface of the connection layer 314b is also designed to include a ring configuration. 3 and 4B, in a top view of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b, the dielectric structure 312 can be observed from a center of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b. 3 and 4C, in a bottom view of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b, the ring-shaped etch stop layer 316b completely covers the surface of the connection layer 314b to provide protection.

It is worth noting that the etch stop layer 316a and the ring-shaped etch stop layer 316b include materials that are different or sufficiently different in composition so that the etch stop layer 316a and the ring-shaped etch stop layer 316b can use appropriate etching relative to the dielectric structure 312 Chemicals to selectively remove. In some embodiments, the etch stop layer 316a and the ring-shaped etch stop layer 316b may include the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), but the disclosure is not limited thereto.

5 to 9 are schematic diagrams illustrating various manufacturing stages of a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure. 5, next, the substrate 200 and the substrate 300 are bonded. In some embodiments, the substrate 200 is turned over to engage the substrate 300 as shown in FIG. 5. In some embodiments, although not shown, the substrate 300 is flipped to bond to the substrate 300. It should be noted that the substrate 200 and the substrate 300 are joined in a face-to-face manner. By vertically stacking dies with different functions in a face-to-face manner, a face-to-face communication is achieved between the dies with different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor element compared to semiconductor elements having dies having different functions arranged in a laterally adjacent manner. In addition, signals of differently functioning dies are stacked vertically face to face The paths are shorter than the signal paths of the dies with different functions arranged in a laterally adjacent manner; therefore, the dies with different functions stacked vertically in the face-to-face manner of the present invention can be applied to high-speed electronic components.

In some embodiments, according to step 104, the interconnect structure 210 and the interconnect structure 310 are joined to form an interconnect structure 400 disposed between the front surface 202F of the substrate 200 and the front surface 302F of the substrate 300. Therefore, the interconnect structure 400 includes a dielectric structure 402 formed by the dielectric structures 212, 312 and the connection layers 214a to 214c and 314a to 314c. In some embodiments, the interface 404 is formed between the interconnect structure 210 and the interconnect structure 310. In other words, the interface 404 is formed within the interconnect structure 400.

Referring to FIG. 6, according to step 106, a first etching is performed to form a first through-hole opening 410 and a second through-hole opening 412 penetrating through a portion of the substrate 200 and the interconnect structure 400. In some embodiments, a first etch is performed on the rear surface 202B of the substrate 200 as shown in FIG. 6. It should be noted that the first etch removes part of the dielectric structure 402 and stops at the etch stop layers 216a, 316a to form a first via opening 410. It is worth noting that the first etch removes part of the dielectric structure 402 from the center of the annular etch stop layers 216b, 316b and the center of the annular connection layers 214b, 314b, and stops at the etch stop layers 216a, 316a to A second through hole opening 412 is formed. Therefore, the first through-hole opening 402 and the second through-hole opening 404 having the same depth or different depths are formed, as shown in FIG. 6. In some embodiments, by performing the first etching, the substrate 200 and the dielectric structure 402 are exposed through the sidewall of the first via opening 410, and the etch stop layers 216a, 316a are exposed through the bottom of the first via opening 410. It should be noted that the depths of the first through holes 402 may be the same or different from each other. In some embodiments, a depth of the first through hole opening is determined by the layer where the etch stop layers 216a, 316a are located, as shown in FIG.

Still referring to FIG. 6, the second through-hole opening 412 includes a first portion 414a and a second portion 414b connected to each other. In some embodiments, by performing a first etch, the substrate 200 and The dielectric structure 402 is exposed through the sidewall of the first portion 414a of the second via opening 412, and the annular etch stop layers 216b, 316b are exposed through the bottom of the first portion 414a of the second via opening 412. In addition, by performing the first etching, the ring-shaped connection layers 214b, 314b and the dielectric structure 402 are exposed through the sidewall of the second portion 414b of the second through-hole opening 412, and the etch stop layers 216a, 316a pass through the second through-hole opening 412 The bottom of the second portion 414b is exposed. The width of the second portion 414b of the second through-hole opening 412 is smaller than the width of the first portion 414a of the second through-hole opening 412. In some embodiments, the width of the second portion 414b is substantially equal to the inner diameter of the ring-shaped etch stop layers 216b, 316b, or is substantially equal to the inner diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto. Therefore, due to the annular configuration of the annular etch stop layers 216b, 316b and the annular connection layers 214b, 314b, the first portion 414a and the second portion 414b are self-aligned when formed. It should be noted that the depth of the first portion 414a and the depth of the second portion 414b may be the same or different from each other. In some embodiments, the depth of the first portion 414a is determined by the layer where the annular etch stop layers 216b, 316b are located, and the depth of the second portion 414b is determined by the layer where the etch stop layers 216a, 316a are located, as shown in FIG.

It should be noted that because the etch rate of the etch stop layer is different from the etch rate of the dielectric structure 402, the first and second via openings 410 and 412 can be formed without damaging the etch stop layers 216a, 216b, 316a, and 316B.

Referring to FIG. 7, according to step 108, a second etch is performed to remove the etch stop layers 216 a and 316 a from the bottoms of the first and second via openings 410 and 412. Therefore, the connection layers 214 a and 314 a are exposed through the bottom of the first through-hole opening 410. In some embodiments, by performing the second etching, the substrate 200, the dielectric structure 402, and the etch stop layers 216a, 316a are exposed through the sidewall of the first through-hole opening 410, and the connection layers 214a, 314a are performed by performing the second The bottom of the first through-hole opening 410 is etched and exposed.

Still referring to FIG. 7, by performing the second etching, the substrate 200, the dielectric structure 402, and the annular etch stop layers 216b and 316b are exposed through the sidewall of the first portion 414a, and the connection layers 214a and 314a are opened through the second through hole at this time. The bottom of the second portion 414b of 412 is exposed.

It should be noted that because the etch rate of the etch stop layer is different from that of the dielectric structure 402, the etch stop layers 216a, 216b, 316a, 316b can be removed without damaging the dielectric structure 402, as shown in FIG.

8 and FIG. 9, according to step 110, a first first TSV conductor 430 is formed in the first via opening 410, and a second TSV conductor 432 is formed in the second via opening 412. In some embodiments, step 100 further includes the following steps. For example, a blocking / glue layer 420 is disposed above the sidewalls and the bottom of the first through-hole opening 410 and the second through-hole opening 412, as shown in FIG. 8. In some embodiments, the barrier / gluing layer 420 may include a group (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), manganese (Mn), titanium / copper (Ti / Cu), and / or copper (Cu), but the disclosure is not limited thereto.

Referring to FIG. 9, a conductive material 422 such as copper is formed next to fill the first and second via-hole conductors 410 and 412. Therefore, a first TSV conductor 430 and a second TSV conductor 432 are obtained, as shown in FIG. 9.

As shown in FIG. 9, a semiconductor package structure 50 is provided. The semiconductor package structure 50 includes a substrate 200 having a front surface 202F and a rear surface 202B opposite to the front surface 202F; a substrate 300 having a front surface 302F and a rear surface 302B opposite to the front surface 302F; an interconnection structure 400 disposed on the substrate 200 Between the front surface 202F of the substrate 300 and the front surface 302F of the substrate 300; a plurality of first TSV conductors 430 penetrating through a portion of the substrate 200 and the interconnect structure 400 from the rear surface 202B of the substrate 200; and a plurality of second vias Through-silicon via conductors 432 penetrate the substrate 200 and a portion of the interconnect structure 400 from the rear surface 202B of the substrate 200. In some embodiments, At least one of the first TSV conductors 430 passes through the interface 404. In some embodiments, at least one of the second TSV conductors 432 passes through the interface 404.

As shown in FIG. 9, the interconnect structure 400 includes a dielectric structure 402, a plurality of connection layers 214 a and 314 a provided in the dielectric structure 402, and a plurality of ring-shaped connection layers 214 b and 314 b provided in the dielectric structure 402. In some embodiments, at least one of the first TSV conductors 430 is in contact with one of the connection layers 214a or 314a. In some embodiments, at least one of the second TSV conductors 432 is in contact with one of the ring-shaped second connection layers 214b, 314b and the other of the connection layers 214a or 314a. As described above, the interconnect structure 400 may further include a plurality of connection layers 214c, 314c, which are electrically connected to each other and / or electrically connected to the connection layers 214a, 314a. However, the connection layers 214c and 314c are separated from the first TSV conductor 430, the second TSV conductor 432, and the annular connection layers 214b and 314b, as shown in FIG.

In some embodiments, the semiconductor package structure 50 further includes etch stop layers 216a, 316a disposed above the connection layers 214a, 314a and etch stop layers 216b, 316b disposed above the ring-shaped connection layers 214b, 314b. In addition, the etch stop layers 216a, 316a are disposed above a surface of the connection layer 214a, 314a facing the substrate 200, and the ring-shaped etch stop layers 216b, 316b are disposed above a surface of the connection layer 214b, 314b facing the substrate 200. Therefore, the surfaces of the connection layers 214a and 314a are separated from the dielectric structure 402 by the etch stop layers 216a and 316a, and the surfaces of the connection layers 214b and 314b are separated from the dielectric structure 402 by the etch stop layers 216b and 316b.

As shown in FIG. 9, the first TSV conductor 430 passes through a portion of the dielectric structure 402 and the etch stop layers 216a, 316a, and extends to one of the connection layers 214a or 314a. In some embodiments, at least one of the plurality of second TSV conductors 432 includes a first portion 434a and a second portion 434b coupled to the first portion 434a. In some embodiments, the second The first portion 434a of the TSV conductor 432 passes through a portion of the dielectric structure 402 and the annular etch stop layers 216b, 316b. In some embodiments, the second portion 434b of the second TSV conductor 432 passes through the annular connection layers 214b, 314b and a portion of the dielectric structure 402 and the etch stop layers 216a, 316a, and extends to another connection layer 214a or 314a.

Still referring to FIG. 9, the first TSV conductor 430 may have a uniform width, the first portion 434a of the second TSV conductor 432 may have a uniform width, and the second portion 434b of the second TSV conductor 432 Can have a consistent width. In some embodiments, the first TSV conductors 430 may include the same width. In other embodiments, the first TSV conductor 430 may include different widths, as shown in FIG. 9. For example, when the first TSV conductor 430 is electrically connected to a power source or a ground, the width of such a first TSV conductor 430 may be greater than the width of other first TSV conductors 430, but this disclosure does not Limited to this. Similarly, in some embodiments, the second TSV conductors 432 may include the same width. In other embodiments, the second TSV conductor 432 may include different widths. For example, when the second TSV conductor 432 is electrically connected to a power source or a ground, the width of such a second TSV conductor 432 may be greater than the width of other second TSV conductors 432, but the disclosure is not limited to this. this. In addition, the width of the first portion 434a is larger than the width of the second portion 434b. In some embodiments, the width of the first portion 434a is smaller than the outer diameter of the annular etch stop layers 216b, 316b, or smaller than the outer diameter of the annular connection layers 214b, 314b, but the disclosure is not limited thereto. However, the width of the first portion 434a is larger than the inner diameter of the ring-shaped etch stop layers 216b, 316b, or larger than the inner diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto. In some embodiments, the width of the second portion 434b is substantially equal to the inner diameter of the annular etch stop layers 216b, 316b, or is substantially equal to the inner diameter of the annular connection layers 214b, 314b, but the disclosure is not limited thereto.

The present disclosure provides a method 10 for manufacturing a semiconductor package structure. Under preparation Method 10, the connection layers 214a, 214b, 314a, and 314b are designed to provide electrical connection with the first and second TSV conductors 430 and 432, which are divided into two types: connection layers 214a and 314a, and ring-shaped Connection layers 214b and 314b. The etch stop layers 216a and 316a are formed above the connection layers 214a and 314a, and the ring-shaped etch stop layers 216b and 316b are formed above the ring-shaped connection layers 214b and 314b. Therefore, the first etch will stop at the etch stop layers 216a, 316a, but the first etch will continue to etch the dielectric structure 402 through the ring-shaped etch stop layers 216b, 316b and the ring-shaped connection layers 214b, 314b, and finally stop at the etch Stop layers 216a, 316a. As a result, a first via opening 410 and a second via opening 412 are formed. The second through-hole opening 412 includes a first portion 414a and a second portion 414b connected to each other. In addition, due to the annular configuration of the annular etch stop layers 216b, 316b and the annular connection layers 214b, 314b, the first portion 414a and the second portion 414b are self-aligned when formed. Thereafter, the etch stop layers 216a, 316a are removed by performing a second etch to expose the connection layers 214a, 314a.

In the present disclosure, a first TSV conductor 430 formed in the first via opening 410 is in contact with the connection layers 214a, 314a, and a second TSV conductor 432 formed in the second via opening 412 is in contact with The ring-shaped connection layers 214b and 314b are in contact with the connection layers 214a and 314a. It should be noted that since the connection layers 214a, 314a and the ring-shaped connection layers 214b, 314b are provided, vertical electrical connections between different layers in the interconnect structure 400 can be easily formed. Therefore, it is easy to form an electrical connection between the two substrates 200 and 300. Therefore, no extra wiring is needed to place the conductors at the same height.

In contrast, compared to the application method without the ring-shaped second etch stop layer and the ring-shaped second connection layer, additional wiring is required to place conductors having the same height to form an electrical connection. Such extra wiring complicates circuit design, especially in dual-die stacks.

The present disclosure provides a semiconductor package structure. The semiconductor package structure includes: a first substrate having a first front surface and a first back surface opposite to the first front surface; a second substrate having a second front surface and opposite to the second front surface A second back surface; an interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate; a plurality of first TSV conductors from the first substrate The first back surface penetrates the first substrate and a portion of the interconnect structure; and a plurality of second TSV conductors penetrate the first substrate and the first substrate from the first back surface of the first substrate Part of the interconnect structure. The interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of ring-shaped second connection layers disposed in the dielectric structure. In some embodiments, at least one of the plurality of first TSVs is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of through-silicon via conductors is in contact with one of the plurality of second connection layers and the other of the plurality of first connection layers.

The disclosure further provides a method for manufacturing a semiconductor structure. The preparation method includes the following steps. A first substrate is provided. The first substrate has a first front surface, a first back surface opposite to the first front surface, and a first interconnection structure disposed above the first front surface. A second substrate is provided. The second substrate has a second front surface, a second back surface opposite to the second front surface, and a second interconnection structure disposed above the second front surface. The first interconnection structure and the second interconnection structure are bonded to form a third interconnection structure disposed between the first front surface of the first substrate and the second front surface of the second substrate. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers. A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etch stop layers provided above the plurality of ring-shaped second connection layers. Perform a first etch to shape A first through-hole opening and a second through-hole opening are formed to penetrate the first substrate and a portion of the third interconnect structure. In some embodiments, the plurality of first etch stop layers above the plurality of first connection layers are exposed through a bottom of the first through hole opening. The second through-hole opening includes a first portion and a second portion connected to each other. In some embodiments, the first etch stop layer above the first connection layer is exposed through a bottom of the second through hole opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through the bottom of the first via opening and the bottom of the second portion of the second via opening. A first TSV conductor is formed in the first via opening, and a second TSV conductor is formed in the second via opening.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods and steps described in the description. Those skilled in the art can understand from the disclosure of this disclosure that according to this disclosure, they can use existing, or future developmental processes, machinery, manufacturing, materials that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Composition, means, method, or step. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

Claims (20)

A semiconductor package structure includes: a first substrate including a first front surface and a first back surface opposite to the first front surface; a second substrate including a second substrate A front surface and a second back surface opposite to the second front surface; an interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate, wherein the The interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of ring-shaped second connection layers disposed in the dielectric structure; a plurality of first through-silicon vias (Through Silicon Via (TSV) conductor, penetrating the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; and a plurality of second TSV conductors from the first substrate The first back surface penetrates the first substrate and a portion of the interconnect structure; wherein at least one of the plurality of first TSV conductors is in contact with one of the plurality of first connection layers, And at least one of the plurality of through-silicon via conductors A second connection layer of the plurality of ring-shaped and the other contact in the plurality of first connection layer. The semiconductor package structure according to claim 1, further comprising a first etch stop layer disposed above the first connection layer, and a second etch stop layer disposed above the second connection layer. The semiconductor package structure according to claim 2, wherein the first etch stop layer is disposed above a first surface of the first connection layer, the first surface faces the first substrate, and the second etch stop layer is disposed Above a second surface of the second connection layer, the second surface faces the first substrate. The semiconductor package structure according to claim 3, wherein the first surface of the first connection layer is separated from the dielectric structure through the first etch stop layer, and the second surface of the second connection layer is transmitted through the second The etch stop layer is separated from the dielectric structure. The semiconductor package structure according to claim 2, wherein at least one of the plurality of first TSV conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to the first connection layer. The semiconductor package structure according to claim 2, wherein at least one of the plurality of second TSV conductors includes a first portion and a second portion coupled to the first portion. The semiconductor package structure according to claim 6, wherein the first portion of the second TSV conductor passes through a portion of the dielectric structure and the second etch stop layer, and the second TSV conductor A second portion passes through the ring-shaped second connection layer, a portion of the dielectric structure, and the first etch stop layer. The semiconductor package structure according to claim 6, wherein a width of the first portion is greater than a width of the second portion. The semiconductor package structure according to claim 6, wherein the interconnection structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected to the plurality of first through-silicon via conductors and the plurality of The second TSV conductor is separated. The semiconductor package structure according to claim 1, wherein an interface is formed in the interconnection structure. The semiconductor package structure according to claim 10, wherein at least one of the plurality of first TSV conductors passes through the interface. The semiconductor package structure according to claim 10, wherein at least one of the plurality of second TSV conductors passes through the interface. A method for preparing a semiconductor package structure includes: providing a first substrate having a first front surface, a first back surface opposite to the first front surface, and disposed above the first front surface A first interconnect structure; a second substrate is provided, the second substrate has a second front surface, a second back surface opposite to the second front surface, and a second surface disposed above the second front surface A second interconnect structure; joining the first interconnect structure and the second interconnect structure to form a third interconnect structure, the third interconnect structure is disposed on the first front surface of the first substrate and the first interconnect structure; Between the second front surfaces of two substrates, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of first connection layers disposed above the plurality of first connection layers. A first etch stop layer, a plurality of ring-shaped second connection layers provided in the dielectric structure, and a plurality of ring-shaped second etch stop layers provided above the plurality of ring-shaped second connection layers; An etch to form a through A first via hole opening and a second via hole opening of the first substrate and a portion of the third interconnect structure, wherein the plurality of first etch stop layers above the plurality of first connection layers pass through the first A bottom of the through-hole opening is exposed. The second through-hole opening includes a first portion and a second portion coupled to each other. The etch-stop layer above the plurality of first connection layers passes through the second through-hole opening. A bottom of the second portion is exposed; a second etch is performed to remove a portion of the first etch stop layer and expose the bottom through the bottom of the first through hole opening and the bottom of the second portion of the second through hole opening. A plurality of first connection layers; and forming a first TSV conductor in the first via opening, and forming a second TSV conductor in the second via opening. The method according to claim 13, wherein the dielectric structure is exposed through a side wall of the first through-hole opening by performing the first etching, and the first through-hole opening is performed through the second etching. The sidewall exposes the first etch stop layer. The preparation method according to claim 13, wherein the dielectric structure is exposed through a side wall of the first portion of the second through-hole opening by performing the first etching, and by performing the first etching, by the first A side wall of the second portion of the two-via opening exposes the annular second etch stop layer, the annular second connection layer, and the dielectric structure. The manufacturing method according to claim 15, wherein the dielectric structure and the ring-shaped second etch stop layer are exposed through the sidewall of the first portion of the second through-hole opening by performing the second etching, and transmitting The second etching is performed, and the dielectric structure and the first etch stop layer are exposed through the sidewall of the second portion of the second via opening. The method of claim 13, wherein a width of the second portion of the second through-hole opening is smaller than a width of the first portion of the second through-hole opening. The method according to claim 13, wherein the first etch stop layer is provided above the plurality of first connection layers and above a surface facing the first substrate, and the ring-shaped second etch stop layer is provided at Above the ring-shaped second connection layer, above a surface facing the first substrate. The method according to claim 13, wherein the third interconnect structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected to the first TSV conductor and the second The TSV conductors are separated. The method according to claim 13, wherein an interface is formed between the first interconnection structure and the second interconnection structure.