TW202021083A - Semiconductor package structure and method for preparing the same - Google Patents

Abstract

The present disclosure provides a semiconductor package structure and method for preparing the same. The semiconductor package structure includes a first substrate, a second substrate, an interconnection structure disposed between the first substrate and the second substrate, a plurality of first TSV (through silicon via) conductors penetrating the first substrate and a portion of the interconnect structure, and a plurality of second TSV conductors penetrating the first substrate and a portion of the interconnect structure. The interconnect structure includes a dielectric structure and a plurality of first connecting layers and a plurality of annular second connecting layers disposed within the dielectric structure. At least one of plurality of first TSV conductors is in contact with one of the first connecting layers. At least one of plurality of second TSV conductors is in contact with one of the annular second connecting layers and another one of the first connecting layers.

Description

Semiconductor packaging structure and preparation method thereof

This application claims the priority and benefits of US Provisional Application No. 62/770,942 filed on November 23, 2018 and US Official Application No. 16/244,794 filed on January 10, 2019. The content of the official application in the United States is incorporated into this article by citation.

The present disclosure relates to a semiconductor packaging structure and a preparation method thereof, and particularly to a semiconductor packaging structure including through silicon via (TSV) and a preparation method thereof.

Semiconductor components are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor elements has become smaller and smaller, while having more functions and a larger number of integrated circuits. Due to the miniaturization of semiconductor elements, chip-on-chip technology is widely used in the manufacture of semiconductor packages.

In one method, a stack of at least two wafers (or dies) is used to form, for example, a memory device in the form of a three-dimensional (3D) package. Thus, compared to other semiconductor manufacturing processes, two A product with double the memory capacity. In addition to increasing memory capacity, stacked packages also provide improved mounting density and utilization efficiency of the mounting area. Because of these advantages, the research and development of stacked packaging technology is more accelerated.

A stacked package using through silicon via (TSV) is disclosed in the art. A stacked package using through-silicon vias has a structure with through-silicon vias in it, so the chips are electrically connected to each other through the through-silicon vias. Generally, through-silicon vias are formed by etching vertical vias through the substrate and filling the vias with a conductive material such as copper (Cu). Generally, the vertical vias formed through the substrate all have the same depth and are aligned with the pads formed in the wafer. In addition, a specific wiring line is designed and formed, and is formed as an endpoint where the TSV is located. However, this specific wiring will complicate the circuit design, especially in the dual-die stack design.

The above "prior art" description is only for providing background technology, and does not acknowledge that the above "prior art" description reveals the subject of this disclosure, does not constitute the prior art of this disclosure, and any description of "above technology" above Neither should be part of this case.

The present disclosure provides a semiconductor package structure, including: a first substrate, a second substrate, an interconnect structure, a plurality of first TSV conductors, and a plurality of second TSV conductors. The first substrate has a first front surface and a first back surface opposite to the first front surface. The second substrate has a second front surface and a second back surface opposite to the second front surface. The interconnect structure is disposed between the first front surface of the first substrate and the second front surface of the second substrate. The plurality of first TSV conductors penetrates the first substrate and a portion of the interconnection structure from the first back surface of the first substrate; the plurality of second TSV conductors from the first The first back surface of a substrate penetrates the first substrate and a portion of the interconnect structure. The interconnection structure includes a dielectric structure, a plurality of first connection layers are disposed in the dielectric structure, and a plurality of ring-shaped second connection layers are disposed in the dielectric structure. In some embodiments, at least one of the plurality of first TSV conductors is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of second TSV conductors is in contact with one of the plurality of ring-shaped second connection layers and the other of the plurality of first connection layers.

In some embodiments, the semiconductor package structure further includes a first etch stop layer disposed above the first connection layer, and a second etch stop layer disposed above the second connection layer.

In some embodiments, the first etch stop layer is disposed above a surface of the first connection layer facing the first substrate, and the second etch stop layer is disposed on a surface of the second connection layer facing the first substrate Above the surface.

In some embodiments, the surface of the first connection layer is separated from the dielectric structure through the first etch stop layer, and the surface of the second connection layer is separated from the dielectric structure through the second etch stop layer.

In some embodiments, the one of at least one of the plurality of first through-silicon via conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to the one of the first connection layer .

In some embodiments, the one of at least one of the plurality of second through-silicon via conductors includes a first portion and a second portion coupled to the first portion.

In some embodiments, the first portion of the second TSV conductor passes through a portion of the dielectric structure and the second etch stop layer. In some embodiments, the second portion of the second TSV conductor passes through the ring-shaped second connection layer, a portion of the dielectric structure, and the first etch stop layer and extends to the plurality of first Connect the other one in the layer.

In some embodiments, a width of the first part is greater than a width of the second part.

In some embodiments, the interconnect structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers. In some embodiments, the plurality of third connection layers are separated from the plurality of first TSV conductors and the plurality of second TSV conductors.

In some embodiments, an interface is formed within the interconnect structure.

In some embodiments, at least one of the plurality of first TSV conductors passes through the interface.

In some embodiments, at least one of the plurality of second TSV conductors passes through the interface.

The disclosure also provides a method for manufacturing a semiconductor structure, including the following steps. A first substrate is provided. The first substrate has a first front surface, a first back surface opposite to the first front surface, and a first interconnect structure disposed above the first front surface. A second substrate is provided. The second substrate has a second front surface, a second back surface opposite to the second front surface, and a second interconnect structure disposed above the second front surface. The first interconnect structure and the second interconnect structure are joined to form a third interconnect structure, the third interconnect structure is disposed on the first front surface of the first substrate and the second of the second substrate Between the front surface. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etching stop layers provided above the plurality of ring-shaped second connection layers. A first etching is performed to form a first via opening and a second via opening penetrating the first substrate and a portion of the third interconnect structure. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first via opening. The second through hole opening includes a first portion and a second portion coupled to each other. In some embodiments, the first etch stop layer above the first connection layer is exposed through a bottom of the second portion of the second via opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through the bottom of the first via opening and the bottom of the second portion of the second via opening. A first TSV conductor is formed in the first through hole opening, and a second TSV conductor is formed in the second through hole opening.

In some embodiments, by performing the first etching, the dielectric structure is exposed through a sidewall of the first through hole opening, and by performing the second etching, the sidewall is exposed through the sidewall of the first through hole opening The first etch stop layer.

In some embodiments, by performing the first etching, the dielectric structure is exposed through a sidewall of the first portion of the second via opening. In some embodiments, by performing the first etching, the annular second etch stop layer, the annular second connection layer, and the dielectric are exposed through a sidewall of the second portion of the second via opening Electrical structure.

In some embodiments, by performing the second etch, the dielectric structure and the ring-shaped second etch stop layer are exposed through the sidewall of the first portion of the second via opening. In some embodiments, by performing the second etch, the dielectric structure and the first etch stop layer are exposed through the sidewall of the second portion of the second via opening.

In some embodiments, a width of the second portion of the second through hole opening is smaller than a width of the first portion of the second through hole opening.

In some embodiments, the first etch stop layer is disposed above the first connection layer and above a surface facing the first substrate, and the ring-shaped second etch stop layer is disposed on the ring-shaped second connection layer Above and above a surface facing the first substrate.

In some embodiments, the third interconnection structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected to the first TSV conductor and the second TSV conductor separate.

In some embodiments, an interface is formed between the first interconnect structure and the second interconnect structure.

The disclosure also provides a method for manufacturing a semiconductor packaging structure. According to the manufacturing method, the connection layer is designed to provide electrical connection with the first and second through-silicon via conductors and is divided into two types: the first connection layer and the ring-shaped second connection layer. The first etch stop layer is formed above the first connection layer, and the ring-shaped second etch stop layer is formed above the ring-shaped second connection layer. Therefore, the first etch will stop at the first etch stop layer, but the first etch will continue to etch the dielectric structure through the ring-shaped second etch stop layer and the ring-shaped second connection layer, and finally stop at the The first etch stop layer.

Therefore, a first via opening is formed, wherein the dielectric structure is exposed through the sidewall of the first via opening, and the first etch stop layer is exposed through the bottom of the first via opening. Unlike the first through hole opening, the second through hole opening includes the first portion and the second portion connected to each other. In addition, due to the annular configuration of the second etch stop layer and the second connection layer, the first portion and the second portion are self-aligned when formed. The dielectric structure is exposed through the side wall of the first portion of the second through hole opening, and the dielectric structure, the ring-shaped second etch stop layer and the ring-shaped connection layer pass through the second of the second through hole opening Part of the side wall is exposed, and the first etch stop layer is exposed through a bottom of the second part of the second via opening. Then the first etch stop layer is removed to expose the first connection layer. Therefore, the dielectric structure and the first etch stop layer are now exposed through the side wall of the first through hole opening, and the first connection layer is exposed through the bottom of the first through hole opening. Unlike the first via opening, the dielectric structure and the ring-shaped second etch stop layer are now exposed through the sidewall of the first portion of the second via opening, the ring-shaped second connection layer, the dielectric The electrical structure and the first etch stop layer are now exposed through the sidewall of the second portion of the second via opening, and the first connection layer is exposed through the bottom of the second portion of the second via opening.

In the present disclosure, the first through silicon via conductor formed in the first through hole opening is in contact with the first connection layer, and the second through silicon via conductor formed in the second through hole opening is in contact with the first connection layer The ring-shaped second connection layer is in contact with the first connection layer. It should be noted that by providing the first connection layer and the ring-shaped second connection layer, it is possible to easily construct vertical electrical connections between different layers in the interconnect structure. Therefore, it is easy to construct the electrical connection between the two substrates. Therefore, no additional wiring for placing the conductors at the same height is required.

In contrast, compared to the application method without the ring-shaped second etch stop layer and the ring-shaped second connection layer, additional wiring is required to place conductors having the same height to form an electrical connection. Such extra wiring complicates the circuit design, especially in the dual die stack.

The technical features and advantages of the present disclosure have been summarized quite broadly above, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject of the patent application scope of the present disclosure will be described below. Those of ordinary skill in the technical field of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs should also understand that such equivalent construction cannot deviate from the spirit and scope of this disclosure defined by the appended patent application scope.

The following description of the present disclosure is accompanied by the drawings incorporated in and forming a part of the description to illustrate the disclosed embodiment, but the present disclosure is not limited to the embodiment. In addition, the following embodiments can appropriately integrate the following embodiments to complete another embodiment.

"One embodiment", "embodiment", "exemplary embodiment", "other embodiment", "another embodiment", etc. means that the embodiments described in this disclosure may include specific features, structures, or characteristics, however, Not every embodiment must include that particular feature, structure, or characteristic. Furthermore, repeated use of the term "in an embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment.

In order for the present disclosure to be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps will not be described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiment of the present disclosure is described in detail below. However, in addition to the implementation, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application.

FIG. 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor structure in some embodiments of the present disclosure. The manufacturing method 10 includes step 101, providing a first substrate having a first front surface, a first back surface opposite to the first front surface, and a first interconnect structure disposed above the first front surface . The manufacturing method 10 further includes step 102 of providing a second substrate having a second front surface, a second back surface opposite to the second front surface, and a second interconnection disposed above the second front surface structure. According to this embodiment, step 101 may be performed before, after, or simultaneously with step 102. The manufacturing method 10 further includes a step 104 of joining the first interconnect structure and the second interconnect structure to form the first front surface of the first substrate and the second front surface of the second substrate A third interconnection structure. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etching stop layers provided above the plurality of ring-shaped second connection layers. The manufacturing method 10 further includes step 106, performing a first etch to form a first via opening and a second via opening penetrating the first substrate and a portion of the third interconnect structure. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first via opening. In some embodiments, the second through-hole opening includes a first portion and a second portion coupled to each other, and the first etch stop layer above the first connection layer penetrates through the second through-hole opening One bottom of the two parts is exposed. Preparation method 10 further includes step 108, performing a second etch to remove a portion of the first etch stop layer and exposing the bottom of the first through-hole opening and the second portion of the second through-hole opening to expose the The first connection layer. The manufacturing method 10 further includes step 110, forming a first first TSV conductor in the first via opening, and forming a second TSV conductor in the second via opening. According to one or more embodiments, the method 10 of manufacturing the semiconductor structure will be further described.

FIG. 2 and FIG. 3 are schematic diagrams illustrating the manufacturing stages of the manufacturing method of the semiconductor package structure of some embodiments of the present disclosure. Referring to FIG. 2, a substrate 200 is provided according to step 101. In some embodiments, the substrate 200 includes silicon (Si). In other embodiments, the substrate 200 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon (strained silicon), silicon germanium (SiGe), silicon carbide (SiC), diamond, An epitaxial layer (epitaxy layer) or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 200 may include a silicon-on-insulator (SOI) substrate, but the disclosure is not limited thereto. The substrate 200 has a front surface 202F and a back surface 202B opposite to the front surface 202F, as shown in FIG. 2. In some embodiments, a circuit layer (not shown) is formed above or within the substrate 200 of the front surface 202F. The circuit layer may include circuit patterns or circuit elements, such as transistors, capacitors, and diodes, but the disclosure is not limited thereto. Therefore, the front surface 202F may be referred to as an active surface, but the present disclosure is not limited thereto.

The substrate 200 further includes an interconnect structure 210 disposed above the front surface 202F. The interconnect structure 210 includes a dielectric structure 212 formed by a plurality of dielectric layers, wherein a plurality of connection layers are formed in the plurality of dielectric layers. The dielectric structure 212 used to isolate the connection layer is also referred to as an inter-metal dielectric (IMD) layer. The dielectric structure 212 may include, but is not limited to, for example, silicon oxide (SiO), tetraethoxysilane (TEOS), phosphosilicate glass (PSG), or boron-phosphosilicate glass (BPSG). The connection layers in different dielectric layers are generally described as being in different layers, and the first to nth layers are called M1 to Mn. For example, the interconnect structure 210 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in FIG. 2. However, those skilled in the art should easily understand that the number of layers is not limited to three. A circuit layer and an interconnect structure 210 are disposed above the substrate 200. The substrate 200 may be a semiconductor chip or a die used for 3D chip packaging, wafer level packaging (WLP) or wafer bonding processes.

Still referring to FIG. 2, in this embodiment, the connection layer in the interconnect structure 210 is formed according to different purposes. For example, the connection layers 214a and 214b are designated to be electrically connected to the via conductor, and the connection layer 214c is designated to be the internal connection layer without contacting the via conductor. In some embodiments, the connection layers 214a, 214b, and 214c may be formed through conventional processes, such as but not limited to a dual damascene process. The connection layers 214a and 214b are different from the connection layer 214c. As shown in FIG. 2, the etch stop layer 216 a is disposed above a surface facing the connection layer 214 a of the substrate 200, and the etch stop layer 216 b is disposed above a surface facing the connection layer 214 b of the substrate 200. Unlike the connection layers 214a and 214b, the connection layer 214c does not have any etch stop layer on any of its surfaces, as shown in FIG. In some embodiments, the connection layers 214a, 214a, and 214c may include conductive materials such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co) , But this disclosure is not limited to this.

Importantly, the connection layers 214a and 214b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 214a serves as an end point of the vertical electrical connection, so it is designed to include a flat plate structure, wherein the surface of the connection layer 214a covered by the etch stop layer 216a also has a flat plate structure. Therefore, a sufficient contact area for the via conductor is provided through the connection layer 214a. The connection layers 214c are electrically connected to each other and/or to the connection layer 214a.

4A is a partial cross-sectional view of FIGS. 2 and 3, FIG. 4B is a schematic top view (or bottom view) of FIG. 4A, and FIG. 4C is a view opposite to the view shown in FIG. 4B. 4A-4C, in some embodiments, the connection layer 214b is used as part of the vertical connection. Therefore, the connection layer 214b is designed to include a ring configuration, and the etch stop layer 216b covering the surface of the connection layer 214b is also designed to include a ring configuration. 2 and 4B, in a top view of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b, the dielectric structure 212 can be observed from a center of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b. 2 and 4C, in a bottom view of the ring-shaped connection layer 214b and the ring-shaped etch stop layer 216b, the ring-shaped etch stop layer 216b completely covers the surface of the connection layer 214b to provide protection.

It is worth noting that the etch stop layer 216a and the ring-shaped etch stop layer 216b include materials that are different or sufficiently different in composition so that the etch stop layer 216a and the ring-shaped etch stop layer 216b can use appropriate etching relative to the dielectric structure 112 Chemical substances are selectively removed. In some embodiments, the etch stop layer 216a and the ring-shaped etch stop layer 216b may include the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), but the disclosure is not limited thereto.

Referring to FIG. 3, a substrate 300 is provided according to step 102. As described above, according to an embodiment, step 101 may be performed before, after, or simultaneously with step 102. In some embodiments, the substrate 300 includes silicon (Si). In other embodiments, the substrate 300 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon (strained silicon), silicon germanium (SiGe), silicon carbide (SiC), diamond, An epitaxial layer (epitaxy layer) or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 300 may include a silicon-on-insulator (SOI) substrate, but the disclosure is not limited thereto. The substrate 300 has a front surface 302F and a back surface 302B opposite to the front surface 302F, as shown in FIG. 3. In some embodiments, a circuit layer (not shown) is formed on or in the substrate 300 of the front surface 302F. The circuit layer may include circuit patterns or circuit elements, such as transistors, capacitors, and diodes, but the disclosure is not limited thereto. Therefore, the front surface 302F may be referred to as an active surface, but the present disclosure is not limited thereto.

The substrate 300 further includes an interconnect structure 310 disposed above the front surface 302F. The interconnect structure 310 includes a dielectric structure 312 formed by a plurality of dielectric layers, wherein a plurality of connection layers are formed in the plurality of dielectric layers. The dielectric structure 312 used to isolate the connection layer is also referred to as an inter-metal dielectric (IMD) layer. The dielectric structure 312 may include, but is not limited to, for example, silicon oxide (SiO), tetraethoxysilane (TEOS), phosphosilicate glass (PSG), or boron-phosphosilicate glass (BPSG). The connection layers in different dielectric layers are generally described as being in different layers, and the first to nth layers are called M1 to Mn. For example, the interconnect structure 310 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in FIG. 3. However, those skilled in the art should easily understand that the number of layers is not limited to three. A circuit layer and an interconnect structure 310 are disposed above the substrate 300. The substrate 300 may be a semiconductor chip or a die used for 3D chip packaging, wafer level packaging (WLP), or wafer bonding processes.

Still referring to FIG. 3, in this embodiment, the connection layer in the interconnect structure 310 is formed according to different purposes. For example, the connection layers 314a and 314b are designated to be electrically connected to the via conductor, and the connection layer 314c is designated to be the internal connection layer without contacting the via conductor. In some embodiments, the connection layers 314a, 314b, and 314c may be formed by conventional processes, such as but not limited to a dual damascene process. The connection layers 314a and 314b are different from the connection layer 314c. As shown in FIG. 3, the etch stop layer 316 a is provided above a surface facing the connection layer 314 a of the substrate 300, and the etch stop layer 316 b is provided above a surface facing the connection layer 314 b of the substrate 300. Unlike the connection layers 314a and 314b, the connection layer 314c does not have any etch stop layer on any of its surfaces, as shown in FIG. In some embodiments, the connection layers 314a, 314a, and 314c may include conductive materials such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co) , But this disclosure is not limited to this.

Importantly, the connection layers 314a and 314b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 314a serves as an end point of the vertical electrical connection, so it is designed to include a flat plate structure, wherein the surface of the connection layer 314a covered by the etch stop layer 316a also has a flat plate structure. Therefore, a sufficient contact area for the via conductor is provided through the connection layer 314a. In addition, the connection layers 314c are electrically connected to each other and/or to the connection layer 314a.

4A-4C, in some embodiments, the connection layer 314b is used as a part of the vertical connection. Therefore, the connection layer 314b is designed to include a ring configuration, and the etch stop layer 316b covering the surface of the connection layer 314b is also designed to include a ring configuration. Referring to FIGS. 3 and 4B, in a top view of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b, the dielectric structure 312 can be observed from a center of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b. 3 and 4C, in a bottom view of the ring-shaped connection layer 314b and the ring-shaped etch stop layer 316b, the ring-shaped etch stop layer 316b completely covers the surface of the connection layer 314b to provide protection.

It is worth noting that the etch stop layer 316a and the ring-shaped etch stop layer 316b include materials that are different or sufficiently different in composition so that the etch stop layer 316a and the ring-shaped etch stop layer 316b can use appropriate etching relative to the dielectric structure 312 Chemical substances are selectively removed. In some embodiments, the etch stop layer 316a and the ring-shaped etch stop layer 316b may include the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), but the disclosure is not limited thereto.

5 to 9 are schematic diagrams illustrating various manufacturing stages of the manufacturing method of the semiconductor package structure of the disclosed embodiment. 5, next, the substrate 200 and the substrate 300 are bonded. In some embodiments, the substrate 200 is turned over to be bonded to the substrate 300, as shown in FIG. In some embodiments, although not shown, the substrate 300 is turned over to be bonded to the substrate 300. It should be noted that the substrate 200 and the substrate 300 are joined in a face-to-face manner. By vertically stacking dies with different functions in a face-to-face manner, a face-to-face communication is realized between dies with different functions. In addition, compared with a semiconductor element having dies having different functions arranged in a laterally adjacent manner, vertically stacking dies having different functions in a face-to-face manner reduces the occupied area of the semiconductor element. In addition, the signal paths of different-function dies stacked vertically in a face-to-face manner are shorter than the signal paths of different-function dies arranged laterally adjacent; therefore, the different-function dies vertically stacked in the face-to-face manner of the present invention Can be applied to high-speed electronic components.

In some embodiments, according to step 104, the interconnect structure 210 and the interconnect structure 310 are joined to form the interconnect structure 400 disposed between the front surface 202F of the substrate 200 and the front surface 302F of the substrate 300. Therefore, the interconnect structure 400 includes the dielectric structure 402 formed by the dielectric structures 212, 312 and the connection layers 214a to 214c and 314a to 314c. In some embodiments, the interface 404 is formed between the interconnect structure 210 and the interconnect structure 310. In other words, the interface 404 is formed within the interconnect structure 400.

Referring to FIG. 6, according to step 106, a first etching is performed to form a first through-hole opening 410 and a second through-hole opening 412 penetrating a portion of the substrate 200 and the interconnect structure 400. In some embodiments, a first etch is performed on the rear surface 202B of the substrate 200, as shown in FIG. It should be noted that the first etch removes part of the dielectric structure 402 and stops at the etch stop layers 216a, 316a to form the first via opening 410. It is worth noting that the first etching removes part of the dielectric structure 402 from the center of the ring-shaped etch stop layers 216b, 316b and the center of the ring-shaped connection layers 214b, 314b, and stops at the etch stop layers 216a, 316a to The second through hole opening 412 is formed. Therefore, the first through hole opening 402 and the second through hole opening 404 having the same depth or different depths are formed as shown in FIG. 6. In some embodiments, by performing the first etching, the substrate 200 and the dielectric structure 402 are exposed through the sidewalls of the first via opening 410, and the etch stop layers 216a, 316a are exposed through the bottom of the first via opening 410. It should be noted that the depths of the first through holes 402 may be the same as or different from each other. In some embodiments, a depth of the first via opening is determined by the layer where the etch stop layers 216a, 316a are located, as shown in FIG.

Still referring to FIG. 6, the second through hole opening 412 includes a first portion 414a and a second portion 414b connected to each other. In some embodiments, by performing the first etch, the substrate 200 and the dielectric structure 402 are exposed through the sidewalls of the first portion 414a of the second via opening 412, and the ring-shaped etch stop layers 216b, 316b pass through the second via opening 412 The bottom of the first portion 414a is exposed. In addition, by performing the first etching, the annular connection layers 214b, 314b and the dielectric structure 402 are exposed through the sidewalls of the second portion 414b of the second via opening 412, and the etch stop layers 216a, 316a are penetrated through the second via opening 412 The bottom of the second portion 414b is exposed. The width of the second portion 414b of the second through hole opening 412 is smaller than the width of the first portion 414a of the second through hole opening 412. In some embodiments, the width of the second portion 414b is substantially equal to the inner diameter of the ring-shaped etch stop layers 216b, 316b, or substantially equal to the inner diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto. Therefore, due to the annular configuration of the annular etch stop layers 216b, 316b and the annular connection layers 214b, 314b, the first portion 414a and the second portion 414b are self-aligned when formed. It should be noted that the depth of the first portion 414a and the depth of the second portion 414b may be the same as or different from each other. In some embodiments, the depth of the first portion 414a is determined by the layer where the annular etch stop layers 216b, 316b are located, and the depth of the second portion 414b is determined by the layer where the etch stop layers 216a, 316a are located, as shown in FIG.

It should be noted that because the etch rate of the etch stop layer is different from the etch rate of the dielectric structure 402, the first via opening 410 and the second via opening 412 can be formed without damaging the etch stop layers 216a, 216b, 316a, and 316B.

Referring to FIG. 7, according to step 108, a second etch is performed to remove the etch stop layers 216a and 316a from the bottom of the first and second via openings 410 and 412. Therefore, the connection layers 214a, 314a are exposed through the bottom of the first via opening 410. In some embodiments, by performing the second etching, the substrate 200, the dielectric structure 402, and the etch stop layers 216a, 316a are exposed through the sidewalls of the first via opening 410, and the connection layers 214a, 314a are now performed by performing the second The etching is exposed through the bottom of the first via opening 410.

Still referring to FIG. 7, by performing the second etching, the substrate 200, the dielectric structure 402 and the ring-shaped etch stop layers 216b, 316b are exposed through the sidewalls of the first portion 414a, and the connection layers 214a, 314a are now opened through the second through holes The bottom of the second portion 414b of 412 is exposed.

It should be noted that because the etch rate of the etch stop layer is different from the etch rate of the dielectric structure 402, the etch stop layers 216a, 216b, 316a, 316b can be removed without damaging the dielectric structure 402, as shown in FIG.

8 and 9, according to step 110, a first first TSV conductor 430 is formed in the first via opening 410, and a second TSV conductor 432 is formed in the second via opening 412. In some embodiments, step 100 further includes the following steps: For example, a barrier/glue layer 420 is disposed above the sidewalls and bottom of the first through hole opening 410 and the second through hole opening 412, as shown in FIG. 8. In some embodiments, the barrier/glue layer 420 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), manganese (Mn), titanium/copper (Ti/Cu), and/or copper (Cu), but the disclosure is not limited thereto.

Referring to FIG. 9, a conductive material 422 such as copper is next formed to fill the first and second via conductors 410 and 412. Therefore, the first TSV conductor 430 and the second TSV conductor 432 are obtained, as shown in FIG. 9.

As shown in FIG. 9, a semiconductor package structure 50 is provided. The semiconductor package structure 50 includes a substrate 200 having a front surface 202F and a rear surface 202B opposite the front surface 202F; a substrate 300 having a front surface 302F and a rear surface 302B opposite the front surface 302F; an interconnect structure 400 provided on the substrate 200 Between the front surface 202F of the substrate and the front surface 302F of the substrate 300; a plurality of first through-silicon via conductors 430 penetrating a portion of the substrate 200 and the interconnection structure 400 from the rear surface 202B of the substrate 200; The TSV conductor 432 penetrates the substrate 200 and a portion of the interconnect structure 400 from the rear surface 202B of the substrate 200. In some embodiments, at least one of the first through-silicon via conductors 430 passes through the interface 404. In some embodiments, at least one of the second through-silicon via conductors 432 passes through the interface 404.

As shown in FIG. 9, the interconnection structure 400 includes a dielectric structure 402, a plurality of connection layers 214 a and 314 a disposed in the dielectric structure 402, and a plurality of ring-shaped connection layers 214 b and 314 b disposed in the dielectric structure 402. In some embodiments, at least one of the first TSV conductors 430 is in contact with one of the connection layers 214a or 314a. In some embodiments, at least one of the second TSV conductors 432 is in contact with one of the ring-shaped second connection layers 214b, 314b and the other of the connection layers 214a or 314a. As described above, the interconnect structure 400 may further include a plurality of connection layers 214c, 314c, which are electrically connected to each other and/or electrically connected to the connection layers 214a, 314a. However, the connection layers 214c, 314c are separated from the first TSV conductor 430, the second TSV conductor 432, and the ring-shaped connection layers 214b, 314b, as shown in FIG.

In some embodiments, the semiconductor package structure 50 further includes etch stop layers 216a, 316a disposed above the connection layers 214a, 314a and etch stop layers 216b, 316b disposed above the ring-shaped connection layers 214b, 314b. In addition, the etch stop layers 216 a and 316 a are provided above a surface of the connection layer 214 a and 314 a facing the substrate 200, and the ring-shaped etch stop layers 216 b and 316 b are provided above a surface of the connection layer 214 b and 314 b facing the substrate 200. Therefore, the surfaces of the connection layers 214a, 314a are separated from the dielectric structure 402 by the etch stop layers 216a, 316a, and the surfaces of the ring-shaped connection layers 214b, 314b are separated from the dielectric structure 402 by the ring-shaped etch stop layers 216b, 316b.

As shown in FIG. 9, the first TSV conductor 430 passes through a portion of the dielectric structure 402 and the etch stop layers 216a, 316a, and extends to one of the connection layers 214a or 314a. In some embodiments, at least one of the plurality of second through-silicon via conductors 432 includes a first portion 434a and a second portion 434b coupled to the first portion 434a. In some embodiments, the first portion 434a of the second TSV conductor 432 passes through a portion of the dielectric structure 402 and the ring-shaped etch stop layers 216b, 316b. In some embodiments, the second portion 434b of the second TSV conductor 432 passes through the ring-shaped connection layers 214b, 314b and a portion of the dielectric structure 402 and the etch stop layers 216a, 316a, and extends to another connection layer 214a or 314a.

9, the first TSV conductor 430 may have a uniform width, the first portion 434a of the second TSV conductor 432 may have a uniform width, and the second portion 434b of the second TSV conductor 432 Can have a consistent width. In some embodiments, the first TSV conductor 430 may include the same width. In other embodiments, the first TSV conductor 430 may include different widths, as shown in FIG. 9. For example, when the first TSV conductor 430 is electrically connected to a power source or ground, the width of such a first TSV conductor 430 may be greater than the width of other first TSV conductors 430, but this disclosure does not Limited to this. Similarly, in some embodiments, the second TSV conductor 432 may include the same width. In other embodiments, the second TSV conductor 432 may include different widths. For example, when the second TSV conductor 432 is electrically connected to a power source or ground, the width of this second TSV conductor 432 may be greater than the width of other second TSV conductors 432, but the disclosure is not limited to this. In addition, the width of the first portion 434a is greater than the width of the second portion 434b. In some embodiments, the width of the first portion 434a is smaller than the outer diameter of the ring-shaped etch stop layers 216b, 316b, or smaller than the outer diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto. However, the width of the first portion 434a is larger than the inner diameter of the ring-shaped etch stop layers 216b, 316b, or larger than the inner diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto. In some embodiments, the width of the second portion 434b is substantially equal to the inner diameter of the ring-shaped etch stop layers 216b, 316b, or substantially equal to the inner diameter of the ring-shaped connection layers 214b, 314b, but the disclosure is not limited thereto.

The present disclosure provides a method 10 for preparing a semiconductor packaging structure. According to the manufacturing method 10, the connection layers 214a, 214b, 314a, and 314b are designed to provide electrical connection with the first and second through-silicon via conductors 430 and 432, which are divided into two types: connection layers 214a and 314a, and Ring-shaped connection layers 214b and 314b. The etch stop layers 216a, 316a are formed above the connection layers 214a, 314a, and the ring-shaped etch stop layers 216b, 316b are formed above the ring-shaped connection layers 214b, 314b. Therefore, the first etch will stop at the etch stop layers 216a, 316a, but the first etch will continue to etch the dielectric structure 402 through the ring-shaped etch stop layers 216b, 316b and the ring-shaped connection layers 214b, 314b, and finally stop at the etch Stop layers 216a, 316a. As a result, the first via opening 410 and the second via opening 412 are formed. The second through hole opening 412 includes a first portion 414a and a second portion 414b connected to each other. Furthermore, due to the annular configuration of the annular etch stop layers 216b, 316b and the annular connection layers 214b, 314b, the first portion 414a and the second portion 414b are self-aligned when formed. Thereafter, the etch stop layers 216a, 316a are removed by performing a second etch to expose the connection layers 214a, 314a.

In the present disclosure, the first TSV conductor 430 formed in the first TSV 410 is in contact with the connection layers 214a, 314a, and the second TSV conductor 432 formed in the second TSV 412 is The ring-shaped connection layers 214b and 314b are in contact with the connection layers 214a and 314a. It should be noted that because the connection layers 214a, 314a and the ring-shaped connection layers 214b, 314b are provided, vertical electrical connections between different layers in the interconnect structure 400 can be easily formed. Therefore, the electrical connection between the two substrates 200 and 300 is easily formed. Therefore, no additional wiring for placing the conductors at the same height is required.

In contrast, compared to the application method without the ring-shaped second etch stop layer and the ring-shaped second connection layer, additional wiring is required to place conductors having the same height to form an electrical connection. Such extra wiring complicates the circuit design, especially in the dual die stack.

The present disclosure provides a semiconductor packaging structure. The semiconductor package structure includes: a first substrate having a first front surface and a first back surface opposite to the first front surface; a second substrate having a second front surface and opposite the second front surface A second back surface; an interconnection structure disposed between the first front surface of the first substrate and the second front surface of the second substrate; a plurality of first TSV conductors from the first substrate The first back surface penetrates the first substrate and a portion of the interconnect structure; and a plurality of second TSV conductors penetrate the first substrate and the first substrate from the first back surface Part of the interconnect structure. The interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of ring-shaped second connection layers disposed in the dielectric structure. In some embodiments, at least one of the plurality of first TSV conductors is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of second through-silicon via conductors is in contact with one of the plurality of second connection layers and the other of the plurality of first connection layers.

The disclosure also provides a method for manufacturing a semiconductor structure. The preparation method includes the following steps. A first substrate is provided. The first substrate has a first front surface, a first back surface opposite to the first front surface, and a first interconnect structure disposed above the first front surface. A second substrate is provided. The second substrate has a second front surface, a second back surface opposite to the second front surface, and a second interconnect structure disposed above the second front surface. The first interconnect structure and the second interconnect structure are joined to form a third interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers A plurality of ring-shaped second connection layers provided in the dielectric structure and a plurality of ring-shaped second etching stop layers provided above the plurality of ring-shaped second connection layers. A first etching is performed to form a first via opening and a second via opening penetrating the first substrate and a portion of the third interconnect structure. In some embodiments, the plurality of first etch stop layers above the plurality of first connection layers are exposed through a bottom of the first via opening. The second through hole opening includes a first part and a second part connected to each other. In some embodiments, the first etch stop layer above the first connection layer is exposed through a bottom of the second via opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through the bottom of the first via opening and the bottom of the second portion of the second via opening. A first TSV conductor is formed in the first through hole opening, and a second TSV conductor is formed in the second through hole opening.

Although the disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the above processes can be implemented by different methods, and many of the above processes can be replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of this disclosure that they can use existing or future development processes, machinery, manufacturing, and materials that have the same functions or achieve substantially the same results as the corresponding embodiments described in this disclosure. Composition, means, method, or step. Accordingly, these processes, machinery, manufacturing, material composition, means, methods, or steps are included in the scope of the patent application of this application.

10: Preparation method 50: Semiconductor packaging structure 101: Step 102: Step 104: Step 106: Step 108: Step 110: Step 200: base 202B: back surface 202F: front surface 210: Interconnect structure 212: Dielectric structure 214a: connection layer 214b: connection layer 214c: connection layer 216a: Etching stop layer 216b: etch stop layer 300: base 302B: Back surface 302F: front surface 310: Interconnect structure 312: Dielectric structure 314a: connection layer 314b: Connection layer 314c: Connection layer 316a: Etching stop layer 316b: Etching stop layer 400: interconnection structure 402: Dielectric structure 404: Interface 410: first through hole opening 412: Second through hole opening 414a: Part I 414b: Part Two 420: barrier and glue layer 422: conductive material 430: First through-silicon via conductor 432: Second TSV conductor 434a: Part One 434b: Part Two M1: first floor M2: second floor M3: third floor

When referring to the embodiment and the scope of patent application for consideration of the drawings, the disclosure content of the present application can be more fully understood, and the same element symbols in the drawings refer to the same elements. FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor package structure in some embodiments of the present disclosure. FIG. 2 and FIG. 3 are schematic diagrams illustrating the manufacturing stages of the manufacturing method of the semiconductor package structure of some embodiments of the present disclosure. 4A is a partial cross-sectional view of FIGS. 2 and 3. 4B is a schematic top view (or schematic bottom view) of FIG. 4. 4C is a view opposite to that shown in FIG. 4B. 5 to 9 are schematic diagrams illustrating various manufacturing stages of the manufacturing method of the semiconductor package structure of the disclosed embodiment.

10: Preparation method

101: Step

102: Step

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Claims (20)

A semiconductor packaging structure, including: A first substrate, the first substrate includes a first front surface and a first back surface opposite to the first front surface; A second substrate including a second front surface and a second back surface opposite to the second front surface; An interconnection structure disposed between the first front surface of the first substrate and the second front surface of the second substrate, wherein the interconnection structure includes a dielectric structure and a plurality of first connection layers are disposed on In the dielectric structure, and a plurality of ring-shaped second connection layers are disposed in the dielectric structure; A plurality of first through silicon via (TSV) conductors, penetrating the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; and A plurality of second TSV conductors, penetrating the first substrate and a part of the interconnection structure from the first back surface of the first substrate; Wherein at least one of the plurality of first through-silicon via conductors is in contact with one of the plurality of first connection layers, and at least one of the plurality of second through-silicon via conductors and the plurality of ring-shaped first One of the two connection layers and the other of the plurality of first connection layers are in contact. The semiconductor package structure according to claim 1, further comprising a first etch stop layer disposed above the first connection layer, and a second etch stop layer disposed above the second connection layer. The semiconductor package structure according to claim 2, wherein the first etch stop layer is disposed above a surface of the first connection layer facing the first substrate, and the second etch stop layer is disposed on the second connection layer facing Above a surface of the first substrate. The semiconductor package structure according to claim 3, wherein the surface of the first connection layer is separated from the dielectric structure through the first etch stop layer, and the surface of the second connection layer passes through the second etch stop layer and The dielectric structure is separated. The semiconductor package structure of claim 2, wherein the one of at least one of the plurality of first through-silicon via conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to the first Connect this one in the layer. The semiconductor package structure of claim 2, wherein the one of at least one of the plurality of second through-silicon via conductors includes a first portion and a second portion coupled to the first portion. The semiconductor package structure of claim 6, wherein the first portion of the second TSV conductor passes through a portion of the dielectric structure and the second etch stop layer, and the second TSV conductor of the The second portion passes through the ring-shaped second connection layer, a portion of the dielectric structure and the first etch stop layer and extends to the other of the plurality of first connection layers. The semiconductor package structure of claim 6, wherein a width of the first part is greater than a width of the second part. The semiconductor package structure according to claim 6, wherein the interconnection structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected with the plurality of first through-silicon via conductors and the plurality of The second TSV conductor is separated. The semiconductor package structure of claim 1, wherein an interface is formed within the interconnect structure. The semiconductor package structure of claim 10, wherein at least one of the plurality of first TSV conductors passes through the interface. The semiconductor package structure of claim 10, wherein at least one of the plurality of second TSV conductors passes through the interface. A method for preparing a semiconductor packaging structure includes: Providing a first substrate having a first front surface, a first back surface opposite to the first front surface, and a first interconnect structure disposed above the first front surface; Providing a second substrate having a second front surface, a second back surface opposite to the second front surface, and a second interconnect structure disposed above the second front surface; The first interconnect structure and the second interconnect structure are joined to form a third interconnect structure, the third interconnect structure is disposed on the first front surface of the first substrate and the second of the second substrate Between the front surfaces, wherein the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed in the dielectric structure, and a plurality of first etch stop layers disposed above the plurality of first connection layers A plurality of ring-shaped second connection layers disposed in the dielectric structure and a plurality of ring-shaped second etching stop layers disposed above the plurality of ring-shaped second connection layers; Performing a first etching to form a first through hole opening and a second through hole opening penetrating the first substrate and a portion of the third interconnect structure, wherein the plurality of first connection layers above the plurality of first connection layers The first etch stop layer is exposed through a bottom of the first through hole opening, the second through hole opening includes a first portion and a second portion coupled to each other, and the etch stop layer above the first connection layer penetrates through the A bottom of the second portion of the second through hole opening is exposed; Performing a second etch to remove a portion of the first etch stop layer and expose the first connection layer through the bottom of the first via opening and the bottom of the second portion of the second via opening; and A first through silicon via conductor is formed in the first through hole opening, and a second through silicon via conductor is formed in the second through hole opening. The manufacturing method according to claim 13, wherein by performing the first etching, the dielectric structure is exposed through a sidewall of the first through hole opening, and by performing the second etching, through the first through hole opening The side wall of the exposed first etching stop layer. The manufacturing method according to claim 13, wherein by performing the first etching, the dielectric structure is exposed through a sidewall of the first portion of the second through hole opening, by performing the first etching, by performing the first A side wall of the second portion of the two via openings exposes the annular second etch stop layer, the annular second connection layer and the dielectric structure. The manufacturing method according to claim 15, wherein by performing the second etching, the sidewall of the first portion of the second through hole opening exposes the dielectric structure and the ring-shaped second etching stop layer, and penetrates The second etch is performed, exposing the dielectric structure and the first etch stop layer through the sidewall of the second portion of the second via opening. The manufacturing method according to claim 13, wherein a width of the second portion of the second through hole opening is smaller than a width of the first portion of the second through hole opening. The manufacturing method according to claim 13, wherein the first etch stop layer is provided above the first connection layer and above a surface facing the first substrate, and the ring-shaped second etch stop layer is provided in the ring Above the second connection layer and above a surface facing the first substrate. The manufacturing method according to claim 13, wherein the third interconnection structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and connected to the first TSV conductor and the second The through-silicon via conductors are separated. The manufacturing method according to claim 13, wherein an interface is formed between the first interconnect structure and the second interconnect structure.

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