CN111223831A

CN111223831A - Semiconductor packaging structure and preparation method thereof

Info

Publication number: CN111223831A
Application number: CN201910160409.2A
Authority: CN
Inventors: 丘世仰
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2018-11-23
Filing date: 2019-03-04
Publication date: 2020-06-02
Anticipated expiration: 2039-03-04
Also published as: TWI680557B; TW202021083A; CN111223831B

Abstract

The present disclosure provides a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a first substrate, a second substrate, an interconnect structure disposed between the first substrate and the second substrate, a plurality of first through-silicon-via conductors penetrating the first substrate and a portion of the interconnect structure, and a plurality of second through-silicon-via conductors penetrating the first substrate and a portion of the interconnect structure. The interconnect structure includes a dielectric structure, a plurality of first connection layers, and a plurality of annular second connection layers disposed within the dielectric structure. At least one of the first through-silicon vias is in contact with one of the first connection layers. At least one of the plurality of second through-silicon via conductors is in contact with one of the annular second connection layers and another one of the first connection layers.

Description

Semiconductor packaging structure and preparation method thereof

The present application claims priority and benefit from U.S. provisional application nos. 62/770,942 of 2018/11/23 and 16/244,794 of U.S. official application No. 2019/01/10, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a semiconductor package structure and a method for fabricating the same, and more particularly, to a semiconductor package structure including Through Silicon Vias (TSVs) and a method for fabricating the same.

Background

Semiconductor components are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor components has become smaller and smaller, while having more functions and a larger number of integrated circuits. Due to the miniaturization of semiconductor elements, wafer-on-wafer (chip) technology is widely used in the manufacture of semiconductor packages.

In one approach, a memory device, for example, is formed in a three-dimensional (3D) package using a stack of at least two dies (or dies), which may produce a product with twice the memory capacity compared to other semiconductor integration processes. In addition to increasing memory capacity, stacked packages also provide improved mounting density and efficiency of utilization of the mounting area. Due to these advantages, research and development of the stack packaging technology is more accelerated.

A stack package using through-silicon vias (through-silicon vias) is disclosed in the art. The stack package using the through-silicon-via has a structure having the through-silicon-via therein, so that the wafers are electrically connected to each other through the through-silicon-via. Generally, through-silicon vias are formed by etching vertical vias through a substrate and filling the vias with a conductive material, such as copper (Cu). Typically, the vertical vias formed through the substrate are all of the same depth and are aligned with the pads formed in the wafer. In addition, a specific wiring line is designed and formed as a terminal where a through-silicon via is located. However, such special routing would complicate circuit design, especially in dual die stacked designs.

The above description of "prior art" is merely provided as background, and is not an admission that the above description of "prior art" is disclosing the object of the present disclosure, does not constitute prior art to the present disclosure, and should not be taken as any part of the present disclosure.

Disclosure of Invention

The present disclosure provides a semiconductor package structure, including: a first substrate, a second substrate, an interconnect structure, a plurality of first through-silicon-via conductors, and a plurality of second through-silicon-via conductors. The first substrate has a first front surface and a first back surface opposite to the first front surface. The second substrate has a second front surface and a second back surface opposite to the second front surface. The interconnect structure is disposed between the first front surface of the first substrate and the second front surface of the second substrate. The plurality of first through-silicon-via conductors penetrate the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; the plurality of second through-silicon via conductors penetrate the first substrate and a portion of the interconnect structure from the first back surface of the first substrate. The interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of annular second connection layers disposed within the dielectric structure. In some embodiments, at least one of the plurality of first through-silicon-via conductors is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of second through-silicon-via conductors is in contact with one of the plurality of annular second connection layers and another of the plurality of first connection layers.

In some embodiments, the semiconductor package structure further comprises: a first etch stop layer disposed over the first connection layer; and a second etch stop layer disposed above the second connection layer.

In some embodiments, the first etch stop layer is disposed over a surface of the first connection layer facing the first substrate, and the second etch stop layer is disposed over a surface of the second connection layer facing the first substrate.

In some embodiments, the surface of the first connection layer is separated from the dielectric structure by the first etch stop layer, and the surface of the second connection layer is separated from the dielectric structure by the second etch stop layer.

In some embodiments, the at least one of the plurality of first through-silicon-via conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to the one of the first connection layers.

In some embodiments, the at least one of the plurality of second through-silicon-via conductors includes a first portion and a second portion coupled to the first portion.

In some embodiments, the first portion of the second through-silicon-via conductor passes through a portion of the dielectric structure and the second etch stop layer. In some embodiments, the second portion of the second through-silicon-via conductor passes through the annular second connection layer, a portion of the dielectric structure, and the first etch stop layer and extends to the another of the plurality of first connection layers.

In some embodiments, a width of the first portion is greater than a width of the second portion.

In some embodiments, the interconnect structure further comprises a plurality of third connection layers electrically connected to the plurality of first connection layers. In some embodiments, the plurality of third connection layers are separate from the plurality of first through-silicon via conductors and the plurality of second through-silicon via conductors.

In some embodiments, an interface is formed within the interconnect structure.

In some embodiments, at least one of the plurality of first through-silicon-via conductors passes through the interface.

In some embodiments, at least one of the plurality of second through-silicon-via conductors passes through the interface.

The present disclosure further provides a method for fabricating a semiconductor structure, comprising the following steps. A first substrate is provided, the first substrate having a first front surface, a first back surface opposite the first front surface, and a first interconnect structure disposed over the first front surface. A second substrate is provided, the second substrate having a second front surface, a second back surface opposite to the second front surface, and a second interconnect structure disposed over the second front surface. Bonding the first interconnect structure and the second interconnect structure to form a third interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, a plurality of first etch stop layers disposed above the plurality of first connection layers, a plurality of annular second connection layers disposed within the dielectric structure, and a plurality of annular second etch stop layers disposed above the plurality of annular second connection layers. A first etch is performed to form a first via opening and a second via opening through the first substrate and a portion of the third interconnect structure. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first via opening. The second via opening includes a first portion and a second portion coupled to each other. In some embodiments, the first etch stop layer over the first connection layer is exposed through a bottom of the second portion of the second via opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through a bottom of the first via opening and a bottom of the second portion of the second via opening. A first through-silicon-via conductor is formed in the first through-hole opening, and a second through-silicon-via conductor is formed in the second through-hole opening.

In some embodiments, the dielectric structure is exposed through a sidewall of the first via opening by performing the first etch, and the first etch stop layer is exposed through the sidewall of the first via opening by performing the second etch.

In some embodiments, the dielectric structure is exposed through a sidewall of the first portion of the second via opening by performing the first etch. In some embodiments, by performing the first etch, the annular second etch stop layer, the annular second connection layer, and the dielectric structure are exposed through a sidewall of the second portion of the second via opening.

In some embodiments, the dielectric structure and the annular second etch stop layer are exposed through the sidewall of the first portion of the second via opening by performing the second etch. In some embodiments, the dielectric structure and the first etch stop layer are exposed through the sidewall of the second portion of the second via opening by performing the second etch.

In some embodiments, a width of the second portion of the second via opening is less than a width of the first portion of the second via opening.

In some embodiments, the first etch stop layer is disposed over the first connection layer and over a surface facing the first substrate, and the annular second etch stop layer is disposed over the annular second connection layer and over a surface facing the first substrate.

In some embodiments, the third interconnect structure further includes a plurality of third connection layers electrically connected to the plurality of first connection layers and separated from the first and second through-silicon via conductors.

In some embodiments, an interface is formed between the first interconnect structure and the second interconnect structure.

The present disclosure further provides a method for manufacturing a semiconductor package structure. According to the manufacturing method, the connection layer is designed to provide electrical connection to the first and the second through-silicon via conductors, which are classified into two types: the first tie layer and the annular second tie layer. The first etching stop layer is formed above the first connection layer, and the annular second etching stop layer is formed above the annular second connection layer. Thus, the first etch will stop at the first etch stop layer, but the first etch will continue to etch the dielectric structure through the annular second etch stop layer and the annular second connection layer, eventually stopping at the first etch stop layer.

Thus, a first via opening is formed, wherein the dielectric structure is exposed through the sidewall of the first via opening and the first etch stop layer is exposed through a bottom of the first via opening. The second via opening includes the first portion and the second portion connected to each other, different from the first via opening. Furthermore, due to the annular configuration of the second etch stop layer and the second connection layer, the first portion and the second portion are self-aligned when formed. The dielectric structure is exposed through the sidewall of the first portion of the second via opening, the dielectric structure, the annular second etch stop layer, and the annular connection layer are exposed through the sidewall of the second portion of the second via opening, and the first etch stop layer is exposed through a bottom of the second portion of the second via opening. The first etch stop layer is then removed to expose the first connection layer. Thus, the dielectric structure and the first etch stop layer are now exposed through the sidewall of the first via opening, and the first connection layer is exposed through the bottom of the first via opening. The dielectric structure and the annular second etch stop layer are now exposed through the sidewall of the first portion of the second via opening, different from the first via opening, the annular second connection layer, the dielectric structure and the first etch stop layer are now exposed through the sidewall of the second portion of the second via opening, and the first connection layer is exposed through the bottom of the second portion of the second via opening.

In the present disclosure, the first through-silicon via conductor formed in the first via opening is in contact with the first connection layer, and the second through-silicon via conductor formed in the second via opening is in contact with the annular second connection layer and the first connection layer. It should be noted that by providing the first connection layer and the ring-shaped second connection layer, vertical electrical connections between different layers in the interconnect structure can be easily constructed. Therefore, the electrical connection between the two substrates is easily constructed. Therefore, additional wiring for placing the conductors at the same height is not required.

In contrast, compared to the application method without the annular second etch stop layer and the annular second connection layer, an additional wiring is required to place conductors having the same height to form an electrical connection. Such additional routing complicates circuit design, particularly in dual die stacks.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages, as defined in the claims, which constitute this disclosure, will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure may be more fully understood by reference to the following description and appended claims, taken together with the accompanying drawings, in which like reference numerals refer to like elements.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor package structure in some embodiments of the present disclosure.

Fig. 2 and 3 are schematic diagrams illustrating stages in the manufacture of methods for fabricating semiconductor packages according to some embodiments of the present disclosure.

Fig. 4A is a partial sectional view of fig. 2 and 3.

Fig. 4B is a schematic top view (or schematic bottom view) of fig. 4A.

Fig. 4C is a view opposite to the view shown in fig. 4B.

Fig. 5 to 9 are schematic views illustrating various stages of manufacturing methods of a semiconductor package structure according to embodiments of the present disclosure.

[ description of reference ]

10 preparation method

50 semiconductor packaging structure

101 step

102 step

104 step

106 step

108 step

110 step

200 substrate

202B back surface

202F front surface

210 interconnect structure

212 dielectric structure

214a connecting layer

214b connecting layer

214c connection layer

216a etch stop layer

216b etch stop layer

300 base

302B back surface

302F front surface

310 interconnect structure

312 dielectric structure

314a connecting layer

314b connecting layer

314c connecting layer

316a etch stop layer

316b etch stop layer

400 interconnect structure

402 dielectric structure

404 interface

410 first via opening

412 second through hole opening

414a first part

414b second part

420 barrier and glue layer

422 conductive material

430 first through-silicon-via conductor

432 second through-silicon via conductor

434a first part

434b second part

M1 first layer

M2 second layer

M3 third layer

Detailed Description

The following description of the present disclosure, which is incorporated in and constitutes a part of this specification, illustrates embodiments of the disclosure, however the disclosure is not limited to these embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the present disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be widely implemented in other embodiments besides the embodiments. The scope of the present disclosure is not limited to the content of the embodiments but is defined by the claims.

Fig. 1 is a flow chart illustrating a method 10 of fabricating a semiconductor structure in some embodiments of the present disclosure. The method 10 includes a step 101 of providing a first substrate having a first front surface, a first back surface opposite the first front surface, and a first interconnect structure disposed over the first front surface. The method 10 further includes providing 102 a second substrate having a second front surface, a second back surface opposite the second front surface, and a second interconnect structure disposed over the second front surface. According to this embodiment, step 101 may be performed before, after, or simultaneously with step 102. The method 10 further includes a step 104 of bonding the first interconnect structure and the second interconnect structure to form a third interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, a plurality of first etch stop layers disposed above the plurality of first connection layers, a plurality of annular second connection layers disposed within the dielectric structure, and a plurality of annular second etch stop layers disposed above the plurality of annular second connection layers. The method 10 further includes performing a first etch to form a first via opening and a second via opening through the first substrate and a portion of the third interconnect structure 106. In some embodiments, at least one of the plurality of first etch stop layers above the first connection layer is exposed through a bottom of the first via opening. In some embodiments, the second via opening includes a first portion and a second portion coupled to each other, and the first etch stop layer over the first connection layer is exposed through a bottom of the second portion of the second via opening. The method 10 further includes performing a second etch to remove a portion of the first etch stop layer and expose the first connection layer through a bottom of the first via opening and a bottom of the second portion of the second via opening, step 108. The method 10 further includes a step 110 of forming a first through-silicon via conductor in the first via opening and forming a second through-silicon via conductor in the second via opening. The method 10 for fabricating the semiconductor structure will be further described in accordance with one or more embodiments.

Fig. 2 and 3 are schematic diagrams illustrating stages in the manufacture of methods for fabricating semiconductor packages according to some embodiments of the present disclosure. Referring to fig. 2, a substrate 200 is provided according to step 101. In some embodiments, the substrate 200 comprises silicon (Si). In other embodiments, the substrate 200 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon (strained dsilicon), silicon germanium (SiGe), silicon carbide (SiC), diamond, epitaxial layer (epitaxiy layer), or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 200 may include a silicon-on-insulator (SOI) substrate, but the present disclosure is not limited thereto. The substrate 200 has a front surface 202F and a back surface 202B opposite to the front surface 202F, as shown in FIG. 2. In some embodiments, a circuit layer (not shown) is formed over the substrate 200 or within the substrate 200 at the front surface 202F. The circuit layer may include circuit patterns or circuit elements such as transistors, capacitors, and or diodes, but the present disclosure is not limited thereto. Thus, the front surface 202F may be referred to as an active surface, although the disclosure is not so limited.

The substrate 200 also includes an interconnect structure 210 disposed over the front surface 202F. Interconnect structure 210 includes a dielectric structure 212 formed from a plurality of dielectric layers with a plurality of interconnect layers formed within the plurality of dielectric layers. The dielectric structure 212 used to isolate the interconnect layer is also referred to as an inter-metal dielectric (IMD) layer. Dielectric structure 212 may include, but is not limited to, for example, silicon oxide (SiO), Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), or boron-phosphosilicate glass (BPSG). The connecting layers in different dielectric layers are generally described as being in different layers, the first through nth layers being referred to as M1 through Mn. For example, the interconnect structure 210 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in fig. 2. However, those skilled in the art should readily appreciate that the number of layers is not limited to 3. Above the substrate 200, which may be a semiconductor chip or a die for 3D chip packaging, Wafer Level Packaging (WLP) or wafer bonding process, is disposed a circuit layer and an interconnect structure 210.

Still referring to fig. 2, in this embodiment, the connection layers in the interconnect structure 210 are formed according to different purposes. For example,

connection layers

214a and 214b are designated as electrically connected to via conductors, and connection layer 214c is designated as an internal connection layer without contacting via conductors. In some embodiments, the

connection layers

214a, 214b, and 214c may be formed by a conventional process, such as, but not limited to, a dual damascene (dual damascene) process. The connection layers 214a and 214b are different from the connection layer 214 c. As shown in fig. 2, the etch stop layer 216a is disposed over a surface of the connection layer 214a facing the substrate 200, and the etch stop layer 216b is disposed over a surface of the connection layer 214b facing the substrate 200. Unlike the connection layers 214a and 214b, the connection layer 214c does not have any etch stop layer on any of its surfaces, as shown in fig. 2. In some embodiments, the

connection layers

214a, and 214c may include a conductive material such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co), but the disclosure is not limited thereto.

Importantly, the connection layers 214a and 214b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 214a serves as a terminal of a vertical electrical connection and is therefore designed to include a planar structure, wherein the surface of the connection layer 214a covered by the etch stop layer 216a also has a planar structure. Thus, a sufficient contact area for a via conductor is provided by the connection layer 214 a. The connection layers 214c are electrically connected to each other and/or to the connection layer 214 a.

Fig. 4A is a partial sectional view of fig. 2 and 3, fig. 4B is a schematic top view (or schematic bottom view) of fig. 4A, and fig. 4C is a view opposite to the view shown in fig. 4B. Referring to fig. 4A-4C, in some embodiments, the connection layer 214b is used as part of a vertical connection. Thus, the connection layer 214b is designed to include a ring configuration, and the etch stop layer 216b covering the surface of the connection layer 214b is also designed to include a ring configuration. Referring to fig. 2 and 4B, in a top view of the annular connection layer 214B and the annular etch stop layer 216B, the dielectric structure 212 can be viewed from a center of the annular connection layer 214B and the annular etch stop layer 216B. Referring to fig. 2 and 4C, in bottom views of the annular connection layer 214b and the annular etch stop layer 216b, the annular etch stop layer 216b completely covers the surface of the connection layer 214b to provide protection.

Notably, the etch stop layer 216a and the annular etch stop layer 216b comprise materials that are different in composition or sufficiently different such that the etch stop layer 216a and the annular etch stop layer 216b may be selectively removed using an appropriate etch chemistry relative to the dielectric structure 112. In some embodiments, the etch stop layer 216a and the annular etch stop layer 216b may comprise the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), although the disclosure is not limited thereto.

Referring to fig. 3, a substrate 300 is provided according to step 102. As described above, step 101 may be performed before, after, or simultaneously with step 102, depending on the embodiment. In some embodiments, the substrate 300 comprises silicon (Si). In other embodiments, the substrate 300 may include gallium (Ga), gallium arsenide (GaAs), gallium nitride (GaN), strained silicon (strained silicon), silicon germanium (SiGe), silicon carbide (SiC), diamond, epitaxial layer (epitaxiy layer), or a combination thereof, but the disclosure is not limited thereto. In other embodiments, the substrate 300 may include a silicon-on-insulator (SOI) substrate, but the present disclosure is not limited thereto. The substrate 300 has a front surface 302F and a back surface 302B opposite the front surface 302F, as shown in FIG. 3. In some embodiments, a circuit layer (not shown) is formed over the substrate 300 or within the substrate 300 at the front surface 302F. The circuit layer may include circuit patterns or circuit elements such as transistors, capacitors, and or diodes, but the present disclosure is not limited thereto. Thus, the front surface 302F may be referred to as an active surface, although the disclosure is not limited thereto.

The substrate 300 also includes an interconnect structure 310 disposed over the front surface 302F. Interconnect structure 310 includes a dielectric structure 312 formed from multiple dielectric layers with multiple interconnect layers formed within the multiple dielectric layers. The dielectric structure 312 used to isolate the connection layer is also referred to as an inter-metal dielectric (IMD) layer. Dielectric structure 312 may include, but is not limited to, for example, silicon oxide (SiO), Tetraethoxysilane (TEOS), phosphosilicate glass (PSG), or boron-phosphosilicate glass (BPSG). The connecting layers in different dielectric layers are generally described as being in different layers, the first through nth layers being referred to as M1 through Mn. For example, the interconnect structure 310 includes three layers, and the first to third layers are referred to as M1 to M3, as shown in fig. 3. However, those skilled in the art should readily appreciate that the number of layers is not limited to 3. Above the substrate 300, there are circuit layers and interconnect structures 310, and the substrate 300 may be a semiconductor chip or a die for 3D chip packaging, Wafer Level Packaging (WLP) or wafer bonding process.

Still referring to fig. 3, in this embodiment, the connection layers in interconnect structure 310 are formed according to different purposes. For example, the connection layers 314a and 314b are designated as electrically connected to via conductors, and the connection layer 314c is designated as an internal connection layer without being in contact with via conductors. In some embodiments, the

connection layers

314a, 314b, and 314c may be formed by conventional processes, such as, but not limited to, dual damascene (dual damascene) processes. The connection layers 314a and 314b are different from the connection layer 314 c. As shown in fig. 3, the etch stop layer 316a is disposed over a surface of the connection layer 314a facing the substrate 300, and the etch stop layer 316b is disposed over a surface of the connection layer 314b facing the substrate 300. Unlike the connection layers 314a and 314b, the connection layer 314c does not have any etch stop layer on any of its surfaces, as shown in fig. 3. In some embodiments, the

connection layers

314a, and 314c may include a conductive material such as tungsten (W), tungsten silicide (WSi), aluminum (Al), titanium (Ti), titanium nitride (TiN), or cobalt (Co), but the disclosure is not limited thereto.

Importantly, the connection layers 314a and 314b are divided into two configurations according to their function in electrical connection. In some embodiments, the connection layer 314a serves as a terminal of a vertical electrical connection and is therefore designed to include a planar structure, wherein the surface of the connection layer 314a covered by the etch stop layer 316a also has a planar structure. Thus, a sufficient contact area for a via conductor is provided by the connection layer 314 a. In addition, the connection layers 314c are electrically connected to each other and/or the connection layers 314 a.

Referring to fig. 4A-4C, in some embodiments, the connection layer 314b is used as part of a vertical connection. Therefore, the connection layer 314b is designed to include a ring configuration, and the etch stop layer 316b covering the surface of the connection layer 314b is also designed to include a ring configuration. Referring to fig. 3 and 4B, in a top view of the annular connection layer 314B and the annular etch stop layer 316B, the dielectric structure 312 can be observed from a center of the annular connection layer 314B and the annular etch stop layer 316B. Referring to fig. 3 and 4C, in a bottom view of the annular connection layer 314b and the annular etch stop layer 316b, the annular etch stop layer 316b completely covers the surface of the connection layer 314b to provide protection.

Notably, the etch stop layer 316a and the annular etch stop layer 316b comprise materials that are different in composition or sufficiently different such that the etch stop layer 316a and the annular etch stop layer 316b may be selectively removed using an appropriate etch chemistry relative to the dielectric structure 312. In some embodiments, the etch stop layer 316a and the annular etch stop layer 316b may comprise the same material, such as silicon nitride (SiN) or silicon oxynitride (SiON), although the disclosure is not limited thereto.

Fig. 5 to 9 are schematic views illustrating various stages of manufacturing methods of a semiconductor package structure according to embodiments of the present disclosure. Referring to fig. 5, next, the substrate 200 and the substrate 300 are bonded. In some embodiments, the substrate 200 is flipped over to be bonded to the substrate 300, as shown in fig. 5. In some embodiments, although not shown, the substrate 300 is flipped over to be bonded to the substrate 300. It should be noted that the substrate 200 and the substrate 300 are joined in a face-to-face manner. By vertically stacking dies having different functions in a face-to-face manner, a face-to-face communication is achieved between the dies having different functions. Further, vertically stacking the die having different functions in a face-to-face manner reduces the footprint of the semiconductor device compared to a semiconductor device having die having different functions arranged in a laterally adjacent manner. Further, the signal paths of the different-function dies vertically stacked in a face-to-face manner are shorter than those of the different-function dies arranged in a laterally adjacent manner; therefore, the different-function dies vertically stacked in a face-to-face manner in the present invention can be applied to high-speed electronic components.

In some embodiments, interconnect structure 210 and interconnect structure 310 are bonded to form interconnect structure 400 disposed between front surface 202F of substrate 200 and front surface 302F of substrate 300, in accordance with step 104. Accordingly, interconnect structure 400 includes a dielectric structure 402 formed from

dielectric structures

212, 312 and connection layers 214 a-214 c and 314 a-314 c. In some embodiments, an interface 404 is formed between interconnect structure 210 and interconnect structure 310. In other words, the interface 404 is formed within the interconnect structure 400.

Referring to fig. 6, a first etch is performed to form a first via opening 410 and a second via opening 412 that penetrate through the substrate 200 and a portion of the interconnect structure 400, in accordance with step 106. In some embodiments, a first etch is performed on the back surface 202B of the substrate 200, as shown in fig. 6. It is noted that the first etch removes portions of the dielectric structure 402 and stops at the

etch stop layers

216a, 316a to form the first via opening 410. Notably, the first etch removes portions of the dielectric structure 402 from the center of the annular etch stop

layers

216b, 316b and the center of the annular connecting

layers

214b, 314b and stops at the

etch stop layers

216a, 316a to form the second via opening 412. Thus, a first via opening 402 and a second via opening 404 having the same depth or different depths are formed, as shown in fig. 6. In some embodiments, by performing this first etch, the substrate 200 and the dielectric structure 402 are exposed through the sidewalls of the first via opening 410 and the

etch stop layers

216a, 316a are exposed through the bottom of the first via opening 410. It should be noted that the depths of the first vias 402 may be the same or different from each other. In some embodiments, a depth of the first via opening is determined by the layer in which the

etch stop layer

216a, 316a is located, as shown in fig. 6.

Still referring to fig. 6, the second via opening 412 includes a first portion 414a and a second portion 414b connected to each other. In some embodiments, by performing the first etch, the substrate 200 and the dielectric structure 402 are exposed through the sidewall of the first portion 414a of the second via opening 412, and the annular etch stop

layers

216b, 316b are exposed through the bottom of the first portion 414a of the second via opening 412. Furthermore, by performing the first etching, the ring-shaped connection layers 214b, 314b and the dielectric structure 402 are exposed through the sidewall of the second portion 414b of the second via opening 412, and the

etch stop layers

216a, 316a are exposed through the bottom of the second portion 414b of the second via opening 412. The width of the second portion 414b of the second via opening 412 is less than the width of the first portion 414a of the second via opening 412. In some embodiments, the width of the second portion 414b is substantially equal to the inner diameter of the annular etch stop

layers

216b, 316b, or substantially equal to the inner diameter of the annular connection layers 214b, 314b, although the disclosure is not limited thereto. Thus, due to the ring-shaped configuration of the ring-shaped etch stop layers 216b, 316b and the ring-shaped connection layers 214b, 314b, the first portion 414a and the second portion 414b are self-aligned (self-aligned) when formed. It should be noted that the depth of the first portion 414a and the depth of the second portion 414b may be the same as or different from each other. In some embodiments, the depth of the first portion 414a is determined by the layer in which the annular

etch stop layer

216b, 316b is located, and the depth of the second portion 414b is determined by the layer in which the

etch stop layer

216a, 316a is located, as shown in fig. 6.

It should be noted that because the etch rate of the etch stop layer is different from the etch rate of the dielectric structure 402, the first and second via

openings

410 and 412 may be formed without damaging the

etch stop layers

216a, 216B, 316a, and 316B.

Referring to fig. 7, a second etch is performed to remove the

etch stop layers

216a and 316a from the bottom of the first and second via

openings

410 and 412, in accordance with step 108. Thus, the

connection layers

214a, 314a are exposed through the bottom of the first via opening 410. In some embodiments, the substrate 200, the dielectric structure 402, and the

etch stop layers

216a, 316a are exposed through the sidewalls of the first via opening 410 by performing a second etch, while the

connection layers

214a, 314a are exposed through the bottom of the first via opening 410 by performing a second etch.

Still referring to fig. 7, by performing the second etch, the substrate 200, the dielectric structure 402, and the annular etch stop

layers

216b, 316b are exposed through the sidewalls of the first portion 414a, and the

connection layers

214a, 314a are now exposed through the bottom of the second portion 414b of the second via opening 412.

It should be noted that because the etch stop layer has a different etch rate than the dielectric structure 402, the

etch stop layers

216a, 216b, 316a, 316b may be removed without damaging the dielectric structure 402, as shown in fig. 7.

Referring to fig. 8 and 9, a first through-silicon via conductor 430 is formed within the first via opening 410 and a second through-silicon via conductor 432 is formed within the second via opening 412, according to step 110. In some embodiments, step 100 further comprises the steps of: for example, a barrier/glue layer 420 is disposed over the sidewalls and bottom of the first and second via

openings

410, 412, as shown in fig. 8. In some embodiments, the barrier/glue layer 420 may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), molybdenum (Mo), manganese (Mn), titanium/copper (Ti/Cu), and/or copper (Cu), although the disclosure is not limited thereto.

Referring to fig. 9, a conductive material 422, such as copper, is next formed to fill the first and second via

conductors

410 and 412. Thus, a first through-silicon via conductor 430 and a second through-silicon via conductor 432 are obtained, as shown in fig. 9.

As shown in fig. 9, a semiconductor package structure 50 is provided. The semiconductor package structure 50 includes: a substrate 200 having a front surface 202F and a back surface 202B opposite the front surface 202F; a substrate 300 having a front surface 302F and a back surface 302B opposite the front surface 302F; an interconnect structure 400 disposed between the front surface 202F of the substrate 200 and the front surface 302F of the substrate 300; a plurality of first through-silicon-via conductors 430 penetrating the substrate 200 and a portion of the interconnect structure 400 from the back surface 202B of the substrate 200; and a plurality of second through-silicon via conductors 432 penetrating the substrate 200 and a portion of the interconnect structure 400 from the back surface 202B of the substrate 200. In some embodiments, at least one of the first through-silicon via conductors 430 passes through the interface 404. In some embodiments, at least one of the second through-silicon via conductors 432 passes through the interface 404.

As shown in fig. 9, the interconnect structure 400 includes a dielectric structure 402, a plurality of

connection layers

214a, 314a disposed within the dielectric structure 402, and a plurality of annular connection layers 214b, 314b disposed within the dielectric structure 402. In some embodiments, at least one of the first through-silicon-via conductors 430 is in contact with one of the

connection layers

214a or 314 a. In some embodiments, at least one of the second through-silicon via conductors 432 is in contact with one of the second connection layers 214b, 314b and the other of the

connection layers

214a or 314a in a ring shape. As described above, the interconnect structure 400 may also include a plurality of connection layers 214c, 314c that are electrically connected to each other and/or to the

connection layers

214a, 314 a. However, the connection layers 214c, 314c are separated from the first through-silicon-via conductor 430, the second through-silicon-via conductor 432, and the ring-shaped connection layers 214b, 314b, as shown in fig. 9.

In some embodiments, the semiconductor package structure 50 further includes an

etch stop layer

216a, 316a disposed over the

connection layer

214a, 314a and an

etch stop layer

216b, 316b disposed over the

annular connection layer

214b, 314 b. In addition, the

etch stop layers

216a, 316a are disposed over a surface of the

connection layers

214a, 314a facing the substrate 200, and the annular etch stop

layers

216b, 316b are disposed over a surface of the annular connection layers 214b, 314b facing the substrate 200. Thus, the surface of the connecting

layer

214a, 314a is separated from the dielectric structure 402 by the

etch stop layer

216a, 316a, and the surface of the annular connecting

layer

214b, 314b is separated from the dielectric structure 402 by the annular

etch stop layer

216b, 316 b.

As shown in fig. 9, a first through-silicon via conductor 430 passes through a portion of the dielectric structure 402 and the

etch stop layers

216a, 316a, and extends to one of the

connection layers

214a or 314 a. In some embodiments, at least one of the plurality of second through-silicon via conductors 432 includes a first portion 434a and a second portion 434b coupled to the first portion 434 a. In some embodiments, a first portion 434a of the second through-silicon via conductor 432 passes through a portion of the dielectric structure 402 and the annular etch stop

layers

216b, 316 b. In some embodiments, a second portion 434b of the second through-silicon-via conductor 432 passes through the annular connection layers 214b, 314b and a portion of the dielectric structure 402 and the

etch stop layers

216a, 316a, and extends to the

other connection layer

214a or 314 a.

Still referring to fig. 9, the first through-silicon via conductor 430 may have a uniform width, the first portion 434a of the second through-silicon via conductor 432 may have a uniform width, and the second portion 434b of the second through-silicon via conductor 432 may have a uniform width. In some embodiments, the first through silicon via conductors 430 may comprise the same width. In other embodiments, the first through-silicon via conductor 430 may comprise a different width, as shown in fig. 9. For example, when the first through-silicon via conductor 430 is electrically connected to a power supply or a ground, the width of such first through-silicon via conductor 430 may be greater than the widths of the other first through-silicon via conductors 430, but the present disclosure is not limited thereto. Similarly, in some embodiments, the second through-silicon via conductors 432 may comprise the same width. In other embodiments, the second through silicon via conductor 432 may comprise a different width. For example, when the second through-silicon via conductor 432 is electrically connected to a power supply or a ground, the width of such second through-silicon via conductor 432 may be greater than the widths of the other second through-silicon via conductors 432, but the present disclosure is not limited thereto. Further, the width of the first portion 434a is greater than the width of the second portion 434 b. In some embodiments, the width of the first portion 434a is less than the outer diameter of the annular etch stop

layers

216b, 316b, or less than the outer diameter of the annular connecting

layers

214b, 314b, although the disclosure is not so limited. However, the width of the first portion 434a is greater than the inner diameter of the annular etch stop

layers

216b, 316b or the inner diameter of the annular connection layers 214b, 314b, but the disclosure is not limited thereto. In some embodiments, the width of the second portion 434b is substantially equal to the inner diameter of the annular

etch stop layer

216b, 316b, or substantially equal to the inner diameter of the

annular connection layer

214b, 314b, although the disclosure is not limited thereto.

The present disclosure provides a method 10 for fabricating a semiconductor package structure. According to the manufacturing method 10, the

connection layers

214a, 214b, 314a, and 314b are designed to provide electrical connection to the first and second through-silicon via

conductors

430 and 432, which are classified into two types:

connection layers

214a and 314a, and annular connection layers 214b and 314 b. The

etch stop layers

216a, 316a are formed above the

connection layers

214a, 314a, and the ring-shaped etch stop layers 216b, 316b are formed above the ring-shaped connection layers 214b, 314 b. Thus, the first etch will stop at the

etch stop layer

216a, 316a, but the first etch will continue to etch the dielectric structure 402 through the annular

etch stop layer

216b, 316b and the annular connecting

layer

214b, 314b, eventually stopping at the

etch stop layer

216a, 316 a. As a result, the first and second via

openings

410 and 412 are formed. The second through-hole opening 412 includes a first portion 414a and a second portion 414b connected to each other. Furthermore, due to the annular configuration of the annular etch stop

layers

216b, 316b and the annular connecting

layers

214b, 314b, the first portion 414a and the second portion 414b are self-aligned when formed. The

etch stop layers

216a, 316a are then removed by performing a second etch to expose the

connection layers

214a, 314 a.

In the present disclosure, the first through-silicon via conductor 430 formed in the first via opening 410 is in contact with the

connection layers

214a, 314a, and the second through-silicon via conductor 432 formed in the second via opening 412 is in contact with the annular connection layers 214b, 314b and the

connection layers

214a, 314 a. It should be noted that because connection layers 214a, 314a and ring-shaped connection layers 214b, 314b are provided, vertical electrical connections between different layers in interconnect structure 400 can be easily formed. Therefore, the electrical connection between the two

substrates

200 and 300 is easily formed. Therefore, additional wiring for placing the conductors at the same height is not required.

The present disclosure provides a semiconductor package structure. The semiconductor package structure includes: the first substrate is provided with a first front surface and a first back surface opposite to the first front surface; a second substrate having a second front surface and a second back surface opposite to the second front surface; an interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate; a plurality of first through-silicon-via conductors penetrate the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; and a plurality of second through-silicon via conductors penetrate the first substrate and a portion of the interconnect structure from the first back surface of the first substrate. The interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of annular second connection layers disposed within the dielectric structure. In some embodiments, at least one of the plurality of first through-silicon-via conductors is in contact with one of the plurality of first connection layers. In some embodiments, at least one of the plurality of second through-silicon-via conductors is in contact with one of the plurality of second connection layers and another of the plurality of first connection layers.

The present disclosure further provides a method for fabricating a semiconductor structure. The preparation method comprises the following steps. A first substrate is provided, the first substrate having a first front surface, a first back surface opposite the first front surface, and a first interconnect structure disposed over the first front surface. A second substrate is provided, the second substrate having a second front surface, a second back surface opposite the second front surface, and a second interconnect structure disposed over the second front surface. The first interconnect structure and the second interconnect structure are bonded to form a third interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate. In some embodiments, the third interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, a plurality of first etch stop layers disposed above the plurality of first connection layers, a plurality of annular second connection layers disposed within the dielectric structure, and a plurality of annular second etch stop layers disposed above the plurality of annular second connection layers. A first etch is performed to form a first via opening and a second via opening through the first substrate and a portion of the third interconnect structure. In some embodiments, the plurality of first etch stop layers over the plurality of first connection layers are exposed through a bottom of the first via opening. The second through-hole opening includes a first portion and a second portion connected to each other. In some embodiments, the first etch stop layer over the first connection layer is exposed through a bottom of the second via opening. A second etch is performed to remove a portion of the first etch stop layer and expose the first connection layer through a bottom of the first via opening and a bottom of the second portion of the second via opening. A first through-silicon-via conductor is formed in the first through-hole opening, and a second through-silicon-via conductor is formed in the second through-hole opening.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are intended to be included within the scope of this application.

Claims

1. A semiconductor package structure, comprising:

a first substrate including a first front surface and a first back surface opposite the first front surface;

a second substrate including a second front surface and a second back surface facing the second front surface;

an interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate, wherein the interconnect structure includes a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, and a plurality of annular second connection layers disposed within the dielectric structure;

a plurality of first through-silicon-via conductors penetrating the first substrate and a portion of the interconnect structure from the first back surface of the first substrate; and

a plurality of second through-silicon-via conductors penetrating the first substrate and a portion of the interconnect structure from the first back surface of the first substrate;

wherein at least one of the plurality of first through-silicon via conductors is in contact with one of the plurality of first connection layers, and at least one of the plurality of second through-silicon via conductors is in contact with one of the plurality of annular second connection layers and another one of the plurality of first connection layers.

2. The semiconductor package structure of claim 1, further comprising: a first etch stop layer disposed over the first connection layer; and a second etch stop layer disposed above the second connection layer.

3. The semiconductor package structure of claim 2, wherein the first etch stop layer is disposed over a surface of the first connection layer facing the first substrate, and the second etch stop layer is disposed over a surface of the second connection layer facing the first substrate.

4. The semiconductor package structure of claim 3, wherein the surface of the first connection layer is separated from the dielectric structure by the first etch stop layer, and the surface of the second connection layer is separated from the dielectric structure by the second etch stop layer.

5. The semiconductor package structure of claim 2, wherein said at least one of said plurality of first through silicon via conductors passes through a portion of the dielectric structure and the first etch stop layer and extends to said one of the first connection layers.

6. The semiconductor package structure of claim 2, wherein the at least one of the plurality of second through silicon via conductors comprises a first portion and a second portion coupled to the first portion.

7. The semiconductor package structure of claim 6, wherein the first portion of the second through-silicon via conductor passes through a portion of the dielectric structure and the second etch stop layer, the second portion of the second through-silicon via conductor passes through the annular second connection layer, a portion of the dielectric structure, and the first etch stop layer and extends to the another of the plurality of first connection layers.

8. The semiconductor package according to claim 6, wherein a width of the first portion is greater than a width of the second portion.

9. The semiconductor package structure of claim 6, wherein the interconnect structure further comprises a plurality of third connection layers electrically connected to the plurality of first connection layers and separated from the plurality of first through-silicon via conductors and the plurality of second through-silicon via conductors.

10. The semiconductor package according to claim 1, wherein an interface is formed within the interconnect structure.

11. The semiconductor package structure of claim 10, wherein at least one of the plurality of first through-silicon-via conductors passes through the interface.

12. The semiconductor package structure of claim 10, wherein at least one of the plurality of second through-silicon via conductors passes through the interface.

13. A preparation method of a semiconductor packaging structure comprises the following steps:

providing a first substrate having a first front surface, a first back surface opposite the first front surface, and a first interconnect structure disposed over the first front surface;

providing a second substrate having a second front surface, a second back surface opposite the second front surface, and a second interconnect structure disposed over the second front surface;

bonding the first interconnect structure and the second interconnect structure to form a third interconnect structure disposed between the first front surface of the first substrate and the second front surface of the second substrate, wherein the third interconnect structure comprises a dielectric structure, a plurality of first connection layers disposed within the dielectric structure, a plurality of first etch stop layers disposed above the plurality of first connection layers, a plurality of annular second connection layers disposed within the dielectric structure, and a plurality of annular second etch stop layers disposed above the plurality of annular second connection layers;

performing a first etch to form a first via opening and a second via opening penetrating through the first substrate and a portion of the third interconnect structure, wherein a plurality of first etch stop layers over the plurality of first connection layers are exposed through a bottom of the first via opening, the second via opening includes a first portion and a second portion coupled to each other, the etch stop layer over the first connection layer is exposed through a bottom of the second portion of the second via opening;

performing a second etch to remove a portion of the first etch stop layer and expose the first connection layer through a bottom of the first via opening and a bottom of the second portion of the second via opening; and

a first through-silicon-via conductor is formed in the first through-hole opening, and a second through-silicon-via conductor is formed in the second through-hole opening.

14. The method of claim 13, wherein the dielectric structure is exposed through a sidewall of the first via opening by performing the first etch, and the first etch stop layer is exposed through the sidewall of the first via opening by performing the second etch.

15. The method of claim 13, wherein the dielectric structure is exposed through a sidewall of the first portion of the second via opening by performing the first etch, and the annular second etch stop layer, the annular second connection layer, and the dielectric structure are exposed through a sidewall of the second portion of the second via opening by performing the first etch.

16. The method of claim 15, wherein the dielectric structure and the annular second etch stop layer are exposed through the sidewall of the first portion of the second via opening by performing the second etch, and the dielectric structure and the first etch stop layer are exposed through the sidewall of the second portion of the second via opening by performing the second etch.

17. The method of claim 13, wherein a width of the second portion of the second via opening is less than a width of the first portion of the second via opening.

18. The method of claim 13, wherein the first etch stop layer is disposed over the first connection layer and over a surface facing the first substrate, and the annular second etch stop layer is disposed over the annular second connection layer and over a surface facing the first substrate.

19. The method of claim 13, wherein the third interconnect structure further comprises a plurality of third connection layers electrically connected to the plurality of first connection layers and separated from the first and second through-silicon via conductors.

20. The method of claim 13, wherein an interface is formed between the first interconnect structure and the second interconnect structure.