JP2003017642A - Tool for processing semiconductor lead - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tool for processing semiconductor lead which can improve long operation life of die and punch by reducing deposition of solder for plating to the processing portion of die and punch from lead of semiconductor package, and eliminating working process to remove the plated solder in order to improve production efficiency. SOLUTION: A die side processing part 16, in which a semiconductor package is placed and a lead L is processed to the predetermined shape with a punch side processing part 17, is provided to a die 11 which may be relatively connected and isolated to and from the punch 12. Moreover, a punch side processing part 17, in which a lead L of semiconductor package P placed in the die side processing part 16 is processed to the predetermined shape with the die side processing part 16, is provided to the punch 12 which may be respectively connected and isolated to and from the die 11. The surfaces of mother materials of these processing parts 16, 17 are formed in the surface roughness of Ry 0.1 S or less and DLC coating is performed on the surface thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor lead processing tool for processing leads protruding from a semiconductor package into a predetermined shape.

[0002]

2. Description of the Related Art For example, in a semiconductor package such as a QFP (quad flat package) or a DIP (dual inline package), a lead is horizontally projected on a side surface of the semiconductor package. It must be bent into a letter shape or an S shape, and inserted into a circuit board or soldered to be processed into a predetermined shape that can be attached. Therefore, a lead processing tool as shown in FIG. 8 is used for processing such a lead.

In FIG. 8, reference numerals 1 and 2 indicate that
A die and a punch, which are attached to a processing machine (not shown) and face each other so as to be relatively detachable from each other, and are a die and a punch as the semiconductor lead processing tool, and a semiconductor package is provided in a portion of the die 1 facing the punch 2 side. The die-side processing portion 3 having a protruding wall shape on which the lead L of P is placed is provided, and the die-side processing portion 3 is provided in a portion of the punch 2 facing the die 1 side.
Punch-side processing part 4 that also has a protruding wall shape at a position corresponding to
Is provided, and by sandwiching and bending the lead L between the die side processing section 3 and the punch side processing section 4, the lead L is processed into a predetermined L-shaped or S-shaped shape. Is configured. It should be noted that the tip end portions of the die-side processed portion 3 and the punch-side processed portion 4 which are in contact with the leads L are concave and convex curved portions 5 and 6 which are butted against each other with a space therebetween.
And the lead L is formed in accordance with the shape of the gap defined between the concave and convex curved portions 5 and 6.
It is processed into a letter shape or an S shape.

By the way, the semiconductor lead processing tools for these dies 1 and punches 2 are conventionally made of harder cemented carbide from the viewpoint of wear resistance. 4 The wear is rapid at the uneven curved portions 5 and 6 at the tip, particularly in contact with the lead L, and the lead L
Since the solder plating of will be welded to these processed parts 3 and 4,
Even when this was removed by polishing, the surface was worn out and the life was shortened. If the solder plating adhered to the processed parts 3 and 4 is not removed, the leads L are short-circuited when the solder plating spontaneously drops off, and it is determined that the product is defective during the final product inspection. . Therefore, recently, a DLC is attached to the tip of the die side processing section 3 and the punch side processing section 4.
It has been proposed that a hard coating such as a (diamond like carbon) coating is provided to further improve its wear resistance and reduce friction with the lead L, thereby preventing the solder plating from welding.

[0005]

However, the thickness of the DLC coating is 1 μm in order to achieve adhesion with the base material.
The surface roughness of the base material affects the surface roughness of the DLC coating as a result of the DLC following the shape of the surface of the base material, which is thin. Therefore, even if the DLC coating is applied, the solder plating is still welded to the processed part of the die or punch, and although the number of times is reduced by the DLC coating, it is still necessary to polish and remove the welded solder plating. It was essential.

The present invention has been made in view of the above circumstances, and is a work process for removing solder plating by reducing welding of solder plating from a lead of a semiconductor package to a processed portion of a die or a punch. It is an object of the present invention to provide a semiconductor lead processing tool capable of improving production efficiency by eliminating the need for a long life of dies and punches.

[0007]

In order to solve the above-mentioned problems and to achieve such an object, the present invention firstly provides a die which can be relatively contacted and separated from a punch. , A die-side processing portion for processing the leads of the semiconductor package on the punch-side processing portion on the punch side into a predetermined shape is provided, and the base material surface of the die-side processing portion has a rough surface. Formed on the surface of the base material with a degree of Ry of 0.1 S or less.
Secondly, the semiconductor package mounted on the die-side processing portion on the die side is mounted on a punch that can be relatively separated from and facing the die. A punch side processing section for processing a lead into a predetermined shape is provided between the lead and the die side processing section, and a base material surface of the punch side processing section is formed to have a surface roughness Ry of 0.1 S or less.
It is characterized in that a DLC coating is applied on the surface of the base material.

That is, in the present invention, the base material surface of the die side processing portion or the punch side processing portion is formed so that the surface roughness defined by JIS B 0610 is Ry 0.1 S or less. The surface roughness of the surface of the DLC coating formed with a thickness of about 1 μm on the surface is reduced. As a result, the unevenness of the surface of the semiconductor package, which is the lead, that comes into contact with the work is reduced, and the welding of solder plating from the leads of the semiconductor package to the processed parts of the die or punch can be reduced. As a result, abrasion due to polishing of the processed parts of the die and punch, peeling of the DLC coating, and the like are eliminated, and the life of the die and punch can be extended. Further, it is possible to improve the production efficiency by omitting the work process for removing the solder plating.

Further, in the semiconductor lead processing tool of the present invention, the base material of the die side processing portion or the punch side processing portion having the DLC coating has an average grain size of 1 μm.
It is characterized in that it is formed from a cemented carbide containing tungsten carbide as a main component and having a thickness of m or less.

With this structure, the surface of the base material of the die-side processed portion or the punch-side processed portion has a surface roughness Ry of 0.1.
It becomes possible to polish so as to be S or less.

The semiconductor lead processing tool of the present invention is characterized in that the coercive force of the cemented carbide is 200 to 400 Oersted.

That is, in the present invention, the binder phase of the cemented carbide has a small diameter of cobalt with a small mean free path, and the average grain size of cobalt has a coercive force of 20.
It is said to be 0 to 400 Oersted. The adhesion strength between cobalt in the binder phase appearing on the surface of the base metal and the DLC coating is weak, but the binder phase starts from cobalt with a small mean free path such that the coercive force of the cemented carbide is 200 to 400 oersted. By being formed, the adhesion with the DLC coating is enhanced, and D
It is possible to prevent peeling of the LC coating.

[0013]

1 to 3 show a die 11 and a punch 12 as an embodiment of the present invention, in which the die 11 is attached to the lower side of a processing machine (not shown) and the upper side thereof. Punch 12 is attached to
The die 11 and the punch 12 are opposed to each other and can be relatively contacted and separated in the vertical direction by the processing machine. Here, these die 11 and punch 12 are the same as those shown in FIG.
As shown in FIG. 4, the semiconductor package P is packaged in the shape of a rectangular flat plate, and is for processing the lead L of the DIP in which the leads L are projected from a pair of side surfaces facing opposite sides. The flat plate-shaped mounting portions 14 and 15 to be mounted are integrally provided with the processing portions 16 and 17 having a "concave" cross section and extending in a protruding wall shape.

Among these, at the tip of the processing portion 16 on the die 11 side, inner wall surfaces 18A, 18A of the pair of convex wall portions 18, 18 having a "concave" cross section of the processing portion 16 on the die side are opposed to each other. The interval between them is set to be slightly larger than the width of the semiconductor package P, and the inner wall surface 1 of these is set.
In the state where the semiconductor package P is located between 8A and 18A, the tip surfaces 18B and 18 facing upward of the projecting wall portions 18 and 18 are formed.
The leads L on both sides of the semiconductor package P can be mounted on the B, respectively. Also, the ridge line portion intersecting with the above-mentioned tip surface 18B of the projecting wall portion 18 and the outer wall surface 18C of each projecting wall portion 18 facing the opposite side between the projecting wall portions 18, 18 has a 1/4 arc shape in cross section. The convex curved portion 18D is formed.

On the other hand, also in the processing portion 17 on the punch 12 side, a pair of projecting wall portions 19 having a "concave" cross section,
The interval between the inner wall surfaces 19A, 19A of the 19 opposite to each other is set to be larger than the width of the semiconductor package P, and in particular, slightly larger than the interval between the inner wall surfaces 18A, 18A of the die-side processed portion 16. , Both projecting walls 19,
The distance between the outer wall surfaces 19B, 19B facing each other at 19 is also made larger than the distance between the outer wall surfaces 18C, 18C of the die side processing portion 16. Furthermore, each projecting wall portion 19
At the intersection ridgeline between the tip surface 19C facing downward and the inner wall surface 19A, a concave curved portion having a 1/4 arc shape in section having a radius of curvature substantially larger than that of the convex curved surface 18D by the thickness of the lead L. 19D is formed.

In the processing portions 16 and 17 of the die 11 and the punch 12, the base material surfaces of the convex curved portion 18D and the concave curved portion 19D have a surface roughness Ry0.sr specified by JIS B 0610. It is formed to have a thickness of 05S or more and 0.1S or less, and a thickness of 1 μm on the surface.
About m of DLC coating is applied. The base material of the die 11 and the punch 12 is made of an ultrafine-grained cemented carbide containing tungsten carbide as a main component and having an average grain size of 1 μm or less. Here, the binder phase of the cemented carbide is formed from a small diameter cobalt having a small mean free path, which occupies 8 to 18% by weight of the whole,
The average particle size is such that the coercive force of the cemented carbide is 200 to 400 Oersted.

In the semiconductor lead processing tool thus constructed, that is, in the die 11 and the punch 12, first, as shown in FIG. 2, the tip surfaces 18B of the projecting wall portions 18, 18 of the processing portion 16 of the die 11 are The lead L is placed on 18B, and the semiconductor package P is placed on the processed portion 16. Next, by making the die 11 and the punch 12 relatively close to each other, as shown in FIG. 3, the lead L is sandwiched and bent between the die side processing portion 16 and the punch side processing portion 17. , L-shaped so as to extend downward. That is, more specifically, the portion of the lead L located on the convex curved portion 18D is sandwiched between the convex curved portion 18D and the concave curved portion 19D of the punch 12 to form a quarter arc shape. As described above, the lead L is bent downward by 90 °, so that the lead L is processed into an L-shape with its tip end facing downward.

However, according to the die 11 and the punch 12 having the above-described structures, the surface of the base material of the processed portions 16 and 17 for bending and processing the lead L in this manner has a surface roughness of Ry 0.05 S or more. Since the surface roughness of the DLC coating formed on the surface of the base material is reduced, the surface roughness of the DLC coating formed on the surface of the base material is reduced. Becomes smaller, and the processing part 1 from the lead L to the die 11 and the punch 12
It is possible to reduce the welding of the solder plating to 6,17. As a result, the abrasion due to the polishing of the processed portions 16 and 17 and the peeling of the DLC coating are eliminated, and the life of the die 11 and the punch 12 can be extended. Further, it is possible to improve the production efficiency by omitting the work process for removing the solder plating.

For example, in FIG. 7, the surface roughness Ry of the base material surfaces of the processed portions 16 and 17 and the welded solder plating are processed portion 1.
The relationship with the number of cleanings to be removed from Nos. 6 and 17 is shown below. By setting the surface roughness to Ry 0.1 S or less,
The result was that the work of removing the solder plating was unnecessary for two years.

Above all, the base material of the processed portions 16 and 17 of the die 11 and the punch 12 is an ultrafine grained cemented carbide containing tungsten carbide as a main component and having an average grain size of 1 μm or less as described above. Formed from an alloy,
The surfaces of the base materials of the processed parts 16 and 17 can be polished into a mirror surface, and the surface roughness Ry of 0.05 S or more and 0.1 S or less can be realized. Further, although the adhesion strength between the cobalt in the binder phase appearing on the surface of the base material and the DLC coating is weak, the cemented carbide is bonded from a cobalt having a small mean free path such that the coercive force is 200 to 400 oersted. Since the phase is formed, the adhesion with the DLC coating is enhanced, and peeling of the DLC coating can be prevented.

Next, FIGS. 4 to 6 show a die 24 and a punch 25 as another embodiment of the present invention, and the parts common to the embodiment shown in FIGS. 1 to 3 are shown. Are assigned the same reference numerals and description thereof will be omitted. That is, the die 24 and the punch 25 as the semiconductor lead processing tool of the present embodiment are for the QFP in which the leads L project from the four side surfaces of the rectangular flat plate-shaped semiconductor package P,
Four protrusion walls 18 ..., 19 ... Are provided in a square shape in a plan view on each of the mounting portions 14 and 15 mounted on the processing machine side, and the die side processing portion 26 and the punch side processing portion 2 are provided.
It is said to be 7.

In such a QFP semiconductor package P, the tip of the lead L is positioned and placed on the terminal of the circuit board, and then the tip of the lead L and the terminal are soldered. Often implemented by
Therefore, the lead L is once bent downward in an L-shape as in the case of the DIP and then the lower end thereof is outwardly L-shaped.
It will be bent into a letter shape, and will be processed into an approximately S shape. Therefore, in accordance with this, in the present embodiment, the tip end surface 18B of the projecting wall portion 18 of the die side processing portion 26 is further retracted by one step from the inner wall surface 18A side portion 18a of the outer wall surface 18C side portion 18c. The inner wall surface 18A side portion 18a and the outer wall surface 18C side portion 18c side wall portion 18b toward the portion 18c side, the convex curved portion 18D, Recessed curved portions 18F are formed at the ridges intersecting with the wall surface portion 18b and the outer wall portion 18C side portion 18c.

On the other hand, the protruding wall portion 1 of the punch side processing portion 27
On the other hand, the inner wall surface 1 of the tip surface 19C of
The portion 19a on the 9A side is formed so as to recede one step further than the portion 19c on the outer wall surface 19B side.
The wall surface portion 19b between 19c and the inner wall surface 19A side portion 1
A concave curved portion 19D is formed at a ridge line intersecting with 9a, and a convex curved portion 19F is formed at a ridge line intersecting with the wall surface portion 19b and a portion 19c on the outer wall surface 19B side.
Therefore, in this embodiment, these portions 18a-18
c, 19a to 19c and the concave and convex curved portions 18F and 19
The base material surface of the tip portion of the projecting wall portions 18 and 19 on which D, 18D, and 19F are formed is formed so that the surface roughness defined by JIS B 0610 is Ry 0.05 S or more and 0.1 S or less. Further, a DLC coating having a thickness of about 1 μm is applied on the surface thereof. The base material of the die 24 and the punch 25 is formed of an ultrafine-grained cemented carbide containing tungsten carbide as a main component and having an average grain size of 1 μm or less. Here, the binder phase of this cemented carbide is formed from small-diameter cobalt having a small mean free path, which occupies 8 to 18% by weight of the whole, and its average particle size is 200- It is supposed to be 400 Oersted.

Therefore, in the semiconductor lead processing tool according to the present embodiment having such a configuration, that is, in the die 24 and the punch 25, first, as shown in FIG. 5, the protruding wall portion 18 of the processing portion 26 of the die 24 is formed. Tip surface 18B
The lead L is mounted on the portion 18a on the inner wall surface 18A side of the semiconductor package P and the semiconductor package P is mounted on the processed portion 26. Next, by making the die 24 and the punch 25 relatively close to each other, as shown in FIG.
The lead L is sandwiched and bent between 6 and the punch side processing portion 27, and processed into a substantially S shape. That is, more specifically, the portion of the lead L located on the convex curved portion 18D is sandwiched between the convex curved portion 18D and the concave curved portion 19D of the punch 25 and corresponds to the concave curved portion 18F. The lead L is processed into an S-shape with its tip facing downward by sandwiching the portion to be bent between the concave curved portion 18F and the convex curved portion 19F of the punch 25.

However, first, according to the die 24 and the punch 25 having the above-described structure, the surface of the base material of the processing portions 26 and 27 for bending and processing the lead L in this manner has a surface roughness of Ry 0.05 S or more. Since the surface roughness of the DLC coating formed on the surface of the base material is reduced, the surface roughness of the DLC coating formed on the surface of the base material is reduced. Becomes smaller, and the processing section 2 from the lead L to the die 24 and the punch 25
It is possible to reduce the welding of the solder plating to 6, 27. As a result, abrasion due to polishing of the processed portions 26 and 27, peeling of the DLC coating, and the like are eliminated, and the life of the die 24 and the punch 25 can be extended. Further, it is possible to improve the production efficiency by omitting the work process for removing the solder plating. Also in the present embodiment, the reduction of the work steps for removing the plating by improving the surface roughness of the base material surfaces of the processed portions 26 and 27 is as shown in FIG. 7.

The base materials of the processing portions 26 and 27 of the die 24 and the punch 25 have an average grain size of 1 as described above.
Since it is formed from an ultrafine-grained cemented carbide containing tungsten carbide as a main component, the processed portion 26,
The base material surface of No. 27 can be mirror-polished, and the surface roughness Ry of 0.05 S or more and 0.1 S or less can be realized. Further, although the adhesion strength between the cobalt in the binder phase appearing on the surface of the base material and the DLC coating is weak, the cemented carbide is bonded from a cobalt having a small mean free path such that the coercive force is 200 to 400 oersted. Since the phase is formed, the adhesion with the DLC coating is enhanced, and peeling of the DLC coating can be prevented.

In the above-described embodiment, the solder plating adhesion can be sufficiently reduced in practical use, and the surface roughness Ry is 0.05 S or more to 0.1 or less so that the polishing work is not troublesome.
However, if the surface of the base material is further polished, the surface roughness is improved to Ry0.03S, and the surface roughness Ry0.03S is obtained.
It is also possible to set the value to 0.1 S or less. This allows
It is possible to further reduce the welding of the solder plating from the leads of the semiconductor package to the processed portion of the die or punch.

[0028]

As described above, according to the present invention,
The base material surface of the die side processing part and the punch side processing part is formed to have a surface roughness Ry of 0.1 S or less, and DLC is formed on the base material surface.
Since it is configured to be coated, it reduces welding of solder plating from the leads of the semiconductor package to the processed parts of the die and punch, and improves the production efficiency by eliminating the work process for removing the solder plating. As a result, the life of the die and punch can be extended. In particular, the base material of the die-side processing part and the punch-side processing part has an average grain size of 1 μm.
Since it is formed of the following cemented carbide containing tungsten carbide as a main component, the surface of the base material has a surface roughness Ry of 0.1.
It becomes possible to easily polish it to be S or less.
Further, according to the present invention, the coercive force of the cemented carbide is 200 to 4
Since it is set to 00 Oersted, the binder phase is formed from cobalt having a small mean free path, the adhesion with the DLC coating is enhanced, and peeling of the DLC coating can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

2 is a cross-sectional view before processing according to the embodiment shown in FIG.

FIG. 3 is a cross-sectional view during processing according to the embodiment shown in FIG.

FIG. 4 is a diagram showing another embodiment of the present invention.

5 is a cross-sectional view before processing according to the embodiment shown in FIG.

6 is a cross-sectional view at the time of processing according to the embodiment shown in FIG.

FIG. 7 is a diagram showing the relationship between the surface roughness of the base material surface of the processed portion and the number of cleanings for removing the deposited solder plating from the processed portion.

FIG. 8 is a view showing a conventional semiconductor lead processing tool.

[Explanation of symbols]

11, 24 ... Die (tool for semiconductor lead processing) 12, 25 ... Punch (semiconductor lead processing tool) 16, 26 ... Die side processing part 17, 27 ... Punch side processing part 18D, 19F ... Convex curve 18F, 19D ... Recessed curved part P: Semiconductor package L ... Lead

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ken Takahashi             1528, Nakashinden, Yokoi, Kobe-cho, Anpachi-gun, Gifu Prefecture             Address Ryotec Co., Ltd. wear-resistant tool factory             Within F term (reference) 5F067 DB01

Claims (4)

[Claims] 1. A semiconductor package is mounted on a die which can face and separate from a punch, and the leads of the semiconductor package are processed into a predetermined shape between the lead and the punch-side processing portion on the punch side. A semiconductor lead characterized in that a die side processed portion is provided, a base material surface of the die side processed portion is formed to have a surface roughness Ry of 0.1 S or less, and a DLC coating is applied on the base material surface. Processing tool. 2. The punch of the semiconductor package, which is mounted on the die side processing portion on the die side, is fixed to a punch which can face the die and can be relatively separated from the die side processing portion. The punch side processing portion for processing into the shape of is formed, and the base material surface of the punch side processing portion has a surface roughness Ry0.1S.
A semiconductor lead processing tool, which is formed as described below and has a DLC coating on the surface of the base material. 3. The semiconductor lead processing tool according to claim 1 or 2, wherein the DLC-coated base material of the die-side processing portion or the punch-side processing portion has an average grain size of 1 μm or less. A tool for semiconductor lead processing, which is formed from a cemented carbide containing tungsten carbide as a main component. 4. The semiconductor lead processing tool according to claim 3, wherein the cemented carbide has a coercive force of 200 to 400 oersteds.