JP2003017638A - Stacked multi-chip semiconductor device - Google Patents

Stacked multi-chip semiconductor device

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Publication number
JP2003017638A
JP2003017638A JP2001201072A JP2001201072A JP2003017638A JP 2003017638 A JP2003017638 A JP 2003017638A JP 2001201072 A JP2001201072 A JP 2001201072A JP 2001201072 A JP2001201072 A JP 2001201072A JP 2003017638 A JP2003017638 A JP 2003017638A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor
semiconductor device
heat
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001201072A
Other languages
Japanese (ja)
Other versions
JP4817543B2 (en
Inventor
Fumihiko Taniguchi
文彦 谷口
Akira Takashima
晃 高島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2001201072A priority Critical patent/JP4817543B2/en
Publication of JP2003017638A publication Critical patent/JP2003017638A/en
Application granted granted Critical
Publication of JP4817543B2 publication Critical patent/JP4817543B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/01005—Boron [B]
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a stacked multi-chip semiconductor device in which transfer of heat generated from each semiconductor element can be controlled in stacking a plurality of semiconductor elements. SOLUTION: A Peltier element 8 is disposed between a plurality of semiconductor elements 2A and 2B which are stacked and mounted on an interposer element 1, in order to promote the transfer (transmission) of heat from the element 2B on the upper part of the element 8 to the element 2A on the lower part of the element 8. Also, another Peltier element 8 is disposed between the lower element 2A and the interposer 1 to promote the transfer (transmission) of the heat from the upper element 2B to the lower element 2A. Thus, all the semiconductor elements can be efficiently cooled.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に係り、
特に複数の半導体素子が積層されて搭載された積層型マ
ルチチップ半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a stacked multi-chip semiconductor device in which a plurality of semiconductor elements are stacked and mounted.

【０００２】[0002]

【従来の技術】電子機器の小型化に伴い、半導体装置の
小型化への要求も高まっている。このような半導体装置
への小型化への要求にこたえるべく、半導体装置の構造
は、従来のリードフレーム構造から、外部端子としてハ
ンダボールのように突起電極を備えるＣＳＰ（チップサ
イズパッケージ）構造へと移行してきている。2. Description of the Related Art With the miniaturization of electronic equipment, there is an increasing demand for miniaturization of semiconductor devices. In order to meet the demand for miniaturization of such a semiconductor device, the structure of the semiconductor device is changed from a conventional lead frame structure to a CSP (chip size package) structure having a protruding electrode like a solder ball as an external terminal. It is migrating.

【０００３】近年では、ＲＣＳＰ（リアルチップサイズ
パッケージ）が開発され、これにより半導体装置の２次
元的な小型化は限界となっている。そこで、半導体装置
の更なる高密度化のために、複数個の半導体素子を積層
したスタック型のＭＣＰ（マルチチップパッケージ）が
開発されている。スタック型のＭＣＰの例を図１に示
す。In recent years, RCSP (Real Chip Size Package) has been developed, which limits the two-dimensional miniaturization of semiconductor devices. Therefore, in order to further increase the density of the semiconductor device, a stack type MCP (multi-chip package) in which a plurality of semiconductor elements are stacked has been developed. An example of a stack type MCP is shown in FIG.

【０００４】図１(ａ）に示すスタック型のＭＣＰは、
インターポーザ（再配線基板）１の上に半導体素子２Ａ
を搭載し、その上に半導体素子２Ｂを積層して搭載した
半導体装置である。半導体素子２Ａはダイス付け材３に
よりインターポーザ１上に固定される。同様に、半導体
素子２Ｂもダイス付け材３により半導体措置２Ａ上に固
定される。半導体素子２Ｂの端子は半導体素子２Ａの端
子にボンディングワイヤ５Ａにより接続される。また、
半導体素子２Ａの端子はインターポーザ１の端子にボン
ディングワイヤ５Ｂにより接続される。半導体素子２Ａ
及び２Ｂは、インターポーザ１上でモールドレジン７に
より封止される。インターポーザ１の底面には、外部接
続用端子としてハンダボール６が形成される。The stack type MCP shown in FIG.
The semiconductor element 2A is formed on the interposer (rewiring board) 1.
Is a semiconductor device in which the semiconductor element 2B is mounted and the semiconductor element 2B is stacked thereon. The semiconductor element 2A is fixed on the interposer 1 by the dicing material 3. Similarly, the semiconductor element 2B is also fixed on the semiconductor device 2A by the dicing material 3. The terminal of the semiconductor element 2B is connected to the terminal of the semiconductor element 2A by the bonding wire 5A. Also,
The terminals of the semiconductor element 2A are connected to the terminals of the interposer 1 by the bonding wires 5B. Semiconductor element 2A
And 2B are sealed by the mold resin 7 on the interposer 1. Solder balls 6 are formed on the bottom surface of the interposer 1 as external connection terminals.

【０００５】図１（ｂ）に示すスタック型のＭＣＰは、
半導体素子２Ａにバンプ４Ａを設け、フリップチップ実
装によりインターポーザ１に搭載したものである。した
がって、上側の半導体素子２Ｂの端子はボンディングワ
イヤ５Ｂにより直接インターポーザ１の端子に接続され
る。The stack type MCP shown in FIG.
The bumps 4A are provided on the semiconductor element 2A and are mounted on the interposer 1 by flip-chip mounting. Therefore, the terminal of the upper semiconductor element 2B is directly connected to the terminal of the interposer 1 by the bonding wire 5B.

【０００６】図１（ｃ）に示すスタック型のＭＣＰは、
半導体素子２Ｂにバンプ４Ｂを設け、フリップチップ実
装により半導体素子２Ａに搭載したものである。したが
って、下側の半導体素子２Ａのみがボンディングワイヤ
５Ａによりインターポーザ１の端子に接続される。The stack type MCP shown in FIG.
The bumps 4B are provided on the semiconductor element 2B and mounted on the semiconductor element 2A by flip-chip mounting. Therefore, only the lower semiconductor element 2A is connected to the terminal of the interposer 1 by the bonding wire 5A.

【０００７】ここで、図１（ａ）及び（ｂ）に示す半導
体装置では、半導体装置２Ａ，２Ｂをダイス付け材３に
より接合しているが、ダイス付け材３の厚みは非常に薄
いため、接合された半導体装置２Ａ，２Ｂは、発熱量が
異なっていてもほぼ同じ温度となる。また、図１（ｃ）
に示す半導体装置でも、半導体装置２Ａ，２Ｂがバンプ
により接続されているため、半導体装置２Ａ，２Ｂの温
度はほぼ同じ温度となる。Here, in the semiconductor device shown in FIGS. 1A and 1B, the semiconductor devices 2A and 2B are joined by the dicing material 3, but the thickness of the dicing material 3 is very thin. The joined semiconductor devices 2A and 2B have substantially the same temperature even if the calorific values are different. Also, FIG. 1 (c)
Also in the semiconductor device shown in (1), since the semiconductor devices 2A and 2B are connected by the bumps, the temperatures of the semiconductor devices 2A and 2B are almost the same.

【０００８】[0008]

【発明が解決しようとする課題】図１に示すような従来
のスタック型のＭＣＰは、比較的消費電力の小さいメモ
リ系の半導体素子同士の組み合わせで主に使用されてい
た。このため、半導体素子の発熱による問題はあまり生
じておらず、半導体素子の放熱に関してはほとんど対策
が施されていなかった。The conventional stack type MCP as shown in FIG. 1 is mainly used in a combination of semiconductor elements of a memory system having relatively low power consumption. Therefore, the problem due to heat generation of the semiconductor element has not occurred so much, and almost no countermeasure has been taken for heat dissipation of the semiconductor element.

【０００９】しかし、近年において、スタック型のＭＣ
Ｐには、メモリ同士の組み合わせばかりでなく、ロジッ
ク＋メモリ、アナログ＋デジタル、あるいは低消費電力
素子＋高消費電力素子といった組み合わせのように、シ
ステムあるいはサブシステムとしての機能が要求されて
いる。このような機能を有するスタック型のＭＣＰで
は、ジャンクション温度（Ｔｊ）の異なる半導体素子を
積層して搭載する必要がある。However, in recent years, stack type MC
The P is required to have a function as a system or a subsystem, such as not only a combination of memories but also a combination of logic + memory, analog + digital, or low power consumption element + high power consumption element. In the stack type MCP having such a function, it is necessary to stack and mount semiconductor elements having different junction temperatures (Tj).

【００１０】上述のように、従来の構成のスタック型の
ＭＣＰでは、積層された半導体素子は、全てほぼ等しい
温度となってしまう。このため、ジャンクション温度が
異なる半導体素子を積層した場合、ジャンクション温度
の低い方の半導体素子に合わせた熱抵抗を有するパッケ
ージとする必要がある。あるいは、発熱に対するマージ
ンが少ない方の半導体素子に対して熱がなるべく伝達さ
れないような構成とする必要がある。As described above, in the stack type MCP having the conventional structure, the temperature of the stacked semiconductor elements is almost the same. Therefore, when semiconductor elements having different junction temperatures are stacked, it is necessary to make a package having a thermal resistance matched to the semiconductor element having the lower junction temperature. Alternatively, it is necessary to have a configuration in which heat is not transmitted to the semiconductor element having the smaller margin for heat generation as much as possible.

【００１１】本発明は上記の点に鑑みてなされたもので
あり、複数の半導体素子を積層した際に各半導体素子か
ら発生する熱の移動を制御することのできる積層型マル
チチップ半導体装置を提供することを目的とする。The present invention has been made in view of the above points, and provides a stacked multi-chip semiconductor device capable of controlling the movement of heat generated from each semiconductor element when a plurality of semiconductor elements are stacked. The purpose is to do.

【００１２】[0012]

【課題を解決するための手段】上記の課題を解決するた
めに本発明では、次に述べる各手段を講じたことを特徴
とするものである。In order to solve the above problems, the present invention is characterized by taking the following means.

【００１３】請求項１記載の発明は、配線基板上に積層
して搭載された複数の半導体素子を有する積層型マルチ
チップ半導体装置であって、前記複数の半導体素子に対
して積層した状態で電子冷却素子を配置したことを特徴
とするものである。According to a first aspect of the present invention, there is provided a laminated multi-chip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, wherein the plurality of semiconductor elements are stacked in an electronic state. It is characterized in that a cooling element is arranged.

【００１４】請求項１記載の発明によれば、積層した半
導体素子の間又は最下段の半導体素子の下に電子冷却装
置を配置することができる。電子冷却素子を半導体素子
の中間に配置した場合は、電子冷却素子の上側の半導体
素子から下側の半導体素子への熱の移動（伝達）を促進
することができ、上側と下側の半導体素子の間に積極的
に温度差を設けることができる。これにより、電子冷却
素子の上側の半導体素子のジャンクション温度が、電子
冷却素子の下側の半導体素子のジャンクション温度より
低い場合であっても、積層可能となる。また、電子冷却
素子を最下段の半導体素子の下に配置した場合は、上側
の半導体素子から下側の半導体素子への熱の移動（伝
達）が促進され、全ての半導体素子を効率よく冷却する
ことができる。According to the first aspect of the invention, the electronic cooling device can be arranged between the stacked semiconductor elements or below the lowest semiconductor element. When the electronic cooling element is arranged in the middle of the semiconductor elements, it is possible to promote the transfer (transfer) of heat from the semiconductor element on the upper side of the electronic cooling element to the semiconductor element on the lower side. A temperature difference can be positively provided between the two. Accordingly, even if the junction temperature of the semiconductor element above the electronic cooling element is lower than the junction temperature of the semiconductor element below the electronic cooling element, stacking is possible. Further, when the electronic cooling element is arranged below the lowermost semiconductor element, heat transfer (transfer) from the upper semiconductor element to the lower semiconductor element is promoted, and all the semiconductor elements are efficiently cooled. be able to.

【００１５】請求項２記載の発明は、複数の半導体素子
を積層した搭載した積層型マルチチップ半導体装置であ
って、前記複数の半導体素子のうち最もジャンクション
温度が低い半導体素子に対して電子冷却素子を積層して
配置したことを特徴とするものである。According to a second aspect of the present invention, there is provided a stacked multi-chip semiconductor device in which a plurality of semiconductor elements are stacked and mounted, wherein the electronic cooling element is the semiconductor element having the lowest junction temperature among the plurality of semiconductor elements. It is characterized in that they are arranged in layers.

【００１６】請求項２記載の発明によれば、ジャンクシ
ョン温度の低い半導体素子、すなわち発熱に対するマー
ジンが少ない半導体素子の熱を集中的に吸収して冷却
し、吸収した熱をジャンクション温度の高い半導体装置
へと移動（伝達）することができる。したがって、半導
体装置全体を、ジャンクション温度の高い半導体素子に
合わせた熱抵抗に基づいて設計することができる。According to the second aspect of the present invention, the semiconductor device having a low junction temperature, that is, the semiconductor device having a small margin for heat generation is intensively absorbed and cooled, and the absorbed heat is a semiconductor device having a high junction temperature. Can be moved (transmitted) to. Therefore, the entire semiconductor device can be designed based on the thermal resistance matched to the semiconductor element having a high junction temperature.

【００１７】請求項３記載の発明は、請求項１又は２記
載の積層型マルチチップ半導体装置であって、前記電子
冷却素子はペルチェ素子であることを特徴とするもので
ある。According to a third aspect of the present invention, there is provided the laminated multichip semiconductor device according to the first or second aspect, wherein the electronic cooling element is a Peltier element.

【００１８】請求項３記載の発明によれば、半導体素子
を同様な構成及び材料にて電子冷却素子を作ることがで
き、電子冷却素子を容易に積層することができる。According to the third aspect of the invention, the semiconductor element can be made into an electronic cooling element with the same structure and material, and the electronic cooling elements can be easily laminated.

【００１９】請求項４記載の発明は、請求項１記載の積
層型マルチチップ半導体装置であって、前記電子冷却素
子はペルチェ素子であり、該ペルチェ素子の低温側を最
上段の半導体素子に接合し、前記ペルチェ素子の高温側
を放熱板に接合したことを特徴とするものである。According to a fourth aspect of the present invention, in the stacked multi-chip semiconductor device according to the first aspect, the electronic cooling element is a Peltier element, and the low temperature side of the Peltier element is bonded to the uppermost semiconductor element. The high temperature side of the Peltier element is joined to the heat dissipation plate.

【００２０】請求項４記載の発明によれば、最上段の半
導体素子からも積極的に放熱することができ、半導体装
置の温度を効率的に低減することができる。According to the fourth aspect of the invention, the heat can be positively radiated from the uppermost semiconductor element, and the temperature of the semiconductor device can be efficiently reduced.

【００２１】請求項５記載の発明は、配線基板上に積層
して搭載された複数の半導体素子を有する積層型マルチ
チップ半導体装置であって、前記複数の半導体素子の間
に積層した状態で熱絶縁体を配置し、該熱絶縁体を挟む
半導体装置の間に温度差を設けたことを特徴とするもの
である。According to a fifth aspect of the present invention, there is provided a laminated multi-chip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, wherein the plurality of semiconductor elements are heat-sealed in a laminated state. It is characterized in that an insulator is arranged and a temperature difference is provided between the semiconductor devices sandwiching the heat insulator.

【００２２】請求項５記載の発明によれば、熱絶縁体を
半導体素子の間に配置することにより、熱絶縁体の上側
の半導体素子と下側の半導体素子との間に積極的に温度
差を設けることができる。また、熱絶縁体の下側の半導
体素子の熱が熱絶縁体の上側の半導体素子に移動（伝
達）することが防止され、上側の半導体素子の温度上昇
を抑制することができる。According to the fifth aspect of the present invention, by disposing the thermal insulator between the semiconductor elements, the temperature difference between the semiconductor element above the thermal insulator and the semiconductor element below the thermal insulator is positively influenced. Can be provided. Further, the heat of the semiconductor element on the lower side of the heat insulator is prevented from being transferred (transmitted) to the semiconductor element on the upper side of the heat insulator, and the temperature rise of the semiconductor element on the upper side can be suppressed.

【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

【００２３】図２は本発明の第１の実施の形態による積
層型マルチチップ半導体装置の断面図である。図２にお
いて、図１に示す構成部品と同等な部品には同じ符号を
付し、その説明は適宜省略する。FIG. 2 is a sectional view of a stacked multi-chip semiconductor device according to the first embodiment of the present invention. 2, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

【００２４】図２に示す半導体装置は、下側の半導体素
子２Ａと上側の半導体素子２Ｂとの間に電子冷却素子と
してのペルチェ素子８が設けられている。ペルチェ素子
８は放熱面８ａと反対側の吸熱面８ｂとを有しており、
放熱面８ａ側にバンプ８ｃが形成される。バンプ８ｃは
ペルチェ素子８に電流を供給するための端子であり、２
個設けられていればよいが、本実施の形態ではペルチェ
素子８から半導体素子２Ａへの熱の伝達を促進するため
に多数のバンプ８ｃが設けられている。In the semiconductor device shown in FIG. 2, a Peltier element 8 as an electronic cooling element is provided between the lower semiconductor element 2A and the upper semiconductor element 2B. The Peltier element 8 has a heat radiation surface 8a and a heat absorption surface 8b on the opposite side,
Bumps 8c are formed on the heat dissipation surface 8a side. The bump 8c is a terminal for supplying a current to the Peltier element 8 and
In this embodiment, a large number of bumps 8c are provided in order to promote the transfer of heat from the Peltier device 8 to the semiconductor device 2A.

【００２５】上側の半導体素子２Ｂは、ペルチェ素子８
の吸熱面８Ｂに対してダイス付け材３により固定され
る。そして、半導体素子２Ｂの端子はボンディングワイ
ヤ５Ｂにより半導体素子２Ａの端子に接続され、半導体
素子２Ａの端子はボンディングワイヤ５Ａによりインタ
ーポーザ１の端子に接続される。The upper semiconductor element 2B is a Peltier element 8
It is fixed to the heat absorbing surface 8B by the die attaching material 3. The terminal of the semiconductor element 2B is connected to the terminal of the semiconductor element 2A by the bonding wire 5B, and the terminal of the semiconductor element 2A is connected to the terminal of the interposer 1 by the bonding wire 5A.

【００２６】以上のような構成の半導体装置において、
ペルチェ素子８に電流を流すと、吸熱面８ｂで吸収した
熱が放熱面８ａから放出される。したがって、上側の半
導体素子２Ｂの熱がペルチェ素子８により吸収され、下
側の半導体素子２Ａに対して放出される。すなわち、上
側の半導体素子２Ａで発生した熱は、ペルチェ素子８に
より下側の半導体素子２Ａに移動される。下側の半導体
素子２Ａに移動した熱は、従来と同様にインターポーザ
１及びハンダボール６を介して半導体装置の外部へと放
出される。In the semiconductor device having the above structure,
When a current is passed through the Peltier element 8, the heat absorbed by the heat absorbing surface 8b is released from the heat radiating surface 8a. Therefore, the heat of the upper semiconductor element 2B is absorbed by the Peltier element 8 and is radiated to the lower semiconductor element 2A. That is, the heat generated in the upper semiconductor element 2A is transferred to the lower semiconductor element 2A by the Peltier element 8. The heat transferred to the lower semiconductor element 2A is released to the outside of the semiconductor device via the interposer 1 and the solder balls 6 as in the conventional case.

【００２７】ここで、ペルチェ素子８の構成について図
３を参照しながら説明する。図３はペルチェ素子８の構
成を示す図である。ペルチェ素子８は、直列に接続され
た複数のＮ型半導体とＰ型半導体で構成される。図３に
示すように電流Ｉを流すと、両面８ａと８ｂとの間に温
度差ΔＴが発生する。ペルチェ素子８の電極側が放熱面
８ａとなり、反対側の面が吸熱面８ｂとなる。すなわ
ち、吸熱面８ｂでは熱を吸収し、吸収した熱を放熱面８
ｂから放出する。したがって、ペルチェ素子は、吸熱面
側から放熱面側へと熱を移動させる機能を有し、これに
より、吸熱面８ｂ側を冷却することができる。The structure of the Peltier device 8 will be described with reference to FIG. FIG. 3 is a diagram showing the configuration of the Peltier device 8. The Peltier device 8 is composed of a plurality of N-type semiconductors and P-type semiconductors connected in series. When a current I is passed as shown in FIG. 3, a temperature difference ΔT is generated between the both surfaces 8a and 8b. The electrode side of the Peltier element 8 serves as the heat radiation surface 8a, and the opposite surface serves as the heat absorption surface 8b. That is, the heat absorbing surface 8b absorbs heat and the absorbed heat is absorbed by the heat radiating surface 8b.
Release from b. Therefore, the Peltier element has a function of transferring heat from the heat absorbing surface side to the heat radiating surface side, whereby the heat absorbing surface 8b side can be cooled.

【００２８】以上のようなペルチェ素子８により、上側
の半導体素子２Ａが発生した熱は、下側の半導体素子２
Ａに移動（伝達）されるため、上側の半導体素子２Ｂに
対して冷却効果が提供される。すなわち、上側の半導体
素子２Ｂより下側の半導体素子２Ａの方が発熱量が大き
い場合であっても、ペルチェ素子８の作用により下側の
半導体素子２Ａから上側の半導体素子２Ｂへと熱が伝わ
ることが防止される。これにより、上側の半導体素子２
Ｂの温度を下側の半導体素子２Ａの温度より低く維持す
ることができる。The heat generated by the upper semiconductor element 2A by the Peltier element 8 as described above is transferred to the lower semiconductor element 2A.
Since it is moved (transmitted) to A, a cooling effect is provided to the upper semiconductor element 2B. That is, even when the lower semiconductor element 2A has a larger amount of heat generation than the upper semiconductor element 2B, heat is transferred from the lower semiconductor element 2A to the upper semiconductor element 2B by the action of the Peltier element 8. Is prevented. Thereby, the upper semiconductor element 2
The temperature of B can be kept lower than the temperature of the lower semiconductor element 2A.

【００２９】すなわち、上側の半導体素子２Ｂのジャン
クション温度が、下側の半導体素子２Ａのジャンクショ
ン温度より低いような場合、図２に示すようにペルチェ
素子８を設けることにより、下側の半導体素子２Ａから
の熱の伝達を防止し、上側の半導体素子２Ｂをそのジャ
ンクション温度より低く維持することができる。換言す
ると、下側の半導体素子２Ａの温度許容範囲に対して上
側の半導体素子２Ｂの温度許容範囲の方がマージンが小
さい場合であっても、ペルチェ素子８を設けることによ
り、下側の半導体素子２Ａの温度を許容範囲の上限に近
く維持しながら、上側の半導体素子２Ｂの温度をその許
容範囲内に維持することができる。That is, when the junction temperature of the upper semiconductor element 2B is lower than the junction temperature of the lower semiconductor element 2A, by providing the Peltier element 8 as shown in FIG. 2, the lower semiconductor element 2A is provided. It is possible to prevent the transfer of heat from the semiconductor element 2B and keep the upper semiconductor element 2B at a temperature lower than its junction temperature. In other words, by providing the Peltier element 8 even if the temperature allowable range of the upper semiconductor element 2B has a smaller margin than the temperature allowable range of the lower semiconductor element 2A, by providing the Peltier element 8, the lower semiconductor element It is possible to maintain the temperature of the upper semiconductor element 2B within the allowable range while maintaining the temperature of 2A near the upper limit of the allowable range.

【００３０】図２に示す半導体素装置では、ペルチェ素
子８と下側の半導体素子２Ａとの間にはモールドレジン
７が充填される構成であるが、図４に示すように、ペル
チェ素子８と下側の半導体素子２Ａとの間にアンダーフ
ィル材９を充填することとしてもよい。アンダーフィル
材９に伝熱特性の高い材料を使用すれば、ペルチェ素子
８から半導体素子２Ａへの熱の伝達を促進することがで
きる。In the semiconductor element device shown in FIG. 2, the mold resin 7 is filled between the Peltier element 8 and the lower semiconductor element 2A, but as shown in FIG. An underfill material 9 may be filled between the lower semiconductor element 2A and the semiconductor element 2A. If a material having a high heat transfer characteristic is used for the underfill material 9, the transfer of heat from the Peltier element 8 to the semiconductor element 2A can be promoted.

【００３１】次に、本発明の第２の実施の形態による積
層型マルチチップ半導体装置について、図５を参照しな
がら説明する。図５は本発明の第２の実施の形態による
積層型マルチチップ半導体装置の断面図である。図５に
おいて、図２に示す構成部品と同等な部品には同じ符号
を付し、その説明は適宜省略する。Next, a laminated multi-chip semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a sectional view of a stacked multi-chip semiconductor device according to the second embodiment of the present invention. 5, parts that are the same as the parts shown in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

【００３２】本発明の第２の実施の形態による半導体装
置では、ペルチェ素子８がインターポーザ１に搭載さ
れ、ペルチェ素子８の上に半導体素子２Ａ，２Ｂが積層
された状態で搭載される。本実施の形態の場合、ペルチ
ェ素子８は、下側の半導体素子２Ａから熱を吸収して、
吸収した熱をインターポーザ１に対して放出する。イン
ターポーザ１に伝達された熱は、インターポーザ１から
外部へと放出される。In the semiconductor device according to the second embodiment of the present invention, the Peltier element 8 is mounted on the interposer 1, and the semiconductor elements 2A and 2B are mounted on the Peltier element 8 in a stacked state. In the case of the present embodiment, the Peltier element 8 absorbs heat from the lower semiconductor element 2A,
The absorbed heat is released to the interposer 1. The heat transferred to the interposer 1 is released from the interposer 1 to the outside.

【００３３】したがって、本実施の形態の場合、半導体
素子２Ｂの熱は半導体素子２Ａを介してペルチェ素子８
に伝達され、インターポーザ１から外部に放出される。
これにより、半導体素子２Ｂの温度と半導体素子２Ａの
温度とはほぼ同じ温度となるが、半導体素子２Ａと半導
体素子２Ｂとの間にダイス付け材３の熱抵抗があるた
め、半導体素子２Ｂの温度のほうが僅かに高くなる。Therefore, in the case of the present embodiment, the heat of the semiconductor element 2B is transferred to the Peltier element 8 via the semiconductor element 2A.
And is released to the outside from the interposer 1.
As a result, the temperature of the semiconductor element 2B and the temperature of the semiconductor element 2A are almost the same, but the temperature of the semiconductor element 2B is the same because of the thermal resistance of the die attaching material 3 between the semiconductor element 2A and the semiconductor element 2B. Is slightly higher.

【００３４】本実施の形態の場合、半導体素子２Ａと半
導体素子２Ｂとの温度差は僅かであるが、ペルチェ素子
８を下側の半導体素子２Ａに等しい大きさか、それより
大きくできるため、冷却効果を大きくすることができ、
発熱量の大きな半導体素子であっても十分に冷却するこ
とができる。In the case of the present embodiment, the temperature difference between the semiconductor element 2A and the semiconductor element 2B is small, but the Peltier element 8 can be made equal to or larger than the lower semiconductor element 2A, so that the cooling effect can be obtained. Can be increased,
Even a semiconductor element that generates a large amount of heat can be sufficiently cooled.

【００３５】次に、本発明の第３の実施の形態につい
て、図６を参照しながら説明する。図６は本発明の第３
の実施の形態による積層型マルチチップ半導体装置の断
面図である。図６において、図２に示す構成部品と同等
な部品には同じ符号を付し、その説明は適宜省略する。Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 shows the third aspect of the present invention.
4 is a cross-sectional view of the stacked multi-chip semiconductor device according to the embodiment of FIG. 6, parts that are the same as the parts shown in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

【００３６】本発明の第３の実施の形態による半導体装
置は、上側の半導体素子２Ｂの上にペルチェ素子８を積
層して搭載したものである。すなわち、インターポーザ
１上に下側の半導体素子２Ａを搭載し、その上に半導体
素子２Ｂを積層して搭載し、更にその上にペルチェ素子
８を積層して搭載したものである。また、ペルチェ素子
８は、吸熱面８ｂが半導体素子２Ｂに対向した状態で積
層される。更に、ペルチェ素子８の放熱面８ａにはヒー
トシンク１０が接合される。The semiconductor device according to the third embodiment of the present invention is one in which the Peltier element 8 is laminated and mounted on the upper semiconductor element 2B. That is, the lower semiconductor element 2A is mounted on the interposer 1, the semiconductor element 2B is stacked and mounted thereon, and the Peltier element 8 is further stacked and mounted thereon. Further, the Peltier element 8 is laminated with the heat absorption surface 8b facing the semiconductor element 2B. Further, a heat sink 10 is joined to the heat radiation surface 8a of the Peltier element 8.

【００３７】そして、下側の半導体素子２Ａの端子はイ
ンターポーザ１の端子にワイヤボンディングされ、上側
の半導体素子２Ｂの端子は下側の半導体素子２Ａの端子
にワイヤボンディングされる。また、図６に示す例で
は、ペルチェ素子８の端子が半導体素子２Ｂの端子にワ
イヤボンディングされ電流が供給される。The terminals of the lower semiconductor element 2A are wire-bonded to the terminals of the interposer 1, and the terminals of the upper semiconductor element 2B are wire-bonded to the terminals of the lower semiconductor element 2A. Further, in the example shown in FIG. 6, the terminal of the Peltier element 8 is wire-bonded to the terminal of the semiconductor element 2B and the current is supplied.

【００３８】以上のような構成の半導体装置では、半導
体装置と実装基板との接続状況にも依存するが、インタ
ーポーザ１からの放熱量よりヒートシンク１０からの放
熱量の方が大きくなり、上側の半導体素子２Ｂの温度を
半導体素子２Ａの温度より低く維持することができる。In the semiconductor device configured as described above, the amount of heat radiated from the heat sink 10 is larger than the amount of heat radiated from the interposer 1, depending on the connection state between the semiconductor device and the mounting substrate, and the semiconductor above The temperature of the element 2B can be kept lower than the temperature of the semiconductor element 2A.

【００３９】図７及び図８は、図６に示す半導体装置の
変形例を示す断面図である。図７に示す半導体装置で
は、下側の半導体素子２Ａがフリップチップボンディン
グによりインターポーザ１に搭載されている。また、図
８に示す半導体装置では、上側の半導体素子２Ｂがフリ
ップチップボンディングにより下側の半導体素子２Ａに
搭載されている。したがって、ペルチェ素子８の端子
は、下側の半導体素子２Ａの端子にワイヤボンディング
される。7 and 8 are sectional views showing modifications of the semiconductor device shown in FIG. In the semiconductor device shown in FIG. 7, the lower semiconductor element 2A is mounted on the interposer 1 by flip chip bonding. Further, in the semiconductor device shown in FIG. 8, the upper semiconductor element 2B is mounted on the lower semiconductor element 2A by flip chip bonding. Therefore, the terminal of the Peltier element 8 is wire-bonded to the terminal of the lower semiconductor element 2A.

【００４０】次に、本発明の第４の実施の形態につい
て、図９を参照しながら説明する。図９は本発明の第４
の実施の形態による積層型マルチチップ半導体装置の断
面図である。図９において、図２に示す構成部品と同等
な部品には同じ符号を付し、その説明は適宜省略する。Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 shows the fourth embodiment of the present invention.
4 is a cross-sectional view of the stacked multi-chip semiconductor device according to the embodiment of FIG. 9, parts that are the same as the parts shown in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

【００４１】本発明の第４の実施の形態は、上述の実施
の形態とは異なり、ペルチェ素子のような電子冷却素子
を用いない。その代わり、下側の半導体素子２Ａと上側
の半導体素子２Ｂとの間に、熱絶縁体１１が配置され
る。熱絶縁体１１は、例えばエポキシ樹脂のように熱伝
導率の小さい材料により形成される。そして、熱絶縁体
１１の厚みは、例えば１５０μｍ以上であり、従来の積
層型の半導体装置のダイス付け材３の厚みより十分大き
い厚みである。したがって、上側の半導体素子２Ｂは、
下側の半導体素子２Ａから熱的に絶縁された状態とな
り、下側の半導体素子２Ａから上側の半導体素子２Ｂへ
の熱伝達が防止される。これにより、上側の半導体素子
２Ｂの温度を下側の半導体素子２Ａの温度より低く維持
することができる。The fourth embodiment of the present invention does not use an electronic cooling element such as a Peltier element unlike the above-mentioned embodiments. Instead, the thermal insulator 11 is arranged between the lower semiconductor element 2A and the upper semiconductor element 2B. The thermal insulator 11 is formed of a material having a low thermal conductivity such as epoxy resin. The thickness of the heat insulator 11 is, for example, 150 μm or more, which is sufficiently larger than the thickness of the die attaching material 3 of the conventional laminated semiconductor device. Therefore, the upper semiconductor element 2B is
The semiconductor element 2A on the lower side is thermally insulated, and heat transfer from the semiconductor element 2A on the lower side to the semiconductor element 2B on the upper side is prevented. Thereby, the temperature of the upper semiconductor element 2B can be kept lower than the temperature of the lower semiconductor element 2A.

【００４２】なお、上側の半導体素子２Ｂの発熱量が多
い場合は、図６に示すようなヒートシンクを上側の半導
体素子２Ｂに接合することにより、上側の半導体素子２
Ｂの温度を低く維持することができる。また、熱絶縁体
１１を熱伝送率の低い材料で形成されたダミーチップと
しても同様な熱絶縁効果を得ることができる。When the amount of heat generated by the upper semiconductor element 2B is large, a heat sink as shown in FIG. 6 is joined to the upper semiconductor element 2B, so that the upper semiconductor element 2
The temperature of B can be kept low. Further, the same heat insulating effect can be obtained even if the heat insulator 11 is a dummy chip formed of a material having a low heat transfer rate.

【００４３】図１０は、図９に示す半導体装置の変形例
を示す断面図である。図１０に示す半導体装置は、熱絶
縁体１１の代わりにポスト状（柱状）の熱絶縁体１１Ａ
を設けたものである。熱絶縁体１１Ａは半導体素子の接
合材料により形成し、その周囲に熱伝導率の低いエポキ
シ樹脂等をオーバーモールドすることとしてもよい。FIG. 10 is a sectional view showing a modification of the semiconductor device shown in FIG. The semiconductor device shown in FIG. 10 has a post-shaped (columnar) heat insulator 11A instead of the heat insulator 11.
Is provided. The thermal insulator 11A may be formed of a bonding material for a semiconductor element, and the periphery thereof may be overmolded with an epoxy resin or the like having a low thermal conductivity.

【００４４】以上説明した実施の形態による半導体装置
は、２つの半導体素子を有するものとして説明したが、
本発明は３つ以上の半導体素子が積層されたマルチチッ
プ半導体装置にも適用することができ、上述したものと
同様の効果を得ることができる。Although the semiconductor device according to the above-described embodiments has been described as having two semiconductor elements,
The present invention can be applied to a multi-chip semiconductor device in which three or more semiconductor elements are stacked, and the same effects as those described above can be obtained.

【発明の効果】上述の如く本発明によれば、次に述べる
種々の効果を実現することができる。As described above, according to the present invention, various effects described below can be realized.

【００４５】請求項１記載の発明によれば、積層した半
導体素子の間又は最下段の半導体素子の下に電子冷却装
置を配置することができる。電子冷却素子を半導体素子
の中間に配置した場合は、電子冷却素子の上側の半導体
素子から下側の半導体素子への熱の移動（伝達）を促進
することができ、上側と下側の半導体素子の間に積極的
に温度差を設けることができる。これにより、電子冷却
素子の上側の半導体素子のジャンクション温度が、電子
冷却素子の下側の半導体素子のジャンクション温度より
低い場合であっても、積層可能となる。また、電子冷却
素子を最下段の半導体素子の下に配置した場合は、上側
の半導体素子から下側の半導体素子への熱の移動（伝
達）が促進され、全ての半導体素子を効率よく冷却する
ことができる。According to the first aspect of the invention, the electronic cooling device can be arranged between the stacked semiconductor elements or below the lowermost semiconductor element. When the electronic cooling element is arranged in the middle of the semiconductor elements, it is possible to promote the transfer (transfer) of heat from the semiconductor element on the upper side of the electronic cooling element to the semiconductor element on the lower side. A temperature difference can be positively provided between the two. Accordingly, even if the junction temperature of the semiconductor element above the electronic cooling element is lower than the junction temperature of the semiconductor element below the electronic cooling element, stacking is possible. Further, when the electronic cooling element is arranged below the lowermost semiconductor element, heat transfer (transfer) from the upper semiconductor element to the lower semiconductor element is promoted, and all the semiconductor elements are efficiently cooled. be able to.

【００４６】請求項２記載の発明によれば、ジャンクシ
ョン温度の低い半導体素子、すなわち発熱に対するマー
ジンが少ない半導体素子の熱を集中的に吸収して冷却
し、吸収した熱をジャンクション温度の高い半導体装置
へと移動（伝達）することができる。したがって、半導
体装置全体を、ジャンクション温度の高い半導体素子に
合わせた熱抵抗に基づいて設計することができる。According to the second aspect of the present invention, the semiconductor device having a low junction temperature, that is, the semiconductor device having a small margin for heat generation is intensively absorbed and cooled, and the absorbed heat is a semiconductor device having a high junction temperature. Can be moved (transmitted) to. Therefore, the entire semiconductor device can be designed based on the thermal resistance matched to the semiconductor element having a high junction temperature.

【００４７】請求項３記載の発明によれば、半導体素子
を同様な構成及び材料にて電子冷却素子を作ることがで
き、電子冷却素子を容易に積層することができる。According to the third aspect of the invention, the semiconductor element can be made into an electronic cooling element with the same structure and material, and the electronic cooling elements can be easily laminated.

【００４８】請求項４記載の発明によれば、最上段の半
導体素子からも積極的に放熱することができ、半導体装
置の温度を効率的に低減することができる。According to the fourth aspect of the present invention, the heat can be positively radiated from the uppermost semiconductor element, and the temperature of the semiconductor device can be efficiently reduced.

【００４９】請求項５記載の発明によれば、熱絶縁体を
半導体素子の間に配置することにより、熱絶縁体の上側
の半導体素子と下側の半導体素子との間に積極的に温度
差を設けることができる。また、熱絶縁体の下側の半導
体素子の熱が熱絶縁体の上側の半導体素子に移動（伝
達）することが防止され、上側の半導体素子の温度上昇
を抑制することができる。According to the fifth aspect of the present invention, by disposing the thermal insulator between the semiconductor elements, the temperature difference between the semiconductor element above the thermal insulator and the semiconductor element below the thermal insulator is positively increased. Can be provided. Further, the heat of the semiconductor element on the lower side of the heat insulator is prevented from being transferred (transmitted) to the semiconductor element on the upper side of the heat insulator, and the temperature rise of the semiconductor element on the upper side can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来のスタック型のＭＣＰの構成を示す断面図
である。FIG. 1 is a cross-sectional view showing a configuration of a conventional stack type MCP.

【図２】本発明の第１の実施の形態による積層型マルチ
チップ半導体装置の断面図である。FIG. 2 is a cross-sectional view of the stacked multi-chip semiconductor device according to the first embodiment of the present invention.

【図３】図２に示すペルチェ素子の構成を示す図であ
る。FIG. 3 is a diagram showing a configuration of a Peltier device shown in FIG.

【図４】図２に示す半導体装置の変形例を示す断面図で
ある。FIG. 4 is a cross-sectional view showing a modified example of the semiconductor device shown in FIG.

【図５】本発明の第２の実施の形態による積層型マルチ
チップ半導体装置の断面図である。FIG. 5 is a sectional view of a stacked multi-chip semiconductor device according to a second embodiment of the present invention.

【図６】本発明の第３の実施の形態による積層型マルチ
チップ半導体装置の断面図である。FIG. 6 is a sectional view of a stacked multi-chip semiconductor device according to a third embodiment of the present invention.

【図７】図６に示す半導体装置の変形例を示す断面図で
ある。FIG. 7 is a cross-sectional view showing a modified example of the semiconductor device shown in FIG.

【図８】図６に示す半導体装置の他の変形例を示す断面
図である。8 is a cross-sectional view showing another modification of the semiconductor device shown in FIG.

【図９】本発明の第４の実施の形態による積層型マルチ
チップ半導体装置の断面図である。FIG. 9 is a sectional view of a stacked multi-chip semiconductor device according to a fourth embodiment of the present invention.

【図１０】図９に示す半導体装置の変形例を示す断面図
である。10 is a cross-sectional view showing a modified example of the semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

１ インターポーザ ２Ａ，２Ｂ 半導体素子 ３ ダイス付け材 ５Ａ，５Ｂ ボンディングワイヤ ６ ハンダボール ７ モールドレジン ８ ペルチェ素子 ８ａ 放熱面 ８ｂ 吸熱面 ８ｃ バンプ ９ アンダーフィル材 １０ ヒートシンク １１，１１Ａ 熱絶縁体 1 Interposer 2A, 2B semiconductor element 3 Die attaching material 5A, 5B Bonding wire 6 solder balls 7 Mold resin 8 Peltier element 8a Heat dissipation surface 8b Endothermic surface 8c bump 9 Underfill material 10 heat sink 11,11A heat insulator

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 配線基板上に積層して搭載された複数の
半導体素子を有する積層型マルチチップ半導体装置であ
って、 前記複数の半導体素子に対して積層した状態で電子冷却
素子を配置したことを特徴とする積層型マルチチップ半
導体装置。1. A stacked multi-chip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, wherein an electronic cooling element is arranged in a stacked state with respect to the plurality of semiconductor elements. A stacked multi-chip semiconductor device characterized by: 【請求項２】 複数の半導体素子を積層した搭載した積
層型マルチチップ半導体装置であって、 前記複数の半導体素子のうち最もジャンクション温度が
低い半導体素子に対して電子冷却素子を積層して配置し
たことを特徴とする積層型マルチチップ半導体装置。2. A stacked multi-chip semiconductor device in which a plurality of semiconductor elements are stacked and mounted, wherein an electronic cooling element is stacked and arranged on a semiconductor element having the lowest junction temperature among the plurality of semiconductor elements. A stacked multi-chip semiconductor device characterized by the above. 【請求項３】 請求項１又は２記載の積層型マルチチッ
プ半導体装置であって、 前記電子冷却素子はペルチェ素子であることを特徴とす
る積層型マルチチップ半導体装置。3. The stacked multi-chip semiconductor device according to claim 1, wherein the electronic cooling element is a Peltier element. 【請求項４】 請求項１記載の積層型マルチチップ半導
体装置であって、 前記電子冷却素子はペルチェ素子であり、該ペルチェ素
子の低温側を最上段の半導体素子に接合し、前記ペルチ
ェ素子の高温側を放熱板に接合したことを特徴とする積
層型マルチチップ半導体装置。4. The stacked multi-chip semiconductor device according to claim 1, wherein the electronic cooling element is a Peltier element, and the low temperature side of the Peltier element is bonded to the uppermost semiconductor element, A laminated multi-chip semiconductor device characterized in that a high temperature side is joined to a heat sink. 【請求項５】 配線基板上に積層して搭載された複数の
半導体素子を有する積層型マルチチップ半導体装置であ
って、 前記複数の半導体素子の間に積層した状態で熱絶縁体を
配置し、該熱絶縁体を挟む半導体装置の間に温度差を設
けたことを特徴とする積層型マルチチップ半導体装置。5. A stacked multi-chip semiconductor device having a plurality of semiconductor elements stacked and mounted on a wiring board, wherein a thermal insulator is arranged in a stacked state between the plurality of semiconductor elements, A laminated multi-chip semiconductor device, wherein a temperature difference is provided between the semiconductor devices sandwiching the thermal insulator.
JP2001201072A 2001-07-02 2001-07-02 Multilayer multichip semiconductor device Expired - Fee Related JP4817543B2 (en)

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