JP2003017622A - Semiconductor chip and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor chip capable of fining a wiring layer formed on a semiconductor element. SOLUTION: A laminate 10B at the upper part of a semiconductor chip 10 and a semiconductor element 10A at the lower part of the chip 10 are independently formed. The laminate 10B is collectively laminated on the element 10A, thereby forming the chip 10. In this way, since a through hole conductor 160 is arbitrarily formed, the aspect ratio of the conductor 160 can be made to be higher than that in conventional technique. Accordingly, the wiring layer provided on the chip 10 can be made finer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip in which a wiring layer is laminated on a semiconductor element and a manufacturing method thereof.

[0002]

2. Description of the Related Art The wiring layer of this type of semiconductor chip is generally manufactured by a build-up method, and the manufacturing process is outlined below, for example. First, a photosensitive curable resin is spin-coated on one side of a disk-shaped silicon wafer, and exposed and developed to form a via from the upper surface of the curable resin to the wafer at a predetermined position. Form a hole. Then, the curable resin is cured to form the first insulating layer. Next, a copper film is formed on the surface of the insulating layer and in the via hole by electroless copper plating, a photosensitive resist is laminated on the copper film by, for example, spin coating, and exposure is performed while masking a predetermined pattern. Perform development processing. Then, copper is filled by electrolytic copper plating to form the inner via and the first conductor circuit,
Isolate the resist. Then, the electroless copper plating film is removed by etching by a known etching method.

When a circuit is further laminated on the first conductor circuit, a photosensitive curable resin is laminated and cured on the first conductor circuit to form a second insulating layer, and the second insulating layer is formed on the second insulating layer. A second conductor circuit is formed in the same manner as above.

In this way, the wiring layer is formed on the semiconductor element by alternately forming the insulating layer made of the curable resin and the conductor circuit utilizing the via hole provided at a predetermined position of the insulating layer. The formed semiconductor chips are formed vertically and horizontally. Finally, a semiconductor chip is manufactured by performing a dicing operation for cutting the wafer into each chip along the dicing streets that partition each semiconductor chip.

[0005]

However, in the case where the insulating layer and the conductor circuit are multilayered by the above-mentioned manufacturing method,
There is a limit to increasing the aspect ratio of via holes and the like provided in the insulating layer, which is a factor that prevents the fineness of the wiring layer provided in the semiconductor chip. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor chip and a method for manufacturing the semiconductor chip, which enable finer wiring layers formed on a semiconductor element.

[0006]

In order to solve the above problems, in the method of manufacturing a semiconductor chip according to the invention of claim 1, an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element. The semiconductor chip is technically characterized by undergoing at least the following steps (a) to (c). (A) a step of forming a through hole at a predetermined position of the insulating substrate; (b) a step of filling the through hole with a conductive metal to form a through conductor; (c) a semiconductor element. Stacking the insulating substrates.

According to the invention of claim 1, a semiconductor chip is formed by stacking an insulating substrate having a through conductor formed thereon on a semiconductor element. That is, unlike the conventional manufacturing method in which the conductor circuit and the interlayer insulating layer are directly laminated on the semiconductor element, the interlayer insulating layer and the conductor circuit (through conductor) in the upper layer portion of the semiconductor chip and the conductor in the lower layer portion of the semiconductor chip are different from each other. A semiconductor element having a circuit is separately manufactured in advance. Then, the semiconductor chip is formed by stacking the upper layer portion and the lower layer portion together. Thereby, since the through conductor can be formed freely, the aspect ratio of the through conductor can be increased as compared with the conventional case.
Therefore, finer wiring layers provided on the semiconductor chip can be achieved.

According to a second aspect of the present invention, an uncured resin layer is provided on the surface of the insulating substrate, and an electric conductor penetrating the resin layer is provided on the through conductor. That is, the semi-cured resin layer is crushed while being sandwiched between the semiconductor element and the insulating substrate when the insulating substrate is laminated on the semiconductor element,
It can be easily adhered to the surface of the semiconductor element. This serves as an adhesive layer, so that the connectivity between the semiconductor element and the insulating substrate can be improved. In addition, since a conductor having plasticity preferably penetrates through the resin layer, it enhances the connectivity between the through conductor and the conductor circuit of the semiconductor element. Thereby, electrical connection can be improved.

According to the third aspect of the present invention, since the conductor protrudes in a convex shape from the surface of the resin layer, when the insulating substrate is laminated on the semiconductor element, the through conductor and the semiconductor element can be reliably formed. Can be connected to the conductor circuit. Thereby, electrical connectivity can be improved.

According to the invention of claim 4, instead of the conventional glass fiber, the polymer is used for the core material in the insulating substrate. That is, since the core material is a polymer, when laser drilling is performed, the core material can be easily melted and vaporized by the energy of the laser, similarly to the resin portion with which the core material is impregnated. Thereby, the through conductor can be formed freely, so that the aspect ratio of the through conductor can be increased.

According to a fifth aspect of the invention, the core portion is made of aramid fiber. The coefficient of linear thermal expansion of aramid fiber is close to that of silicon used for semiconductor elements. Accordingly, during heating, expansion and contraction of the interlayer insulating layer due to the linear thermal expansion coefficient can be suppressed, so that stress generated in the interlayer insulating layer can be relaxed. Further, since the aramid fiber is easily melted and vaporized by the energy of the laser, the through conductor can be freely formed. Thereby, the aspect ratio of the through conductor can be increased.

The transition layer defined in the present invention will be described. The transition layer means an intermediate intermediary layer provided to directly connect the IC chip, which is a semiconductor element, to the printed wiring board. The feature is that it is formed of two or more metal layers and is larger than the die pad of the IC chip which is a semiconductor element. This improves electrical connection and alignment. Further, it is possible to directly form a metal, which is a conductor layer of the printed wiring board, on the transition layer.

The reason for providing the transition layer on the die pad of the IC chip is as follows. The die pad of the IC chip is made to have a diameter of about 20 to 60 μm, and the via hole is larger than that, so that disconnection is likely to occur at the time of displacement. Therefore, the via hole can be surely connected by interposing the transition layer having a diameter larger than 20 μm on the die pad of the IC chip. Desirably, the transition layer has a diameter equal to or larger than the via hole diameter.

Although each of them functions only by a multilayer printed wiring board, in some cases, in order to function as a package board as a semiconductor chip, it is connected to an external board such as a mother board or a daughter board.
BGA, solder bumps, or PGA (conductive connection pin) may be provided. Further, with this configuration, the wiring length can be shortened and the loop inductance can be reduced as compared with the case where the connection is performed by the conventional mounting method.

Vapor deposition, sputtering, electroless plating or the like is performed on the entire surface of the core substrate containing the IC chip to form a conductive metal film (first thin film layer) on the entire surface. The metals include tin, chromium, titanium, nickel, zinc,
Cobalt, gold, copper, etc. are good. The thickness is 0.00
It is preferable to form it between 1 and 2.0 μm. 0.001
If it is less than μm, it cannot be uniformly laminated on the entire surface. 2.0 μm
It has been difficult to form more than 10%, and the effect has not been enhanced. In the case of chromium, a thickness of 0.1 μm is desirable.

The first thin film layer can cover the die pad to improve the adhesion between the transition layer and the IC chip at the interface with the die pad. Further, by covering the die pad with these metals, it is possible to prevent moisture from entering the interface, prevent the die pad from melting and corroding, and improve the reliability. In addition, the first thin film layer enables connection with the IC chip by a leadless mounting method. Here, it is desirable to use copper, chromium, nickel, or titanium in order to improve the adhesion to a metal and to prevent moisture from entering the interface. If the die pad is made of copper, then copper is optimal for the first thin film layer.

A second thin film layer may be provided on the first thin film layer. The metal includes nickel, copper, gold and silver. Particularly when the die pad is made of copper, the second thin film layer is formed on the first thin film layer by sputtering, vapor deposition, or electroless plating. Copper is preferably used for the second thin film layer because electrical characteristics, economy, and the die pad is made of copper, and the thick layer formed later is mainly copper.

The reason why the second thin film layer is provided here is that it is difficult to take a lead for electrolytic plating for forming a thickening layer described later in the first thin film layer. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5.0 μm. 0.
If it is less than 01 μm, it cannot serve as a lead,
This is because if the thickness exceeds 5.0 μm, the lower first thin film layer is shaved more to form a gap during etching, moisture is likely to enter, and the reliability is reduced. Electrical characteristics,
Copper is preferably used because it is economical and the thick layer formed later is mainly copper. Copper is most suitable when the die pad is made of copper.

The second thin film layer is thickly applied by electroless or electrolytic plating. The types of metals that can be formed include nickel, copper, gold, silver, zinc and iron. Electrical properties, economy, strength as a transition layer and structural resistance, and the conductor layer that is the buildup that is formed later is mainly copper, so it is desirable to form it by electrolytic plating using copper. . The thickness is preferably in the range of 1 to 20 μm. When the thickness is less than 1 μm, the connection reliability with the upper via hole decreases, and when the thickness is more than 20 μm, undercut occurs during etching, and a gap is generated at the interface between the formed transition layer and the via hole. Because. In some cases, the first thin film layer may be directly subjected to thick plating, or may be further laminated in multiple layers.

After that, an etching resist is formed,
The transition layer is formed on the die pad of the IC chip by exposing and developing to expose the metal in the portion other than the transition layer to perform etching.

In addition to the above-mentioned method of manufacturing the transition layer, a dry film resist is formed on the metal film formed on the IC chip and the core substrate to remove a portion corresponding to the transition layer, and electrolytic plating is performed. After thickening, the resist may be peeled off and an etching solution may be used to similarly form a transition layer on the die pad of the IC chip.

According to a fourteenth aspect of the present invention, there is provided a semiconductor chip in which an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, and an insulating substrate having a through conductor formed by filling a through hole with a conductive metal. And a semiconductor element having an interlayer resin insulation layer provided with a via hole and a conductor circuit, which are laminated with a resin layer interposed between the through conductor of the insulating substrate and the conductor circuit of the semiconductor element. The technical feature is that the connection is made through a conductor having plasticity.

The semiconductor chip according to claim 14 is different from the conventional manufacturing method in which the conductor circuit and the interlayer insulating layer are directly laminated on the semiconductor element, and the interlayer insulating layer and the conductor circuit (penetrating conductor) in the upper layer portion of the semiconductor chip. And a semiconductor element having a conductor circuit in the lower layer portion of the semiconductor chip are separately prepared in advance. Then, the semiconductor chip is formed by stacking the upper layer portion and the lower layer portion together. Thereby, since the through conductor can be formed freely, the aspect ratio of the through conductor can be increased as compared with the conventional case. Therefore, finer wiring layers provided on the semiconductor chip can be achieved.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor chip (chip size package) according to the present invention will be described below with reference to the drawings. [Semiconductor Chip] The configuration of the semiconductor chip according to the first embodiment formed by stacking the laminated plates having the through conductors on the semiconductor element will be described with reference to FIG. The semiconductor chip 10 includes a semiconductor element 10 </ b> A in which the interlayer resin insulation layer 50 is formed on the IC chip 20, and a through conductor 160.
And a laminated plate 10B. Semiconductor chip 10
The transition layer 38 is formed on the die pad 22 of the IC chip 20, and the conductor circuit 58 is connected to the transition layer 38 via the via hole 60. Solder bumps 176 are arranged on the through conductors 160 of the laminated plate 10B via the conductor circuits 81.
It is connected to an external substrate such as a daughter board via. The semiconductor element 10A and the laminated plate 10B are connected to the conductor circuit 58 of the semiconductor element 10A and the through conductor 160 of the laminated plate 10B via the conductive bumps 76 made of a low melting point metal.

According to the semiconductor chip of this embodiment, instead of directly forming the adhesive layer 150 and the penetrating conductor 160 on the conductor circuit 58, the semiconductor element 10A and the laminated plate 10B are individually formed in advance, and are collectively packaged. It is configured to be laminated on.
Accordingly, since the through conductor 160 can be formed freely, the aspect ratio of the through conductor 160 can be increased as compared with the conventional case.

Further, the adhesive layer 150 provided on the laminated board 10B of this embodiment is a semi-cured epoxy resin layer, and when the laminated board 10B is laminated on the semiconductor element 10A, it is laminated with the semiconductor element 10A. It is squeezed while being sandwiched between the plate 10B and the plate 10B, and can easily adhere to the surface of the semiconductor element 10A. This serves as an adhesive layer, so that the connectivity between the semiconductor element 10A and the laminated plate 10B can be improved.

The interlayer resin insulation layer 250 uses aramid fiber as a core material as a reinforcing material. Therefore, the coefficient of linear thermal expansion of the wafer 20A made of silicon is close to that of the wafer 20A, and expansion and contraction of the interlayer insulating layer due to the linear thermal expansion coefficient can be suppressed during heating. Thereby, the stress generated in the interlayer insulating layer can be relaxed. Further, since the aramid fiber is easily melted and vaporized by the energy of the laser, the through conductor 160 can be freely formed. Thereby, the aspect ratio of the through conductor 160 can be increased.

[Insulating Layer (Laminated Plate) Comprising Through Conductor and Conductor Layer] Next, FIG. 13 shows the structure of the laminated plate 10B including the through conductor laminated on the semiconductor element described above.
This will be described in more detail with reference to (D). As shown in FIG. 13D, the laminated plate 10B has a copper foil 80 and a heat release sheet 8
The interlayer resin insulation layer 250 is laminated on the second resin layer 2, and the adhesive layer 150 is formed on the surface of the interlayer resin insulation layer 250. The through conductor 160 and the conductive bump 76 are provided on the adhesive layer 150 and the interlayer resin insulation layer 250. In addition, the copper foil 80, the adhesive layer 150, the interlayer resin insulation layer 2
An alignment hole 68 for positioning is formed so as to penetrate 50.

The semi-cured adhesive layer 150 plays a role of adhering the laminated plate 10B and the semiconductor element 10A. Therefore, when the laminated plate 10B is laminated on the semiconductor element 10A, the semiconductor element 10A and the laminated plate 10B can be easily brought into close contact with each other. In addition, the through conductor 160 has the adhesive layer 15
Since it penetrates 0, the through conductor 160 and the semiconductor element 1
The connectivity with the 0 A conductor circuit 58 is enhanced. Thereby, electrical connection can be improved.

Since the conductive bumps 76 provided on the through conductors 160 project from the surface of the adhesive layer 150, when the laminated plate 10B is laminated on the semiconductor element 10A, the through conductors 160 and the semiconductor element can be reliably made. Conductor circuit 5 on 10A
8 can be connected. This makes it possible to improve electrical connectivity.

[Semiconductor Element Comprising Conductor Circuit]
The configuration of the semiconductor element 10A formed by stacking the interlayer resin insulation layer on the above-described semiconductor element (IC chip) will be described in more detail. First, the semiconductor element (I
The configuration of the (C chip) will be described with reference to FIG. 3A showing a cross section of the semiconductor element 20 and FIG. 4B showing a plan view. The wafer 20A used for the semiconductor element 20 is made of silicon single crystal and has a diameter of 4 inches, for example.
The thickness is about 300 μm. This wafer 20
For example, a square semiconductor device 20 having a side of about 10 mm is manufactured in A in a state of being aligned vertically and horizontally.

As shown in FIG. 3B, a die pad 22 and wiring (not shown) are provided on the upper surface of the semiconductor element 20, and the protective film 24 covers the die pad 22 and the wiring. The die pad 22 is formed with an opening of a protective film 24. A transition layer 38 mainly made of copper is formed on the die pad 22. The transition layer 38 includes the thin film layer 33 and the thickening layer 3
It consists of 7. In other words, it is formed of two or more metal layers.

As shown in FIG. 11D, the semiconductor element 10A of the first embodiment comprises the above-mentioned IC chip 20 and the interlayer resin insulation layer 50. A via hole 60 and a conductor circuit 58 are formed in the interlayer resin insulation layer 50.

In the semiconductor element 10A of this embodiment, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, and the upper interlayer insulating layer 50 is also flattened. The film thickness also becomes uniform. Further, the transition layer 38 can maintain the shape stability even when the upper via hole 60 is formed.

Furthermore, by providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the pad 22, and to immerse the resin in an acid, an oxidant or an etching solution in a later step, Discoloration and dissolution of the pad 22 do not occur even after various annealing steps. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Furthermore, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be surely connected.

[Manufacturing Method of Semiconductor Chip] Next, a manufacturing method of the above-described semiconductor chip will be described. First,
A method of manufacturing a semiconductor device used for the chip size package described above with reference to FIG. 3B will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 2 are formed on the silicon wafer 20A shown in FIG.
2 is formed (see FIGS. 4A and 4B which are plan views of FIGS. 1B and 1B), and FIG. 1B is a cross-sectional view taken along line BB of FIG. Exist). (2) Next, a protective film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (see FIG. 1C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (see FIG. 2A). The thickness is preferably formed in the range of 0.001 to 2.0 μm. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals serve as a protective film for the die pad and do not deteriorate the electrical characteristics. In the first embodiment, the thin film layer 33 is made of chromium by sputtering. Chromium has good adhesion to metal and can suppress the ingress of moisture. Alternatively, copper may be sputtered on the chromium layer. Two layers of chromium and copper may be continuously formed in the vacuum chamber. At this time, the thickness is about 0.05-0.1 μm for chromium and about 0.5 μm for copper.

(4) After that, a resist layer of any one of liquid resist, photosensitive resist and dry film is formed on the thin film layer 33. A mask (not shown) in which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed to form a non-formation portion 35a in the resist 35. Electrolytic plating is performed to form a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 2B). The types of plating formed include nickel, copper, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer that is a buildup to be formed later are mainly copper. In the first embodiment, copper is used. Its thickness is 1 to 20
It is preferable to perform in the range of μm.

(5) After removing the plating resist 35 with an alkaline solution or the like, the metal film 33 below the plating resist 35 is treated with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic. The transition layer 38 is formed on the pad 22 of the IC chip by removing it with an etching solution such as acid salt.
Are formed (see FIG. 2C).

(6) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (FIG. 3 (A)).
reference). The roughened surface can also be formed using electroless plating or redox treatment.

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (FIG. 3).
FIG. 4B is a plan view of FIGS. 3B and 3B. Then, if necessary, the divided semiconductor element 2
0 operation check and electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pin can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

The thin film layer 33 can also be formed of titanium. Titanium is applied by vapor deposition or sputtering.
Titanium has good adhesion to metal and can suppress the ingress of moisture. Further, the thin film layer can be formed of tin, zinc, or cobalt. Further, the thin film layer can be formed of nickel. Nickel is formed by sputtering. Nickel has good adhesion to metal and can suppress ingress of moisture. On top of the thin film layer,
Further, copper may be laminated.

[Second Manufacturing Method] Next, a semiconductor element according to the second manufacturing method will be described with reference to FIGS. Regarding the semiconductor element 20 according to the second manufacturing method,
This will be described with reference to FIG. In the semiconductor device according to the first example described above with reference to FIG. 3B, the transition layer 38 includes the thin film layer 33 and the thickening layer 37.
It was a layered structure. On the other hand, in the second manufacturing method,
As shown in FIG. 7B, the transition layer 38 has a three-layer structure including a first thin film layer 33, a second thin film layer 36, and a thickening layer 37.

5 to 7 for the method of manufacturing a semiconductor device according to the second manufacturing method described above with reference to FIG.
Will be described with reference to.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (see FIG. 5B). (2) Next, the protective film 2 is formed on the die pad 22 and the wiring.
4 is formed (see FIG. 5C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (FIG. 5D).
reference). The thickness is preferably formed in the range of 0.001 to 2 μm. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary.
The optimum range is 0.01 to 1.0 μm. The metals to be formed include tin, chromium, titanium, nickel, zinc,
It is preferable to use one selected from cobalt, gold, and copper. Those metals become the protective film of the die pad,
Moreover, the electrical characteristics are not deteriorated. In the second manufacturing method, the first thin film layer 33 is made of chromium.
Chromium, nickel and titanium have good adhesion to metals,
Ingress of moisture can be suppressed.

(4) Sputtering on the first thin film layer 33,
The second thin film layer 36 is laminated by either vapor deposition or electroless plating (see FIG. 6A). In this case, the metal that can be laminated is preferably selected from nickel, copper, gold and silver. In particular, it is preferable to use copper or nickel. This is because copper is inexpensive and has good electric conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. In addition,
A desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel, or the like. It is superior to other combinations in terms of bondability with metals and electric conductivity.

(5) Thereafter, the resist layer is used as the second thin film layer 3
6 is formed. A mask (not shown) is placed on the resist layer, and after exposure and development, a non-forming portion 35a is formed in the resist 35. Electrolytic plating is performed to form a thickening layer (electrolytic plating film) 37 on the resist layer non-forming portion 35a (see FIG. 6B). The types of plating formed include copper, nickel, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer that is a build-up to be formed later are mainly copper. In the second manufacturing method, copper is used. Thickness is 1 to 20
The range of μm is preferable.

(6) After removing the plating resist 35 with an alkaline solution or the like, the second thin film layer 3 under the plating resist 35 is removed.
6. By removing the first thin film layer 33 with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc., the first thin film layer 33 is formed on the pad 22 of the IC chip. The transition layer 38 is formed (see FIG. 6C).

(7) Next, an etching solution is sprayed onto the substrate to etch the surface of the transition layer 38 to form a roughened surface 38α (FIG. 7A).
reference). The roughened surface can also be formed using electroless plating or redox treatment.

(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor element 20 (FIG. 7).
(See (B)).

In the second manufacturing method described above, the first thin film layer 33 is formed of chromium, the second thin film layer 36 is formed of electroless plated copper, and the thick layer 37 is formed of electrolytic copper plating. On the other hand, the first thin film layer 33 is made of chrome and the second thin film layer 3 is
6 may be sputtered copper and the thickening layer 37 may be formed by electrolytic copper plating. Chromium 0.07 as the thickness of each layer
μm, copper 0.5 μm, and electrolytic copper 15 μm.

Further, the first thin film layer 33 is made of titanium,
The second thin film layer 36 may be formed of electroless copper and the thickening layer 37 may be formed of electrolytic copper plating. As the thickness of each layer, titanium 0.07 μm, plated copper 1.0 μm, electrolytic copper 17 μm
Is.

Furthermore, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 of sputtered copper, and the thickening layer 37 of electrolytic copper plating. As the thickness of each layer, titanium 0.06 μm, copper 0.5 μm, electrolytic copper 15 μm
m.

The first thin film layer 33 is made of chromium, the second thin film layer 36 is made of electroless plated nickel, and the thickening layer 37 is made.
Can also be formed by electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 1.0 μm plated copper, and 15 μm electrolytic copper.

The first thin film layer 33 is made of titanium, the second thin film layer 36 is made of electroless plated nickel, and the thick layer 37 is formed.
Can also be formed by electrolytic copper plating. As the thickness of each layer, titanium 0.05μm, plated nickel 1.2μ
m, electrolytic copper 15 μm.

[Third Manufacturing Method] The semiconductor element 20 according to the third manufacturing method will be described. The configuration of the semiconductor device of the third manufacturing method is almost the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the semi-additive process is used, and the thickening layer 37 is formed on the resist non-forming portion.
To form the transition layer 38. On the other hand, in the third manufacturing method, an additive process is used to uniformly form the thickening layer 37, a resist is provided, and the non-resist formation portion is removed by etching to form the transition layer 38.

A method of manufacturing a semiconductor device according to the third manufacturing method will be described with reference to FIG. (1) As described above with reference to FIG. 2A in the first embodiment, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form the conductive thin film layer 33 on the entire surface ( See FIG. 8 (A). Its thickness is 0.00
The range of 1 to 2.0 μm is preferable. If it is below the range, the thin film layer cannot be formed on the entire surface. If it is above the range, the thickness of the formed film will vary. The optimum range is preferably 0.01 to 1.0 μm. As the metal to be formed, it is preferable to use a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. These metals protect the die pad and do not deteriorate the electrical characteristics. In the third manufacturing method, the thin film layer 33 is
It is formed by sputtering chromium. The thickness of chromium is 0.05 μm.

(2) Electrolytic plating is performed to uniformly form a thickening layer (electrolytic plating film) 37 on the thin film layer 33 (FIG. 8).
(See (B)). The types of plating formed include copper, nickel, gold, silver, zinc and iron. Copper is preferably used because the electrical characteristics, economy, and the conductor layer, which is a buildup formed later, are mainly copper, and copper is used in the third manufacturing method. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut may occur at the time of etching which will be described later, and a gap may be generated at the interface between the formed transition layer and the via hole.

(3) Then, the resist layer 35 is formed on the thickening layer 37 (see FIG. 8C).

(4) Thin film layer 3 in the non-formed portion of resist 35
3 and the thickening layer 37 are removed by an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt or the like, and then the resist 35 is peeled off to form an IC. Transition layer 38 on the pad 22 of the chip
Are formed (see FIG. 8D). Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted. The thin film layer 3
It is also possible to form 3 with titanium.

[Fourth Manufacturing Method] The semiconductor element 20 according to the fourth manufacturing method will be described. In the semiconductor element according to the third manufacturing method described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the thickening layer 37. On the other hand, in the fourth manufacturing method, as shown in FIG.
The thin film layer 33, the second thin film layer 36, and the thickening layer 37 have a three-layer structure.

A method of manufacturing a semiconductor device according to the fourth manufacturing method will be described with reference to FIG. (1) Similar to the second manufacturing method described above with reference to FIG. 6A, the second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, or electroless plating (see FIG. 9
(See (A)). In that case, the metal that can be stacked is nickel,
The one selected from copper, gold and silver is preferable. In particular, it is preferable to use copper or nickel. This is because copper is inexpensive and has good electric conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the fourth manufacturing method, the second thin film layer 36 is formed by electroless copper plating. The desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, titanium-nickel. It is superior to other combinations in terms of bondability with metals and electric conductivity.

(2) The second thin film layer 36 is formed by electrolytic plating.
A thickening film 37 is evenly provided on the upper surface (see FIG. 9B).

(3) After that, the resist layer 35 is formed on the thickening layer 37 (see FIG. 9C).

(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 in the non-formed portion of the resist 35 are treated with sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, and cupric. After removing the complex-organic acid salt with an etching solution, the resist 3
By peeling 5 away, the transition layer 38 is formed on the pad 22 of the IC chip (see FIG. 9D). Since the subsequent steps are the same as those in the first embodiment, the description thereof will be omitted.

It is also possible to form the first thin film layer 33 with chromium, the second thin film layer 36 with sputtered copper, and the thickening layer 37 with electrolytic copper plating. The thickness of each layer is 0.07 μm chromium, 0.5 μm copper, and 15 μm electrolytic copper.
The first thin film layer 33 is made of titanium and the second thin film layer 36 is made of titanium.
Can be formed by electroless copper and the thickening layer 37 can be formed by electrolytic copper plating. The thickness of each layer is 0.07 μm of titanium, 1.0 μm of copper, and 15 μm of electrolytic copper.

Further, the first thin film layer 33 is made of titanium,
The second thin film layer 36 may be formed of sputtered copper, and the thickening layer 37 may be formed of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 0.5 μm copper, and 18 μm electrolytic copper.

The first thin film layer 33 is made of chromium, the second thin film layer 36 is made of electroless plated nickel, and the thickening layer 37 is made.
Can also be formed by electrolytic copper plating. The thickness of each layer is 0.06 μm chromium, 1.2 μm nickel, and 16 μm electrolytic copper.

Furthermore, the first thin film layer 33 may be formed of titanium, the second thin film layer 36 of electroless plated nickel, and the thickening layer 37 of electrolytic copper plating. The thickness of each layer is 0.07 μm titanium, 1.1 μm nickel, and 15 μm electrolytic copper.

[Fifth Manufacturing Method] In the fifth manufacturing method, the surface of the die pad 22 is treated with zincate. The IC chip 20 is immersed in a nickel electroless or plating bath to deposit a nickel plating film on the die pad 22. Then I
The C chip 20 is dipped in a nickel-copper composite plating solution,
A nickel-copper composite plating layer having a thickness of 0.01 to 5 μm is formed on the nickel plating layer.

Next, a semiconductor element having a conductor circuit formed by laminating an interlayer resin insulation layer on the semiconductor element (IC chip) formed by the manufacturing method described above with reference to FIG. 3B. About the manufacturing method of FIG.
This will be described with reference to FIG.

(1) First, the IC chip 20 provided with the transition layer 38 is used as a starting material by the above-described semiconductor element manufacturing process (see FIG. 10A). Next, an interlayer resin insulation layer 50 is provided by applying a photosensitive curable resin to the IC chip 20 (FIG. 10).
(See (B)). As the curable resin, for example, a photosensitive polyimide resin can be used. Here, since the transition layer 38 is formed in the IC chip 20, the thickness of the interlayer resin insulation layer 50 can be made uniform, and the formation of the via hole 60 described later can be stabilized.

(2) Next, the photomask film 49 having a black circle 49a corresponding to the via hole forming position is placed on the interlayer resin insulating layer 50 and exposed (FIG. 10C).
reference).

(3) The interlayer resin insulation layer 50 is provided with the via hole opening 48 having a diameter of 85 μm by spray development with a DMTG solution and heat treatment (see FIG. 10D). The resin residue in the openings 48 is removed by using permanganate having a liquid temperature of 60 ° C.

By providing the copper transition layer 38 on the die pad 22, it is possible to prevent resin residue on the die pad 22, thereby improving the connectivity and reliability between the die pad 22 and a via hole 60 described later. .
Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the via hole opening 48 having a diameter of 60 μm can be surely connected. Although the resin residue was removed using an oxidizing agent such as permanganate here, desmear treatment can be performed using oxygen plasma or corona treatment.

(4) Next, the surface of the interlayer resin insulation layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 11A). Roughened surface is 0.05 ~
A distance of 5 μm is desirable.

(5) The metal layer 52 is provided on the interlayer resin insulation layer 50 on which the roughened surface 50α is formed. The metal layer 52 is
It was formed by electroless plating. By previously applying a catalyst such as palladium to the surface layer of the interlayer resin insulation layer 50 and immersing it in the electroless plating solution for 5 to 60 minutes,
A metal layer 52, which is a plating film, was provided in the range of 1 to 5 μm (see FIG. 11B). As an example thereof, [electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α ′ -Bipyrudil 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Immersed at a liquid temperature of 34 ° C. for 40 minutes.

Instead of plating, SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. was used, and sputtering using Ni--Cu alloy as a target was performed at a pressure of 0.6 Pa and a temperature of 80.
℃, power 200W, time 5 minutes, Ni-C
The u alloy 52 may be formed on the surface of the interlayer resin insulation layer 50. At this time, the formed Ni-Cu alloy layer 52
Has a thickness of 0.2 μm.

(6) IC chip 20 that has undergone the above processing
Then, a commercially available photosensitive dry film was attached to the substrate, a photomask film was placed thereon, the film was exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate to a thickness of 15
A plating resist 54 of μm is provided. Next, electroplating is performed under the following conditions to form an electroplated film 5 having a thickness of 15 μm.
6 is formed (see FIG. 11C). The additive in the electrolytic plating solution is Caparaside HL manufactured by Atotech Japan.

[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Atotech Japan, Kaparaside HL) 19.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(7) The plating resist 54 is 5% NaOH.
After peeling and removing with a metal layer 52 under the plating resist
Is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid, and hydrogen peroxide, and a conductor circuit 58 and a via hole 6 each having a thickness of 16 μm and formed of a metal layer 52 and an electrolytic plating film 56.
Form 0. Then, roughening surfaces 58α and 60α are formed on the surfaces of the conductor circuit 58 and the via hole 60 by an etching solution containing a cupric complex and an organic acid, thereby manufacturing the semiconductor element 10A (FIG. 11 ( See D)). Since the transition layer 38 is formed on the IC chip 20, the stability of the shape of the via hole 60 can be maintained when the via hole 60 is formed.

Next, referring to FIG. 13D, the method of manufacturing the laminated plate including the through conductor described above will be described with reference to FIG.
2, with reference to FIG.

(1) The starting material for the laminate 10B is the single-sided copper-clad laminate 12. This single-sided copper-clad laminate 12 is formed by impregnating "Aramica" (trademark) manufactured by Asahi Kasei Co., Ltd. (corresponding to the aramid fiber of the present invention) with an epoxy resin and curing the interlayer resin insulation layer 250 with a copper foil 80 of 18 μm in thickness. Is pasted. Then, an adhesive layer 150 made of an epoxy resin half-cured by heating is laminated on the one-sided copper-clad laminate 12 (see FIG. 12A). Although not shown,
The surface of the semi-cured adhesive layer 150 is covered with a protective film made of polyethylene terephthalate, for example.

(2) A laser or the like is used to form an alignment hole 68 having a diameter of 0.3φ which penetrates the one-sided copper clad laminate 12 in the thickness direction (see FIG. 12B). Semiconductor element 1
When the laminated plate 10B is laminated on the 0A, the alignment holes 68
The positioning can be performed by. As a result, the laminated plate 10B can be accurately laminated at a predetermined position on the semiconductor element 10A.

(3) Next, the copper foil 8 of the single-sided copper-clad laminate 12
The 0-side is protected with a heat release sheet 82 (for example, "Riva Alpha" (trademark) manufactured by Nitto Denko Corporation). The thermal release sheet 82 has a structure in which an adhesive layer containing a foaming agent is formed on one surface of a polyester film, for example, and the adhesive layer side is laminated with the copper foil 80 surface side (FIG. 12). (See (C)).

(4) Next, at a predetermined position of the single-sided copper-clad laminate 12, the surface on the adhesive layer 150 side (upper surface side in FIG. 12).
The through conductor opening 158 reaching the copper foil 80 from is formed. For example, laser irradiation is performed by a pulse oscillation type carbon dioxide gas laser processing device under the conditions of pulse energy of 2.0 to 10.0 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot number of 3 to 50, and the interlayer resin insulation layer 250. A through conductor opening 158 having an inner diameter of 100 μm is formed by the opening 157 and the opening 159 of the adhesive layer 150 (see FIG. 12D). Thereafter, the alignment hole 24 is sealed, and a dry desmear process is performed to remove the resin remaining inside the formed through conductor opening 158.
The dry desmear treatment can be performed by, for example, oxygen plasma discharge, corona discharge treatment, or the like.

In this embodiment, since the aramid fiber is used as the reinforcing material in the interlayer resin insulation layer 250 as the core material, it is easily melted and evaporated by the energy of the laser. As a result, the through conductor 160 can be formed freely without causing defective formation of the through conductor opening 158, so that the aspect ratio of the through conductor 160 can be increased.

Further, since the aramid fiber used for the interlayer resin insulation layer 250 has a value close to the linear thermal expansion coefficient of the wafer 20A made of silicon, the value of the interlayer insulation layer caused by the linear thermal expansion coefficient during heating is increased. Expansion and contraction can be suppressed. Thereby, the stress generated in the interlayer insulating layer can be relaxed.

(5) Next, the inside of the through-conductor opening 158 of the interlayer resin insulation layer 250 is roughened with permanganic acid to make the roughened surface 1
58α is formed (see FIG. 13A). The roughened surface is
It is desirable that the thickness is between 0.05 and 5 μm.

(6) Next, in the through conductor opening 158,
By the electroplating method using the copper foil 80 as one electrode, electrolytic plating is performed under the following conditions to form the through conductor 160 made of the electrolytic copper plating 156 (see FIG. 13B).
The filling amount of the electrolytic copper plating 156 is preferably such that the upper surface thereof is slightly lower than the surface of the insulating layer. In this embodiment, copper is used as the plating metal, but Sn, Ag,
Any metal that can be plated, such as Cu / Sn and Cu / Ag, may be used. The additive in the electrolytic plating solution is Caparaside HL manufactured by Atotech Japan.

[Electrolytic plating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Atotech Japan, Kaparaside HL) 19.5 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(7) Then, a roughened surface 160α is formed on the surface of the through conductor 160 with an etching solution containing a cupric complex and an organic acid (see FIG. 13C).

(8) After that, by printing a solder paste made of a low melting point material such as solder so as to overlap the through conductor 160 in the through conductor opening 158, the inside of the through conductor opening 158 is electrically conductive. The property bump 76 is filled. The conductive bump 76 is filled so as to slightly project from the upper surface of the adhesive layer 150. After that, the alignment hole 6
By removing the sealing of No. 8 and forming a through hole 82a communicating with the alignment hole 68 in the heat release sheet 82, the laminated plate 10B having the through conductor 160 can be obtained (FIG. 1).
3 (D)).

Since the conductive bumps 76 are filled so as to slightly project from the upper surface of the adhesive layer 150, when the laminated plate 10B is laminated on the semiconductor element 10A, the penetrating conductor 160 and the semiconductor element 10A are surely made. Connection with the upper conductor circuit 58 is made. Thereby, electrical connectivity can be improved.

For the solder paste, Sn / Pb, Sn / S
b, Sn / Ag, Sn / Ag / Cu, etc. can be used. Of course, a low α-ray type solder paste of radiation may be used.

Subsequently, the semiconductor element 10A and the laminated plate 10 are
The stacking process with B will be described with reference to FIGS. 14 to 16.

(1) Laminated board 10B (see FIG. 13D)
Is turned upside down and placed on the semiconductor element 10A (see FIG. 11D) (see FIG. 14A).

(2) Next, a positioning mark (not shown) and an alignment hole 68 provided on the semiconductor element 10A so that the conductive bump 76 can be connected to the conductor circuit 58.
And the laminated plate 10B is positioned by the semiconductor element 10A.
Lamination is performed at a predetermined position above (see FIG. 14B).

Since the adhesive layer 150 provided on the laminated board 10B of this embodiment is a semi-cured epoxy resin layer,
When laminating the laminated plate 10B on the semiconductor element 10A,
It is crushed while being sandwiched between the semiconductor element 10A and the laminated plate 10B, and can be easily adhered to the surface of the semiconductor element 10A. This serves as an adhesive layer,
The connectivity between the semiconductor element 10A and the laminated plate 10B can be improved. In addition, the through conductor 160 has the resin layer 150.
The conductive bump 76 and the conductor circuit 58,
Increase the connectivity with. Thereby, electrical connection can be improved.

Further, the conductive bumps 76 are formed on the adhesive layer 150.
Since it protrudes from the semiconductor element 10A, the laminated plate 1 is placed on the semiconductor element 10A.
When stacking 0B, the through conductor 160 and the conductor circuit 58 on the semiconductor element 10A can be reliably connected. Thereby, electrical connectivity can be improved.

(3) Subsequently, the adhesive layer 150 is cured by vacuum pressure lamination at a pressure of 5 kg / cm ² while raising the temperature to 50 to 150 ° C. As a result, the conductor circuit 58 and the laminated board 10B are adhered (see FIG. 1).
4 (C)). The degree of vacuum during vacuum pressure bonding is 10 mmHg
Is. In this embodiment, the vacuum pressure-bonding laminate is 50 to 1
It was carried out at 50 ° C. Here, the temperature of the vacuum compression lamination may be higher than the peeling temperature at which the heat release sheet 82 loses its adhesive force. Thereby, the thermal release sheet 82 can be easily released.

Individually formed semiconductor elements 10A,
Since the penetrating conductor 160 can be freely formed by stacking the laminated plates 10B together, the aspect ratio of the penetrating conductor 160 can be increased as compared with the conventional case.

(4) Next, the outermost copper foil 80 is pattern-etched to form a conductor circuit 81, and then the surface of the conductor circuit 81 is roughened with an etching solution containing a cupric complex and an organic acid. The converted surface 81α is formed (see FIG. 15A). The roughened surface is preferably between 0.05 and 5 μm.

(5) Next, a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.), which was dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight, was acrylated with 50% epoxy groups. Oligomer (molecular weight 4000) 46.67
15 parts by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., trade name: Epicoat 1001) of 80% by weight dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer which is a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604)
Similarly, polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
DPE6A) 1.5 parts by weight, dispersion type antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.71 parts by weight are put in a container, stirred and mixed to prepare a mixed composition, and this mixed composition To the composition, 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photogravimetric initiator and 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at 0 ° C. is obtained. The viscosity was measured with a B-type viscometer (DVL-B type manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm, rotor No. 4, and at 6 rpm, rotor No. 3.
According to

(6) Next, on the interlayer resin insulation layer 250,
The solder resist composition was applied to a thickness of 20 μm and dried under conditions of 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, and then a solder resist resist opening pattern having a thickness of 5 mm was drawn. A photomask is brought into close contact with the solder resist layer 70, exposed to ultraviolet rays of 1000 mJ / cm ² , and developed with a DMTG solution to give 200 μm.
An opening 71 having a diameter of m is formed (see FIG. 15B).
Alternatively, a commercially available solder resist may be used.

(7) Next, the semiconductor chip 10 having the solder resist layer (organic resin insulating layer) 70 formed thereon is treated with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphate (2. PH = 4.5 containing 8 × 10 ⁻¹ mol / l) and sodium citrate (1.6 × 10 ⁻¹ mol / l)
Then, the nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing it in the electroless nickel plating solution for 20 minutes.
Further, the substrate is replaced with potassium gold cyanide (7.6 × 1).
0 ^-3 mol / l), ammonium chloride (1.9 × 10 ^-1)
mol / l), sodium citrate (1.2 × 10 ^-1 m
ol / l), sodium hypophosphite (1.7 × 10 ⁻¹ m
ol / l) in an electroless plating solution at 80 ° C. 7.
Immerse for 5 minutes to form a 0.0
By forming the gold plating layer 74 of 3 μm, the through conductor 1
The solder pad 75 is formed on the substrate 60 (see FIG. 15C).

(8) Then, solder paste is printed on the openings 71 of the solder resist layer 70 and reflowed at 200 ° C. to form solder bumps 176.
As a result, the semiconductor chip 10 can be obtained (see FIG. 16).

For the solder paste, Sn / Pb, Sn / S
b, Sn / Ag, Sn / Ag / Cu, etc. can be used. Of course, a low α-ray type solder paste of radiation may be used.

In this embodiment, the semiconductor element 20 (see FIG. 3B) divided into individual pieces by dicing or the like is used as the starting material. Here, the semiconductor element 20 (see FIG. 3A) that is not divided into individual pieces may be used as a starting material, and after the semiconductor chip is formed, this semiconductor chip may be divided into individual pieces by dicing or the like.

By the above steps, the adhesive layer 150 and the through conductor 160 are not directly formed on the conductor circuit 58, but the semiconductor element 10A and the laminated plate 10B are separately formed in advance and are laminated together. is there. This allows
Since the penetrating conductor 160 can be freely formed, the aspect ratio of the penetrating conductor 160 can be increased as compared with the conventional case.

Further, since the through conductor 160 projects from the surface of the adhesive layer 150, when the laminated plate 10B is laminated on the semiconductor element 10A, the through conductor 160 and the conductor circuit 58 on the semiconductor element 10A are surely formed. And can be connected. Thereby, electrical connectivity can be improved.

Since the adhesive layer 150 provided on the laminated board 10B of this embodiment is a semi-cured epoxy resin layer,
When laminating the laminated plate 10B on the semiconductor element 10A,
It is crushed while being sandwiched between the semiconductor element 10A and the laminated plate 10B, and can be easily adhered to the surface of the semiconductor element 10A. This serves as an adhesive layer,
The connectivity between the semiconductor element 10A and the laminated plate 10B can be improved. In addition, the through conductor 160 has the resin layer 150.
Since it penetrates through the through conductor 160 and the semiconductor element 10
The connectivity with the conductor circuit 58 of A is increased. This allows
The electrical connection can be improved.

[Second Embodiment] Next, a semiconductor chip according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment, the conductor circuit 81 is formed on the through conductor 160.
Although the solder bumps 176 are provided with the solder bumps 176 interposed therebetween, in the second embodiment, the solder bumps 176 are directly disposed on the through conductors 160.

Further, in the above-described first embodiment, the wafer 2
An IC chip (see FIG. 3B) formed by arranging a die pad made of aluminum on 0A and arranging a transition layer made of two layers of a thin film layer 33 and a thickening layer 37 on the die pad is provided. The semiconductor chip 10 is formed by using. On the other hand, in the second embodiment, as shown in FIG. 17, a die pad made of copper is provided on the wafer 20A, and the first thin film layer 33, the second thin film layer 36, and the thickening layer 37 are formed on the die pad. IC chip having a transition layer having a three-layer structure (see FIG. 7B)
Is used to form the semiconductor chip 110. The manufacturing method of the semiconductor chip 110 according to the second embodiment is the same as that of the first embodiment described above, and thus the description thereof is omitted.

<Other Embodiments> The present invention is not limited to the embodiments described with reference to the above description and drawings.
For example, the following embodiments are also included in the technical scope of the present invention, and can be variously modified and implemented within the scope other than the following without departing from the gist.

In the above embodiment, the interlayer resin insulation layer 250 is made of aramid fibers impregnated with epoxy resin, but the invention is not limited to this. For example, those impregnated with polyimide resin or epoxy resin and other than epoxy resin may be used. Various combinations can be used, such as impregnating a composite with a liquid crystal polymer.

In this embodiment, the interlayer resin insulation layer 50 and the conductor circuit 58 are formed on the IC chip 20, and the laminated board 10B is laminated on the upper surface thereof. However, it is not always necessary to form the interlayer resin insulation layer 50, and the through conductor 160 may be directly connected onto the transition layer 38.
The laminated plate 10B may be laminated on the IC chip.

[Brief description of drawings]

1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first exemplary embodiment of the present invention.

2A, 2B, and 2C are manufacturing process diagrams of the semiconductor device according to the first embodiment.

3A and 3B are manufacturing process diagrams of the semiconductor device according to the first embodiment.

FIG. 4A is a plan view of a silicon wafer 20A according to the first embodiment, and FIG. 4B is a plan view of a semiconductor element that is divided into individual pieces.

5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the first embodiment.

6 (A), (B), and (C) are the second of the first embodiment.
It is a manufacturing process diagram of a semiconductor element according to the manufacturing method.

7A and 7B are manufacturing process diagrams of a semiconductor device according to a second manufacturing method of the first embodiment.

8A, 8B, 8C and 8D are manufacturing process diagrams of a semiconductor device according to a third manufacturing method of the first embodiment.

9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a fourth manufacturing method of the first embodiment.

10 (A), (B), (C), and (D) are manufacturing process diagrams of a semiconductor device including a conductor circuit according to the first embodiment of the present invention.

11 (A), (B), (C), and (D) are manufacturing process diagrams of a semiconductor device including a conductor circuit according to the first embodiment.

12 (A), (B), (C) and (D) are manufacturing process diagrams of an insulating layer including a through conductor and a conductor layer according to the first example.

13 (A), (B), (C), and (D) are manufacturing process diagrams of an insulating layer including a through conductor and a conductor layer according to the first example.

14A, 14B, and 14C are manufacturing process diagrams of the semiconductor chip according to the first example.

15A, 15B, and 15C are manufacturing process diagrams of the semiconductor chip according to the first example.

FIG. 16 is a cross-sectional view of the semiconductor chip according to the first example.

FIG. 17 is a sectional view of a semiconductor chip according to a second embodiment of the present invention.

[Explanation of symbols]

10 semiconductor chips 10A semiconductor element 10B laminated board 20 IC chip (semiconductor element) 20A wafer 22 Die pad 24 Protective film 33 thin film layer 36 thin film layers 37 Thick layer 38 transition layers 50 interlayer resin insulation layer 58 Conductor circuit 60 via holes 68 alignment holes 70 Solder resist layer 76 Solder paste 80 copper foil 82 Thermal release sheet 150 adhesive layer 160 through conductor 176 Solder bump 250 interlayer resin insulation layer

Claims (14)

[Claims] 1. A method of manufacturing a semiconductor chip, which is a semiconductor chip in which an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, and which includes at least the following steps (a) to (c): : (A) a step of forming a through hole at a predetermined position of the insulating substrate; (b) a step of filling the through hole with a conductive metal to form a through conductor; (c) a semiconductor element Stacking the insulating substrates. 2. The surface of the insulating substrate is provided with an uncured resin layer, and a conductor penetrating the resin layer is provided on the through conductor. A method of manufacturing a semiconductor chip according to. 3. The method of manufacturing a semiconductor chip according to claim 2, wherein the conductor is convexly projected from the surface of the resin layer. 4. The insulating substrate includes a core member made of a polymer.
2. The method for manufacturing a semiconductor chip according to any one of 1. 5. The method of manufacturing a semiconductor chip according to claim 4, wherein the core member is made of aramid fiber. 6. The semiconductor according to claim 1, wherein a transition layer is formed on the die pad of the semiconductor element, and the transition layer is at least two layers. Chip manufacturing method. 7. The lowermost layer of the transition layer is tin, chromium, titanium, nickel, zinc, cobalt, gold,
The method for manufacturing a semiconductor chip according to claim 6, wherein at least one kind selected from any of copper is laminated. 8. The method of manufacturing a semiconductor chip according to claim 6, wherein the uppermost layer of the transition layer is selected from nickel, copper, gold, silver, zinc, and iron. 9. A transition layer is formed on the die pad of the semiconductor device, and the transition layer comprises the first transition layer.
The method of manufacturing a semiconductor chip according to claim 1, wherein the method comprises a thin film layer, a second thin film layer, and a thickening layer. 10. The method of manufacturing a semiconductor chip according to claim 9, wherein the die pad is copper. 11. The first thin film layer of the transition layer is laminated with at least one selected from the group consisting of tin, chromium, titanium, nickel, zinc, cobalt, gold and copper. Item 11. A method of manufacturing a semiconductor chip according to item 9 or 10. 12. The semiconductor chip according to claim 9, wherein the second thin film layer of the transition layer is one or more kinds selected from nickel, copper, gold, and silver. Production method. 13. The thickening layer comprises nickel, copper, gold,
The method for manufacturing a semiconductor chip according to claim 9 or 10, wherein the method is one or more selected from silver, zinc, and iron. 14. A semiconductor chip in which an interlayer insulating layer and a conductor circuit are repeatedly formed on a semiconductor element, the insulating substrate having a through conductor formed by filling a through hole with a conductive metal, and a via. A semiconductor element having an interlayer resin insulation layer provided with holes and conductor circuits is laminated with a resin layer interposed, and the through conductor of the insulating substrate and the conductor circuit of the semiconductor element have plasticity. A semiconductor chip characterized by being connected via a conductor.