JP2002540628A5 - - Google Patents

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Publication number
JP2002540628A5
JP2002540628A5 JP2000608429A JP2000608429A JP2002540628A5 JP 2002540628 A5 JP2002540628 A5 JP 2002540628A5 JP 2000608429 A JP2000608429 A JP 2000608429A JP 2000608429 A JP2000608429 A JP 2000608429A JP 2002540628 A5 JP2002540628 A5 JP 2002540628A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000608429A
Other languages
Japanese (ja)
Other versions
JP2002540628A (ja
Filing date
Publication date
Priority claimed from US09/277,511 external-priority patent/US6417041B1/en
Application filed filed Critical
Publication of JP2002540628A publication Critical patent/JP2002540628A/ja
Publication of JP2002540628A5 publication Critical patent/JP2002540628A5/ja
Pending legal-status Critical Current

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JP2000608429A 1999-03-26 2000-02-29 低バッファ酸化膜を有する高誘電率の誘電スタックの製作方法 Pending JP2002540628A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/277,511 US6417041B1 (en) 1999-03-26 1999-03-26 Method for fabricating high permitivity dielectric stacks having low buffer oxide
US09/277,511 1999-03-26
PCT/US2000/005156 WO2000059023A1 (en) 1999-03-26 2000-02-29 Method for fabricating high permitivity dielectric stacks having low buffer oxide

Publications (2)

Publication Number Publication Date
JP2002540628A JP2002540628A (ja) 2002-11-26
JP2002540628A5 true JP2002540628A5 (de) 2007-03-08

Family

ID=23061192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000608429A Pending JP2002540628A (ja) 1999-03-26 2000-02-29 低バッファ酸化膜を有する高誘電率の誘電スタックの製作方法

Country Status (5)

Country Link
US (1) US6417041B1 (de)
EP (1) EP1173886A1 (de)
JP (1) JP2002540628A (de)
KR (1) KR20020012163A (de)
WO (1) WO2000059023A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095460B2 (en) 2001-02-26 2006-08-22 Samsung Electronics Co., Ltd. Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same
US6806145B2 (en) * 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US6800568B1 (en) 2002-07-02 2004-10-05 Advanced Micro Devices, Inc. Methods for the deposition of high-K films and high-K films produced thereby
EP2058844A1 (de) * 2007-10-30 2009-05-13 Interuniversitair Microelektronica Centrum (IMEC) Herstellungsverfahren für eine Halbleitervorrichtung
US9087716B2 (en) * 2013-07-15 2015-07-21 Globalfoundries Inc. Channel semiconductor alloy layer growth adjusted by impurity ion implantation
CN115132570B (zh) * 2022-09-01 2022-11-25 睿力集成电路有限公司 一种半导体结构的处理方法及装置

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US4698787A (en) 1984-11-21 1987-10-06 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4877641A (en) * 1988-05-31 1989-10-31 Olin Corporation Process for plasma depositing silicon nitride and silicon dioxide films onto a substrate
JPH0637079A (ja) * 1992-07-16 1994-02-10 Toshiba Corp 半導体装置及びその製造装置及びその製造方法
JP2786071B2 (ja) * 1993-02-17 1998-08-13 日本電気株式会社 半導体装置の製造方法
EP0637063B1 (de) 1993-07-30 1999-11-03 Applied Materials, Inc. Verfahren zur Ablagerung von Silzium-Nitrid auf Siliziumoberflächen
JPH0776781A (ja) * 1993-09-10 1995-03-20 Matsushita Electric Ind Co Ltd プラズマ気相成長装置
US5374586A (en) * 1993-09-27 1994-12-20 United Microelectronics Corporation Multi-LOCOS (local oxidation of silicon) isolation process
US5511026A (en) 1993-12-01 1996-04-23 Advanced Micro Devices, Inc. Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories
JPH07176627A (ja) * 1993-12-17 1995-07-14 Nec Corp 半導体装置の製造方法
JP2778451B2 (ja) * 1994-01-27 1998-07-23 日本電気株式会社 半導体装置の製造方法
US5608246A (en) * 1994-02-10 1997-03-04 Ramtron International Corporation Integration of high value capacitor with ferroelectric memory
US5470773A (en) 1994-04-25 1995-11-28 Advanced Micro Devices, Inc. Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch
JP3660391B2 (ja) * 1994-05-27 2005-06-15 株式会社東芝 半導体装置の製造方法
US5663088A (en) * 1995-05-19 1997-09-02 Micron Technology, Inc. Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer
US5786248A (en) * 1995-10-12 1998-07-28 Micron Technology, Inc. Semiconductor processing method of forming a tantalum oxide containing capacitor
US6004875A (en) * 1995-11-15 1999-12-21 Micron Technology, Inc. Etch stop for use in etching of silicon oxide
US5939333A (en) * 1996-05-30 1999-08-17 Micron Technology, Inc. Silicon nitride deposition method
US5824590A (en) * 1996-07-23 1998-10-20 Micron Technology, Inc. Method for oxidation and crystallization of ferroelectric material
JPH10229080A (ja) * 1996-12-10 1998-08-25 Sony Corp 酸化物の処理方法、アモルファス酸化膜の形成方法およびアモルファス酸化タンタル膜
US5834371A (en) * 1997-01-31 1998-11-10 Tokyo Electron Limited Method and apparatus for preparing and metallizing high aspect ratio silicon semiconductor device contacts to reduce the resistivity thereof
JP4283904B2 (ja) * 1997-07-11 2009-06-24 株式会社東芝 半導体装置の製造方法
FR2766211B1 (fr) 1997-07-15 1999-10-15 France Telecom PROCEDE DE DEPOT D'UNE COUCHE DIELECTRIQUE DE Ta2O5
US6020024A (en) * 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
KR100258979B1 (ko) * 1997-08-14 2000-06-15 윤종용 유전막을 수소 분위기에서 열처리하는 반도체장치의 커패시터 제조방법
US6077737A (en) * 1998-06-02 2000-06-20 Mosel Vitelic, Inc. Method for forming a DRAM having improved capacitor dielectric layers
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