JP2002533812A5 - - Google Patents
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- JP2002533812A5 JP2002533812A5 JP2000590061A JP2000590061A JP2002533812A5 JP 2002533812 A5 JP2002533812 A5 JP 2002533812A5 JP 2000590061 A JP2000590061 A JP 2000590061A JP 2000590061 A JP2000590061 A JP 2000590061A JP 2002533812 A5 JP2002533812 A5 JP 2002533812A5
- Authority
- JP
- Japan
- Prior art keywords
- node
- probe
- response
- data
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000523 sample Substances 0.000 description 33
- 230000005540 biological transmission Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/217,367 US6631401B1 (en) | 1998-12-21 | 1998-12-21 | Flexible probe/probe response routing for maintaining coherency |
| US09/217,367 | 1998-12-21 | ||
| PCT/US1999/019471 WO2000038069A1 (en) | 1998-12-21 | 1999-08-26 | Flexible probe/probe response routing for maintaining coherency |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002533812A JP2002533812A (ja) | 2002-10-08 |
| JP2002533812A5 true JP2002533812A5 (enExample) | 2006-09-14 |
| JP4712974B2 JP4712974B2 (ja) | 2011-06-29 |
Family
ID=22810782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000590061A Expired - Fee Related JP4712974B2 (ja) | 1998-12-21 | 1999-08-26 | コヒーレンシ維持のための柔軟なプローブ/プローブ応答経路制御 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6631401B1 (enExample) |
| EP (1) | EP1141839B1 (enExample) |
| JP (1) | JP4712974B2 (enExample) |
| KR (1) | KR100605142B1 (enExample) |
| BR (1) | BR9907499A (enExample) |
| DE (1) | DE69904758T2 (enExample) |
| WO (1) | WO2000038069A1 (enExample) |
Families Citing this family (70)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4718012B2 (ja) * | 1998-12-21 | 2011-07-06 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持 |
| US6370621B1 (en) | 1998-12-21 | 2002-04-09 | Advanced Micro Devices, Inc. | Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation |
| US6631401B1 (en) | 1998-12-21 | 2003-10-07 | Advanced Micro Devices, Inc. | Flexible probe/probe response routing for maintaining coherency |
| US7529799B2 (en) * | 1999-11-08 | 2009-05-05 | International Business Machines Corporation | Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system |
| US6757793B1 (en) * | 2000-03-29 | 2004-06-29 | Advanced Micro Devices, Inc. | Reducing probe traffic in multiprocessor systems using a victim record table |
| US20020082621A1 (en) | 2000-09-22 | 2002-06-27 | Schurr Marc O. | Methods and devices for folding and securing tissue |
| US6745272B2 (en) | 2001-04-04 | 2004-06-01 | Advanced Micro Devices, Inc. | System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system |
| US6574708B2 (en) * | 2001-05-18 | 2003-06-03 | Broadcom Corporation | Source controlled cache allocation |
| US7227870B2 (en) | 2001-11-20 | 2007-06-05 | Broadcom Corporation | Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams |
| US7206879B2 (en) * | 2001-11-20 | 2007-04-17 | Broadcom Corporation | Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems |
| US7752281B2 (en) | 2001-11-20 | 2010-07-06 | Broadcom Corporation | Bridges performing remote reads and writes as uncacheable coherent operations |
| US6748479B2 (en) | 2001-11-20 | 2004-06-08 | Broadcom Corporation | System having interfaces and switch that separates coherent and packet traffic |
| US7394823B2 (en) | 2001-11-20 | 2008-07-01 | Broadcom Corporation | System having configurable interfaces for flexible system configurations |
| US6912602B2 (en) | 2001-11-20 | 2005-06-28 | Broadcom Corporation | System having two or more packet interfaces, a switch, and a shared packet DMA circuit |
| US7653790B2 (en) * | 2002-05-13 | 2010-01-26 | Glasco David B | Methods and apparatus for responding to a request cluster |
| US7395379B2 (en) * | 2002-05-13 | 2008-07-01 | Newisys, Inc. | Methods and apparatus for responding to a request cluster |
| US7003631B2 (en) * | 2002-05-15 | 2006-02-21 | Broadcom Corporation | System having address-based intranode coherency and data-based internode coherency |
| US7266587B2 (en) | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
| US6993631B2 (en) | 2002-05-15 | 2006-01-31 | Broadcom Corporation | L2 cache maintaining local ownership of remote coherency blocks |
| US6965973B2 (en) | 2002-05-15 | 2005-11-15 | Broadcom Corporation | Remote line directory which covers subset of shareable CC-NUMA memory space |
| US7296121B2 (en) * | 2002-11-04 | 2007-11-13 | Newisys, Inc. | Reducing probe traffic in multiprocessor systems |
| US8185602B2 (en) | 2002-11-05 | 2012-05-22 | Newisys, Inc. | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters |
| US7155572B2 (en) * | 2003-01-27 | 2006-12-26 | Advanced Micro Devices, Inc. | Method and apparatus for injecting write data into a cache |
| EP1616260A2 (en) * | 2003-04-11 | 2006-01-18 | Sun Microsystems, Inc. | Multi-node system with global access states |
| US7334102B1 (en) | 2003-05-09 | 2008-02-19 | Advanced Micro Devices, Inc. | Apparatus and method for balanced spinlock support in NUMA systems |
| US7962696B2 (en) * | 2004-01-15 | 2011-06-14 | Hewlett-Packard Development Company, L.P. | System and method for updating owner predictors |
| US7240165B2 (en) * | 2004-01-15 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | System and method for providing parallel data requests |
| US7856534B2 (en) | 2004-01-15 | 2010-12-21 | Hewlett-Packard Development Company, L.P. | Transaction references for requests in a multi-processor network |
| US20050160238A1 (en) * | 2004-01-20 | 2005-07-21 | Steely Simon C.Jr. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
| US7395374B2 (en) * | 2004-01-20 | 2008-07-01 | Hewlett-Packard Company, L.P. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
| US7620696B2 (en) * | 2004-01-20 | 2009-11-17 | Hewlett-Packard Development Company, L.P. | System and method for conflict responses in a cache coherency protocol |
| US7769959B2 (en) * | 2004-01-20 | 2010-08-03 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration to memory |
| US7818391B2 (en) | 2004-01-20 | 2010-10-19 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration |
| US8145847B2 (en) * | 2004-01-20 | 2012-03-27 | Hewlett-Packard Development Company, L.P. | Cache coherency protocol with ordering points |
| US8090914B2 (en) * | 2004-01-20 | 2012-01-03 | Hewlett-Packard Development Company, L.P. | System and method for creating ordering points |
| US8176259B2 (en) * | 2004-01-20 | 2012-05-08 | Hewlett-Packard Development Company, L.P. | System and method for resolving transactions in a cache coherency protocol |
| US7143245B2 (en) * | 2004-01-20 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | System and method for read migratory optimization in a cache coherency protocol |
| US7177987B2 (en) * | 2004-01-20 | 2007-02-13 | Hewlett-Packard Development Company, L.P. | System and method for responses between different cache coherency protocols |
| US8468308B2 (en) * | 2004-01-20 | 2013-06-18 | Hewlett-Packard Development Company, L.P. | System and method for non-migratory requests in a cache coherency protocol |
| US7149852B2 (en) * | 2004-01-20 | 2006-12-12 | Hewlett Packard Development Company, Lp. | System and method for blocking data responses |
| US7350032B2 (en) | 2004-03-22 | 2008-03-25 | Sun Microsystems, Inc. | Cache coherency protocol including generic transient states |
| US20070186043A1 (en) * | 2004-07-23 | 2007-08-09 | Darel Emmot | System and method for managing cache access in a distributed system |
| US7296167B1 (en) | 2004-10-01 | 2007-11-13 | Advanced Micro Devices, Inc. | Combined system responses in a chip multiprocessor |
| US8254411B2 (en) * | 2005-02-10 | 2012-08-28 | International Business Machines Corporation | Data processing system, method and interconnect fabric having a flow governor |
| US7619982B2 (en) * | 2005-04-25 | 2009-11-17 | Cisco Technology, Inc. | Active probe path management |
| US7398360B2 (en) * | 2005-08-17 | 2008-07-08 | Sun Microsystems, Inc. | Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors |
| US7529894B2 (en) * | 2005-08-17 | 2009-05-05 | Sun Microsystems, Inc. | Use of FBDIMM channel as memory channel and coherence channel |
| US7353340B2 (en) * | 2005-08-17 | 2008-04-01 | Sun Microsystems, Inc. | Multiple independent coherence planes for maintaining coherency |
| JP4572169B2 (ja) * | 2006-01-26 | 2010-10-27 | エヌイーシーコンピュータテクノ株式会社 | マルチプロセッサシステム及びその動作方法 |
| US7721050B2 (en) * | 2006-06-30 | 2010-05-18 | Intel Corporation | Re-snoop for conflict resolution in a cache coherency protocol |
| US7536515B2 (en) | 2006-06-30 | 2009-05-19 | Intel Corporation | Repeated conflict acknowledgements in a cache coherency protocol |
| US7506108B2 (en) * | 2006-06-30 | 2009-03-17 | Intel Corporation | Requester-generated forward for late conflicts in a cache coherency protocol |
| US7640401B2 (en) | 2007-03-26 | 2009-12-29 | Advanced Micro Devices, Inc. | Remote hit predictor |
| US20080298246A1 (en) * | 2007-06-01 | 2008-12-04 | Hughes William A | Multiple Link Traffic Distribution |
| US20080320233A1 (en) * | 2007-06-22 | 2008-12-25 | Mips Technologies Inc. | Reduced Handling of Writeback Data |
| US7769957B2 (en) * | 2007-06-22 | 2010-08-03 | Mips Technologies, Inc. | Preventing writeback race in multiple core processors |
| US7992209B1 (en) | 2007-07-19 | 2011-08-02 | Owl Computing Technologies, Inc. | Bilateral communication using multiple one-way data links |
| JP5283128B2 (ja) * | 2009-12-16 | 2013-09-04 | 学校法人早稲田大学 | プロセッサによって実行可能なコードの生成方法、記憶領域の管理方法及びコード生成プログラム |
| US20120054439A1 (en) * | 2010-08-24 | 2012-03-01 | Walker William L | Method and apparatus for allocating cache bandwidth to multiple processors |
| US10268583B2 (en) | 2012-10-22 | 2019-04-23 | Intel Corporation | High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier |
| US9952975B2 (en) * | 2013-04-30 | 2018-04-24 | Hewlett Packard Enterprise Development Lp | Memory network to route memory traffic and I/O traffic |
| US11159636B2 (en) | 2017-02-08 | 2021-10-26 | Arm Limited | Forwarding responses to snoop requests |
| US10747298B2 (en) | 2017-11-29 | 2020-08-18 | Advanced Micro Devices, Inc. | Dynamic interrupt rate control in computing system |
| US10503648B2 (en) | 2017-12-12 | 2019-12-10 | Advanced Micro Devices, Inc. | Cache to cache data transfer acceleration techniques |
| US10776282B2 (en) | 2017-12-15 | 2020-09-15 | Advanced Micro Devices, Inc. | Home agent based cache transfer acceleration scheme |
| US10917198B2 (en) * | 2018-05-03 | 2021-02-09 | Arm Limited | Transfer protocol in a data processing network |
| US11210246B2 (en) | 2018-08-24 | 2021-12-28 | Advanced Micro Devices, Inc. | Probe interrupt delivery |
| US12167102B2 (en) | 2018-09-21 | 2024-12-10 | Advanced Micro Devices, Inc. | Multicast in the probe channel |
| US12332795B2 (en) | 2022-04-12 | 2025-06-17 | Advanced Micro Devices, Inc. | Reducing probe filter accesses for processing in memory requests |
| US12450182B2 (en) * | 2022-11-14 | 2025-10-21 | Faisal A. Qureshi | Distributed queue multi-bus on multi-CPU chips |
Family Cites Families (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02205963A (ja) | 1989-01-27 | 1990-08-15 | Digital Equip Corp <Dec> | 読取中断処理 |
| EP0412353A3 (en) | 1989-08-11 | 1992-05-27 | Hitachi, Ltd. | Multiprocessor cache system having three states for generating invalidating signals upon write accesses |
| US5303362A (en) | 1991-03-20 | 1994-04-12 | Digital Equipment Corporation | Coupled memory multiprocessor computer system including cache coherency management protocols |
| US5412788A (en) * | 1992-04-16 | 1995-05-02 | Digital Equipment Corporation | Memory bank management and arbitration in multiprocessor computer system |
| US5590307A (en) | 1993-01-05 | 1996-12-31 | Sgs-Thomson Microelectronics, Inc. | Dual-port data cache memory |
| JP2819982B2 (ja) * | 1993-03-18 | 1998-11-05 | 株式会社日立製作所 | 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム |
| US6049851A (en) | 1994-02-14 | 2000-04-11 | Hewlett-Packard Company | Method and apparatus for checking cache coherency in a computer architecture |
| JPH0816474A (ja) * | 1994-06-29 | 1996-01-19 | Hitachi Ltd | マルチプロセッサシステム |
| US5537575A (en) | 1994-06-30 | 1996-07-16 | Foley; Denis | System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information |
| US5655140A (en) | 1994-07-22 | 1997-08-05 | Network Peripherals | Apparatus for translating frames of data transferred between heterogeneous local area networks |
| US5517494A (en) * | 1994-09-30 | 1996-05-14 | Apple Computer, Inc. | Method and system of multicast routing for groups with a single transmitter |
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| JP3872118B2 (ja) * | 1995-03-20 | 2007-01-24 | 富士通株式会社 | キャッシュコヒーレンス装置 |
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| US5673413A (en) | 1995-12-15 | 1997-09-30 | International Business Machines Corporation | Method and apparatus for coherency reporting in a multiprocessing system |
| US5893144A (en) | 1995-12-22 | 1999-04-06 | Sun Microsystems, Inc. | Hybrid NUMA COMA caching system and methods for selecting between the caching modes |
| US6038644A (en) | 1996-03-19 | 2000-03-14 | Hitachi, Ltd. | Multiprocessor system with partial broadcast capability of a cache coherent processing request |
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| US5878268A (en) | 1996-07-01 | 1999-03-02 | Sun Microsystems, Inc. | Multiprocessing system configured to store coherency state within multiple subnodes of a processing node |
| US5749095A (en) | 1996-07-01 | 1998-05-05 | Sun Microsystems, Inc. | Multiprocessing system configured to perform efficient write operations |
| US5859983A (en) | 1996-07-01 | 1999-01-12 | Sun Microsystems, Inc | Non-hypercube interconnection subsystem having a subset of nodes interconnected using polygonal topology and other nodes connect to the nodes in the subset |
| US5991819A (en) | 1996-12-03 | 1999-11-23 | Intel Corporation | Dual-ported memory controller which maintains cache coherency using a memory line status table |
| US5924118A (en) | 1997-04-14 | 1999-07-13 | International Business Machines Corporation | Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system |
| US6018791A (en) | 1997-04-14 | 2000-01-25 | International Business Machines Corporation | Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states |
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| US6112281A (en) * | 1997-10-07 | 2000-08-29 | Oracle Corporation | I/O forwarding in a cache coherent shared disk computer system |
| US6209065B1 (en) | 1997-10-24 | 2001-03-27 | Compaq Computer Corporation | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system |
| US6101420A (en) | 1997-10-24 | 2000-08-08 | Compaq Computer Corporation | Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories |
| US6085263A (en) | 1997-10-24 | 2000-07-04 | Compaq Computer Corp. | Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor |
| US6108737A (en) | 1997-10-24 | 2000-08-22 | Compaq Computer Corporation | Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system |
| US6085294A (en) | 1997-10-24 | 2000-07-04 | Compaq Computer Corporation | Distributed data dependency stall mechanism |
| US6108752A (en) | 1997-10-24 | 2000-08-22 | Compaq Computer Corporation | Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency |
| US6070231A (en) * | 1997-12-02 | 2000-05-30 | Intel Corporation | Method and apparatus for processing memory requests that require coherency transactions |
| US6292705B1 (en) | 1998-09-29 | 2001-09-18 | Conexant Systems, Inc. | Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system |
| US6012127A (en) | 1997-12-12 | 2000-01-04 | Intel Corporation | Multiprocessor computing apparatus with optional coherency directory |
| US6138218A (en) | 1998-02-17 | 2000-10-24 | International Business Machines Corporation | Forward progress on retried snoop hits by altering the coherency state of a local cache |
| US6098115A (en) | 1998-04-08 | 2000-08-01 | International Business Machines Corporation | System for reducing storage access latency with accessing main storage and data bus simultaneously |
| US6286090B1 (en) | 1998-05-26 | 2001-09-04 | Compaq Computer Corporation | Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches |
| US6199153B1 (en) | 1998-06-18 | 2001-03-06 | Digital Equipment Corporation | Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements |
| US6295583B1 (en) * | 1998-06-18 | 2001-09-25 | Compaq Information Technologies Group, L.P. | Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering |
| JP4718012B2 (ja) * | 1998-12-21 | 2011-07-06 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | メモリキャンセルメッセージを用いたシステムメモリ帯域幅の節約およびキャッシュコヒーレンシ維持 |
| US6275905B1 (en) * | 1998-12-21 | 2001-08-14 | Advanced Micro Devices, Inc. | Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system |
| US6370621B1 (en) | 1998-12-21 | 2002-04-09 | Advanced Micro Devices, Inc. | Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation |
| US6631401B1 (en) | 1998-12-21 | 2003-10-07 | Advanced Micro Devices, Inc. | Flexible probe/probe response routing for maintaining coherency |
-
1998
- 1998-12-21 US US09/217,367 patent/US6631401B1/en not_active Expired - Lifetime
-
1999
- 1999-08-26 DE DE69904758T patent/DE69904758T2/de not_active Expired - Lifetime
- 1999-08-26 KR KR1020017007739A patent/KR100605142B1/ko not_active Expired - Fee Related
- 1999-08-26 JP JP2000590061A patent/JP4712974B2/ja not_active Expired - Fee Related
- 1999-08-26 EP EP99946646A patent/EP1141839B1/en not_active Expired - Lifetime
- 1999-08-26 WO PCT/US1999/019471 patent/WO2000038069A1/en not_active Ceased
- 1999-12-17 BR BR9907499-0A patent/BR9907499A/pt not_active IP Right Cessation
-
2003
- 2003-07-28 US US10/628,715 patent/US7296122B2/en not_active Expired - Fee Related
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