DE69904758T2 - Flexible sondierungsbefehl/sondierungrespons-leitweglenkung zur aufrechterhaltung der speicherkohärenz - Google Patents
Flexible sondierungsbefehl/sondierungrespons-leitweglenkung zur aufrechterhaltung der speicherkohärenzInfo
- Publication number
- DE69904758T2 DE69904758T2 DE69904758T DE69904758T DE69904758T2 DE 69904758 T2 DE69904758 T2 DE 69904758T2 DE 69904758 T DE69904758 T DE 69904758T DE 69904758 T DE69904758 T DE 69904758T DE 69904758 T2 DE69904758 T2 DE 69904758T2
- Authority
- DE
- Germany
- Prior art keywords
- respons
- sounding
- guide
- maintain storage
- flexible sanding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
- G06F2212/254—Distributed memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Noise Elimination (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/217,367 US6631401B1 (en) | 1998-12-21 | 1998-12-21 | Flexible probe/probe response routing for maintaining coherency |
PCT/US1999/019471 WO2000038069A1 (en) | 1998-12-21 | 1999-08-26 | Flexible probe/probe response routing for maintaining coherency |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69904758D1 DE69904758D1 (de) | 2003-02-06 |
DE69904758T2 true DE69904758T2 (de) | 2003-10-16 |
Family
ID=22810782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69904758T Expired - Lifetime DE69904758T2 (de) | 1998-12-21 | 1999-08-26 | Flexible sondierungsbefehl/sondierungrespons-leitweglenkung zur aufrechterhaltung der speicherkohärenz |
Country Status (7)
Country | Link |
---|---|
US (2) | US6631401B1 (de) |
EP (1) | EP1141839B1 (de) |
JP (1) | JP4712974B2 (de) |
KR (1) | KR100605142B1 (de) |
BR (1) | BR9907499A (de) |
DE (1) | DE69904758T2 (de) |
WO (1) | WO2000038069A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005029428B4 (de) * | 2004-07-23 | 2013-08-08 | Hewlett-Packard Development Co., L.P. | System und Verfahren zum Verwalten eines Cachezugriffs in einem verteilten System |
Families Citing this family (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6631401B1 (en) | 1998-12-21 | 2003-10-07 | Advanced Micro Devices, Inc. | Flexible probe/probe response routing for maintaining coherency |
EP2320322A3 (de) * | 1998-12-21 | 2011-08-03 | Advanced Micro Devices, Inc. | Einsparung der Systemspeicherbandbreite und Aufrechterhaltung der Cachespeicherkohärenz mit Speicherannulierungsnachrichten |
US6370621B1 (en) | 1998-12-21 | 2002-04-09 | Advanced Micro Devices, Inc. | Memory cancel response optionally cancelling memory controller's providing of data in response to a read operation |
US7529799B2 (en) * | 1999-11-08 | 2009-05-05 | International Business Machines Corporation | Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system |
US6757793B1 (en) * | 2000-03-29 | 2004-06-29 | Advanced Micro Devices, Inc. | Reducing probe traffic in multiprocessor systems using a victim record table |
US20020082621A1 (en) | 2000-09-22 | 2002-06-27 | Schurr Marc O. | Methods and devices for folding and securing tissue |
US6745272B2 (en) | 2001-04-04 | 2004-06-01 | Advanced Micro Devices, Inc. | System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system |
US6574708B2 (en) * | 2001-05-18 | 2003-06-03 | Broadcom Corporation | Source controlled cache allocation |
US6748479B2 (en) | 2001-11-20 | 2004-06-08 | Broadcom Corporation | System having interfaces and switch that separates coherent and packet traffic |
US7394823B2 (en) | 2001-11-20 | 2008-07-01 | Broadcom Corporation | System having configurable interfaces for flexible system configurations |
US7752281B2 (en) | 2001-11-20 | 2010-07-06 | Broadcom Corporation | Bridges performing remote reads and writes as uncacheable coherent operations |
US6912602B2 (en) | 2001-11-20 | 2005-06-28 | Broadcom Corporation | System having two or more packet interfaces, a switch, and a shared packet DMA circuit |
US7227870B2 (en) | 2001-11-20 | 2007-06-05 | Broadcom Corporation | Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams |
US7206879B2 (en) | 2001-11-20 | 2007-04-17 | Broadcom Corporation | Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems |
US7395379B2 (en) * | 2002-05-13 | 2008-07-01 | Newisys, Inc. | Methods and apparatus for responding to a request cluster |
US7653790B2 (en) * | 2002-05-13 | 2010-01-26 | Glasco David B | Methods and apparatus for responding to a request cluster |
US6965973B2 (en) | 2002-05-15 | 2005-11-15 | Broadcom Corporation | Remote line directory which covers subset of shareable CC-NUMA memory space |
US7003631B2 (en) * | 2002-05-15 | 2006-02-21 | Broadcom Corporation | System having address-based intranode coherency and data-based internode coherency |
US6993631B2 (en) | 2002-05-15 | 2006-01-31 | Broadcom Corporation | L2 cache maintaining local ownership of remote coherency blocks |
US7266587B2 (en) | 2002-05-15 | 2007-09-04 | Broadcom Corporation | System having interfaces, switch, and memory bridge for CC-NUMA operation |
US7296121B2 (en) * | 2002-11-04 | 2007-11-13 | Newisys, Inc. | Reducing probe traffic in multiprocessor systems |
US8185602B2 (en) | 2002-11-05 | 2012-05-22 | Newisys, Inc. | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters |
US7155572B2 (en) * | 2003-01-27 | 2006-12-26 | Advanced Micro Devices, Inc. | Method and apparatus for injecting write data into a cache |
EP1616260A2 (de) * | 2003-04-11 | 2006-01-18 | Sun Microsystems, Inc. | Mehrknotensystem mit globalen zugangszuständen |
US7334102B1 (en) | 2003-05-09 | 2008-02-19 | Advanced Micro Devices, Inc. | Apparatus and method for balanced spinlock support in NUMA systems |
US7240165B2 (en) * | 2004-01-15 | 2007-07-03 | Hewlett-Packard Development Company, L.P. | System and method for providing parallel data requests |
US7856534B2 (en) | 2004-01-15 | 2010-12-21 | Hewlett-Packard Development Company, L.P. | Transaction references for requests in a multi-processor network |
US7962696B2 (en) * | 2004-01-15 | 2011-06-14 | Hewlett-Packard Development Company, L.P. | System and method for updating owner predictors |
US7818391B2 (en) | 2004-01-20 | 2010-10-19 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration |
US7769959B2 (en) * | 2004-01-20 | 2010-08-03 | Hewlett-Packard Development Company, L.P. | System and method to facilitate ordering point migration to memory |
US20050160238A1 (en) * | 2004-01-20 | 2005-07-21 | Steely Simon C.Jr. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
US8145847B2 (en) * | 2004-01-20 | 2012-03-27 | Hewlett-Packard Development Company, L.P. | Cache coherency protocol with ordering points |
US7395374B2 (en) * | 2004-01-20 | 2008-07-01 | Hewlett-Packard Company, L.P. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
US7177987B2 (en) * | 2004-01-20 | 2007-02-13 | Hewlett-Packard Development Company, L.P. | System and method for responses between different cache coherency protocols |
US8468308B2 (en) * | 2004-01-20 | 2013-06-18 | Hewlett-Packard Development Company, L.P. | System and method for non-migratory requests in a cache coherency protocol |
US7143245B2 (en) * | 2004-01-20 | 2006-11-28 | Hewlett-Packard Development Company, L.P. | System and method for read migratory optimization in a cache coherency protocol |
US7149852B2 (en) * | 2004-01-20 | 2006-12-12 | Hewlett Packard Development Company, Lp. | System and method for blocking data responses |
US8176259B2 (en) * | 2004-01-20 | 2012-05-08 | Hewlett-Packard Development Company, L.P. | System and method for resolving transactions in a cache coherency protocol |
US8090914B2 (en) * | 2004-01-20 | 2012-01-03 | Hewlett-Packard Development Company, L.P. | System and method for creating ordering points |
US7620696B2 (en) * | 2004-01-20 | 2009-11-17 | Hewlett-Packard Development Company, L.P. | System and method for conflict responses in a cache coherency protocol |
US7350032B2 (en) | 2004-03-22 | 2008-03-25 | Sun Microsystems, Inc. | Cache coherency protocol including generic transient states |
US7296167B1 (en) | 2004-10-01 | 2007-11-13 | Advanced Micro Devices, Inc. | Combined system responses in a chip multiprocessor |
US8254411B2 (en) * | 2005-02-10 | 2012-08-28 | International Business Machines Corporation | Data processing system, method and interconnect fabric having a flow governor |
US7619982B2 (en) * | 2005-04-25 | 2009-11-17 | Cisco Technology, Inc. | Active probe path management |
US7398360B2 (en) * | 2005-08-17 | 2008-07-08 | Sun Microsystems, Inc. | Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors |
US7529894B2 (en) * | 2005-08-17 | 2009-05-05 | Sun Microsystems, Inc. | Use of FBDIMM channel as memory channel and coherence channel |
US7353340B2 (en) * | 2005-08-17 | 2008-04-01 | Sun Microsystems, Inc. | Multiple independent coherence planes for maintaining coherency |
JP4572169B2 (ja) * | 2006-01-26 | 2010-10-27 | エヌイーシーコンピュータテクノ株式会社 | マルチプロセッサシステム及びその動作方法 |
US7506108B2 (en) * | 2006-06-30 | 2009-03-17 | Intel Corporation | Requester-generated forward for late conflicts in a cache coherency protocol |
US7536515B2 (en) * | 2006-06-30 | 2009-05-19 | Intel Corporation | Repeated conflict acknowledgements in a cache coherency protocol |
US7721050B2 (en) * | 2006-06-30 | 2010-05-18 | Intel Corporation | Re-snoop for conflict resolution in a cache coherency protocol |
US7640401B2 (en) | 2007-03-26 | 2009-12-29 | Advanced Micro Devices, Inc. | Remote hit predictor |
US20080298246A1 (en) * | 2007-06-01 | 2008-12-04 | Hughes William A | Multiple Link Traffic Distribution |
US20080320233A1 (en) * | 2007-06-22 | 2008-12-25 | Mips Technologies Inc. | Reduced Handling of Writeback Data |
US7769957B2 (en) * | 2007-06-22 | 2010-08-03 | Mips Technologies, Inc. | Preventing writeback race in multiple core processors |
US7992209B1 (en) | 2007-07-19 | 2011-08-02 | Owl Computing Technologies, Inc. | Bilateral communication using multiple one-way data links |
JP5283128B2 (ja) * | 2009-12-16 | 2013-09-04 | 学校法人早稲田大学 | プロセッサによって実行可能なコードの生成方法、記憶領域の管理方法及びコード生成プログラム |
US20120054439A1 (en) * | 2010-08-24 | 2012-03-01 | Walker William L | Method and apparatus for allocating cache bandwidth to multiple processors |
US10268583B2 (en) | 2012-10-22 | 2019-04-23 | Intel Corporation | High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier |
US9952975B2 (en) * | 2013-04-30 | 2018-04-24 | Hewlett Packard Enterprise Development Lp | Memory network to route memory traffic and I/O traffic |
US11159636B2 (en) | 2017-02-08 | 2021-10-26 | Arm Limited | Forwarding responses to snoop requests |
US10747298B2 (en) | 2017-11-29 | 2020-08-18 | Advanced Micro Devices, Inc. | Dynamic interrupt rate control in computing system |
US10503648B2 (en) | 2017-12-12 | 2019-12-10 | Advanced Micro Devices, Inc. | Cache to cache data transfer acceleration techniques |
US10776282B2 (en) | 2017-12-15 | 2020-09-15 | Advanced Micro Devices, Inc. | Home agent based cache transfer acceleration scheme |
US10917198B2 (en) * | 2018-05-03 | 2021-02-09 | Arm Limited | Transfer protocol in a data processing network |
US11210246B2 (en) | 2018-08-24 | 2021-12-28 | Advanced Micro Devices, Inc. | Probe interrupt delivery |
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JPH02205963A (ja) | 1989-01-27 | 1990-08-15 | Digital Equip Corp <Dec> | 読取中断処理 |
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EP2320322A3 (de) * | 1998-12-21 | 2011-08-03 | Advanced Micro Devices, Inc. | Einsparung der Systemspeicherbandbreite und Aufrechterhaltung der Cachespeicherkohärenz mit Speicherannulierungsnachrichten |
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-
1998
- 1998-12-21 US US09/217,367 patent/US6631401B1/en not_active Expired - Lifetime
-
1999
- 1999-08-26 WO PCT/US1999/019471 patent/WO2000038069A1/en active IP Right Grant
- 1999-08-26 KR KR1020017007739A patent/KR100605142B1/ko not_active IP Right Cessation
- 1999-08-26 EP EP99946646A patent/EP1141839B1/de not_active Expired - Lifetime
- 1999-08-26 DE DE69904758T patent/DE69904758T2/de not_active Expired - Lifetime
- 1999-08-26 JP JP2000590061A patent/JP4712974B2/ja not_active Expired - Fee Related
- 1999-12-17 BR BR9907499-0A patent/BR9907499A/pt not_active IP Right Cessation
-
2003
- 2003-07-28 US US10/628,715 patent/US7296122B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005029428B4 (de) * | 2004-07-23 | 2013-08-08 | Hewlett-Packard Development Co., L.P. | System und Verfahren zum Verwalten eines Cachezugriffs in einem verteilten System |
Also Published As
Publication number | Publication date |
---|---|
US7296122B2 (en) | 2007-11-13 |
BR9907499A (pt) | 2000-10-03 |
KR100605142B1 (ko) | 2006-07-28 |
JP4712974B2 (ja) | 2011-06-29 |
KR20010082373A (ko) | 2001-08-29 |
WO2000038069A1 (en) | 2000-06-29 |
EP1141839A1 (de) | 2001-10-10 |
EP1141839B1 (de) | 2003-01-02 |
US6631401B1 (en) | 2003-10-07 |
DE69904758D1 (de) | 2003-02-06 |
JP2002533812A (ja) | 2002-10-08 |
US20040024836A1 (en) | 2004-02-05 |
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