JP2002368010A - Manufacturing method of thin-film transistor - Google Patents

Manufacturing method of thin-film transistor

Info

Publication number
JP2002368010A
JP2002368010A JP2001170028A JP2001170028A JP2002368010A JP 2002368010 A JP2002368010 A JP 2002368010A JP 2001170028 A JP2001170028 A JP 2001170028A JP 2001170028 A JP2001170028 A JP 2001170028A JP 2002368010 A JP2002368010 A JP 2002368010A
Authority
JP
Japan
Prior art keywords
film
amorphous silicon
silicon film
thin
hydrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001170028A
Other languages
Japanese (ja)
Inventor
Takashi Yamamoto
貴史 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001170028A priority Critical patent/JP2002368010A/en
Publication of JP2002368010A publication Critical patent/JP2002368010A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To form a thin oxide film on the surface, and to prevent contaminants from adhering to a silicon film by carrying out annealing in oxidation atmosphere in a hydrogenation process after amorphous silicon is deposited. SOLUTION: In the manufacturing method of a thin-film transistor where an amorphous silicon film 21 is formed on a glass substrate 11, hydrogen in the amorphous silicon film is separated, the amorphous silicon film is machined to a polycrystalline silicon film 13, island-like polycrystalline silicon films 13a, 13b, and 13c are formed, a gate electrode 15 is formed, impurities are injected to the island-like polycrystalline silicon film, and the impurities are activated, the amorphous silicon film 21 is deposited to form a silicon oxide film 22 when the hydrogen contained in the amorphous silicon film 21 is separated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ガラス基板上に形
成された絶縁膜上に設けられた薄膜トランジスタ(TF
T)、またはそれらを応用した薄膜集積回路、特にアク
ティブ型液晶表示装置(液晶ディスプレー)用薄膜集積
回路の作製方法に関するものである。
The present invention relates to a thin film transistor (TF) provided on an insulating film formed on a glass substrate.
T) or a method of manufacturing a thin film integrated circuit using the same, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

【0002】[0002]

【従来の技術】近年、ガラス等の絶縁基板上に薄膜トラ
ンジスタを有する半導体装置、例えば、薄膜トランジス
タを画素の駆動に用いるアクティブ型液晶表示装置が開
発されている。これらの装置に用いられる薄膜トランジ
スタには、薄膜状のシリコン半導体を用いるのが一般的
である。薄膜状のシリコン半導体の中で、結晶性を有す
る多結晶シリコンからなるものがあり、この多結晶シリ
コン薄膜トランジスタは非晶質シリコン薄膜トランジス
タに比べて電子移動度が2桁以上大きく、素子の微細化
や駆動回路を同一基板上に集積可能である等の利点を有
している。近年液晶表示装置の分野ではこの多結晶シリ
コン薄膜トランジスタを用いた駆動回路内蔵型薄膜トラ
ンジスタアレイを安価で大面積化が容易なガラス基板上
に作製する技術の開発が活発であり実用化が始まってい
る。
2. Description of the Related Art In recent years, a semiconductor device having a thin film transistor on an insulating substrate such as glass, for example, an active liquid crystal display device using the thin film transistor for driving pixels has been developed. In general, a thin film silicon semiconductor is used for a thin film transistor used in these devices. Among thin-film silicon semiconductors, there is a thin-film silicon semiconductor that is made of polycrystalline silicon having crystallinity. The polycrystalline silicon thin-film transistor has an electron mobility that is at least two orders of magnitude higher than that of an amorphous silicon thin-film transistor. It has an advantage that the driving circuit can be integrated on the same substrate. In recent years, in the field of liquid crystal display devices, technology for manufacturing a thin film transistor array with a built-in drive circuit using a polycrystalline silicon thin film transistor on a glass substrate that is inexpensive and easy to increase in area has been actively developed, and practical use has begun.

【0003】従来の液晶表示装置に用いられるアクティ
ブマトリックスアレイ用薄膜トランジスタの製造方法を
図面を用いて説明する。まず図5(a)に示すようにガラ
ス基板11にプラズマCVD法にてバッファー層12と
なる酸化シリコン膜を形成する。その後、前記酸化シリ
コン薄膜を形成したガラス基板を大気中に取り出すこと
なくプラズマCVD法にて非晶質シリコン(a-Si)21を
堆積する。ついでa-Si膜中の水素を低減するために窒素
雰囲気下で400〜450℃、60分程度の熱処理を行った後、
エキシマレーザーを用いたアニールにてa-Si膜を多結晶
化し多結晶シリコン(poly-Si)膜13を形成する。こ
のときエキシマレーザーは波長308nmのXeClエキシマレ
ーザーを用いる。次に図5(b)に示すように、poly-S
i膜を所望の形状に加工した後、フォトレジスト22に
て不純物注入用のマスクを形成しソースおよびドレイン
領域13cに不純物(燐イオン)を注入する。次に、ゲ
ート絶縁膜14となる酸化シリコン膜を形成する。その
後、ゲート電極15を形成し薄膜トランジスタに低濃度
不純物注入(LDD)領域13bを形成するため不純物(燐
イオン)を注入する。不純物が注入されていない領域1
3aは真性多結晶シリコンであり、チャネル領域とな
る。次に、図5(c)に示すように、層間絶縁膜となる
酸化シリコン膜16を形成した後、注入した不純物の活
性化を、減圧窒素雰囲気下で500〜600℃の温度でアニー
ルを施すことにより行う。次に、ソースおよびドレイン
領域上の絶縁膜にコンタクトホールを開口し、配線1
7,18を形成する。最後に窒化シリコンからなる保護
絶縁膜19を形成し、水素雰囲気でのアニールを行うこ
とで、多結晶シリコン薄膜中の未結合手を水素にて補償
し特性を向上させ薄膜トランジスタが完成する。
A method for manufacturing a thin film transistor for an active matrix array used in a conventional liquid crystal display device will be described with reference to the drawings. First, as shown in FIG. 5A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11 by a plasma CVD method. Thereafter, amorphous silicon (a-Si) 21 is deposited by a plasma CVD method without taking the glass substrate on which the silicon oxide thin film is formed into the atmosphere. Then, after performing a heat treatment of about 400 to 450 ° C. for about 60 minutes in a nitrogen atmosphere to reduce hydrogen in the a-Si film,
The a-Si film is polycrystallized by annealing using an excimer laser to form a polycrystalline silicon (poly-Si) film 13. At this time, an XeCl excimer laser having a wavelength of 308 nm is used as the excimer laser. Next, as shown in FIG.
After processing the i-film into a desired shape, a mask for impurity implantation is formed with the photoresist 22, and impurities (phosphorous ions) are implanted into the source and drain regions 13c. Next, a silicon oxide film to be the gate insulating film 14 is formed. Thereafter, an impurity (phosphorus ion) is implanted to form the gate electrode 15 and to form the low concentration impurity implantation (LDD) region 13b in the thin film transistor. Region 1 in which impurities are not implanted
Reference numeral 3a denotes intrinsic polycrystalline silicon, which becomes a channel region. Next, as shown in FIG. 5C, after forming a silicon oxide film 16 serving as an interlayer insulating film, annealing of the implanted impurities is performed at a temperature of 500 to 600 ° C. in a reduced-pressure nitrogen atmosphere. It is done by doing. Next, a contact hole is opened in the insulating film on the source and drain regions, and a wiring 1 is formed.
7 and 18 are formed. Finally, a protective insulating film 19 made of silicon nitride is formed, and annealing is performed in a hydrogen atmosphere, whereby dangling bonds in the polycrystalline silicon thin film are compensated with hydrogen to improve characteristics and a thin film transistor is completed.

【0004】[0004]

【発明が解決しようとする課題】前記従来法において
は、非晶質シリコン膜堆積後、または脱水素後、クリー
ンルーム内の雰囲気に晒されることにより、膜表面が有
機物,ホウ素,アルカリ金属等により汚染される可能性
がある。膜表面が汚染されたままの状態で結晶化を行う
と、汚染物質がpoly-Si膜内に取り込まれてしまう。こ
れはトランジスタ特性および信頼性を悪化させる原因と
なる。
In the above-mentioned conventional method, after the amorphous silicon film is deposited or dehydrogenated, the film surface is contaminated with organic substances, boron, alkali metals and the like by being exposed to an atmosphere in a clean room. Could be done. If crystallization is performed while the film surface is still contaminated, contaminants will be taken into the poly-Si film. This causes deterioration of transistor characteristics and reliability.

【0005】本発明は、前記従来の問題を解決するた
め、非晶質シリコン堆積後の脱水素工程において、酸化
雰囲気中でアニールすることにより、表面に薄い酸化膜
を形成し、汚染物質がシリコン膜に付着するのを防止す
る薄膜トランジスタの製造方法を提供する。
According to the present invention, a thin oxide film is formed on a surface by annealing in an oxidizing atmosphere in a dehydrogenation step after deposition of amorphous silicon to solve the above-mentioned conventional problem. Provided is a method for manufacturing a thin film transistor which prevents the thin film from being attached to a film.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するた
め、本発明の薄膜トランジスタの製造方法は、ガラス基
板上に非晶質シリコン膜を形成し、非晶質シリコン膜中
の水素を離脱させ、非晶質シリコン膜を多結晶シリコン
膜に加工し、島状多結晶シリコン膜を形成し、ゲート電
極を形成し、前記島状多結晶シリコン膜に不純物を注入
し、前記不純物を活性化する薄膜トランジスタの製造方
法において、前記ガラス基板上に、非晶質シリコン膜を
堆積した後、前記非晶質シリコン膜中に含有している水
素を離脱させる際に、酸化雰囲気中でアニールして酸化
シリコン膜を形成することを特徴とする。
In order to achieve the above object, a method for manufacturing a thin film transistor according to the present invention comprises forming an amorphous silicon film on a glass substrate, releasing hydrogen in the amorphous silicon film, Processing an amorphous silicon film into a polycrystalline silicon film, forming an island-shaped polycrystalline silicon film, forming a gate electrode, implanting impurities into the island-shaped polycrystalline silicon film, and activating the impurities In the manufacturing method, after depositing an amorphous silicon film on the glass substrate, when desorbing hydrogen contained in the amorphous silicon film, annealing is performed in an oxidizing atmosphere to form a silicon oxide film. Is formed.

【0007】本発明によれば、非晶質シリコン堆積後の
脱水素工程において、酸化雰囲気中でアニールすること
により、表面に薄い酸化膜を形成し、汚染物質がシリコ
ン膜に付着するのを防止する。また、酸化膜表面に汚染
物質が付着しても、レーザー結晶化を行う直前にこの酸
化膜を除去することにより、汚染物質も同時に除去され
る。
According to the present invention, in the dehydrogenation step after the deposition of amorphous silicon, annealing is performed in an oxidizing atmosphere to form a thin oxide film on the surface and prevent contaminants from adhering to the silicon film. I do. Further, even if a contaminant adheres to the surface of the oxide film, the contaminant is also removed by removing the oxide film immediately before performing the laser crystallization.

【0008】[0008]

【発明の実施の形態】本発明においては、前記水素を離
脱させる際のアニール条件が、400℃以上600℃以下の温
度であり、非晶質シリコン膜中の水素を脱離させかつ非
晶質シリコン膜表面に薄い酸化シリコン膜を形成するこ
とが好ましい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the annealing condition for desorbing hydrogen is a temperature of 400 ° C. or more and 600 ° C. or less, so that hydrogen in the amorphous silicon film is desorbed and amorphous. It is preferable to form a thin silicon oxide film on the surface of the silicon film.

【0009】また、前記水素を離脱させる際に、プラズ
マ放電するすることが好ましい。
Further, it is preferable to perform plasma discharge when the hydrogen is desorbed.

【0010】また、前記水素の脱離を、紫外域から近赤
外域の範囲の波長を有する強光を照射することによって
行うことが好ましい。前記において、強光とは、例えば
Xeアークランプが発光する5kW以上の光をいう。
It is preferable that the desorption of hydrogen is performed by irradiating strong light having a wavelength in the range from the ultraviolet region to the near infrared region. In the above, the intense light refers to, for example, light of 5 kW or more emitted by a Xe arc lamp.

【0011】また、前記酸化シリコン膜は、非晶質シリ
コン膜を多結晶シリコン膜に加工する前または後に除去
することが好ましい。
Preferably, the silicon oxide film is removed before or after processing the amorphous silicon film into a polycrystalline silicon film.

【0012】以下、本発明の実施の形態について図面を
参照しながら説明する。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0013】(実施例1)まず図1(a)に示すようにガ
ラス基板11上にバッファー層12となる酸化シリコン
膜を形成する。その後、前記酸化シリコン薄膜を形成し
たガラス基板を大気中に取り出すことなくプラズマCV
D法にて非晶質シリコン(a-Si)膜21をガラス基板に堆
積する。次いでa-Si膜中の水素を低減するためと、a-Si
膜表面に薄い熱酸化膜22を形成するために、酸化雰囲
気下(酸素、オゾン、酸素と窒素の混合気体等)で400
〜600℃、60分程度の熱処理を行う。次に希フッ酸でウ
エットエッチングを行い、熱酸化膜22を除去した直後
に、エキシマレーザーアニールにてa-Si膜を多結晶化し
poly-Si膜13を形成する。このとき、エキシマレーザ
ーは波長308nmのXeClエキシマレーザーを用いる。次に
図1(b)に示すように、poly-Si膜を所望の形状に加
工した後、フォトレジスト23にて不純物注入用のマス
クを形成しソースおよびドレイン領域13cに不純物
(燐イオン)を注入する。次に、ゲート絶縁膜14とな
る酸化シリコン膜を形成する。その後ゲート電極15を
形成し薄膜トランジスタにLDD領域13bを形成するた
め不純物(燐イオン)を注入する。不純物が注入されて
いない領域13aは真性多結晶シリコンであり、チャネ
ル領域となる。次に、図1(c)に示すように、層間絶
縁膜となる酸化シリコン膜16を形成した後、注入した
不純物の活性化を、減圧窒素雰囲気下で500〜600℃の温
度でアニールを施すことにより行う。次に、ソースおよ
びドレイン領域上の絶縁膜にコンタクトホールを開口
し、配線17,18を形成する。最後に窒化シリコンか
らなる保護絶縁膜19を形成し、水素雰囲気でのアニー
ルを行うことで、多結晶シリコン薄膜中の未結合手を水
素にて補償し特性を向上させ薄膜トランジスタが完成す
る。
Embodiment 1 First, as shown in FIG. 1A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11. Thereafter, the plasma CV was removed without taking out the glass substrate on which the silicon oxide thin film was formed into the atmosphere.
An amorphous silicon (a-Si) film 21 is deposited on a glass substrate by the method D. Next, to reduce hydrogen in the a-Si film,
In order to form a thin thermal oxide film 22 on the film surface, 400 mm
A heat treatment of about 600 ° C. for about 60 minutes is performed. Next, the a-Si film was polycrystallized by excimer laser annealing immediately after the thermal oxide film 22 was removed by wet etching with diluted hydrofluoric acid.
A poly-Si film 13 is formed. At this time, an XeCl excimer laser having a wavelength of 308 nm is used as the excimer laser. Next, as shown in FIG. 1B, after processing the poly-Si film into a desired shape, a mask for impurity implantation is formed by a photoresist 23, and impurities (phosphor ions) are implanted into the source and drain regions 13c. inject. Next, a silicon oxide film to be the gate insulating film 14 is formed. Thereafter, an impurity (phosphorus ion) is implanted to form the gate electrode 15 and to form the LDD region 13b in the thin film transistor. The region 13a into which impurities are not implanted is intrinsic polycrystalline silicon, and serves as a channel region. Next, as shown in FIG. 1C, after a silicon oxide film 16 serving as an interlayer insulating film is formed, the implanted impurities are activated by annealing at a temperature of 500 to 600 ° C. in a reduced-pressure nitrogen atmosphere. It is done by doing. Next, contact holes are opened in the insulating film on the source and drain regions, and wirings 17 and 18 are formed. Finally, a protective insulating film 19 made of silicon nitride is formed, and annealing is performed in a hydrogen atmosphere, whereby dangling bonds in the polycrystalline silicon thin film are compensated with hydrogen to improve characteristics and a thin film transistor is completed.

【0014】(実施例2)まず図2(a)に示すようにガ
ラス基板11上にバッファー層12となる酸化シリコン
膜を形成する。その後、前記酸化シリコン薄膜を形成し
たガラス基板を大気中に取り出すことなくプラズマCV
D法にて非晶質シリコン(a-Si)膜21をガラス基板に堆
積する。続いてa-Si膜中の水素を低減するためと、a-Si
膜表面に薄い酸化膜を形成するために、酸化雰囲気下
(酸素、オゾン、酸素と窒素の混合気体等)で400〜450
℃に基板温度を保ちながら、プラズマ放電を行う。次に
希フッ酸でウエットエッチングを行い、熱酸化膜22を
除去した直後に、エキシマレーザーアニールにてa-Si膜
を多結晶化し、poly-Si膜13を形成する。このとき、
エキシマレーザーは波長308nmのXeClエキシマレーザー
を用いる。次に図2(b)に示すように、poly-Si膜を
所望の形状に加工した後、フォトレジスト23にて不純
物注入用のマスクを形成しソースおよびドレイン領域1
3cに不純物(燐イオン)を注入する。次に、ゲート絶
縁膜14となる酸化シリコン膜を形成する。その後ゲー
ト電極15を形成し薄膜トランジスタにLDD領域13b
を形成するため不純物(燐イオン)を注入する。不純物
が注入されていない領域13aは真性多結晶シリコンで
あり、チャネル領域となる。次に、図2(c)に示すよ
うに、層間絶縁膜となる酸化シリコン膜16を形成した
後、注入した不純物の活性化を、減圧窒素雰囲気下で50
0〜600℃の温度でアニールを施すことにより行う。次
に、ソースおよびドレイン領域上の絶縁膜にコンタクト
ホールを開口し、配線17,18を形成する。最後に窒
化シリコンからなる保護絶縁膜19を形成し、水素雰囲
気でのアニールを行うことで、多結晶シリコン薄膜中の
未結合手を水素にて補償し特性を向上させ薄膜トランジ
スタが完成する。
Embodiment 2 First, as shown in FIG. 2A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11. Thereafter, the plasma CV was removed without taking out the glass substrate on which the silicon oxide thin film was formed into the atmosphere.
An amorphous silicon (a-Si) film 21 is deposited on a glass substrate by the method D. Next, to reduce hydrogen in the a-Si film,
400-450 under oxidizing atmosphere (oxygen, ozone, mixed gas of oxygen and nitrogen, etc.) to form a thin oxide film on the film surface
Plasma discharge is performed while maintaining the substrate temperature at ° C. Next, wet etching is performed with dilute hydrofluoric acid, and immediately after the thermal oxide film 22 is removed, the a-Si film is polycrystallized by excimer laser annealing to form a poly-Si film 13. At this time,
As the excimer laser, a XeCl excimer laser having a wavelength of 308 nm is used. Next, as shown in FIG. 2B, after processing the poly-Si film into a desired shape, a mask for impurity implantation is formed by a photoresist 23, and the source and drain regions 1 are formed.
Impurities (phosphorus ions) are implanted into 3c. Next, a silicon oxide film to be the gate insulating film 14 is formed. Thereafter, a gate electrode 15 is formed, and the LDD region 13b is formed on the thin film transistor.
Is implanted to form (). The region 13a into which impurities are not implanted is intrinsic polycrystalline silicon, and serves as a channel region. Next, as shown in FIG. 2C, after a silicon oxide film 16 serving as an interlayer insulating film is formed, the activation of the implanted impurities is performed under a reduced-pressure nitrogen atmosphere.
This is performed by annealing at a temperature of 0 to 600 ° C. Next, contact holes are opened in the insulating film on the source and drain regions, and wirings 17 and 18 are formed. Finally, a protective insulating film 19 made of silicon nitride is formed, and annealing is performed in a hydrogen atmosphere, whereby dangling bonds in the polycrystalline silicon thin film are compensated with hydrogen to improve characteristics and a thin film transistor is completed.

【0015】(実施例3)まず図3(a)に示すようにガ
ラス基板11上にバッファー層12となる酸化シリコン
膜を形成する。その後、前記酸化シリコン薄膜を形成し
たガラス基板を大気中に取り出すことなくプラズマCV
D法にて非晶質シリコン(a-Si)膜21をガラス基板に堆
積する。ついでa-Si膜中の水素を低減するためと、a-Si
膜表面に薄い熱酸化膜22を形成するために、酸化雰囲
気下(酸素、オゾン、酸素と窒素の混合気体等)で基板
温度が400〜600℃になるような出力(20kW)および
基板送りスピード(20mm/s)でXeアークランプ
によるアニールを行う。次に希フッ酸でウエットエッチ
ングを行い、熱酸化膜22を除去した直後に、エキシマ
レーザーアニールにてa-Si膜を多結晶化しpoly-Si膜1
3を形成する。エキシマレーザーは波長308nmのXeClエ
キシマレーザーを用いる。次に図3(b)に示すよう
に、poly-Si膜を所望の形状に加工した後、フォトレジ
スト23にて不純物注入用のマスクを形成しソースおよ
びドレイン領域に不純物(燐イオン)を注入する。次
に、ゲート絶縁膜14となる酸化シリコン膜を形成す
る。その後ゲート電極15を形成し薄膜トランジスタに
LDD領域を形成するため不純物(燐イオン)を注入す
る。不純物が注入されていない領域13aは真性多結晶
シリコンであり、チャネル領域となる。次に、図3
(c)に示すように、層間絶縁膜となる酸化シリコン膜
16を形成した後、注入した不純物の活性化を、窒素雰
囲気下で基板温度が500〜600℃になるような出力(40
kW)と送りスピード(20mm/s)でランプアニー
ルを行う。次に、ソースおよびドレイン領域上の絶縁膜
にコンタクトホールを開口し、配線17,18を形成す
る。最後に窒化シリコンからなる保護絶縁膜19を形成
し、水素雰囲気でのアニールを行うことで、多結晶シリ
コン薄膜中の未結合手を水素にて補償し特性を向上させ
薄膜トランジスタが完成する。
Embodiment 3 First, as shown in FIG. 3A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11. Thereafter, the plasma CV was removed without taking out the glass substrate on which the silicon oxide thin film was formed into the atmosphere.
An amorphous silicon (a-Si) film 21 is deposited on a glass substrate by the method D. Next, to reduce the hydrogen in the a-Si film,
In order to form a thin thermal oxide film 22 on the surface of the film, an output (20 kW) and a substrate feed speed such that the substrate temperature becomes 400 to 600 ° C. under an oxidizing atmosphere (oxygen, ozone, a mixed gas of oxygen and nitrogen, etc.) Anneal by Xe arc lamp at (20 mm / s). Next, the a-Si film is polycrystallized by excimer laser annealing immediately after the thermal oxide film 22 is removed by wet etching with dilute hydrofluoric acid.
Form 3 As the excimer laser, a XeCl excimer laser having a wavelength of 308 nm is used. Next, as shown in FIG. 3B, after processing the poly-Si film into a desired shape, a mask for impurity implantation is formed with a photoresist 23 and impurities (phosphorus ions) are implanted into the source and drain regions. I do. Next, a silicon oxide film to be the gate insulating film 14 is formed. Thereafter, a gate electrode 15 is formed to form a thin film transistor.
Impurities (phosphorus ions) are implanted to form LDD regions. The region 13a into which impurities are not implanted is intrinsic polycrystalline silicon, and serves as a channel region. Next, FIG.
As shown in (c), after the silicon oxide film 16 serving as an interlayer insulating film is formed, the activation of the implanted impurities is performed by an output (40
kW) and a feed speed (20 mm / s) to perform lamp annealing. Next, contact holes are opened in the insulating film on the source and drain regions, and wirings 17 and 18 are formed. Finally, a protective insulating film 19 made of silicon nitride is formed, and annealing is performed in a hydrogen atmosphere, whereby dangling bonds in the polycrystalline silicon thin film are compensated with hydrogen to improve characteristics and a thin film transistor is completed.

【0016】(実施例4)まず図4(a)に示すようにガ
ラス基板11上にバッファー層12となる酸化シリコン
膜を形成する。その後、前記酸化シリコン薄膜を形成し
たガラス基板を大気中に取り出すことなくプラズマCV
D法にて非晶質シリコン(a-Si)膜21をガラス基板に堆
積する。ついでa-Si膜中の水素を低減するためと、a-Si
膜表面に薄い熱酸化膜22を形成するために、酸化雰囲
気下(酸素、オゾン、酸素と窒素の混合気体等)で400
〜600℃、60分程度の熱処理を行う。続いて、エキシマ
レーザーアニールにてa-Si膜を多結晶化しpoly-Si膜1
3を形成する。このとき、エキシマレーザーは波長308n
mのXeClエキシマレーザーを用いる。
Embodiment 4 First, as shown in FIG. 4A, a silicon oxide film serving as a buffer layer 12 is formed on a glass substrate 11. Thereafter, the plasma CV was removed without taking out the glass substrate on which the silicon oxide thin film was formed into the atmosphere.
An amorphous silicon (a-Si) film 21 is deposited on a glass substrate by the method D. Next, to reduce the hydrogen in the a-Si film,
In order to form a thin thermal oxide film 22 on the film surface, 400 mm
A heat treatment of about 600 ° C. for about 60 minutes is performed. Subsequently, the a-Si film is polycrystallized by excimer laser annealing to form a poly-Si film 1.
Form 3 At this time, the wavelength of the excimer laser is 308n
An XeCl excimer laser of m is used.

【0017】次に図4(b)に示すように、poly-Si膜
を所望の形状に加工した後、フォトレジスト23にて不
純物注入用のマスクを形成しソースおよびドレイン領域
13cに不純物(燐イオン)を注入する。希フッ酸でウ
エットエッチングを行い、熱酸化膜22を除去した後、
ゲート絶縁膜14となる酸化シリコン膜を形成する。そ
の後ゲート電極15を形成し薄膜トランジスタにLDD領
域13bを形成するため不純物(燐イオン)を注入す
る。不純物が注入されていない領域13aは真性多結晶
シリコンであり、チャネル領域となる。次に、図4
(c)に示すように、層間絶縁膜となる酸化シリコン膜
16を形成した後、注入した不純物の活性化を、減圧窒
素雰囲気下で500〜600℃の温度でアニールを施すことに
より行う。次に、ソースおよびドレイン領域上の絶縁膜
にコンタクトホールを開口し、配線17,18を形成す
る。最後に窒化シリコンからなる保護絶縁膜19を形成
し、水素雰囲気でのアニールを行うことで、多結晶シリ
コン薄膜中の未結合手を水素にて補償し特性を向上させ
薄膜トランジスタが完成する。
Next, as shown in FIG. 4B, after processing the poly-Si film into a desired shape, a mask for impurity implantation is formed with a photoresist 23 and impurities (phosphorus) are formed in the source and drain regions 13c. Ions). After performing wet etching with dilute hydrofluoric acid to remove the thermal oxide film 22,
A silicon oxide film to be the gate insulating film 14 is formed. Thereafter, an impurity (phosphorus ion) is implanted to form the gate electrode 15 and to form the LDD region 13b in the thin film transistor. The region 13a into which impurities are not implanted is intrinsic polycrystalline silicon, and serves as a channel region. Next, FIG.
As shown in (c), after the silicon oxide film 16 to be the interlayer insulating film is formed, the implanted impurities are activated by annealing at a temperature of 500 to 600 ° C. in a reduced-pressure nitrogen atmosphere. Next, contact holes are opened in the insulating film on the source and drain regions, and wirings 17 and 18 are formed. Finally, a protective insulating film 19 made of silicon nitride is formed, and annealing is performed in a hydrogen atmosphere, whereby dangling bonds in the polycrystalline silicon thin film are compensated with hydrogen to improve characteristics and a thin film transistor is completed.

【0018】[0018]

【発明の効果】以上説明したように本発明方法は、脱水
素処理を酸化雰囲気中で行うことにより、表面に薄い酸
化膜が形成され、汚染物質がシリコン膜に付着するのを
防止する。また、酸化膜表面に汚染物質が付着したとし
ても、レーザー結晶化を行う直前にこの酸化膜を除去す
ることにより、汚染物質も同時に除去されるため、汚染
物質が完全に除去されたpoly-Si膜が得られる。
As described above, according to the method of the present invention, a thin oxide film is formed on the surface by performing the dehydrogenation treatment in an oxidizing atmosphere, and contaminants are prevented from adhering to the silicon film. Even if contaminants adhere to the surface of the oxide film, removing the oxide film immediately before performing laser crystallization also removes the contaminants at the same time. A film is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(c)は本発明の実施例1のn型TFTの
製造工程を示す説明断面図
FIGS. 1A to 1C are explanatory sectional views showing manufacturing steps of an n-type TFT according to a first embodiment of the present invention.

【図2】(a)〜(c)は本発明の実施例2のn型TFT
の製造工程を示す説明断面図
FIGS. 2A to 2C are n-type TFTs according to a second embodiment of the present invention;
Explanatory sectional view showing the manufacturing process of

【図3】(a)〜(c)は本発明の実施例3のn型TFT
の製造工程を示す説明断面図
FIGS. 3A to 3C are n-type TFTs according to a third embodiment of the present invention;
Explanatory sectional view showing the manufacturing process of

【図4】(a)〜(c)は本発明の実施例4のn型TFT
の製造工程を示す説明断面図
FIGS. 4A to 4C are n-type TFTs according to a fourth embodiment of the present invention;
Explanatory sectional view showing the manufacturing process of

【図5】(a)〜(c)は従来のn型TFT製造工程を示
す説明断面図
5 (a) to 5 (c) are explanatory sectional views showing a conventional n-type TFT manufacturing process.

【符号の説明】[Explanation of symbols]

11 ガラス基板 12 バッファー層(酸化シリコン) 13 多結晶シリコン 13a 真性多結晶シリコン(チャネル領域) 13b 低濃度不純物注入領域(LDD領域) 13c 高濃度不純物注入領域(SD領域) 14 ゲート絶縁膜(酸化シリコン) 15 ゲート電極(MoW合金) 16 層間絶縁膜(酸化シリコン) 17,18 SD配線(Al/Ti) 19 保護絶縁膜(窒化シリコン) 21 非晶質シリコン膜 22 熱酸化膜 23 フォトレジスト Reference Signs List 11 glass substrate 12 buffer layer (silicon oxide) 13 polycrystalline silicon 13a intrinsic polycrystalline silicon (channel region) 13b low concentration impurity implantation region (LDD region) 13c high concentration impurity implantation region (SD region) 14 gate insulating film (silicon oxide 15) Gate electrode (MoW alloy) 16 Interlayer insulating film (silicon oxide) 17, 18 SD wiring (Al / Ti) 19 Protective insulating film (silicon nitride) 21 Amorphous silicon film 22 Thermal oxide film 23 Photoresist

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F052 AA02 AA12 BB07 CA02 DA02 DB03 EA15 FA19 HA06 JA01 5F110 AA14 AA26 BB01 CC02 DD02 DD13 FF02 GG02 GG13 GG35 GG45 HJ01 HJ13 HJ23 HM15 NN02 NN03 NN23 NN24 PP03 PP04 PP35 QQ08 QQ09 QQ11 QQ24  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference)

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】ガラス基板上に非晶質シリコン膜を形成
し、非晶質シリコン膜中の水素を離脱させ、非晶質シリ
コン膜を多結晶シリコン膜に加工し、島状多結晶シリコ
ン膜を形成し、ゲート電極を形成し、前記島状多結晶シ
リコン膜に不純物を注入し、前記不純物を活性化する薄
膜トランジスタの製造方法において、 前記ガラス基板上に、非晶質シリコン膜を堆積した後、
前記非晶質シリコン膜中に含有している水素を離脱させ
る際に、酸化雰囲気中でアニールして酸化シリコン膜を
形成することを特徴とする薄膜トランジスタの製造方
法。
An amorphous silicon film is formed on a glass substrate, hydrogen in the amorphous silicon film is released, and the amorphous silicon film is processed into a polycrystalline silicon film. Forming a gate electrode, implanting an impurity into the island-shaped polycrystalline silicon film, and activating the impurity. A method of manufacturing a thin film transistor, comprising: depositing an amorphous silicon film on the glass substrate; ,
A method for manufacturing a thin film transistor, comprising: annealing in an oxidizing atmosphere to form a silicon oxide film when desorbing hydrogen contained in the amorphous silicon film.
【請求項2】前記水素を離脱させる際のアニール条件
が、400℃以上600℃以下の温度であり、非晶質シリコン
膜中の水素を脱離させかつ非晶質シリコン膜表面に薄い
酸化シリコン膜を形成する請求項1に記載の薄膜トラン
ジスタの製造方法。
2. An annealing condition for releasing hydrogen is a temperature of 400 ° C. or more and 600 ° C. or less, wherein hydrogen in the amorphous silicon film is released and a thin silicon oxide film is formed on the surface of the amorphous silicon film. The method for manufacturing a thin film transistor according to claim 1, wherein a film is formed.
【請求項3】前記水素を離脱させる際に、プラズマ放電
する請求項1または2に記載の薄膜トランジスタの製造
方法。
3. The method of manufacturing a thin film transistor according to claim 1, wherein plasma is discharged when said hydrogen is desorbed.
【請求項4】前記水素の脱離を、紫外域から近赤外域の
範囲の波長を有する強光を照射することによって行う請
求項1〜3のいずれかに記載の薄膜トランジスタの製造
方法。
4. The method of manufacturing a thin film transistor according to claim 1, wherein the desorption of hydrogen is performed by irradiating strong light having a wavelength in a range from ultraviolet to near infrared.
【請求項5】前記酸化シリコン膜は、非晶質シリコン膜
を多結晶シリコン膜に加工する前または後に除去する請
求項1〜4のいずれかに記載の薄膜トランジスタの製造
方法。
5. The method according to claim 1, wherein the silicon oxide film is removed before or after processing the amorphous silicon film into a polycrystalline silicon film.
JP2001170028A 2001-06-05 2001-06-05 Manufacturing method of thin-film transistor Pending JP2002368010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001170028A JP2002368010A (en) 2001-06-05 2001-06-05 Manufacturing method of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001170028A JP2002368010A (en) 2001-06-05 2001-06-05 Manufacturing method of thin-film transistor

Publications (1)

Publication Number Publication Date
JP2002368010A true JP2002368010A (en) 2002-12-20

Family

ID=19012020

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2002368010A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004770A (en) * 2007-06-19 2009-01-08 Samsung Sdi Co Ltd Method of manufacturing polycrystalline silicon layer, thin-film transistor manufactured using the same, manufacturing method thereof, and organic electroluminescent display device equipped with the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004770A (en) * 2007-06-19 2009-01-08 Samsung Sdi Co Ltd Method of manufacturing polycrystalline silicon layer, thin-film transistor manufactured using the same, manufacturing method thereof, and organic electroluminescent display device equipped with the same
US7825476B2 (en) 2007-06-19 2010-11-02 Samsung Mobile Display Co., Ltd. Method of fabricating polycrystalline silicon, TFT fabricated using the same, method of fabricating the TFT, and organic light emitting diode display device including the TFT
US8445336B2 (en) 2007-06-19 2013-05-21 Samsung Display Co., Ltd. Method of fabricating polycrystalline silicon, TFT fabricated using the same, method of fabricating the TFT, and organic light emitting diode display device including the TFT

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