JP2002367879A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress variation in line width which may be produced in a photolithography process. SOLUTION: A plurality of types of semiconductor substrate 1 for forming different products are respectively provided with focus patterns 14f identical in height on scribe lines on the semiconductor substrates 1, and focusing is obtained with reference to these focus patterns. With the focus patterns 14f on a plurality of types of semiconductor substrate 1 identical in height as mentioned above, the focusing height can be made uniform by obtaining focusing with reference to the focus patterns 14f. Thus, variation in line width which may be produced in a photolithography process can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a composite IC, that is, a semiconductor device in which a plurality of types of elements are formed on the same substrate.

[0002]

2. Description of the Related Art There is a photolithography process as one process of manufacturing a semiconductor device. In the photolithography process, after a resist is applied on the substrate surface, a pattern is transferred to the resist and developed to form a resist pattern on the wafer. When transferring a pattern, the average height at a location previously input to the apparatus is measured, and the focus is determined based on the average height.

[0003]

A composite IC is one in which a bipolar transistor, a MOS transistor, a power device, and the like are formed into one chip by using a trench isolation technique. FIGS. 13A to 13C show the layout and cross-sectional configuration of each device. Each cross-sectional view corresponds to a cross section taken along the line AA ′ of each layout diagram.

As can be seen from these figures, in the case of a bipolar transistor, there is almost no Poly-Si 101 and the number of LOCOS oxide films 102 is very small. MO
In the case of the S transistor, the amount of the Poly-Si 101 is small, but the amount of the LOCOS oxide film 102 is large. LDMOS that is a power device is often Poly-Si101,
The amount of the S oxide film 102 is small. The number and layout of these elements are different for each product, such as bipolar transistors, MO
The total area of the S transistor and the LDMOS is different.

For this reason, when different types of products are manufactured using the same photolithography process apparatus,
The average height measured when determining the focus is measured differently for each product, and the focus is largely shifted.

For example, as shown in FIGS. 14 (a) and 14 (b), when a product having a low average height and a product having a high average height have the same resist thickness, the product having a higher average height has a higher resist. The spot size on the top becomes smaller. Therefore, a product having a higher average height has a smaller line width (a width of an exposed portion) than a product having a lower average height, and the line width variation between products is larger.

Such a phenomenon is not a problem if CMOS, bipolar transistors, and LDMOS are arranged at random. However, since CMOS, bipolar transistors, and LDMOS are actually arranged for each circuit block, when a focus measurement is performed, the bipolar transistor becomes rich depending on the product. , CMOS rich or LDMOS rich. Therefore, the focus height differs depending on the product. Since the focus depth (the depth at which focus is achieved) is about ± 0.4 μm with respect to the focus height, line width variations do not occur if the high and low steps are within the focus depth. Actually, the line width varies because the upper side deviates or the lower side deviates. As shown in FIG. 15A, it has been confirmed from the experimental results that line width variation has occurred.

On the other hand, as a parameter for correcting variations in the focus position, there is a focus offset in the exposure file, and if a method such as inputting a predetermined condition is adopted, even if the focus varies, as shown in FIG. The line width variation can be corrected. However, according to this method, it is necessary to set a focus offset value for each product, and it is not possible in a factory with a small number of products, so that products manufactured by the same process are required to have the same exposure conditions. If the same exposure conditions are used, line width variations are likely to occur for the above reasons.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to suppress line width variations caused by a photolithography process.

[0010]

According to the first aspect of the present invention, a resist (7, 13, 15, 17, 19) is formed on a semiconductor substrate (1). A photolithography apparatus is prepared which focuses on the resist (7, 13, 15, 17, 19), transfers and develops the resist (7, 13, 15, 17, 17, 19) to a predetermined pattern. Using the same photolithography apparatus, resists (7, 13, and 13) are respectively applied to a plurality of types of semiconductor substrates (1) on which different products are formed.
In the method of manufacturing a semiconductor device for performing focusing, transfer and development of (15, 17, 19), a plurality of types of semiconductor substrates (1) are focused at desired positions on the semiconductor substrate (1) at the same height. It is characterized in that a pattern is provided and focusing is performed based on this focus pattern.

As described above, when the focus patterns on a plurality of types of semiconductor substrates have the same height, the focus height can be adjusted by adjusting the focus based on the focus patterns. Thereby, the line width variation caused by the photolithography process can be suppressed.

For example, as the second aspect, a focus pattern in which all films formed on a plurality of types of semiconductor substrates are stacked can be used. Such a focus pattern can be formed on the scribe line (20) of the semiconductor substrate (1). In this case, the focus pattern may be formed over the entire area of the scribe line (20) as described in claim 4, or the focus pattern may be formed within the scribe line (20) as described in claim 5. 25).

Further, as described in claim 6, a capacitor (22) commonly formed on a plurality of types of semiconductor substrates (1) can be used as the focus pattern. Further, as described in claim 7, the focus pattern can be formed on a part (23) in each chip (21) partitioned by the scribe line (20) of the semiconductor substrate (1). As shown in FIG. 8, some of the chips (24) of the plurality of chips (21) partitioned by the scribe lines of the semiconductor substrate (1) can be used as the focus pattern.

The reference numerals in the parentheses of the above means indicate the correspondence with the specific means described in the embodiments described later.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method of manufacturing a semiconductor device to which one embodiment of the present invention is applied will be described with reference to FIG.
This will be described with reference to manufacturing steps shown in FIGS.

First, in the step shown in FIG. 1A, trench isolation is performed on the semiconductor substrate 1 to form an NPN bipolar transistor (hereinafter referred to as NPNTr) formation region.
It is divided into an LDMOS formation region and a focus pattern formation region. At this time, the focus pattern formation region is, for example, any position on the scribe line. Then, after the n-type well layer 2 is formed by ion implantation or the like, the p-type base region 3 is formed in the NPN Tr formation region, and the deep p-layer 4 is formed in the LDMOS formation region. Thereafter, a LOCOS oxide film 5 is formed at a desired position on the surface of the semiconductor substrate 1 including the focus pattern formation region by a known LOCOS oxidation method.

Next, in a step shown in FIG. 1B, a Poly-Si layer 6 is formed on the entire upper surface of the semiconductor substrate 1. Then, in the step shown in FIG. 1C, a photolithography step is performed. First, a resist 7 is formed on the Poly-Si layer 6. After that, the focus is set in accordance with the height of the focus pattern formation region, that is, the height of the LOCOS oxide film 5, and after transferring to the resist 7, development is performed. As a result, the resist 7 is left on the predetermined region in the LDMOS formation region and the focus pattern formation region.

Next, in the step shown in FIG. 1D, etching is performed using the resist 7 as a mask, and the poly-Si
The layer 6 is patterned to form the gate electrode 6a in the LDMOS formation region and the first focus pattern 6b in the focus pattern formation region. Thereafter, by performing a photolithography step and an ion implantation step with reference to the first focus pattern 6b, the p-type channel region 8 is formed in the LDMOS formation region, or the n ⁺ -type source region 9 in the LDMOS formation region is formed.
And an n ⁺ -type drain region 10 and an n ⁺ -type emitter region 11 in the NPN Tr formation region.

Next, in a step shown in FIG. 2A, an interlayer insulating film 12 is formed on the entire upper surface of the semiconductor substrate 1. Then, in the step shown in FIG. 2B, a photolithography step is performed. First, a resist 13 is formed on the interlayer insulating film 12.
Is formed. After that, the focus is set according to the height of the first focus pattern formation region, and the resist 13 is set.
After transfer to the surface, development is performed. Thereby, the resist 13 is left on the predetermined region.

Next, in a step shown in FIG. 2C, etching is performed using the resist 13 as a mask, and the interlayer insulating film 1 is etched.
2 is patterned to form a contact hole communicating with each part of the element. At this time, the interlayer insulating film 12 is left in the focus pattern formation region, so that the second focus pattern is formed.

Next, in the step shown in FIG. 2D, the first wiring layer 14 made of Al or the like is formed on the entire upper surface of the semiconductor substrate 1.
Is formed. Then, in the step shown in FIG.
A photolithography process is performed based on the focus pattern. First, the resist 1 is formed on the first wiring layer 14.
5 is formed. After that, the focus is set in accordance with the height of the focus pattern forming region, and after the transfer to the resist 15 is performed, the development is performed. Thereby, LDMOS
The resist 15 is left on a predetermined area in the formation area and on the focus pattern formation area.

Next, in the step shown in FIG. 3B, etching is performed using the resist 15 as a mask, and the first wiring layer 1 is etched.
4 is patterned, and the first Al wirings 14a to 14e are formed.
To form At this time, the first Al wiring 14f is also left in the focus pattern formation region, so that the third focus pattern is formed.

Next, in a step shown in FIG. 3C, an interlayer insulating film 16 is formed on the entire upper surface of the semiconductor substrate 1. Then, in the step shown in FIG. 4A, a photolithography step based on the third focus pattern is performed. First, a resist 17 is formed on the interlayer insulating film 16. After that, the focus is set in accordance with the height of the focus pattern forming region, and after the transfer to the resist 17 is performed, the development is performed. Thereby, the resist 17 is formed on a predetermined area.
Leave.

Next, in the step shown in FIG. 4B, etching is performed using the resist 17 as a mask to form the interlayer insulating film 1.
6 is patterned to form a contact hole communicating with each part of the element. At this time, the interlayer insulating film 16 is also left in the focus pattern formation region, so that the fourth focus pattern is left.

Next, in the step shown in FIG. 4C, the second wiring layer 18 made of Al or the like is formed on the entire upper surface of the semiconductor substrate 1.
Is formed. Then, in the step shown in FIG.
A photolithography process is performed based on the focus pattern. First, the resist 1 is formed on the second wiring layer 18.
9 is formed. Thereafter, in the step shown in FIG. 5B, the focus is set in accordance with the height of the focus pattern formation region, and after the transfer to the resist 19 is performed, the development is performed. As a result, the resist 19 is left on the predetermined region in the LDMOS formation region and the focus pattern formation region.

Next, in the step shown in FIG. 5C, etching is performed using the resist 19 as a mask, and the second wiring layer 1 is etched.
8 and patterning the second Al wirings 18a to 18c
To form At this time, the first Al wiring 14f is also left in the focus pattern formation region. Although the subsequent steps are not shown, the semiconductor device is completed by performing a protective film forming step and the like as necessary.

In the above manufacturing method, when transferring the resists 7, 13, 15, 17, 19,
Focus setting is performed based on the LOCOS oxide film 5 formed in the focus pattern formation region and the first to fourth focus patterns. For example, by inputting the coordinates of several focus pattern formation regions in the semiconductor substrate 1 into the stepper, the average height is measured on each focus pattern. After performing focus setting based on each focus pattern, the resists 7, 13, 15, 1
7, 19 are transferred and developed to form a resist pattern. Each resist pattern is formed by stacking all the films in the manufacturing process.

In the case of manufacturing different products, if the manufacturing process is the same even if the products are different, the focus pattern is the same for both products, and there is no difference in the focus height between the products. That is, as shown in FIGS. 6A and 6B, since the pattern of the region other than the focus pattern differs for each product, the average height in that region may differ for each product. Even in such a case, since the heights of the focus patterns match, the focus height is set based on the focus patterns having the same height.

As described above, the height of the focus can always be set at a constant height without being affected by the pattern of the product, so that all steps are within the depth of focus and the entire product is covered. Focus. This makes it possible to suppress line width variations due to differences in focus height.

(Other Embodiments) In the above embodiment, the focus pattern is formed by forming all the films during the manufacturing process. However, it is not necessary to use all the films, and at least for each product. If the heights of the focus patterns match, the same effect as described above can be obtained.

In the above embodiment, the focus pattern is formed at any position on the scribe line. However, it is not always necessary to form the focus pattern on the scribe line. For example, as shown in a hatched portion in FIG. 7, a focus pattern may be formed on a common device such as a capacitor 22 provided in each chip 21 partitioned by a scribe line 20, and shown in a hatched portion in FIG. like,
It is not limited to a common device such as a capacitor, but may be provided in a partial element isolation region 23 in each product. Further, as shown by a hatched portion in FIG. 9, a chip 24 dedicated to the focus pattern may be provided.

When a focus pattern is provided on the scribe line 20, the entire area of the scribe line 20 may be used as the focus pattern as shown by the hatched portion in FIG. 10, or the scribe line 2 as shown in FIG.
The focus pattern of the solid pattern 25 may be provided in 0. Further, as shown in FIG. 12, a region 26 where a pattern is not formed in each product may be used as a focus pattern.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of the semiconductor device following FIG. 1;

FIG. 3 is a view illustrating a manufacturing step of the semiconductor device following FIG. 2;

FIG. 4 is a view illustrating a manufacturing step of the semiconductor device following FIG. 3;

FIG. 5 is a view illustrating a manufacturing step of the semiconductor device following FIG. 4;

FIG. 6 is a diagram comparing focus heights when the average height differs for each product.

FIG. 7 is a diagram showing a layout example of a focus pattern shown in another embodiment.

FIG. 8 is a diagram showing a layout example of a focus pattern shown in another embodiment.

FIG. 9 is a diagram showing a layout example of a focus pattern shown in another embodiment.

FIG. 10 is a diagram showing a layout example of a focus pattern shown in another embodiment.

FIG. 11 is a diagram showing a layout example of a focus pattern shown in another embodiment.

FIG. 12 is a diagram showing a layout example of a focus pattern shown in another embodiment.

13A and 13B show elements formed in the composite IC, wherein FIG. 13A shows a layout and a cross-sectional configuration of a bipolar transistor, FIG. 13B shows a layout and a cross-sectional configuration of a MOS transistor, (C) is a diagram showing a layout and a cross-sectional configuration of the LDMOS.

FIG. 14 is a diagram for explaining line width variation between a product having a low average height and a product having a high average height.

FIG. 15A is a diagram showing the work of the line width before focus correction, and FIG. 15B is a diagram showing the work of the line width after focus correction.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... n-type well layer, 6 ... Poly-S
i-layer, 7, 13, 15, 17, 19 ... resist, 12,
16: interlayer insulating film, 14: first wiring layer, 18: second wiring layer.

Claims (8)

[Claims] A resist (7, 1) is formed on a semiconductor substrate (1).
3, 15, 17, 19), the resist (7, 13, 15, 17, 19, 19) is focused, transferred and developed to form the resist (7, 1, 17).
3, 15, 17, and 19) are prepared as predetermined patterns, and the resist (7) is applied to each of a plurality of types of semiconductor substrates (1) on which different products are formed using the same photolithography apparatus. , 13, 1
5, 17 and 19), wherein the plurality of types of semiconductor substrates (1) have the same height at desired positions on the semiconductor substrate (1). A method for manufacturing a semiconductor device, comprising: providing a focus pattern; and adjusting the focus based on the focus pattern. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the focus pattern is formed by laminating all films formed on the plurality of types of semiconductor substrates. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said focus pattern is formed on a scribe line of said semiconductor substrate. 4. The method according to claim 3, wherein the focus pattern is formed over the entire area of the scribe line. 5. The method according to claim 3, wherein the focus pattern is formed as a solid pattern (25) in the scribe line (20). 6. The method according to claim 1, wherein a capacitor (22) formed in common with the plurality of types of semiconductor substrates (1) is used as the focus pattern. 7. The semiconductor device according to claim 1, wherein the focus pattern is formed on a part (23) of each chip (21) defined by a scribe line (20) of the semiconductor substrate (1). 13. The method for manufacturing a semiconductor device according to item 5. 8. The semiconductor device according to claim 1, wherein a part of a plurality of chips defined by scribe lines of the semiconductor substrate is used as the focus pattern. The manufacturing method of the semiconductor device described in the above.