KR100205221B1 - Method of manufacture having resistance layer of high and low resistance - Google Patents
Method of manufacture having resistance layer of high and low resistance Download PDFInfo
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- KR100205221B1 KR100205221B1 KR1019960020842A KR19960020842A KR100205221B1 KR 100205221 B1 KR100205221 B1 KR 100205221B1 KR 1019960020842 A KR1019960020842 A KR 1019960020842A KR 19960020842 A KR19960020842 A KR 19960020842A KR 100205221 B1 KR100205221 B1 KR 100205221B1
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- South Korea
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- polysilicon film
- pattern
- resistance
- film
- lower polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 82
- 229920005591 polysilicon Polymers 0.000 claims abstract description 82
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 12
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 238000000206 photolithography Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 92
- 239000010410 layer Substances 0.000 description 26
- 239000003990 capacitor Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 소오스/드레인용 이온주입을 위한 포토레지스트 패턴을 형성할 때, 고저항으로 계속 유지할 하부 폴리실리콘막 패턴을 제외한 저저항으로 전환을 하부 폴리실리콘막 패턴상에도 형성한 후 이러한 포토레지스트 패턴을 마스크로 소오스/드레인용 이온주입을 실시하기 때문에 소오스/드레인영역이 형성됨과 아울어 저, 고저항의 하부 폴리실리콘막 패턴이 구분된다.어In the present invention, when a photoresist pattern for ion implantation for a source / drain is formed, a low resistance is also formed on the lower polysilicon film pattern except for the lower polysilicon film pattern to be maintained at a high resistance, The source / drain regions are formed and the low and high resistance lower polysilicon film patterns are distinguished.
따라서, 본 발명은 고, 저 저항의 하부 폴리실리콘막 패턴을 구분하기 위해 별도의 포토공정을 추가하지 않고 소오스/드레인을 위한 선택적 이온주입공정만을 이용하여 고,저저항의 하부 폴리실리콘막 패턴을 구분할 수 있으므로 그만큼 공정 단순화가 가능하다.Therefore, the present invention is directed to a method of manufacturing a high and low resistance lower polysilicon film pattern using only a selective ion implantation process for a source / drain without adding a separate photolithography process to distinguish the high and low resistance lower polysilicon film patterns. It is possible to simplify the process.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 단순한 공정으로 서로 다른 저항의 폴리실리콘 저항층을 제저할 수 있도록 한 고저항과 저저항의 저항층을 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a resistance layer of a high resistance and a low resistance so that a polysilicon resistance layer having different resistances can be removed by a simple process.
반도체 집적회로는 수많은 트랜지스터와 저항(저항층)으로 구성된다. 일반적으로 반도체 메로리 소자에 있어서, 저항층은 회로상에서 시간지연(time delay)의 목적으로 사용되며, 이런하 목적을 달성하기 위햐 저항층은 안정된 저항값, 즉 균일한 저항값을 유지할 수 있어야 한다.Semiconductor integrated circuits consist of many transistors and resistors (resistance layers). Generally, in a semiconductor memory device, a resistance layer is used for the purpose of time delay on a circuit, and the resistance layer must be able to maintain a stable resistance value, that is, a uniform resistance value, in order to achieve such a lower purpose.
한편, 아날로그(analog)소자는 통상적으로 폴리실리콘막을 이중으로 적층하는 구조를 사용하는데, 상부 폴리실리콘막은 트랜지스터의 게이트전국과 박막 캐패 시터의 상부전극으로 사용하고, 하부 폴리실리콘막은 박막 캐패시터의 하부전극 또는 저항층으로 사용한다. 따라서, 폴리실리콘막의 단위면적당 저항값은 일정한 하나의 값을 가지게 된다.On the other hand, an analog device typically uses a structure in which a polysilicon film is stacked in a double layer, wherein the upper polysilicon film is used as the gate whole of the transistor and the upper electrode of the thin film capacitor, and the lower polysilicon film is used as the lower electrode of the thin film capacitor Or as a resistive layer. Therefore, the resistance value per unit area of the polysilicon film has a constant value.
그런데, 아날로그 소자는 다양한 저항값을 갖는 저항층을 요구하기 때문에, 여러 종류의 저항층을 직렬 또는 병렬로 연결하여 사용하여야 한다. 이와 같이 다양한 저항값을 갖는 저하층이 필요하게 되는 경우, 저항층이 많은 면적을 차지하게 되어 칩사이는 증가한다.However, since the analog device requires a resistance layer having various resistance values, it is necessary to connect a plurality of resistance layers in series or in parallel. If a lowering layer having various resistance values is required in this way, the resistance layer occupies a large area and increases between the chips.
그러나, 종래의 아날로그 소자의 제조방법에 의하면 다양한 저항층, 예컨대 고저항의 저항층을 제조하기 위하여 저항층을 구성하는 폴리실리콘막 상에 또다른 폴리실리콘막을 형성하거나, 상기 폴리실리콘막 상에 별도의 불순물 주입용 마스크 패턴을 형성한 후 불순물을 이온주입해야 한다. 이렇게되면, 폴리실리콘막을 형성하는 공정이 추가되거나 불순물을 주입하기 위한 마스크 공정이 추가되는 문제점이 있다.However, according to the conventional method of manufacturing an analog device, another polysilicon film is formed on the polysilicon film constituting the resistive layer to form various resistive layers, for example, a resistive layer of high resistance, It is necessary to implant the impurity ions after forming the impurity implantation mask pattern. In this case, a process for forming a polysilicon film is added or a mask process for implanting impurities is added.
따라서, 본 발명의 목적은 단순한 공정으로 고저항과 저저항의 하부 폴리실리콘 저항층을 구분하여 형성할 수 있도록 한 반도체 소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a lower polysilicon resistance layer having a high resistance and a low resistance can be separately formed by a simple process.
제1도 내지 제5도는 본 발명에 의한 고저항과 저저항의 저항층(resistor)을 갖는 반도체 소자의 제조방법을 설명하기 위한 단면공정도.FIGS. 1 to 5 are cross-sectional process diagrams for explaining a method of manufacturing a semiconductor device having a resistor having a high resistance and a low resistance according to the present invention.
이와 같은 목적을 달성하기 위한 본 발명에 의한 고저항과 저저항의 저항층을 갖는 반도체 소자의 제조방법은 반도체 기판의 정해진 영역에 필드산화막을 형성하여 활성영역과 비활성영역을 한정하는 단계; 상기 필드산화막을 포함한 상기 반도체 기판의 전면에 하부 폴리실리콘막을 적층하는 단계; 상기 하부 폴리실리콘막에 저항조절용으로 불순물울 이온주입하는 단계; 상기 하부 폴리실리콘막 상에 유전체막을 형성하는 단계; 상기 유전체막 및 하부 폴리실리콘막을 선택적으로 식각하여 상기 필드산화막 상에 저항층으로 이용되는 하부 폴리실리콘막 패턴과 유전체막 패턴을 형성하는 단계; 상기 반도체 기판의 활성영역 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막을 포함한 반도체 기판의 전면에 상부 폴리실리콘막을 적층하는 단계; 상기 상부 폴리실리콘막의 원하는 부분을 선택적으로 식각하여 상기 활성영역의 게이트 산화막 상에 상부 폴리실리콘막 패턴의 게이트 전극을 형성하는 단계; 상기 하부 폴리실리콘막 중 저저항용 하부 폴리실리콘막 패턴을 노출시키고 나머지 하부 폴리실리콘막 패턴을 마스킹하며 또한 소오스/드레인영역을 위한 영역을 노출시키는 포토레지스트 패턴을 형성하는 단계; 그리고 상기 포토레지스트 패턴을 마스크로 소오스/드레인용 불순물을 선택적으로 이온주입하여 소오스/드레인영역을 형성함과 아울러 저저항의 하부 폴리실리콘막 패턴과 고저항의 하부 폴리실리콘막 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device having a high-resistance and low-resistance resistive layer, the method comprising: forming a field oxide film in a predetermined region of a semiconductor substrate to define an active region and an inactive region; Stacking a lower polysilicon film on the entire surface of the semiconductor substrate including the field oxide film; Implanting impurity ions into the lower polysilicon film for resistance control; Forming a dielectric film on the lower polysilicon film; Selectively etching the dielectric film and the lower polysilicon film to form a lower polysilicon film pattern and a dielectric film pattern used as a resistive layer on the field oxide film; Forming a gate oxide film on the active region of the semiconductor substrate; Stacking an upper polysilicon film on the entire surface of the semiconductor substrate including the gate oxide film; Selectively etching a desired portion of the upper polysilicon film to form a gate electrode of the upper polysilicon film pattern on the gate oxide film of the active region; Forming a photoresist pattern exposing a low-resistance lower polysilicon film pattern of the lower polysilicon film and masking the remaining lower polysilicon film pattern and exposing a region for a source / drain region; Then, a source / drain region is formed by selectively ion-implanting impurities for a source / drain using the photoresist pattern as a mask, and a lower polysilicon film pattern having a low resistance and a lower polysilicon film pattern having a high resistance are formed .
상기 소오스/드레인용 불순물은 비소, 인 또는 붕소를 이용할 수 있다. 상기 상부 폴리실리콘막을 형성하는 단계 후에 상기 상부 폴리실리콘막 상에 저저항 물질층, 예컨대 텅스텐실리사이드막을 형성하고, 저저항 물질층과 상부 폴리실리콘막을 선택적으로 식각하여 저저항 물질층의 패턴과 상부 폴리실리콘막 패턴의 적층구조로 이루어진 게이트 전극을 형성할 수도 있다.The impurity for the source / drain may be arsenic, phosphorus, or boron. After forming the upper polysilicon film, a low resistance material layer such as a tungsten silicide film is formed on the upper polysilicon film, and the low resistance material layer and the upper polysilicon film are selectively etched to form a pattern of the low resistance material layer, A gate electrode made of a laminated structure of a silicon film pattern may be formed.
따라서, 본 발명에 의하면, 저저항과 고저항의 저항층을 갖는 하부 폴리실리콘막 패턴의 제조공정을 단순화할 수 있다.Therefore, according to the present invention, it is possible to simplify the manufacturing process of the lower polysilicon film pattern having the resistive layer of low resistance and high resistance.
이하, 본 발명에 의한 저저항과 고저항의 저항층을 갖는 반도체소지자의 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a method for manufacturing a semiconductor holder having a low-resistance and high-resistance resistance layer according to the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제5도는 본 발명에 의한 고저항과 저저항의 저항층을 갖는 반도체 소자의 제조방법을 설명하기 위한 단면 공정도이다.FIGS. 1 to 5 are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device having a high-resistance and low-resistance resistive layer according to the present invention.
제1도는 반도체 기판(1)에 하부 폴리실리콘막(3) 및 유전체막(7)을 형성하는 단계를 나타낸다.FIG. 1 shows a step of forming a lower polysilicon film 3 and a dielectric film 7 on a semiconductor substrate 1.
구체적으로, 반도체 기판(1)에 정해진 영역에 필드산화막(2)을 형성하여 활성영역 및 비활성영역으로 구분한다. 이어서, 필드산화막(2)을 포함한 반도체기판(10)의 전면에 저항층으로 이용할 하부 폴리실리콘막(3)을 적층한다. 하부 폴리실리콘막(3)은 도면에 도시하지는 않았지만 박막 캐패시터의 하부전극으로도 이용된다.Specifically, the field oxide film 2 is formed in a region defined in the semiconductor substrate 1 and is divided into an active region and an inactive region. Then, a lower polysilicon film 3 to be used as a resistive layer is laminated on the entire surface of the semiconductor substrate 10 including the field oxide film 2. Then, The lower polysilicon film 3 is also used as a lower electrode of a thin film capacitor (not shown).
이어서, 하부 폴리실리콘막(3) 상에 n형 불순물 이온(5), 예컨대 비소이온을 이온주입함으로써 하부 폴리실리콘막(3)의 저항 특성을 원하는 값으로 조절한다. 계속하여, 하부 폴리실리콘막(3) 상에 산화막/질화막/산화막(ONO)의 적층구조 또는 질화막/산화막(NO)의 적층구조를 갖는 유전체막(7)을 형성한다.Then, the resistance characteristic of the lower polysilicon film 3 is adjusted to a desired value by implanting n-type impurity ions 5, such as arsenic ions, on the lower polysilicon film 3. [ Subsequently, a dielectric film 7 having a laminated structure of an oxide film / a nitride film / an oxide film (ONO) or a laminated structure of a nitride film / an oxide film (NO) is formed on the lower polysilicon film 3.
제2도는 유전체막 패턴(7a) 및 하부 폴리실리콘막 패턴(3a), (3b)을 형성하는 단계를 나타낸다.FIG. 2 shows the step of forming the dielectric film pattern 7a and the lower polysilicon film patterns 3a and 3b.
구체적으로, 사진식각공정을 이용하여 유전체막(7) 및 하부 폴리실리콘막(3)의 원하는 부분을 활성영역의 반도체기판(1)의 표면이 노출될 때까지 차례로 이방성식각하여 필드산화막(2) 상에 유전체막 패턴(7a) 및 하부 폴리실리콘막 패턴(3a)의 적층구조와, 유전체막 패턴(7a) 및 하부 폴리실리콘막 패턴(3b)의 적층구조를 각각 형성한다.Specifically, a desired portion of the dielectric film 7 and the lower polysilicon film 3 is successively subjected to anisotropic etching until the surface of the semiconductor substrate 1 of the active region is exposed using the photolithography process to form the field oxide film 2, A laminated structure of the dielectric film pattern 7a and the lower polysilicon film pattern 3a and a laminated structure of the dielectric film pattern 7a and the lower polysilicon film pattern 3b are formed on the substrate 1.
제3도는 상부 폴리실리콘막(9) 및 텅스텐실리사이드막(11)을 형성하는 단계를 나타낸다.FIG. 3 shows the step of forming the upper polysilicon film 9 and the tungsten silicide film 11.
구체적으로, 유전체막 패턴(7a) 및 하부 폴리실리콘막 패턴(3a,3b)에 의하여 마스킹되지 않은, 노출된 반도체기판(1)의 활성영역에 게이트 산화막(8)을 형성한다. 이어서, 게이트 산화막(8)을 포함한 반도체 기판(1)의 전면에 불순물이 도핑된 폴리실리콘막을 형성하여 상부 폴리실리콘막(9)을 형성한다. 여기서, 상부 폴리실리콘막(9)은 도시하지는 않았지만 박막 캐패시터의 상부전극으로도 이용된다.Specifically, the gate oxide film 8 is formed in the active region of the exposed semiconductor substrate 1 which is not masked by the dielectric film pattern 7a and the lower polysilicon film patterns 3a and 3b. Then, an impurity-doped polysilicon film is formed on the entire surface of the semiconductor substrate 1 including the gate oxide film 8 to form an upper polysilicon film 9. Here, the upper polysilicon film 9 is also used as an upper electrode of a thin film capacitor (not shown).
그런 다음, 후에 형성될 게이트 전극의 저항을 줄이기 위하여 상부 폴리실리콘막(9)상에 저저항의 물질층, 예를 들어 텅스텐실리사이드막(WSi)(11)을 증착한다.Then, a low-resistance material layer such as a tungsten silicide film (WSi) 11 is deposited on the upper polysilicon film 9 to reduce the resistance of the gate electrode to be formed later.
제4도는 게이트 전극의 텅스텐실리사이드(11a)와 상부 폴리실리콘막 패턴(9a)을 형성하는 단계를 나타낸다.FIG. 4 shows the step of forming the tungsten silicide 11a of the gate electrode and the upper polysilicon film pattern 9a.
구체적으로, 사진식각공정에 의해 텅스텐실리사이드막(WSi)(11)과 상부 폴리실리콘막(9)의 원하는 부분을 차례로 건식식각하여 활성영역의 게이트 산화막(8)상에 텅스텐실리사이드 패턴(11a)과 상부 폴리실리콘막 패턴(9a)의 적층구조를 형성한다. 이때, 하부 폴리실리콘막 패턴(3a),(3b)의 상부에 형성된 상부 폴리실리콘막(9) 및 텅스텐실리사이드막(11)도 완전히 식각된다.Specifically, a desired portion of the tungsten silicide film (WSi) 11 and the upper polysilicon film 9 is dry-etched sequentially by a photolithography process so that a tungsten silicide pattern 11a and a tungsten silicide film 11b are formed on the active region gate oxide film 8, Thereby forming a laminated structure of the upper polysilicon film pattern 9a. At this time, the upper polysilicon film 9 and the tungsten silicide film 11 formed on the upper portions of the lower polysilicon film patterns 3a and 3b are also completely etched.
여기서, 텅스텐 실리사이드 패턴(11a) 및 상부 폴리실리콘막 패턴(9a)은 반도체 소자의 게이트 전극으로서 이용된다.Here, the tungsten silicide pattern 11a and the upper polysilicon film pattern 9a are used as a gate electrode of a semiconductor device.
제5도는 소오스 및 드레인용 이온주입을 실시하는 단계를 나타낸다.FIG. 5 shows the step of performing ion implantation for the source and drain.
구체적으로, 활성영역의 소오스/드레인영역을 선택적으로 이온주입하기 위한 마스크로서 상기 결과 구조의 반도체기판 상에 포토레지스트 패턴(13)을 형성한다. 이때, 포토레지스트 패턴(13)을 하부 폴리실리콘막 패턴(3a),(3b) 중에서 하나의 하부 폴리실리콘막 패턴(3b)이 형성된 영역의 상부에도 형성되도록 한다.Specifically, a photoresist pattern 13 is formed on the resultant structure semiconductor substrate as a mask for selectively ion-implanting the source / drain regions of the active region. At this time, the photoresist pattern 13 is formed on the upper part of the region where one lower polysilicon film pattern 3b is formed among the lower polysilicon film patterns 3a and 3b.
이어서, 포토레지스트 패턴(13)을 마스크로 하여 반도체 기판(1)의 전면에 소오스 및 드레인용 불순물(15)을 이온주입한다. 이때, 포토레지스트 패턴(13)에 의해 마스킹되지 않고 노출된 하부 폴리실리콘막 패턴(3a)이 이온주입되어 저저항으로 전환되고, 포토레지스트 패턴(13)에 의해 마스킹된 하부 폴리실리콘막 패턴(3b)은 전혀 이온주입되지 않아 고저항으로 유지된다.Subsequently, impurities 15 for source and drain are ion-implanted into the entire surface of the semiconductor substrate 1 using the photoresist pattern 13 as a mask. At this time, the lower polysilicon film pattern 3a exposed without being masked by the photoresist pattern 13 is ion-implanted and converted to a low resistance, and the lower polysilicon film pattern 3b (which is masked by the photoresist pattern 13) ) Is not implanted at all and is maintained at a high resistance.
따라서, 하부 폴리실리콘막 패턴(3a),(3b)은 별도의 포토마스크층의 추가 형성없이 소오스 및 드레인용 포토레지스트 패턴(13)을 이용하여 저저항의 하부 폴리실리콘막 패턴(3a) 및 고저항의 폴리실리콘막 패턴(3b)으로 구분되므로 공정 단순화가 가능하다.Therefore, the lower polysilicon film patterns 3a and 3b can be formed by using the photoresist pattern 13 for source and drain without forming additional photomask layers, And the polysilicon film pattern (3b) of the resistance.
한편, 상기 소오스 및 드레인용 불순물로는 PMOS 또는 NMOS트랜스터용에 이용되는 붕소 또는 비소가 적용될 수 있다.The impurities for the source and drain may be boron or arsenic used for PMOS or NMOS transducers.
계속하여, 상기 결과 구조의 반도체 기판의 전면에 콘택홀을 갖는 충간절연막(도시 안됨)과 패드 전극(도시 안됨)을 형성하여 본 발명의 반도체 소자를 완성한다.Subsequently, an insulating interlayer (not shown) and a pad electrode (not shown) having contact holes are formed on the entire surface of the resultant structure of the semiconductor substrate to complete the semiconductor device of the present invention.
이상에서 살펴본 바와 같이, 본 발명에 의한 반도체 소자의 제조방법은 소오스/드레인용 이온주입을 위한 포토레지스트 패턴을 형성할 때, 고저항으로 계속 유지할 하부 폴리실리콘막 패턴을 제외한 저저항으로 전환할 하부 폴리실리콘막 패턴상에도 형성한 후 이러한 포토레지스트 패턴을 마스크로 소오스/드레인용 이온주입을 실시하여 때문에 소오스/드레인영역이 형성됨과 아울러 저, 고저항의 하부 폴리실리콘막 패턴이 구분된다.As described above, in the method of manufacturing a semiconductor device according to the present invention, when a photoresist pattern for ion implantation for a source / drain is formed, the lower polysilicon film pattern After forming the polysilicon film on the polysilicon film pattern, ion implantation for the source / drain is performed using the photoresist pattern as a mask, so that the source / drain regions are formed and the lower polysilicon film pattern of low resistance and high resistance is distinguished.
따라서, 본 발명은 고, 저 저항의 하부 폴리실리콘막 패턴을 구분하기 위해 별도의 포토공정을 추가하지 않고 소오스/드레인을 위한 선택적 이온주입공정만을 이용하여 고,저저항의 하부 폴리실리콘막 패턴을 구분할 수 있으므로 그만큼 공정 단순화가 가능하다.Accordingly, the present invention is directed to a method of fabricating a high and low resistance lower polysilicon film pattern using only a selective ion implantation process for a source / drain without adding a separate photolithography process to distinguish the high and low resistance lower polysilicon film patterns. It is possible to simplify the process.
또한, 후속 이온주입공정은 액티브 영역의 이온주입공정, 예컨대 소스 및 드레인 플로그의 이온주입공정으로 할 수 도 있다.Further, the subsequent ion implantation process may be an ion implantation process of the active region, for example, an ion implantation process of the source and drain flaps.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상내에서 당 분야의 통상의 지식을 가진 자에 의해 변형, 개선 가능함은 물론이다.It is to be understood that the present invention is not limited to the above-described embodiment, and variations and modifications may be made by those skilled in the art without departing from the scope of the present invention.
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