KR100190002B1 - Semiconductor device having resistor and capacitor and method of manufacturing the same - Google Patents
Semiconductor device having resistor and capacitor and method of manufacturing the same Download PDFInfo
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- KR100190002B1 KR100190002B1 KR1019950066838A KR19950066838A KR100190002B1 KR 100190002 B1 KR100190002 B1 KR 100190002B1 KR 1019950066838 A KR1019950066838 A KR 1019950066838A KR 19950066838 A KR19950066838 A KR 19950066838A KR 100190002 B1 KR100190002 B1 KR 100190002B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
- H01L27/0682—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors comprising combinations of capacitors and resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
저항과 캐패시터를 함께 구비하는 반도체 소자 및 그 제조방법에 대해 기재되어 있다.Disclosed are a semiconductor device including a resistor and a capacitor, and a method of manufacturing the same.
이는, 반도체기판 상에 형성되며, 캐패시터의 하부전극으로 공유되는 저항층, 저항층의 상부 표면에 형성된 유전체막 및 유전체막 상부 및 저항층의 측면을 감싸는 형태의 캐패시터의 상부전극을 구비하는 것을 특징으로 한다.It is formed on the semiconductor substrate, characterized in that it comprises a resistor layer which is shared by the lower electrode of the capacitor, a dielectric film formed on the upper surface of the resistive layer and the upper electrode of the capacitor of the type surrounding the upper side of the dielectric film and the resistive layer. It is done.
따라서, 저항층의 침해를 방지할 수 있어, 공정의 안정화 및 수율향상을 도모할 수 있다.Therefore, the invasion of the resistive layer can be prevented, and the process can be stabilized and the yield can be improved.
Description
제1도 내지 제3도는 종래의 저항과 캐패시터를 구비하는 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device having a resistor and a capacitor.
제4도는 본 발명에 의한 반도체 소자를 제조하기 위한 간략한 레이아웃드이다.4 is a simplified layout for manufacturing a semiconductor device according to the present invention.
제5도 내지 제9도는 본 발명에 의한 저항과 캐패시터를 구비하는 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다.5 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a resistor and a capacitor according to the present invention.
본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 특히 저항과 캐패시터를 함께 구비하는 반도체 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a resistor and a capacitor and a method for manufacturing the same.
반도체 집적회로는 수많은 트랜지스터와 저항층으로 구성된다.Semiconductor integrated circuits consist of numerous transistors and resistive layers.
일반적으로 반도체 메모리 소자에 있어서 저항층은, 회로상에서 시간지연(time delay)의 목적으로 사용되며, 이러한 목적을 달성하기 위해 저항층은 안정된 저항값, 즉 균일한 저항값을 유지할 수 있어야 한다.In general, in a semiconductor memory device, a resistive layer is used for the purpose of time delay on a circuit, and in order to achieve this object, the resistive layer must be able to maintain a stable resistance value, that is, a uniform resistance value.
반도체 장치가 고집적화되면서 그 구성요소, 즉 트랜지스터 및 저항은 매우 작게 형성하여야 한다. 그러나, 반도체 집적회로에 고저항이 필요할 경우에는 저항값을 증가시키기 위하여 저항층의 길이를 매우 길게 형성하여야 하므로 넓은 면적을 차지하게 되어 반도체 장치의 집적도를 증가시키는 데 어려움을 준다. 저항층으로는 주로 활성영역에 불순물울 도우프시켜 형성하는 확산저항이나 폴리실리콘층에 불순뭍을 도우프시켜 형성하는 폴리실리콘 저항을 사용한다.As semiconductor devices become highly integrated, their components, i.e. transistors and resistors, must be made very small. However, when a high resistance is required in a semiconductor integrated circuit, the length of the resistance layer must be formed very long in order to increase the resistance value, thus occupying a large area, thereby increasing the degree of integration of the semiconductor device. As the resistive layer, a diffusion resistor formed by doping impurities in the active region or a polysilicon resistor formed by doping impurities in the polysilicon layer is used.
반도체 소자가 고집적화되어 감에 따라 게이트전극의 경우 저항을 줄이기 위하여 저항의 물질을 게이트전극 물질로 사용함으로써, 일정 수준의 저항을 필요로 하는 저항층으로서 적합하지 앞게 되고 있다. 즉, 소자가 고집적화되어감에 따라 트랜지스터로서 제 역할을 다하기 위해서는, 소자의 동작속도를 높이기 위해 저저항의 물질, 예를 들면 불순물이 도우프된 폴리실리콘에 텅스텐 실리사이드(WSix), 타타늄 실리사이드(TiSix) 또는 몰리브덴 실리사이드(MoSi) 등과 같이 저항이 낮은 물질을 사용하여야 하지만, 이는 저항층이 형성되어야 할 면적을 매우 크게 만들뿐만 아니라, 후속 열처리에 따라서 매우 큰 변화를 가져오게 된다.As semiconductor devices are becoming highly integrated, in the case of gate electrodes, a resistive material is used as the gate electrode material to reduce the resistance, thereby becoming unsuitable as a resistive layer requiring a certain level of resistance. That is, in order to function as a transistor as the device is highly integrated, tungsten silicide (WSix) and titanium silicide are applied to a low-resistance material, for example, polysilicon doped with impurities to increase the operation speed of the device. Low resistance materials such as (TiSix) or molybdenum silicide (MoSi) should be used, but this not only makes the area on which the resistance layer should be formed very large, but also causes a very large change in the subsequent heat treatment.
종래의 아날로그(analog) 공정은 통상적으로 폴리실리콘을 이중으로 적층하는 구조를 사용하는데, 상부 폴리실리콘층은 게이트전극으로 사용하고 하부 폴리실리콘층은 박막 캐패시터의 하부전극 또는 저항층으로 사용한다.Conventional analog processes typically employ a structure in which polysilicon is stacked in duplicate, wherein an upper polysilicon layer is used as a gate electrode and a lower polysilicon layer is used as a lower electrode or a resistive layer of a thin film capacitor.
제1도 내지 제3도는 종래의 아날로그 구현을 위한 공정순서에 따른 단면도들이다.1 to 3 are cross-sectional views according to a process sequence for a conventional analog implementation.
제1도는 반도체기판(2)에 필드산화막(4)을 형성하여 활성영역 및 비활성영역으로 구분하고 그 결과물 상에 폴리실리콘(6)을 소정 두께로 증착한 다음 불순물 이온을 주입함로써 하부 폴리실리콘층(6)의 저항특성을 조절하는 단계를 나타낸다.FIG. 1 shows the formation of a field oxide film 4 on the semiconductor substrate 2 to divide the active and inactive regions, deposit polysilicon 6 to a predetermined thickness on the resultant, and inject impurity ions into the lower polysilicon. Adjusting the resistance characteristic of the layer 6 is shown.
제2도는 상기 하부 폴리실리콘층(6)상에 산화막/ 질화막/산화막(ONO) 구조 또는 질화막/산화막(NO) 구조로 절연층을 적층하여 캐패시터의 유전체막(8)을 형성한 후, 상기 하부 폴리실리콘층 및 유전체막을 패터닝하는 단계를 나타낸다.2 shows an insulating layer stacked on the lower polysilicon layer 6 in an oxide film / nitride / oxide film (ONO) structure or a nitride film / oxide film (NO) structure to form a dielectric film 8 of a capacitor. Patterning a polysilicon layer and a dielectric film is shown.
제3도는 상기 결과물 상에 불순물이 도우프된 폴리실리콘(10)을 증착한 후, 게이트 전극의 저항을 줄이기 위하여 상기 상부 폴리실리콘층(10)상에 저저항의 물질, 예를들어 텅스텐 실리사이드(WSi)(12)를 증착한 다음, 상기 텅스덴 실리사이드(WSi)(12) 및 폴리실리콘층(10)을 차례로 건식식각하여 폴리사이드 구조의 게이트전극을 형성하는 단계를 나타낸다.FIG. 3 shows a low-resistance material such as tungsten silicide on the upper polysilicon layer 10 in order to reduce the resistance of the gate electrode after depositing the doped polysilicon 10 on the resultant. After the deposition of the WSi) 12, the tungsten suicide 12 and the polysilicon layer 10 are sequentially etched to form a gate electrode having a polyside structure.
상기 폴리사이드 구조의 게이트를 패터닝하기 위하여 건식식각할 때, 로딩 효과(loading effect)에 의해 부분적으로 식각되지 않은 부분이 발생할 가능성이 있으며, 이를 방지하기 의해 통상적으로 충분한 과도식각(over-etch)이 병행된다. 이 때, 로딩효과에 의해 식각이 많이 되는 부분에서는 하부 폴리실리콘층이 식각되는 등의 침해가 발생하게 된다(제3도의 참조부호 A)이러한 현상은 저항층으로 사용되는 하부 폴리실리콘층의 저항값이 로트(lot)별, 웨이퍼별, 동일 웨이퍼 내의 부위별 산포가 불균일하여 제품의 불량이 발생하는 주요한 원인이 되고 있다. 특히, 상부 폴리실리콘층 상부에 텅스텐 실리사이드(WSix)를 증착할 경우 텅스텐 실리사이드(WSix)와 폴리실리콘의 식각선택비가 크지 않기 때문에(텅스덴 실리사이드 : 폴리실리콘 = 1 : 2 정도), 하부 폴리실리콘의 침해현상은 더욱 심해진다.When dry etching to pattern the gate of the polyside structure, there is a possibility that a part that is not partially etched may occur due to a loading effect, and thus, sufficient over-etch is usually performed by preventing the etching. Parallel. At this time, infringement such as the lower polysilicon layer is etched in a portion where the etching effect is large due to the loading effect (reference A of FIG. 3). This phenomenon is the resistance value of the lower polysilicon layer used as the resistive layer. Dispersion of these lots, wafers, and portions within the same wafer is a major cause of product defects. In particular, when the tungsten silicide (WSix) is deposited on the upper polysilicon layer, the etching selectivity of the tungsten silicide (WSix) and the polysilicon is not large (tungsten silicide: polysilicon = 1: 2). Infringement is even worse.
따라서, 본 발명의 목적은 게이트 괘터닝시 하부 폴리설리콘층의 침해를 방지하여 공정 안정화를 이룰 수 있는 구조의 반도체 소자를 제공함에 있다.Accordingly, an object of the present invention is to provide a semiconductor device having a structure capable of stabilizing a process by preventing intrusion of the lower polysilicon layer during gate rubbing.
상기 목적을 달성하기 위하여 본 발명에 의한 반도체 장치는, 반도체기판 상에 형성되며. 캐패시터의 하부전극으로 공유되는 저항층, 상기 저항층의 상부 표면에 형성된 유전체막 및 상기 유전체막 상부 및 상기 저항층의 측면을 감싸는 형태의 캐패시터의 상부전극을 구비하는 것을 특징으로 한다.In order to achieve the above object, the semiconductor device according to the present invention is formed on a semiconductor substrate. And a resistor layer shared by the lower electrode of the capacitor, a dielectric film formed on the upper surface of the resistor layer, and an upper electrode of the capacitor covering the top of the dielectric film and the side surface of the resistor layer.
여기서, 상기 저항층 및 캐패시티의 상부전극은 폴리실리콘으로 이루어진 것이 바람직하다.Here, the upper electrode of the resistive layer and the capacitor is preferably made of polysilicon.
또한, 상기 캐패시터의 상부전극은 폴리실리콘과 실리사이드가 적층된 구조인 것이 바람직하다.In addition, the upper electrode of the capacitor preferably has a structure in which polysilicon and silicide are stacked.
본 발명의 다른 목적은 공정의 안정화를 이룰 수 있는 구조의 반도체 소자의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method for manufacturing a semiconductor device having a structure capable of stabilizing the process.
상기 목적을 달성하기 위하여 본 발명에 의한 반도체 소자의 제조방법은, 반도체기판 상에 저항이 조절된 제1 도전층을 적층하여 저항층을 형성하는 단계, 상기 저항층 상에 절연물질을 증착하여 유전체막을 형성하는 단계, 상기 유전체막 및 저항층을 패터닝하는 단계, 결과물 상에 전면에 제2 도전층을 형성하는 단계 및 상기 유전체막 패턴 및 제1 폴리실리콘층 패턴을 감싸는 형태가 되도록 상기 제2 도전층을 패터닝하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention may include forming a resistance layer by stacking a first conductive layer having a resistance controlled on a semiconductor substrate, and depositing an insulating material on the resistance layer to form a dielectric. Forming a film, patterning the dielectric film and the resistive layer, forming a second conductive layer on the entire surface on the resultant, and enclosing the dielectric film pattern and the first polysilicon layer pattern. Patterning the layer.
여기서, 상기 제1 및 제2 도전층은 폴리실리콘으로 형성되는 것이 바람직하다.Here, the first and second conductive layers are preferably formed of polysilicon.
상기 제2 도전층은 폴리실리콘의 상부에 실리사이드층이 적층된 구조로 형성하는 것이 바람직하다.The second conductive layer is preferably formed of a structure in which a silicide layer is stacked on top of polysilicon.
본 발명에 따르면, 상부 폴리실리콘을 대상물로 하는 건식식각시 저항이 형성되는 부분에 상부 폴리실리콘층을 적층함으로써 하부 폴리실리콘층이 침해되는 현상을 방지할 수 있다.According to the present invention, by stacking the upper polysilicon layer on the part where the resistance during dry etching using the upper polysilicon as an object, it is possible to prevent the phenomenon of the lower polysilicon layer invading.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제4도는 본 발명에 의한 저항층을 제조하기 위한 간략한 레이아웃도이다.4 is a simplified layout diagram for manufacturing the resistive layer according to the present invention.
도면 참조부호 12는 하부 폴리실리콘층을 패터닝하기 위한 마스크패턴, 14는 상부 폴리실리콘층을 패터닝하기 의한 마스크패턴, 16은 저항층을 금속층과 연결하기 위한 접촉구를 형성하기 위한 마스크패턴을 각각 나타낸다.Reference numeral 12 denotes a mask pattern for patterning a lower polysilicon layer, 14 a mask pattern for patterning an upper polysilicon layer, and 16 a mask pattern for forming a contact hole for connecting a resistance layer with a metal layer, respectively. .
상기 레이아웃도에 따르면, 상부 폴리실리콘층의 폭이 하부 폴리실리콘층의 폭보다 넓게 레이아웃되어 실리사이드층의 건식식각시 상부 폴리실리콘층에 의해 하부 폴리실리콘층이 보호될 수 있도록 되어 있다.According to the layout diagram, the width of the upper polysilicon layer is laid out wider than the width of the lower polysilicon layer so that the lower polysilicon layer may be protected by the upper polysilicon layer during dry etching of the silicide layer.
구조rescue
제5a도 및 제5b도는 본 발명에 의한 반도체 장치의 저항층을 도시한 단면도로서, 제5a도는 상기 제4도의 a-a' 절단면을, 제5b도는 b-b' 절단면을 각각 도시한 것이다.5A and 5B are cross-sectional views showing a resistive layer of the semiconductor device according to the present invention, in which FIG. 5A shows a cut portion a-a 'in FIG. 4 and a cut portion b-b' in FIG. 5B.
도면참조 부호 20은 반도체기판, 22는 필드산화막, 24는 하부 폴리실리콘층, 26은 캐패시터의 유전체막, 28은 상부 폴리실리콘층, 30은 실리사이드를 각각 나타낸다.Reference numeral 20 denotes a semiconductor substrate, 22 a field oxide film, 24 a lower polysilicon layer, 26 a dielectric film of a capacitor, 28 a top polysilicon layer, and 30 a silicide.
본 발명에 의한 반도체 소자는, 반도체기판 상에 폴리실리콘으로 이루어지며, 캐패시터의 하부전극으로 공유되는 저항층(24)과, 상기 저항층의 상부 표면에 형성되며, ONO 또는 NO구조의 유전체막(26)과, 상기 유전체막 상부 및 상기 저항층의 측면을 감싸는 형태의 폴리실리콘으로 이루어진 캐패시터의 상부 전극(28)과, 상기 전극 상에 형성된 실리사이드층(30)으로 구성된다.The semiconductor device according to the present invention comprises a resistive layer 24 made of polysilicon on a semiconductor substrate and shared by a lower electrode of a capacitor, and formed on an upper surface of the resistive layer, and having an ONO or NO dielectric film ( 26), an upper electrode 28 of a capacitor made of polysilicon covering the upper side of the dielectric layer and the resistance layer, and a silicide layer 30 formed on the electrode.
도시된 바와 같이, 상기 저항층(24)은 상부전극(28)에 의해 캐핑되어 있다.As shown, the resistive layer 24 is capped by the upper electrode 28.
제조방법Manufacturing method
제6도 내지 제9도는 본 발명에 의한 반도체 장치의 저항층 형성방법을 설명하기 위하여 공정순서에 따라 도시한 단면도들이다.6 through 9 are cross-sectional views illustrating a method of forming a resistive layer of a semiconductor device according to the present invention, according to a process sequence.
제6도는 반도체기판(20)에 필드산화막(22)을 형성하여 활성영역 및 비활성영역으로 구분하고, 결과물 상에 저항층을 형성하기 위한 폴리실리콘(24)을 소정 두께로 증착한 다음, 상기 폴리실리콘에 불순물 이온을 주입함으로써 하부 폴리실리콘층의 저항특성을 조절하는 단계를 나타낸다.FIG. 6 illustrates forming a field oxide film 22 on the semiconductor substrate 20 to divide the active and inactive regions, depositing polysilicon 24 to form a resistive layer on the resultant, and then depositing the polysilicon 24 to a predetermined thickness. The step of controlling the resistance characteristics of the lower polysilicon layer by implanting impurity ions into the silicon.
제7도는 상기 하부 폴리실리콘층(24) 상에, 예컨대 산화막/질화막/ 산학막(ONO) 구조 또는 질학막/ 산화막(NO) 구조로 절연층을 적층하여 캐패시터의 유전체막(26)을 형성한후, 상기 하부 폴리실리콘층(24) 및 유전체막(26)을 패터닝하는 단계를 나타낸다.FIG. 7 illustrates a dielectric layer 26 of a capacitor formed by stacking an insulating layer on the lower polysilicon layer 24, for example, in an oxide film / nitride film / academic film (ONO) structure or a nitride film / oxide film (NO) structure. Afterwards, the lower polysilicon layer 24 and the dielectric layer 26 are patterned.
제8도는 게이트전극을 형성하기 의하여 상기 결과물 상에 불순물이 도우프된 폴리실리콘(28)을 증착한 후, 게이트전극의 저항을 줄이기 위하여 상기 상부 폴리실리콘층 상에 저저항의 물질, 예를 들어 텅스텐 실리사이드(WSi)(30)를 증착하는 단계를 나타낸다.8 illustrates the deposition of a polysilicon 28 doped with impurities on the resultant by forming a gate electrode, and then a low resistance material, for example, on the upper polysilicon layer to reduce the resistance of the gate electrode. Depositing tungsten silicide (WSi) 30.
여기서, 도시되지는 않았지만, 상기 상부 폴리실리콘층을 형성하기 전에 활성영역에 게이트 절연막을 형성한다. 이 때, 하부 폴리실리콘패턴의 측벽에도 절연막이 형성되어 상부 폴리실리콘(28)과 하부 폴리실리콘(24)이 절연된다.Although not shown, a gate insulating film is formed in an active region before forming the upper polysilicon layer. In this case, an insulating film is formed on the sidewalls of the lower polysilicon pattern to insulate the upper polysilicon 28 and the lower polysilicon 24 from each other.
제9도는 상기 텅스텐 실리사이드(WSi)(30) 및 상부 폴리실리콘층(28)을 차례로 건식식각함으로써, 게이트전극을 형성하는 단계를 나타낸다.FIG. 9 illustrates a step of forming a gate electrode by sequentially dry etching the tungsten silicide (WSi) 30 and the upper polysilicon layer 28.
이 때, 상기 상부 폴리실리콘층(28)이 유전체막(26) 및 하부 폴리실리콘층(24)을 감싸는 형태로 패터닝함으로써, 텅스텐 실리사이드(WSi)(30)와 상부 폴리실리콘(28)을 대상물로 하는 건식식각시 저항(28 : 또는 하부 폴리실리콘)이 형성되는 부분은, 상부 폴리실리콘층(28)이 캐핑층(capping layer)역할을 하여 상기 저항층(또는 하부 폴리실리콘층)(24)이 침해되는 현상을 방지할 수 있다.In this case, the upper polysilicon layer 28 is patterned in such a manner as to surround the dielectric layer 26 and the lower polysilicon layer 24, thereby making tungsten silicide (WSi) 30 and the upper polysilicon 28 target. Where the dry etching resistance 28 (or lower polysilicon) is formed, the upper polysilicon layer 28 acts as a capping layer (capping layer) so that the resistive layer (or lower polysilicon layer) 24 Infringement can be prevented.
상술한 본 발명에 의한 반도체 장치의 저항층 형성방법에 따르면, 상부 폴리실리콘층 패터닝시 저항이 형성될 부분에는 상부 폴리실리콘층이 하부 폴리실리콘층을 감싸는 형태로 패터닝함으로써, 상부 폴리실리콘층이 캐핑층(capping layer) 역할을 하여 하부 폴리실리콘층이 침해되는 현상을 방지할 수 있다. 또한, 향후 소자의 성능향상을 위한 실리사이드(salicide) 공정이 적용될 경우, 종래의 방법에 의해서는 폴리실리콘 저항 패턴의 실리사이데이션(silicidation)됨에 의해 고저항을 얻을 수가 없다. 따라서. 이러한 경우 폴리실리콘저항 패턴을 게이트 폴리에 의해 캐핑함으로써 고저항을 얻을 수가 있다.According to the method of forming a resistive layer of a semiconductor device according to the present invention, the upper polysilicon layer is formed by patterning the upper polysilicon layer to surround the lower polysilicon layer in a portion where resistance is to be formed during patterning of the upper polysilicon layer. By acting as a capping layer, the phenomenon that the lower polysilicon layer is invaded may be prevented. In addition, when a silicide process for improving performance of the device is applied in the future, high resistance may not be obtained by silicidation of the polysilicon resistance pattern by a conventional method. therefore. In such a case, high resistance can be obtained by capping the polysilicon resistance pattern with the gate poly.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상내에서 당 분야의 통상의 지식을 가진 자에 의해 가능함은 물론이다.The present invention is not limited to the above-described embodiments, and the present invention may be made by those skilled in the art within the technical idea to which the present invention pertains.
Claims (6)
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| KR101145569B1 (en) | 2003-06-03 | 2012-05-15 | 칼라한 셀룰러 엘.엘.씨. | Low pass filter and electronic device |
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