JPH11260682A - Formation of alignment mark and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of IC chips that can be taken from one semiconductor substrate, while maintaining alignment accuracy, by forming a first alignment mark on a lower layer and forming a second alignment mark on an upper layer at the same region in the subsequent process. SOLUTION: In a process of forming the emitter part of a transistor part, an oxide film 16c is newly formed by high-temperature heat treatment at the time of forming an emitter diffusion layer, and an alignment mark 14 is covered with oxide films 16 (16a, 16b and 16c) on the front side. Then, in a hole making process for forming the electrode part of the transistor part, a second alignment mark 20 is formed on the same region where the first alignment mark 14 existed. In a process of forming the electrode part of the transistor, a metal layer is aligned by using the alignment mark 20, and the electrode part 22 is formed. In the process of forming the cover film of the transistor part, the cover film 23 is aligned by using the alignment mark 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patterning method for forming a pattern image on a photosensitive substrate using an exposure apparatus in a manufacturing process of a semiconductor device or the like, and more particularly to a method for forming an alignment mark and a semiconductor using the same. The present invention relates to a device manufacturing method.

[0002]

2. Description of the Related Art FIG. 5 shows a layout of alignment marks on a semiconductor substrate of a reticle in a patterning method for performing alignment using a 1: 1 stepper of the conventional example.

In FIG. 5, an alignment mark is formed on a first layer of a semiconductor substrate 50. In the conventional example, an alignment mark (also referred to as an optical alignment target (OAT)) 51 formed on the first layer is deposited on the OAT 51 during a process step. Since the edge contrast is deteriorated and alignment cannot be performed, a new OAT is formed in another part of the semiconductor substrate in an intermediate step. 5
2 is an IC chip, and 53 is a reticle field.

[0004]

However, in the conventional method for forming an alignment mark of a stepper, a new alignment mark must be formed in the middle of the process, so that the area of the OAT in the semiconductor substrate increases ( In FIG. 5, two rows of OATs 51 are shown), which causes a problem that the number of IC chips to be removed per semiconductor substrate decreases, and further increases the man-hour for forming a new alignment mark. There were also problems.

[0005]

According to a first aspect of the present invention, there is provided a method of forming an alignment mark, comprising: forming a first alignment mark in a lower layer; It is characterized by forming a mark.

According to a second aspect of the present invention, there is provided a method of forming an alignment mark, wherein the shape of the second alignment mark formed at the same location is different from the shape of the first alignment mark. is there.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a second alignment mark is formed at the same position as the lower first alignment mark in a subsequent semiconductor device etching step. It is characterized by being formed simultaneously.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 4 relate to an embodiment of the present invention, and will be described below with reference to the drawings.

FIG. 1 is an arrangement view of an alignment mark on a reticle semiconductor substrate in a patterning method for performing alignment using a 1: 1 stepper according to an embodiment of the present invention. The alignment mark is also called an optical alignment target (OAT).

FIGS. 2 and 3 show a semiconductor process (a method of manufacturing a semiconductor device) when the present invention is applied to an example of an IC chip.
FIG. 2 is a diagram for explaining the semiconductor process shown in FIG. 2 and FIG.

FIG. 2A is a schematic cross-sectional view showing a step of forming a buried epitaxial wafer. A buried diffusion layer 12 and an epitaxial layer 1 are formed on a semiconductor substrate 11.
3 are formed, and in this step, a first alignment mark (first OAT) 14 is formed.

FIG. 2B is a schematic cross-sectional view showing a step of separating each cell (each IC element).
6a is an oxide film on the front side, and 17 is an oxide film on the back side. The alignment mark 14 is covered with an oxide film 16a on the front side.

FIG. 2C is a schematic cross section showing a step of forming a base portion of the transistor portion. Reference numeral 18 denotes a base diffusion layer. An oxide film 16b is newly formed by the high-temperature heat treatment at the time of forming the base diffusion layer in this step, and the alignment mark 14 is covered with the oxide film 16b on the front surface side.
Although the contrast of the edge of the alignment mark 14 slightly deteriorates, alignment is still possible.

FIG. 3A is a schematic cross-sectional view showing a step of forming an emitter section of the transistor section. Reference numeral 19 denotes an emitter diffusion layer. An oxide film 16c is newly formed by the high-temperature heat treatment at the time of forming the emitter diffusion layer in this step. As a result, the alignment mark 14 is
(16a, 16b, 16c), the contrast of the edge of the alignment mark 14 is greatly degraded, and the alignment is in a limit state.

FIG. 3B is a schematic cross-sectional view showing a step (etching step) of forming a hole for forming an electrode portion of a transistor portion, and 21 is a hole portion for forming an electrode portion. , 20 are alignment marks (second OATs) made in this step. As shown in FIG. 3B, the second alignment mark 20 is the first first alignment mark.
Are formed at the same place where the first alignment mark 14 was located, so that the edge contrast of the second alignment mark 20 can be restored to the same degree of accuracy as the first first alignment mark 14.
Moreover, since the alignment marks are formed at the same location, the area of the alignment mark occupying the semiconductor substrate does not increase.
There is no problem that the number of IC chips per chip is reduced. According to the present invention, the number of IC chips per semiconductor substrate can be increased by about 2 to 5% as compared with the conventional example. Further, since the second alignment mark 20 is formed at the same time as the step of forming a hole for forming the electrode part of the transistor part (etching step), there is no problem that the number of steps is increased.

FIG. 3C is a schematic cross-sectional view showing a step of forming an electrode portion of the transistor portion, and includes a metal layer (not shown).
Are aligned using the second alignment mark 20 to form the electrode portion 22 of the transistor portion. Since the second alignment mark 20 is used, the alignment accuracy of the electrode section 22 does not deteriorate.

FIG. 3D is a schematic cross section showing a step of forming a cover film of the transistor portion. Since the cover film 23 is aligned using the second alignment mark 20, highly accurate alignment can be performed. .

At the stage shown in FIG. 3D, the semiconductor wafer 10 includes a semiconductor substrate 11, a buried diffusion layer 12, an epitaxial layer 13, a first optical alignment target (first OAT), an isolation diffusion layer 15, and a surface. Oxide film 16 on the side, oxide film 17 on the back side, base diffusion layer 18, emitter diffusion layer 19, second optical alignment target (second OAT) 20, and perforation 21 for forming an electrode portion , An electrode section 22 and a cover film 23.

FIG. 1 shows the optical alignment target (first OAT) 14, which has been described with reference to FIGS.
Alternatively, FIG. 4 is a plan view illustrating a relationship between a (second OAT) 20 and the semiconductor wafer 10. 10 is a semiconductor wafer, 25 is an IC chip, 26 is a reticle field,
It is.

In the examples shown in FIGS. 1 to 3, the first alignment mark 14 in the lower layer is formed, and the second alignment mark 20 in the upper layer is formed at the same position in a subsequent step (etching step). However, the present invention is not limited to such a case, and a new third alignment mark may be formed using the second alignment mark 20 as an alignment mark. May be used as an alignment mark to form a new fourth alignment mark.

FIG. 4 illustrates the shape of an alignment mark according to an embodiment of the present invention. FIG. 4 (a)
Is an example in which a cross-shaped alignment mark is used, and the shape obtained by rotating the first alignment mark 30 shown on the right is the shape of the second alignment mark 31 shown on the left. 25 is an IC chip,
26 is a reticle field.

In FIG. 4B, the first alignment mark 30 shown on the right side has a cross shape, and the second alignment mark 32 shown on the left side has a vertical shape added to the cross shape. Shape. 25 is an IC chip,
26 is a reticle field.

As described above, in the method of forming an alignment mark, the shape of the second alignment mark and the shape of the first alignment mark formed at the same location are made different from each other, so that the alignment mark used in the process is formed. However, it is possible to easily identify whether the mark is the first alignment mark or the second alignment mark, and to prevent a decrease in yield due to misalignment.

[0024]

As described above, according to the method for forming an alignment mark according to the first aspect of the present invention, the first alignment mark of the lower layer is formed, and in the subsequent steps,
An upper layer second alignment mark is formed in the same place, whereby the IC per semiconductor substrate is ensured without increasing the area occupied by the alignment mark and ensuring alignment accuracy. The number of chips can be increased.

According to a second aspect of the present invention, there is provided a method of forming an alignment mark, wherein the shape of the second alignment mark and the shape of the first alignment mark formed at the same location are different from each other. is there. Therefore, it is easy to identify whether the alignment mark used in the process is the first alignment mark or the second alignment mark, and it is possible to prevent a decrease in yield due to misalignment. .

Further, according to a third aspect of the present invention, in the method of manufacturing a semiconductor device, a second alignment mark is formed at the same position as the lower first alignment mark in a subsequent semiconductor device etching step. It is characterized by being formed simultaneously. Therefore, the semiconductor substrate 1 can be manufactured without increasing the number of steps and while maintaining the alignment accuracy.
A method for manufacturing a semiconductor device capable of increasing the number of IC chips per chip can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for patterning an alignment mark according to an embodiment of the present invention, and is a plan view illustrating the relationship between an alignment mark and a semiconductor wafer.

FIGS. 2A and 2B are diagrams illustrating a semiconductor process in a case where an alignment mark patterning method according to an embodiment of the present invention is applied to an example of an IC chip. FIG. 2A illustrates a process of forming a buried epitaxial wafer. FIG. 2B is a schematic cross section showing a step of separating each cell (each IC element), and FIG. 2C is a schematic cross section showing a step of forming a base portion of a transistor section.

3A and 3B are diagrams illustrating a semiconductor process in a case where the patterning method of an alignment mark according to an embodiment of the present invention is applied to an example of an IC chip. FIG. 3A illustrates a process of forming an emitter of a transistor unit. (B) is a schematic cross section showing a step (photolithography step) of forming a hole for forming an electrode section of the transistor section, and (c) is a step of forming an electrode section of the transistor section. And (d) is a schematic cross section showing a step of forming a cover film of the transistor portion.

FIGS. 4A and 4B are explanatory diagrams illustrating a shape of an alignment mark according to an embodiment of the present invention, and FIG. 4A illustrates a shape of a second alignment mark provided by rotating the first alignment mark; (B) is a diagram showing a case where the first alignment mark and the second alignment mark have completely different shapes.

FIG. 5 is an arrangement diagram of an alignment mark on a semiconductor substrate of a reticle in a patterning method for performing alignment using a 1: 1 stepper of a conventional example.

[Explanation of symbols]

Reference Signs List 10 semiconductor wafer 11 semiconductor substrate 12 buried diffusion layer 13 epitaxial layer 14 first alignment mark (first OAT) 15 separation diffusion layer 16 surface-side oxide film (16a, 16b, 16c) 16a surface-side oxide film (each 16b Oxide film on the front surface side (process of forming the base portion of the transistor portion) 16c Oxide film on the front surface side (process of forming the emitter portion of the transistor portion) 17 Oxide film on the back surface 18 Base diffusion layer Reference Signs List 19 emitter diffusion layer 20 second alignment mark (second OAT) 21 hole for forming electrode part 22 electrode part 23 cover film 25 IC chip 26 reticle field 30 first alignment mark 31 first 2nd alignment mark 32 2nd alignment mark

Claims (3)

[Claims] 1. A method for forming an alignment mark, comprising: forming a first alignment mark of a lower layer; and forming a second alignment mark of an upper layer at the same location in a subsequent step. 2. The method according to claim 1, wherein the shape of the second alignment mark and the shape of the first alignment mark formed at the same location are different. . 3. A method of manufacturing a semiconductor device, wherein a second alignment mark is formed simultaneously with a lower alignment mark at the same position as a first alignment mark in a subsequent semiconductor device etching step. A method for manufacturing a semiconductor device.