JP2002319584A - Method for fabricating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device in which desired pattern dimensions can be attained over the entire region of the same layer. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a first resist pattern using a first mask pattern having a circuit pattern for nonspecific region and a protective pattern for specific region, a step for forming a first material film pattern 21a by etching a material film using the first resist pattern as a mask, a step for forming a second resist pattern using a second mask pattern having a circuit pattern for specific region and a protective pattern for nonspecific region, a step for making thin the second resist pattern, and a step for forming a second material film pattern 21d by etching the material film using the thinned second resist pattern 23d as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming a fine pattern in an LSI.

[0002]

2. Description of the Related Art In a semiconductor process, as a method of forming a fine line pattern, a process of forming a resist pattern by a lithography process and then etching the resist pattern to narrow it (trimming process) is known.

[0003] However, when the trimming process is used, a pattern that is not originally desired to be thinned is also thinned, which may cause various problems. For example, if it is desired to obtain both a fine line pattern and a fine narrow space pattern, narrowing the line pattern increases the space width of the narrow space pattern. The previous space dimension must be smaller than the desired narrow space dimension, which makes lithography extremely difficult.

[0004]

As described above, a trimming process is known as a technique for forming a fine line pattern. However, in a conventional trimming process, a desired pattern size is obtained in all regions of the same layer. Was not always easy.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of obtaining a desired pattern size in all regions of the same layer.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device for forming a desired pattern in a specific region and a non-specific region, wherein a first resist is formed on a material film formed on a processing substrate. Forming a film, transferring a first mask pattern having a circuit pattern for a non-specific region and a protection pattern for a specific region to a first resist film using a first exposure mask, Developing the first resist film to which the first mask pattern has been transferred to form a first resist pattern; and etching the material film using the first resist pattern as a mask to form a first material film pattern. Forming, removing the first resist pattern, forming a second resist film on the substrate on which the first material film pattern is formed, and forming a second resist film using the second exposure mask. Transferring a second mask pattern having a circuit pattern for a specific region and a protection pattern for a non-specific region to the resist film, and developing the second resist film on which the second mask pattern has been transferred to form a second mask pattern. Forming a second resist pattern, narrowing the second resist pattern, etching the material film using the thinned second resist pattern as a mask, and forming a second material film pattern. And a step of removing the thin second resist pattern.

Further, the present invention is a method of manufacturing a semiconductor device for forming a desired pattern in a specific region and a non-specific region, wherein a first resist film is formed on a material film formed on a processing substrate. And a first step using a first exposure mask.
Transferring a first mask pattern having a circuit pattern for a specific region and a protection pattern for a non-specific region to the resist film, and developing the first resist film on which the first mask pattern has been transferred. Forming a first resist pattern, narrowing the first resist pattern, and etching the material film using the narrowed first resist pattern as a mask to form a first material film pattern Removing the thin first resist pattern, and forming a second resist pattern on the substrate on which the first material film pattern is formed.
Forming a resist film, and transferring a second mask pattern having a circuit pattern for a non-specific region and a protection pattern for a specific region to the second resist film using a second exposure mask. Developing a second resist film to which a second mask pattern has been transferred to form a second resist pattern; and etching the material film using the second resist pattern as a mask to form a second material film. A step of forming a pattern and a step of removing the second resist pattern.

The concept of the circuit pattern includes a pattern for forming an element such as a transistor, a pattern for forming a wiring, and the like.

[0009]

When forming a circuit pattern in a specific area, a non-specific area is protected by a resist, and when forming a circuit pattern in a non-specific area, the specific area is protected by a resist. Therefore, the size of the circuit pattern in the non-specific region is not affected during the trimming process for reducing the circuit pattern in the specific region. Therefore, a desired pattern size can be obtained for each of the pattern subjected to the trimming process of the same layer and the pattern not subjected to the trimming process.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described. This embodiment relates to the formation of a gate layer pattern in an integrated circuit in which a memory circuit region and a logic circuit region are mixed, and a narrow space pattern is formed in the memory circuit region without using a trimming process, and Is for forming a narrow line pattern by using a trimming process.

FIG. 1 is a diagram showing an outline of an integrated circuit according to this embodiment. As shown in FIG.
And the logic region 12 are separated by an element isolation region 13. In the memory area 11, for example, DRAM, S
Memory circuits such as a RAM and an EEPROM (flash memory) are arranged, and various logic circuits are arranged in the logic area 12.

Hereinafter, a specific example of this embodiment will be described.

(Example 1) FIGS. 2 to 8 are cross-sectional views showing steps of manufacturing a gate layer (gate electrode and gate wiring) according to a first example of this embodiment.

First, as shown in FIG. 2, on a semiconductor substrate having a memory circuit formation region 11, a logic circuit formation region 12, and an element isolation region 13 (an isolation width of about several μm),
For example, a polysilicon film is formed as the gate material film 21, and a resist film is formed on the gate material film 21. Subsequently, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form resist patterns 22a and 22b. The resist pattern 22a is for forming a gate pattern of the memory area 11, and the resist pattern 22b is for covering (protecting) at least an area of the logic area 12 where the gate pattern is to be arranged.

At this time, the logic region 12 is reliably protected even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus and the underlying substrate. Thus, the end of the resist pattern 22b is located on the element isolation region 13. In addition, the exposure mask used in the main exposure step is subjected to proximity effect correction so that the gate pattern is formed to a desired size on the wafer in consideration of the influence of the space between the gate patterns and the pattern arrangement around the gate pattern. It may be applied.

Subsequently, as shown in FIG. 3, the gate material film 21 is formed using the resist patterns 22a and 22b as a mask.
Is etched to form a gate material film pattern 21a.
(Gate pattern) and a gate material film pattern 21b are formed. Further, as shown in FIG. 4, the resist patterns 22a and 22b are peeled off.

Next, as shown in FIG. 5, after forming a resist film on the entire surface, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form resist patterns 23a and 23b. Form. The resist pattern 23b is for forming a gate pattern of the logic region 12, and is formed by the resist pattern 23a.
Covers (protects) at least a region of the memory region 11 where the gate pattern is arranged.

At this time, even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus, the underlying substrate, etc., the memory region 12 is reliably protected. Thus, the end of the resist pattern 23a is located on the element isolation region 13. In order to prevent an unnecessary gate material film from remaining on the element isolation region 13, the end of the resist pattern 23a is separated from the end of the gate material film pattern 21b. In other words, an exposure mask designed so that the end of the resist pattern 23a and the end of the resist pattern 22b formed in the step of FIG. 2 do not overlap even when the dimensional fluctuation due to the process fluctuation is considered. I have to.

The exposure mask used in the main exposure step may have been subjected to proximity effect correction as described in the step of FIG. The resist film used in the present exposure step includes an upper layer resist to which an exposure pattern is transferred, and a lower layer resist having an etching resistance and an optical anti-reflection function while flattening irregularities caused by a step of the underlying pattern. A stacked multilayer resist film may be used.

Next, as shown in FIG. 6, the resist patterns 23a and 23b are etched to form resist patterns 23c and 23d. By this etching, the resist pattern in the logic region 12 is thinned (trimmed).

Subsequently, as shown in FIG. 7, the gate material film is etched using the resist patterns 23c and 23d as a mask to form a gate material film pattern 21d (gate pattern). Further, as shown in FIG. 8, the resist patterns 23c and 23d are peeled off.

As described above, according to this embodiment, in the logic region, the gate pattern can be made smaller than the limit of lithography by the trimming process, and in the memory region, the gate pattern is affected by the trimming process. Therefore, a narrow space pattern can be obtained.

Example 2 FIGS. 9 to 15 are cross-sectional views showing steps of manufacturing a gate layer (gate electrode and gate wiring) according to Example 2 of the present embodiment.

In the first embodiment, the gate pattern of the memory area is formed first, and then the gate pattern of the logic area is formed. In this embodiment, the gate pattern of the logic area is formed first. After that, a gate pattern of the memory area is formed.

First, as shown in FIG. 9, similarly to the first embodiment, a polysilicon film is formed as a gate material film 31 on a processing substrate, and a resist film is formed on the gate material film 31. Subsequently, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form resist patterns 32a and 32b. The resist pattern 32b is for forming a gate pattern of the logic region 12, and the resist pattern 32a covers (protects) at least a region of the memory region 11 where the gate pattern is to be arranged.

At this time, the memory area 11 is reliably protected even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus and the underlying substrate. Thus, the end of the resist pattern 32a is located on the element isolation region 13. The exposure mask used in the main exposure step may have been subjected to proximity effect correction as described in the first embodiment.

Next, as shown in FIG. 10, the resist patterns 32a and 32b are etched into resist patterns 32c and 32d. By this etching,
The resist pattern in the logic region 12 is narrowed (trimmed).

Subsequently, as shown in FIG. 11, the gate material film 3 is formed by using the resist patterns 32c and 32d as a mask.
1 to form a gate material film pattern 31
a and gate material film pattern 31b (gate pattern)
Is formed. Further, as shown in FIG. 12, the resist patterns 32c and 32d are peeled off.

Next, as shown in FIG. 13, after forming a resist film on the entire surface, a pattern is transferred to the resist film using an exposure mask, and the resist film is further developed to form resist patterns 33a and 33b. Form. The resist pattern 33a is for forming a gate pattern of the memory region 11, and is
Covers (protects) at least a region of the logic region 12 where the gate pattern is arranged.

At this time, even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus, the underlying substrate, etc., the logic region 11 is reliably protected. Thus, the end of the resist pattern 33b is located on the element isolation region 13. In order to prevent an unnecessary gate material film from remaining on the element isolation region 13, the end of the resist pattern 33b is separated from the end of the gate material film pattern 31a. In other words, an exposure mask designed so that the end of the resist pattern 33b and the end of the resist pattern 32a formed in the step of FIG. 9 do not overlap even in consideration of dimensional fluctuation due to process fluctuation. I have to.

The exposure mask used in the main exposure step may be subjected to the same proximity effect correction as described in the first embodiment. Further, a multilayer resist film similar to that described in the first embodiment may be used for the resist film used in the main exposure step.

Subsequently, as shown in FIG. 14, the gate material film is etched using the resist patterns 33a and 33b as a mask, thereby forming the gate material film pattern 31c.
(Gate pattern) is formed. Further, as shown in FIG. 15, the resist patterns 33a and 33b are peeled off.

As described above, in the present embodiment, as in the first embodiment, the gate pattern can be narrower than the limit of lithography in the logic region by the trimming process, and the gate pattern in the memory region can be reduced. Because it is not affected by the trimming process,
A narrow space pattern can be obtained.

(Modification 1) FIGS. 16 to 22 are sectional views showing a manufacturing process according to a first modification of the present embodiment. The basic manufacturing process is the same as that of the first embodiment shown in FIGS. 2 to 8, and the components corresponding to the components shown in FIGS. 2 to 8 are denoted by the same reference numerals, Detailed description is omitted.

In the first embodiment, in the step of FIG.
Although the end of the resist pattern 23a is separated from the end of the gate material film pattern 21b, in the present modification, in the process of FIG. 19, the end of the resist pattern 23a is connected to the end of the gate material film pattern 21b. I try to overlap. In other words, an exposure mask is used in which the end of the resist pattern 23a and the end of the resist pattern 22b formed in the step of FIG. 16 overlap even if dimensional fluctuation due to process fluctuation is considered.

By using such a mask pattern, it is possible to prevent the element isolation region 13 from being etched when the gate material film is etched in the step of FIG.

(Modification 2) FIGS. 23 to 29 are sectional views showing a manufacturing process according to a second modification of the present embodiment. The basic manufacturing process is the same as that of the second embodiment shown in FIGS. 9 to 15, and the components corresponding to the components shown in FIGS. 9 to 15 are denoted by the same reference numerals, Detailed description is omitted.

In the second embodiment, the end of the resist pattern 33b is separated from the end of the gate material film pattern 31a in the step of FIG. 13, but in this modification, in the step of FIG. Resist pattern 33b
Is overlapped with the end of the gate material film pattern 31a. In other words, an exposure mask is used in which the end of the resist pattern 33b and the end of the resist pattern 32a formed in the step of FIG. 23 overlap even if dimensional fluctuation due to process fluctuation is considered.

By using such a mask pattern, it is possible to prevent the element isolation region 13 from being etched when the gate material film is etched in the step of FIG.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described. This embodiment relates to formation of a gate layer pattern in an integrated circuit,
A gate electrode is formed in a device region where a device such as a transistor is formed by using a trimming process, and a gate wiring is formed in a device isolation region around the device region without using a trimming process.

Hereinafter, specific examples of the present embodiment will be described.

(Example 1) FIGS. 30 to 36 are views showing a manufacturing process of a gate layer (gate electrode and gate wiring) according to a first example of the present embodiment. Is a diagram showing a plane pattern, and each diagram (b) is a B-
Sectional view along line B, each figure (c) is CC of each figure (a)
It is sectional drawing along the line.

First, as shown in FIG.
For example, a polysilicon film is formed as a gate material film 61 on the semiconductor substrate having the element isolation region 52, and a resist film is formed on the gate material film 61. Subsequently, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form a resist pattern 62. The resist pattern 62 forms a gate pattern (gate electrode pattern) in the element region 51 and covers (protects) at least a region of the element isolation region 52 where the gate pattern is to be arranged.
In FIG. 1A, the device isolation region 5 is not shown due to space limitations.
2, the resist pattern 62 is interrupted on the way,
In fact, it goes without saying that it is formed even to the outer region (the same applies to other drawings).

In the present lithography process, even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus, the underlying substrate, and the like, the gate pattern remains in the element region 51. In order to prevent any other pattern from being formed, the edge of the resist pattern 62 is located outside the element region 51 at the boundary between the element region 51 and the element isolation region 52. In other words, the resist pattern 62
Is shifted in the direction of the element isolation region 52 from the boundary between the element region 51 and the element isolation region 52 (for example, about several tens nm).
An exposure mask designed to be used is used.

The exposure mask used in this exposure process has been subjected to proximity effect correction similar to that described in the first embodiment so that a gate pattern is formed on a wafer to a desired size. Is also good.

Next, as shown in FIG. 31, the resist pattern 62 is thinned (trimmed) by etching.
A resist pattern 62a is formed. Subsequently, as shown in FIG. 32, the gate material film 61 is etched using the resist pattern 62a as a mask to form a gate material film pattern 61a. Further, as shown in FIG. 33, the resist pattern 62a is peeled off.

Next, as shown in FIG. 34, after forming a resist film on the entire surface, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form a resist pattern 63. . The resist pattern 63 forms a gate pattern (gate wiring pattern) in the element isolation region 52 and covers (protects) the entire element region 51.

At this time, even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus and the underlying substrate, the element region 51 is protected. , Element region 5
At the boundary between the element pattern 1 and the element isolation region 52, the end of the resist pattern 63 is positioned outside the element region 51. In other words, an exposure mask designed to shift the end of the resist pattern 63 from the boundary between the element region 51 and the element isolation region 52 toward the element isolation region 52 (for example, about several tens of nm) is used. . Further, in order to prevent an unnecessary gate material film from remaining on the element isolation region 52, at the boundary between the element region 51 and the element isolation region 52, the end of the resist pattern 63 is replaced with the resist pattern 62 shown in FIG. An exposure mask designed to be on the inside (on the element region 51 side) from the end of the element is used.

The exposure mask used in the main exposure step may have been subjected to the same proximity effect correction as described in the first embodiment. Further, a multilayer resist film similar to that described in the first embodiment may be used as the resist film used in the main exposure step.

Next, as shown in FIG. 35, the gate material film is etched using the resist pattern 63 as a mask to form a gate material film pattern 61b. Further, as shown in FIG. 36, the resist pattern 63 is peeled off.

As described above, according to this embodiment, in the element region, the gate pattern can be made smaller than the limit of lithography by the trimming process, and in the element isolation region, the gate pattern is affected by the trimming process. Since it is not received, a narrow space pattern can be obtained.

(Example 2) FIGS. 37 to 43 are views showing a manufacturing process of a gate layer (gate electrode and gate wiring) according to a second example of the present embodiment. Is a diagram showing a plane pattern, and each diagram (b) is a B-
Sectional view along line B, each figure (c) is CC of each figure (a)
It is sectional drawing along the line.

In the first embodiment, the gate pattern of the element region is formed first, and then the gate pattern of the element isolation region is formed. In this embodiment, the gate pattern of the element isolation region is formed first. And then a gate pattern of the element region is formed.

First, as shown in FIG. 37, as in the first embodiment, a polysilicon film is formed as a gate material film 71 on a semiconductor substrate, and a resist film is formed on the gate material film 71. Subsequently, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form a resist pattern 72. The resist pattern 62 forms a gate pattern (gate wiring pattern) in the element isolation region 52 and covers (protects) the entire element region 51.

At this time, even if misalignment occurs during pattern exposure or the size of the resist pattern fluctuates due to process variations in the exposure apparatus, the underlying substrate, etc., the element region 51 is reliably protected. , Element region 5
At the boundary between the element pattern 1 and the element isolation region 52, the end of the resist pattern 72 is located outside the element region 51. In other words, an exposure mask designed to shift the edge of the resist pattern 72 from the boundary between the element region 51 and the element isolation region 52 toward the element isolation region 52 (for example, about several tens of nm) is used. . The exposure mask used in the main exposure step may have been subjected to the same proximity effect correction as described in the first embodiment.

Next, as shown in FIG. 38, the gate material film is etched using the resist pattern 72 as a mask to form a gate material film pattern 71a. Further, as shown in FIG. 39, the resist pattern 72 is peeled off.

Next, as shown in FIG. 40, after forming a resist film on the entire surface, a pattern is transferred to this resist film using an exposure mask, and the resist film is further developed to form a resist pattern 73. . The resist pattern 73 forms a gate pattern (gate electrode pattern) in the element region 51 and covers (protects) at least a region of the element isolation region 52 where the gate pattern is formed.

At this time, even if misalignment occurs during pattern exposure or the resist pattern dimensions fluctuate due to process variations in the exposure apparatus, the underlying substrate, etc., the pattern other than the gate pattern remains in the element region 51. At the boundary between the element region 51 and the element isolation region 52, the end of the resist pattern 73 is located outside the element region 51 in order to prevent the formation of the pattern. In other words, the end of the resist pattern 73 is
An exposure mask designed to shift from the boundary between the element isolation region 52 and the element isolation region 52 (for example, about several tens of nm) is used. Further, in order to prevent an unnecessary gate material film from remaining on the element isolation region 52, at the boundary between the element region 51 and the element isolation region 52, the end of the resist pattern 73 is replaced with the resist pattern 72 shown in FIG. An exposure mask designed so as to be outside (on the element isolation region 52 side) from the end of is used.

The exposure mask used in the main exposure step may have been subjected to the same proximity effect correction as described in the first embodiment. Further, a multilayer resist film similar to that described in the first embodiment may be used as the resist film used in the main exposure step.

Next, as shown in FIG. 41, the resist pattern 73 is thinned (trimmed) by etching.
A resist pattern 73a is formed. Subsequently, as shown in FIG. 42, the gate material film is etched using the resist pattern 73a as a mask to form a gate material film pattern 71b. Further, as shown in FIG. 43, the resist pattern 73a is peeled off.

As described above, in the present embodiment, as in the first embodiment, the gate pattern can be narrower than the lithography limit in the element region by the trimming process, and the gate pattern can be reduced in the element isolation region. Is not affected by the trimming process, so that a narrow space pattern can be obtained.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist of the present invention. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if some constituent elements are deleted from the disclosed constituent elements, they can be extracted as an invention as long as a predetermined effect can be obtained.

[0064]

According to the present invention, a pattern subjected to the trimming process and a pattern not subjected to the trimming process can be obtained in the same layer, and a desired pattern size can be obtained in all regions of the same layer.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 5 is a sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 7 is a sectional view showing a part of a manufacturing process according to the first example of the first embodiment of the present invention.

FIG. 8 is a sectional view showing a part of a manufacturing process according to a first example of the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 10 is a sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 12 is a sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 14 is a sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 15 is a sectional view showing a part of a manufacturing process according to a second example of the first embodiment of the present invention.

FIG. 16 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 18 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 19 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 20 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 21 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 22 is a sectional view showing a part of a manufacturing process according to a first modification of the first embodiment of the present invention.

FIG. 23 is a sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 24 is a cross-sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 25 is a sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 26 is a sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 27 is a sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 29 is a cross-sectional view showing a part of a manufacturing process according to a second modification of the first embodiment of the present invention.

FIG. 30 is a view showing a part of a manufacturing process according to a first example of the second embodiment of the present invention.

FIG. 31 is a view showing a part of a manufacturing process according to a first example of the second embodiment of the present invention.

FIG. 32 is a view showing a part of a manufacturing process according to a first example of the second embodiment of the present invention.

FIG. 33 is a view showing a part of a manufacturing process according to the first example of the second embodiment of the present invention;

FIG. 34 is a view showing a part of the manufacturing process according to the first example of the second embodiment of the present invention.

FIG. 35 is a view showing a part of a manufacturing process according to the first example of the second embodiment of the present invention.

FIG. 36 is a view showing a part of a manufacturing process according to a first example of the second embodiment of the present invention.

FIG. 37 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention.

FIG. 38 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention.

FIG. 39 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention;

FIG. 40 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention.

FIG. 41 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention;

FIG. 42 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention.

FIG. 43 is a view showing a part of a manufacturing process according to a second example of the second embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Memory area 12 ... Logic area 13 ... Element isolation area 21, 31 ... Gate material film 21a-21c, 31a-31c ... Gate material film pattern 22a-22b, 23a-23d, 32a-32d, 3
3a to 33b resist pattern 51 element region 52 element isolation region 61, 71 gate material film 61a, 61b, 71a, 71b gate material film pattern 62, 62a, 63, 72, 73, 73a resist pattern

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 21/82 D 27/10 461 27/04 U (72) Inventor Kei Yoshikawa Yokohama, Kanagawa 8F, Shinsugita-cho, Isogo-ku, Tokyo F-term in the Toshiba Yokohama Office (reference)

Claims (16)

[Claims] 1. A method of manufacturing a semiconductor device for forming a desired pattern in a specific region and a non-specific region, comprising: forming a first resist film on a material film formed on a processing substrate; Transferring a first mask pattern having a circuit pattern for a non-specific region and a protection pattern for a specific region to the first resist film using the first exposure mask; and transferring the first mask pattern. Developing a first resist film to form a first resist pattern; etching the material film using the first resist pattern as a mask to form a first material film pattern; A step of removing the resist pattern; a step of forming a second resist film on the substrate on which the first material film pattern has been formed; and a step of forming a specific area on the second resist film using a second exposure mask. Transferring a second mask pattern having a circuit pattern for the area and a protection pattern for the non-specific area, and developing the second resist pattern on which the second mask pattern has been transferred to form the second resist pattern. Forming the second resist pattern; narrowing the second resist pattern; etching the material film using the thin second resist pattern as a mask to form a second material film pattern; Removing the resist pattern. 2. A method of manufacturing a semiconductor device for forming a desired pattern in a specific region and a non-specific region, comprising: forming a first resist film on a material film formed on a processing substrate; Transferring a first mask pattern having a circuit pattern for a specific area and a protection pattern for a non-specific area to the first resist film using the first exposure mask; and transferring the first mask pattern. Developing the first resist film to form a first resist pattern; thinning the first resist pattern; etching the material film using the thin first resist pattern as a mask; Forming a first material film pattern; removing a thin first resist pattern; forming a second resist film on the substrate on which the first material film pattern is formed; Transferring a second mask pattern having a circuit pattern for a non-specific area and a protection pattern for a specific area to a second resist film using a second exposure mask; and transferring the second mask pattern. Developing the formed second resist film to form a second resist pattern; etching the material film using the second resist pattern as a mask to form a second material film pattern; 2. A method for manufacturing a semiconductor device, comprising: a step of removing the resist pattern. 3. The protection pattern for a specific region protects at least a region where a circuit pattern is to be formed in a specific region, and the protection pattern for a non-specific region is a circuit pattern formed in at least a non-specific region. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the method protects the semiconductor device. 4. The protection pattern for a non-specific region protects at least a region where a circuit pattern is to be formed in the non-specific region, and the protection pattern for the specific region includes at least a circuit pattern formed in the specific region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the method protects the semiconductor device. 5. The non-specific area corresponds to a logic circuit area, the non-specific area corresponds to a memory circuit area, and the logic circuit area and the memory circuit area are separated by an element isolation area. Claims 1 to 4
The method for manufacturing a semiconductor device according to any one of the above. 6. The device according to claim 1, wherein the specific region corresponds to an element region, the non-specific region corresponds to an element isolation region, and the element region is surrounded by the element isolation region. The method for manufacturing a semiconductor device according to any one of the above. 7. The device according to claim 5, wherein, at a portion where the logic circuit region and the memory circuit region face each other, an end of the protection pattern for the specific region is located in the element isolation region. A method for manufacturing a semiconductor device. 8. The device according to claim 5, wherein, in a portion where the logic circuit region and the memory circuit region face each other, an end of the protection pattern for the non-specific region is located in the element isolation region. Of manufacturing a semiconductor device. 9. In a portion where the logic circuit area and the memory circuit area face each other, an end of the protection pattern for the specific area and an end of the protection pattern for the non-specific area are located in the element isolation area. 6. The semiconductor device according to claim 5, wherein the positional relationship between the protection pattern for the specific area and the protection pattern for the non-specific area is determined so that the respective ends do not overlap with each other. Production method. 10. An end portion of the protection pattern for the specific region and an end portion of the protection pattern for the non-specific region are located in the element isolation region in a portion where the logic circuit region and the memory circuit region face each other. 6. The semiconductor device according to claim 5, wherein a positional relationship between the protection pattern for the specific region and the protection pattern for the non-specific region is determined so that the respective ends overlap each other. Production method. 11. The semiconductor according to claim 6, wherein an end of the protection pattern for the specific region is located outside the element region at a boundary between the element region and the element isolation region. Device manufacturing method. 12. The device according to claim 6, wherein an end of the protection pattern for the non-specific area is located outside the element area at a boundary between the element area and the element isolation area. A method for manufacturing a semiconductor device. 13. An end portion of the protection pattern for the specific region is located outside the element region at a boundary between the element region and the element isolation region, and an end portion of the protection pattern for the non-specific region. 7. The method according to claim 6, wherein the semiconductor device is further positioned outside the semiconductor device. 14. The method according to claim 6, wherein the circuit pattern for the specific region extends to a non-specific region. 15. The method according to claim 1, wherein said first exposure mask and said second exposure mask are for forming a gate layer pattern. . 16. The semiconductor device according to claim 1, wherein at least one of the first exposure mask and the second exposure mask has been subjected to proximity effect correction. Method.