KR100477540B1 - Method of manufacture embedded flash cell - Google Patents

Abstract

The present invention relates to a method of manufacturing an embedded flash cell, wherein the method of manufacturing an embedded flash cell of the present invention forms a plurality of ISO layers defining an active region in a semiconductor substrate in a long rectangular shape, and each of the ISOs. Forming a poly1 layer having a width that is smaller than that of the ISO layer, the rectangular shape being the same as the ISO layer so as to be disposed on the layer, and forming a plurality of word lines perpendicular to the ISO layer and the poly1 layer, Source and drain regions are formed in the substrate active regions on both sides of each word line, and a first insulating layer is formed on the substrate resultant, and then a plurality of metal 1 contacts are formed in the first insulating layer to contact the source regions. A metal on the first insulating layer in parallel with the word line and connected to the plurality of metal 1 contacts; A common source line including one layer is formed, and a second insulating layer is formed on the first insulating layer including the common source line, and then metal 2 contacts are formed in the first and second insulating layers to contact the drain regions. The bit line formed of the metal 2 layer is formed on the second insulating layer so as to be connected to the metal 2 contact so as to be perpendicular to the common bus line.

Description

Embedded Flash Cell Manufacturing Method {METHOD OF MANUFACTURE EMBEDDED FLASH CELL}

The present invention relates to a method for manufacturing an embedded flash cell, and more particularly, to produce a shrinked 0.18 μm cell without the addition of a process, and also to a process for a poly1 bridge that has previously occurred. The present invention relates to a method for manufacturing an embedded flash cell that can improve the yield by eliminating the burden.

Flash memory is a nonvolatile memory device, which has started to be used for component parts, and is currently being used for main memory devices, and chip integration is also increasing. In addition, the flash memory is embedded in general logic, and its products have been widely applied.

On the other hand, when the 0.18㎛ class cell was designed with a typical rectangular shape of the 0.25 μm embedded flash wafer under development, the possibility of technology was examined. The rounding of the corner portion of the layer occurred, and thus, even if a slight mask misalignment occurred in the cell gate, that is, the word line forming process, the poly1 layer bridge ( Bridges are more likely to occur, and in particular, cell characteristics have changed, adversely affecting yield.

In order to solve the above problem, an embedded flash cell manufacturing method using a NOR type cell array method for forming an ISO layer and a poly1 layer into a long rectangular shape has been proposed.

However, since NOR-type flash cells use a virtual ground method, the sources of each cell must be connected together. In this regard, a field oxide film (FOX) is generally defined using a self align source etch (SAS), and then a method of connecting the sources of each cell by bonding is used. However, when applying the self-aligned source etch (SAS), there is a process burden that not only transforms the ISO profile but also develops various new technologies.

Hereinafter, a conventional embedded flash cell manufacturing method and a problem thereof will be described in detail with reference to FIG. 1.

1 is a layout diagram of an embedded flash cell using a conventional NOR type cell array method.

In the NOR array cell, as shown, the bit lines 2a to 2c, which are metall layers, are connected to the drain regions of the substrate active region through metall contacts, and the common source line 4 is an ISO layer 3. Is formed into a junction by forming a short rectangle. The word lines 1a to 1c are formed perpendicular to the ISO layer 3, and a polyl layer is formed on each ISO layer 3. Source and drain regions are formed in the substrate active regions on both sides of the word lines 1a to 1c.

However, as the cell size decreases, when the ISO layer and the poly1 layer are implemented by the photo mask process with short rectangles, as shown in FIG. 1, the edge portion 5 of the ISO layer 3 is rounded. In the subsequent process of the cell gate mask process, that is, the photo mask process for forming the word lines 1a to 1c, if a misalignment of the mask occurs, a poly1 layer bridge is more likely to occur. As the profile of the ISO layer 3 is rounded, the shape of the left and right cells is changed to widen the cell current distribution so that the sensing margin is lost, thereby adversely affecting the yield.

In FIG. 1, reference numeral 6 denotes a corner rounding portion after the photomask process for forming the poly1 layer, and reference numeral 7 denotes more corner rounding during photomask progression as the threshold is reduced. The part which becomes.

Accordingly, an object of the present invention is to provide an embedded flash cell manufacturing method capable of easily forming a 0.18 μm cell without the addition of a process, which has been made to solve the above problems.

In addition, another object of the present invention is to provide a method for manufacturing an embedded flash cell that can improve the yield by eliminating the process burden on the poly1 bridge.

The embedded flash cell manufacturing method of the present invention for achieving the above object, in the method of manufacturing an embedded flash cell using a NOR type cell array method, a plurality of ISO layers defining an active region in a semiconductor substrate Forming a long rectangular shape, and forming a poly1 layer having a width smaller than that of the ISO layer, the same rectangular shape as the ISO layer so as to be disposed on each ISO layer, and perpendicular to the ISO layer and the poly1 layer. A plurality of word lines are formed, source and drain regions are formed in the substrate active regions on both sides of each word line, and a first insulating layer is formed on the substrate resultant. Forming a plurality of metal 1 contacts to be in contact with each other; While forming a common source line formed of a metal 1 layer to be connected to the plurality of metal 1 contacts, and forming a second insulating layer on the first insulating layer including the common source line, and forming the second insulating layer in the first and second insulating layers. And forming a metal 2 contact in contact with each drain region, and forming a bit line formed of a metal 2 layer on the second insulating layer to be perpendicular to the common bus line so as to be connected to the metal 2 contact.

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(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout diagram illustrating a method of manufacturing an embedded flash cell according to the present invention.

As shown, according to the present invention, in manufacturing an embedded flash cell in a NOR type cell array method, the ISO layers 13 and 15 and the poly1 layer 16 defining an active area are formed in a long rectangular shape. In this case, the poly1 layer 16 is formed to have a smaller width than the ISO layers 13 and 15 while being disposed on the respective ISO layers 13 and 15. Subsequently, a plurality of word lines 11a to 11c are formed perpendicular to the ISO layers 13 and 15 and the polyl layer 16. Source and drain regions are formed in the substrate active regions on both sides of the word lines 11a to 11c. A first insulating layer (not shown) is formed on the substrate resultant. After the first insulating layer is etched to form via holes exposing the source region of each cell, a conductive film is embedded in the via hole to form the metal 1 contact 14a. A common source line 14 formed of a metal layer 1 connected to the plurality of metal layer 1 contacts 14a in parallel with the word lines 11a to 11c is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer including the common source line 14. After the second and first insulating layers are etched to form a stack via hole (not shown) that exposes each drain region, a metal layer contact is formed by filling a conductive film in the stack via hole. Bit lines 12a to 12c formed of a metal 2 layer connected to the metal 2 contact are formed perpendicular to the common source line 14 on the second insulating layer, thereby manufacturing an embedded flash cell according to the present invention. .

As described above, the present invention forms the common source line 14 as the metal 1 layer while connecting the source regions of each cell through the metal 1 contact, and forms the bit lines 12a to 12c as the metal 2 layer. By using a cell layout that connects to the drain region through a metal2 contact, a 0.18µm embedded flash cell can be manufactured very easily with a conventional process scheme without developing new technologies.

In addition, in relation to forming the ISO layers 13 and 15 and the poly1 layer 16 into a long rectangular shape, the process burden on the existing poly1 layer bridge generation can be eliminated. Since the same cell can be made on both sides, the cell current distribution characteristic can be improved.

As described above, according to the embedded flash cell manufacturing method of the present invention, the ISO layer and the poly1 layer are made long, and the common source line is formed of the metal1 layer and connected to the source regions through the metal1 contact. By connecting the bit line to the drain region through the metal 2 contact while forming the bit line as the metal 2 layer, it is possible to easily manufacture a reduced 0.18 μm cell without additional process, thereby increasing the price competitiveness.

In addition, the yield can be improved by eliminating the process burden on the generation of the bridge of the poly1 layer, which has occurred previously.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1 is a layout for explaining a method for manufacturing an embedded flash cell according to the prior art.

2 is a layout for explaining an embedded flash cell manufacturing method according to the present invention.

(Explanation of symbols for the main parts of the drawing)

11a to 11c: word line 12a to 12c: bit line (= metal 2 layer)

13,15: ISO layer 14: common source line (= metal 1 layer)

14a: metal 1 contact 16: poly 1 layer

Claims (1)

In the method for manufacturing an embedded flash cell using a NOR type cell array method, In the semiconductor substrate, a plurality of ISO layers defining an active region are formed in a long rectangular shape, Forming a poly1 layer having a width smaller than that of the ISO layer, the rectangular shape being the same as the ISO layer so as to be disposed on each ISO layer; Forming a plurality of word lines perpendicular to the ISO layer and the poly1 layer; Source and drain regions are formed in the substrate active regions on both sides of the word lines; Forming a first insulating film on the substrate resultant, and then forming a plurality of metal 1 contacts in contact with the source regions in the first insulating film; Forming a common source line formed of a metal layer on the first insulating layer to be parallel to the word line and connected to the plurality of metal layer contacts; After forming a second insulating layer on the first insulating layer including the common source line, a metal 2 contact is formed in the first and second insulating layers to contact the drain region, and the second insulating layer is connected to the metal 2 contact. And forming a bit line formed of a metal 2 layer perpendicular to the common bus line on the second insulating layer.