JP2002359473A - Surface-mounted multilayer circuit board - Google Patents

Surface-mounted multilayer circuit board

Info

Publication number
JP2002359473A
JP2002359473A JP2001163547A JP2001163547A JP2002359473A JP 2002359473 A JP2002359473 A JP 2002359473A JP 2001163547 A JP2001163547 A JP 2001163547A JP 2001163547 A JP2001163547 A JP 2001163547A JP 2002359473 A JP2002359473 A JP 2002359473A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer
multilayer circuit
substrate
depression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001163547A
Other languages
Japanese (ja)
Inventor
Yoichi Makino
洋一 牧野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001163547A priority Critical patent/JP2002359473A/en
Publication of JP2002359473A publication Critical patent/JP2002359473A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a surface-mounted multilayer circuit board that is improved in mountability by suppressing the occurrence of delamination between insulation layers. SOLUTION: Air entrainment is prevented at formation of a large-sized multilayered substrate 1, by laminating large-sized substrates upon another by forming a surface recessed section 12 in the peripheral edge section on the surface of the substrate 1. The surface recessed section 12 can also prevent infiltration of a sealing member 7 into the rear surface side of the substrate 1 at application of the member 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面実装型多層回
路基板に関するものであり、特にその部品搭載面を封止
部材で被覆して成る表面実装型多層回路基板に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type multilayer circuit board, and more particularly to a surface mount type multilayer circuit board whose component mounting surface is covered with a sealing member.

【0002】[0002]

【従来の技術】表面実装型多層回路基板は、各種電子部
品素子、半導体素子を搭載する実装基板として、また、
各種回路機能を形成した基板として広く実用されてい
る。例えば、アルミナなどのセラミックスは耐熱性、耐
久性、熱伝導性などに優れるため、この多層基板の材料
として適しており、高周波回路においては、所定誘電率
のセラミック材料からなる基板が使用されていた。
2. Description of the Related Art A surface-mounted multilayer circuit board is used as a mounting board for mounting various electronic component elements and semiconductor elements.
It is widely used as a substrate on which various circuit functions are formed. For example, ceramics such as alumina have excellent heat resistance, durability, and thermal conductivity, and thus are suitable as materials for this multilayer substrate.In high-frequency circuits, substrates made of ceramic materials having a predetermined dielectric constant have been used. .

【0003】この多層基板は、製造工程の簡略化のた
め、この多層基板が複数抽出できる大型多層基板を用い
ていた。具体的には、以下のように製造される。まず、
低温焼成ガラスセラミック材料などからなるグリーンシ
ートに、表面配線層、裏面配線層、内部配線層、ビアホ
ール導体となる導体パターンをスクリーン印刷する。次
に、導体パターンが形成された複数のグリーンシートを
積層し、この大型多層基板を熱圧着して一体化する。
尚、このとき、必要に応じて金型を用いて分割溝を形成
する。次に、熱圧着された大型多層基板を焼成する。次
に、大型多層基板上に回路構成部品を半田、フリップチ
ップ実装、ワイヤボンディングなどで接合・実装を行
う。次に、必要に応じて、回路構成部品を外部環境から
保護するために、回路構成部品が実装された基板の部品
実装面全面を樹脂などの封止部材で被覆することによ
り、大型表面実装型多層回路基板が得られる。最後に、
上述の分割溝でもって分割処理することにより、最終製
品としての表面実装型多層回路基板が得られる。なお、
分割溝及び分割処理をせずに、大型表面実装型多層回路
基板をダイシングソー等を用いて切断しても構わない
(以下、分割・切断を含めて、分離という)。
In order to simplify the manufacturing process, a large-sized multilayer substrate from which a plurality of such multilayer substrates can be extracted has been used. Specifically, it is manufactured as follows. First,
A conductor pattern to be a front wiring layer, a rear wiring layer, an internal wiring layer, and a via hole conductor is screen-printed on a green sheet made of a low-temperature fired glass ceramic material or the like. Next, a plurality of green sheets on which the conductor patterns are formed are laminated, and the large-sized multilayer substrate is integrated by thermocompression bonding.
At this time, if necessary, a dividing groove is formed using a mold. Next, the large-sized thermocompression-bonded multilayer substrate is fired. Next, circuit components are joined and mounted on a large-sized multilayer substrate by soldering, flip-chip mounting, wire bonding, or the like. Next, if necessary, in order to protect the circuit components from the external environment, the entire surface of the component mounting surface of the board on which the circuit components are mounted is covered with a sealing member such as a resin, so that a large surface mount type A multilayer circuit board is obtained. Finally,
By performing the division processing using the above-described division grooves, a surface-mounted multilayer circuit board as a final product is obtained. In addition,
The large surface-mount type multilayer circuit board may be cut using a dicing saw or the like without performing the dividing groove and the dividing process (hereinafter, referred to as separation including the dividing / cutting).

【0004】ここで、上記製造方法において、グリーン
シートの積層時に、各グリーンシート間に空気が介在さ
れてしまい、熱圧着してもその空気が充分に逃げず、焼
成時にこの空気がデラミネーションの原因となるという
問題点があった。
Here, in the above manufacturing method, air is interposed between the green sheets when the green sheets are laminated, and the air does not sufficiently escape even when thermocompression-bonded, and this air is delaminated during firing. There was a problem that caused it.

【0005】そこで、図7に示すように、従来、絶縁層
1a〜1eとなるグリーンシートの同一箇所にあらかじ
め空気巻き込み防止用貫通孔19a〜19eを形成して
おき、積層時にこの貫通孔19a〜19eが重なって構
成された貫通孔19から空気が抜け出すようにすること
により、上記デラミネーションを防ぐ方法が行われてき
た。
Therefore, as shown in FIG. 7, conventionally, air entrapment preventing through holes 19a to 19e are previously formed in the same place of the green sheet to be the insulating layers 1a to 1e, and the through holes 19a to 19e are formed at the time of lamination. A method of preventing the above-described delamination has been performed by allowing air to escape from the through-hole 19 formed by overlapping the holes 19e.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、大型多
層基板11に空気巻き込み防止用の貫通孔19が形成さ
れていると、図7に示すように、封止部材7で被覆する
際に、封止部材7が貫通孔19に侵入して、基板1裏側
に回り込んでしまう。そして、回り込んだ封止部材7が
多層基板の裏面側の端子電極5に付着したり、多層基板
1の裏面に凹凸が発生してしまいマザーボードへの実装
が不能となる問題を有していた。
However, if the large multi-layer substrate 11 is provided with the through holes 19 for preventing air entrapment, as shown in FIG. The member 7 enters the through hole 19 and goes around the back side of the substrate 1. Then, there is a problem that the enclosing sealing member 7 adheres to the terminal electrode 5 on the rear surface side of the multilayer substrate, or irregularities are generated on the rear surface of the multilayer substrate 1, so that mounting on the motherboard becomes impossible. .

【0007】本発明は、上述の課題に鑑みて案出された
ものであり、その目的は、グリーンシートの積層・熱圧
着時に巻き込まれた空気によるデラミネーションを防ぎ
できる表面実装型多層回路基板を提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a surface mount type multilayer circuit board capable of preventing delamination due to air entrained during lamination and thermocompression bonding of green sheets. To provide.

【0008】[0008]

【課題を解決するための手段】本発明の表面実装型多層
回路基板は、複数の絶縁層が積層された多層基板の表面
に表面配線層及び回路構成部品を配置するとともに、該
表面配線層及び回路構成部品を封止部材で被覆して成
り、且つ前記多層基板の裏面に端子電極を形成した表面
実装型多層基板において、前記多層基板の表面に表面窪
み部を形成するとともに、該表面窪み部内に、前記封止
部材を充填させた。
According to the surface mounting type multilayer circuit board of the present invention, a surface wiring layer and a circuit component are arranged on a surface of a multilayer board on which a plurality of insulating layers are laminated. In a surface-mounted multilayer substrate formed by covering a circuit component with a sealing member and forming a terminal electrode on the back surface of the multilayer substrate, a surface depression is formed on the surface of the multilayer substrate, and the surface depression is formed in the surface depression. Was filled with the sealing member.

【0009】好ましくは、該表面窪み部と対向する裏面
に、前記絶縁層の1層を挟んで、裏面窪み部が形成され
ていることを特徴とする。
Preferably, a back surface dent portion is formed on the back surface facing the front surface dent portion with one of the insulating layers interposed therebetween.

【0010】さらに好ましくは、前記表面窪み部は、前
記多層基板の周縁部に形成されていることを特徴とす
る。
[0010] More preferably, the surface depression is formed in a peripheral portion of the multilayer substrate.

【0011】なお、ここでいう表面窪み部とは、多層基
板の表面から積層方向に所定枚数の絶縁層に形成された
貫通孔によって構成され、その底面が所定絶縁層によっ
て閉塞された凹部形状となっている。また、多層基板の
実装面側にも形成した凹部も表面窪み部という。また、
多層基板の端面に跨がって形成された表面窪み、大型多
層回路基板で隣接された多層基板と2分割され、また、
多層基板の角部に跨がって形成された表面窪み部は、大
型多層回路基板で隣接された多層基板と4分割されてい
る。これらをすべて表面窪み部という。
Here, the surface depression is formed by a through hole formed in a predetermined number of insulating layers in the stacking direction from the surface of the multilayer substrate, and has a concave shape in which the bottom surface is closed by the predetermined insulating layer. Has become. Also, a concave portion formed on the mounting surface side of the multilayer substrate is also called a surface concave portion. Also,
A surface dent formed over the end face of the multilayer board, divided into two adjacent multilayer boards by a large multilayer circuit board,
The surface dent formed over the corner of the multilayer substrate is divided into four by a large multilayer circuit board and an adjacent multilayer substrate. These are all called surface depressions.

【0012】[0012]

【発明の実施の形態】以下、本発明の表面実装型多層回
路基板を図面に基づいて説明する。尚、図において、従
来と同じ部位は同一符号を付す。また、各符号は製造工
程上、焼成の前後で区別しないことにする。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a surface mount type multilayer circuit board according to the present invention. In the drawings, the same parts as those in the related art are denoted by the same reference numerals. In addition, each code is not distinguished before and after firing in the manufacturing process.

【0013】図1は、本発明の表面実装型多層回路基板
の断面図である。図2は、図1の多層基板が抽出される
大型多層基板の部分断面図である。図3は、図2の大型
多層基板に形成された表面窪み部の形成位置を示す平面
図である。
FIG. 1 is a sectional view of a surface mount type multilayer circuit board according to the present invention. FIG. 2 is a partial cross-sectional view of a large multilayer substrate from which the multilayer substrate of FIG. 1 is extracted. FIG. 3 is a plan view showing a formation position of a surface depression formed on the large-sized multilayer substrate of FIG.

【0014】図において、11は表面実装型多層回路基
板、1は多層基板、1a〜1eは絶縁層、2は多層基板
1の内部に形成された内部配線層、3は多層基板1の内
部に形成されたビアホール導体、4は多層基板1の表面
に形成された表面配線層、5は多層基板1の実装面側に
形成された端子電極、6は表面配線層4上に搭載された
回路構成部品、7は回路構成部品を被覆している封止部
材である。
In the figure, reference numeral 11 denotes a surface mount type multilayer circuit board, 1 denotes a multilayer board, 1a to 1e denote insulating layers, 2 denotes an internal wiring layer formed inside the multilayer board 1, and 3 denotes an internal wiring layer. The formed via-hole conductor, 4 is a surface wiring layer formed on the surface of the multilayer substrate 1, 5 is a terminal electrode formed on the mounting surface side of the multilayer substrate 1, and 6 is a circuit configuration mounted on the surface wiring layer 4. The component 7 is a sealing member that covers the circuit component.

【0015】また、10は大型表面実装型多層回路基
板、8は表面実装型多層回路基板11を各多層基板1に
分離するためのスナップライン(分割溝)や、切断予定
線などの分離線である。12は表面窪み部である。
Reference numeral 10 denotes a large-sized surface-mounted multilayer circuit board; 8 denotes a snap line (division groove) for separating the surface-mounted multilayer circuit board 11 into each multilayer board 1; is there. Reference numeral 12 denotes a surface depression.

【0016】多層基板1は、1層あたり例えば、50〜
300μm程度の厚みを有する絶縁層1a〜1eが積層
して構成されている。絶縁層1a〜1eは、セラミック
材料、低温焼成化が可能なガラス−セラミック材料など
からなる。例えばガラス−セラミック材料では、セラミ
ック材料として、例えば、A123、BaO−TiO 2
系、CaO−TiO2系、MgO−TiO2系などが、ま
た、低温焼成化が可能な酸化物としては、例えば、Bi
VO4、CuO、Li2O、B23などが選ばれる。
The multilayer substrate 1 has, for example, 50 to 50 layers per layer.
Insulating layers 1a to 1e having a thickness of about 300 μm are laminated
It is configured. The insulating layers 1a to 1e are made of ceramic.
Materials, glass-ceramic materials that can be fired at low temperatures, etc.
Consists of For example, in glass-ceramic materials, ceramic
For example, A1TwoOThree, BaO-TiO Two
System, CaO-TiOTwoSystem, MgO-TiOTwoSystem
Examples of oxides that can be fired at low temperatures include, for example, Bi.
VOFour, CuO, LiTwoO, BTwoOThreeAnd so on.

【0017】絶縁層1a〜1eの各層の厚み方向に貫く
ビアホール導体3が形成されている。また、絶縁層1a
〜1eの層間には、所定配線網の他に、容量を形成する
容量電極、インダクタンス成分を形成する導体、ストリ
ップ線路を形成する導体などを含む内部配線層2が形成
されている。また、絶縁層1aの表面には、回路構成部
品6を搭載するための電極パッドを含む表面配線層4が
形成されている。さらに、絶縁層1eの裏面(表面実装
型多層回路基板の実装面)には、多層基板1をマザーボ
ードに接続するための端子電極5やグランド電位となる
裏面導体層が形成されている。
A via-hole conductor 3 is formed to penetrate in the thickness direction of each of the insulating layers 1a to 1e. Also, the insulating layer 1a
In addition to the predetermined wiring network, an internal wiring layer 2 including a capacitor electrode forming a capacitor, a conductor forming an inductance component, a conductor forming a strip line, and the like is formed between the layers 1 to 1e. On the surface of the insulating layer 1a, a surface wiring layer 4 including an electrode pad for mounting the circuit component 6 is formed. Further, on the back surface of the insulating layer 1e (the mounting surface of the surface mount type multilayer circuit board), a terminal electrode 5 for connecting the multilayer substrate 1 to a motherboard and a back surface conductor layer serving as a ground potential are formed.

【0018】そして、表面配線層4、ビアホール導体
3、内部配線層2、端子電極5は、所定回路網を構成す
べく、互いに接続されている。また、これらの導体は、
Ag系(Ag単体又はAg−Pd、Ag−PtなどのA
g合金)や、Cu系(Cu単体又はCu合金)を主成分
とする導体膜(導体)が用いられる。
The surface wiring layer 4, via-hole conductor 3, internal wiring layer 2, and terminal electrode 5 are connected to each other to form a predetermined circuit network. Also, these conductors
Ag-based (Ag alone or Ag-Pd, Ag-Pt, etc.
g alloy) or a conductive film (conductor) mainly composed of Cu (Cu simple substance or Cu alloy).

【0019】回路構成部品6は、積層セラミックコンデ
ンサ、チップ抵抗器、SAW素子、チップ状インダクタ
ンス素子、半導体素子など各種電子部品が例示され、半
田、フリップチップ実装、ワイヤボンディングなどによ
り、表面配線層4上に実装される。
The circuit component 6 is exemplified by various electronic components such as a multilayer ceramic capacitor, a chip resistor, a SAW element, a chip-shaped inductance element, and a semiconductor element. The surface wiring layer 4 is formed by soldering, flip-chip mounting, wire bonding, or the like. Implemented above.

【0020】回路構成部品6の表面には、外部環境から
保護するために、多層基板1表面の全面を覆うように封
止部材7が被覆されている。封止部材7は、エポキシ系
樹脂、フェノール系樹脂、シリコン系樹脂などの熱硬化
性樹脂、紫外線硬化樹脂などが例示できる。このよう
に、多層基板1に回路構成部品6、封止部材7を形成し
て、表面実装型多層回路基板11が構成される。
The surface of the circuit component 6 is covered with a sealing member 7 so as to cover the entire surface of the multilayer substrate 1 in order to protect it from the external environment. Examples of the sealing member 7 include a thermosetting resin such as an epoxy resin, a phenol resin, and a silicon resin, and an ultraviolet curing resin. In this way, the circuit component 6 and the sealing member 7 are formed on the multilayer board 1 to form the surface-mounted multilayer circuit board 11.

【0021】本発明の表面実装型多層回路基板11の特
徴的なことは、多層基板1の表面に表面窪み部12を形
成されているとともに、この表面窪み部12内には、上
述の封止部材7が充填されている。具体的な表面窪み部
12の形成される位置は、例えば、図1に示す大型表面
実装型多層回路基板10で示すように、隣接しあう多層
基板1の境界部分に跨がって形成されている。即ち、表
面実装型多層回路基板11においては、端面、また角部
に形成されている。表面実装型多層回路基板11が複数
抽出できる大型表面実装型多層回路基板10において
は、分離線に跨がるように表面窪み部12が形成されて
いる。その結果、多層基板1の周縁部に位置さている。
表面窪み部12となる貫通孔12a〜12dは、絶縁層
1a〜1dのみだけであり、絶縁層1eが貫通孔12a
〜12dを閉塞して、凹部状の窪み部12を形成してい
る。この絶縁層1a〜1dの貫通孔12a〜12dは、
積層時互いに重なりあうように、同一箇所に形成されて
いる。
The surface mounting type multilayer circuit board 11 of the present invention is characterized in that a surface depression 12 is formed on the surface of the multilayer substrate 1 and the above-described sealing is provided in the surface depression 12. The member 7 is filled. The specific position where the surface depression 12 is formed is, for example, as shown in the large-sized surface mount type multilayer circuit board 10 shown in FIG. I have. That is, in the surface mount type multilayer circuit board 11, it is formed at an end face and a corner. In a large-sized surface-mounted multilayer circuit board 10 from which a plurality of surface-mounted multilayer circuit boards 11 can be extracted, a surface depression 12 is formed so as to straddle a separation line. As a result, it is located at the periphery of the multilayer substrate 1.
The through holes 12a to 12d serving as the surface depressions 12 are only the insulating layers 1a to 1d, and the insulating layer 1e is
To 12d are closed to form a concave portion 12 having a concave shape. The through holes 12a to 12d of the insulating layers 1a to 1d are
They are formed at the same location so as to overlap with each other during lamination.

【0022】また、表面実装型多層回路基板11の表面
には、表面配線層4が、さらに、表面配線層4上に回路
構成部品6が実装され、これら表面配線層4及び回路構
成部品6を覆うように、多層基板1の全面には封止部材
7が被覆されている。そして、この封止部材7は、表面
窪み部12の内部に入り込んでいる。但し、表面窪み部
12に入り込んだ封止部材は、絶縁層1eによって遮ら
れ、多層基板1の実装面側に回り込むことが一切ない。
A surface wiring layer 4 is mounted on the surface of the surface-mount type multilayer circuit board 11, and a circuit component 6 is mounted on the surface wiring layer 4. The surface wiring layer 4 and the circuit component 6 are mounted on the surface wiring layer 4. The sealing member 7 is coated on the entire surface of the multilayer substrate 1 so as to cover it. The sealing member 7 has entered the inside of the surface depression 12. However, the sealing member that has entered the surface recess 12 is blocked by the insulating layer 1e and does not go around the mounting surface side of the multilayer substrate 1 at all.

【0023】この表面窪み部12は、図3に示すよう
に、大型表面実装型多層回路基板10においては、分離
線8の交点にあたる部分に形成されている。
As shown in FIG. 3, the surface depression 12 is formed at a portion corresponding to the intersection of the separation lines 8 in the large surface mount type multilayer circuit board 10.

【0024】次に本発明における表面実装型多層回路基
板11の製造方法を説明する。
Next, a method of manufacturing the surface mount type multilayer circuit board 11 according to the present invention will be described.

【0025】まず、絶縁層1a〜1eは、例えばCaO
−Al23−SiO2−B23系のガラス粉末とアルミ
ナ粉末とを混合したガラス−セラミック材料からなる。
そして、絶縁層1a〜1eとなるグリーンシートは、こ
のようなガラス−セラミック材料のスラリーをドクター
ブレード法によって厚み0.2mmのテープ成形し、さ
らに所定大きさに切断されてシート状に形成することに
より、グリーンシートなる。
First, the insulating layers 1a to 1e are made of, for example, CaO
-Al 2 O 3 -SiO 2 -B 2 O 3 based glass powder and alumina powder and glass were mixed for - a ceramic material.
The green sheets to be the insulating layers 1a to 1e are formed by forming a slurry of such a glass-ceramic material into a tape having a thickness of 0.2 mm by a doctor blade method, and further cutting into a predetermined size to form a sheet. As a result, a green sheet is obtained.

【0026】このようなグリーンシートは、各絶縁層1
a〜1eのビアホール導体3に応じて打ち抜きやパンチ
ングマシーンなどを用いて、複数の所定位置に、例えば
0.2mmφのビアホール用貫通孔を形成する。また、
各グリーンシートの貫通孔には、Ag、Ag−Pd、A
u、Cuなどの導体ペーストを充填し、同時に内部配線
層2となる導体や表面配線層4、端子電極5となる導体
膜をスクリーン印刷により形成する。
Such a green sheet is formed on each insulating layer 1
A through hole for a via hole of, for example, 0.2 mmφ is formed at a plurality of predetermined positions using a punching machine, a punching machine, or the like in accordance with the via hole conductors 3a to 1e. Also,
Ag, Ag-Pd, A
A conductor paste such as u, Cu or the like is filled, and at the same time, a conductor serving as the internal wiring layer 2, a surface wiring layer 4, and a conductor film serving as the terminal electrode 5 are formed by screen printing.

【0027】このとき、絶縁層1a〜1dとなるグリー
ンシートには、積層方向に重なる同一箇所に貫通孔12
a〜12dを形成する。そして、最下層に位置する絶縁
層1eとなるグリーンシートには表面窪み部12となる
貫通孔を形成しない。
At this time, the green sheets serving as the insulating layers 1a to 1d are provided with the through holes 12 at the same positions overlapping in the laminating direction.
a to 12d are formed. Then, no through hole serving as the surface depression 12 is formed in the green sheet serving as the insulating layer 1e located at the lowermost layer.

【0028】そして、このような絶縁層1a〜1eとな
るグリーンシートを積層し、この大型多層基板10を、
例えば80〜150℃、500〜2500N/cm2
条件で熱圧着して一体化する。これにより、未焼成状態
の大型多層基板となる。
Then, such green sheets as the insulating layers 1a to 1e are laminated, and the large-sized multilayer substrate 10 is
For example, they are integrated by thermocompression bonding under the conditions of 80 to 150 ° C. and 500 to 2500 N / cm 2 . Thereby, a large-sized multilayer substrate in an unfired state is obtained.

【0029】次に、必要に応じて、図3に示すように、
未焼成状態の大型多層基板の表裏両面に分離線8とし
て、分割溝を成形する。
Next, if necessary, as shown in FIG.
Separation grooves are formed as separation lines 8 on both the front and back surfaces of the unfired large multilayer substrate.

【0030】次に、未焼成状態の大型多層基板を、電気
式連続ベルト炉を使用して、例えば、空気中で900
℃、20分の保持条件で焼成する。なお、導体ペースト
がNi、Cuの場合は還元または中性雰囲気で焼成す
る。
Next, a large-sized multilayer substrate in an unfired state is placed in an electric continuous belt furnace, for example, in air at 900 ° C.
It is baked at 20 ° C. for 20 minutes. When the conductive paste is Ni or Cu, the paste is reduced or fired in a neutral atmosphere.

【0031】次に、電気テストが行われ、通電状態が検
査され、合格した大型多層基板については、表面処理が
行われる。例えば、表面配線層4に厚膜の抵抗膜を焼き
付けたり、絶縁保護膜を被覆したりする。
Next, an electrical test is performed to check the energization state, and the large multi-layer substrate that has passed is subjected to a surface treatment. For example, a thick resistive film is baked on the surface wiring layer 4 or an insulating protective film is coated.

【0032】次に、大型多層基板上に回路構成部品6を
半田、フリップチップ実装、ワイヤボンディングなどで
接合・実装を行う。
Next, the circuit component 6 is joined and mounted on the large-sized multilayer board by soldering, flip-chip mounting, wire bonding, or the like.

【0033】次に、大型多層基板の表面全面に、樹脂な
どの封止部材7で被覆する。なお、封止の方法は、液状
封止材を用いて注型法により封止する方法、あるいは常
温では固形の封止材を用いて、トランスファーモールド
法により封止する方式を用いることができる。これによ
り、大型表面実装型多層回路基板10となる。
Next, the entire surface of the large multilayer substrate is covered with a sealing member 7 such as a resin. Note that as a sealing method, a method of sealing by a casting method using a liquid sealing material, or a method of sealing by a transfer molding method using a solid sealing material at normal temperature can be used. As a result, a large surface-mounted multilayer circuit board 10 is obtained.

【0034】このようにして得られた大型表面実装型多
層回路基板10を分離線8に沿って、分割処理すること
により、図1に示す表面実装型多層回路基板11が形成
される。尚、分割処理以外に、例えば切断処理により大
型表面実装型多層回路基板10から表面実装型多層回路
基板11に分離しても構わない。
The large surface mounted multilayer circuit board 10 thus obtained is divided along the separation line 8 to form the surface mounted multilayer circuit board 11 shown in FIG. Note that, other than the division processing, the large-sized surface-mounted multilayer circuit board 10 may be separated into the surface-mounted multilayer circuit board 11 by, for example, cutting processing.

【0035】本発明の表面実装型多層基板11によれ
ば、多層基板1の表面の一部には、上述の製造方法にお
いて、絶縁層1a〜1dの貫通孔12a〜12dで構成
される全体として凹部形状となる。即ち、表面窪み部1
2が形成される。しかも、表面窪み部12は、多層基板
1に塗布した封止部材7が充填されることになる。
According to the surface-mount type multilayer substrate 11 of the present invention, a part of the surface of the multilayer substrate 1 is formed as a whole by the through holes 12a to 12d of the insulating layers 1a to 1d in the above-described manufacturing method. It has a concave shape. That is, surface depression 1
2 are formed. In addition, the surface recess 12 is filled with the sealing member 7 applied to the multilayer substrate 1.

【0036】すなわち、このような大型表面実装型多層
回路基板10において、各絶縁層1a〜1eを積層する
にあたり、積層隣接される絶縁層1aと絶縁層1b、絶
縁層1bと絶縁層1c、絶縁層1cと絶縁層1d、絶縁
層1dと絶縁層1eとの層間に巻きこまれる空気は、こ
の表面窪み部12を介して多層基板1の表面側に容易に
逃がすことができる。このため、焼成処理をおこなって
も、絶縁層1a〜1e間のデラミネーションの発生を有
効に防止できる。
That is, in such a large-sized surface-mounted multilayer circuit board 10, when the insulating layers 1a to 1e are stacked, the adjacent insulating layers 1a and 1b, the insulating layers 1b and 1c, The air engulfed between the layers 1c and 1d and between the insulating layers 1d and 1e can easily escape to the front side of the multilayer substrate 1 through the surface depressions 12. For this reason, even if the baking treatment is performed, occurrence of delamination between the insulating layers 1a to 1e can be effectively prevented.

【0037】また、これらの貫通孔12a〜12dから
なる表面窪み部12は、最下層に位置する絶縁層1eに
よって閉塞されているため、多層基板1の表面に封止部
材7を塗布しても、多層基板1の実装面である裏面側に
回り込むことが一切ない。このため、従来のように、多
層基板1の実装面に凹凸状態となり、マザーボードへの
実装が不能となるといった問題を解決できる。
Further, since the surface depression 12 composed of these through holes 12a to 12d is closed by the lowermost insulating layer 1e, even if the sealing member 7 is applied to the surface of the multilayer substrate 1, In addition, it does not go around the back surface side, which is the mounting surface of the multilayer substrate 1 at all. For this reason, it is possible to solve the problem that the mounting surface of the multilayer board 1 becomes uneven as in the related art, and mounting on the motherboard becomes impossible.

【0038】また、表面窪み部12は、多層基板1の周
縁部に形成することにより、表面実装型多層回路基板1
1での表面デッドスペースを減少して、小形、高密度実
装に適した表面実装型多層回路基板11となる。具体的
には、図3に示すように、大型表面実装型多層回路基板
10における表面窪み部12は、表面実装型多層回路基
板10となる各多層基板領域の4つの角部、すなわち分
離線8の交差部分に形成する。
The surface recess 12 is formed in the peripheral portion of the multilayer substrate 1 so that the surface mounting type multilayer circuit substrate 1 is formed.
1, the surface dead space is reduced, and the surface mounting type multilayer circuit board 11 suitable for small size and high density mounting is obtained. Specifically, as shown in FIG. 3, the surface recess 12 in the large-sized surface-mounted multilayer circuit board 10 has four corners of each multilayer substrate region to be the surface-mounted multilayer circuit board 10, that is, the separation line 8. Formed at the intersection of.

【0039】表面窪み部12の形状は、特に、円形に限
るものではないが、例えば、図示したように円形状の場
合、直径は小さいと積層圧着工程でつぶれてしまい、上
述の空気を逃がすことができない。このため、焼成後に
おいて、0.3mm以上、好ましくは0.4mm以上で
あることが望ましい。
The shape of the surface depression 12 is not particularly limited to a circular shape. For example, in the case of a circular shape as shown in the figure, if the diameter is small, the surface depression 12 will be crushed in the lamination press-bonding process, and the above-mentioned air will be released. Can not. Therefore, after firing, it is desirable that the thickness be 0.3 mm or more, preferably 0.4 mm or more.

【0040】表面窪み部12の直径の上限は特に制限は
ないが、表面実装型多層回路基板10の小型化や表面の
高密度実装を考慮する。具体的には、焼成後に4mm以
下であることが望ましい。また、開口形状が円形以外の
場合に、これらの開口面積に相当する開口を有する他の
形状となる。
The upper limit of the diameter of the surface depression 12 is not particularly limited, but the size of the surface mount type multilayer circuit board 10 and the high density mounting of the surface are taken into consideration. Specifically, it is desirable that the thickness after firing is 4 mm or less. Further, when the opening shape is other than the circular shape, the opening shape becomes another shape having an opening corresponding to the opening area.

【0041】図4は、本発明の他の実施例の断面図であ
る。この実施例では、表面窪み部12は、多層基板1の
周縁部から離れ、基板中央よりの位置に形成されてい
る。
FIG. 4 is a sectional view of another embodiment of the present invention. In this embodiment, the surface depression 12 is formed at a position away from the peripheral edge of the multilayer substrate 1 and at a position closer to the center of the substrate.

【0042】図5は、本発明の表面窪み部12の形成位
置を示す平面図である。図5(a)では、表面窪み部1
2を表面実装型多層回路基板10となる各基板形成領域
の4つの角部、すなわち分離線8の交差部分に形成され
ている。
FIG. 5 is a plan view showing the formation position of the surface depression 12 of the present invention. In FIG. 5A, the surface depression 1
2 are formed at four corners of each substrate forming region to be the surface-mounted multilayer circuit board 10, that is, at the intersections of the separation lines 8.

【0043】図5(b)では、表面窪み部12を表面実
装型多層回路基板10となる各基板形成領域の辺部、す
なわち分離線8上に形成されている。図5(c)では、
表面窪み部12を表面実装型多層回路基板10となる各
基板形成領域の分離線8から離れた位置に形成してい
る。ここで、図5(a)、(b)の断面図は、図1に示
す表面実装型多層回路基板のようになり、図5(c)の
断面図は、図4に示す表面実装型多層回路基板のように
なる。
In FIG. 5B, the surface depression 12 is formed on the side of each substrate forming region to be the surface mount type multilayer circuit board 10, that is, on the separation line 8. In FIG. 5C,
The surface depression 12 is formed at a position apart from the separation line 8 in each substrate forming region to be the surface-mounted multilayer circuit substrate 10. Here, the cross-sectional views of FIGS. 5A and 5B are like the surface-mounted multilayer circuit board shown in FIG. 1, and the cross-sectional view of FIG. 5C is the surface-mounted multilayer circuit board shown in FIG. It looks like a circuit board.

【0044】また、図6は、本発明の表面実装型多層回
路基板の他の実施例を示す部分拡大図である。この実施
例は、多層基板1の表面側からは表面窪み部12が形成
されているが、この表面窪み部12を閉塞する絶縁層
が、積層方向の中央に位置する絶縁層1cである。そし
て、多層基板1の実装面側にも、表面窪み部15が形成
されている。即ち、表面窪み部12と表面窪み部15
は、絶縁層1cの1層を挟んで配置されている。この場
合、絶縁層1aと1b、1bと1cとの層間に巻き込ま
れる空気は、表面窪み部12から抜け、絶縁層1cと1
d、1dと1eとの層間に巻き込まれる空気は、表面窪
み部15から抜けることができる。尚、この場合、多層
基板1の表面側の表面窪み部12と多層基板1の実装側
の表面窪み部15を同一箇所に形成する必要はない。即
ち、多層基板1の絶縁層の積層数をN層とした場合、表
面窪み部12は、少なくとも表面側の絶縁層または表面
側から(N−1)層分の貫通孔により構成される。
FIG. 6 is a partially enlarged view showing another embodiment of the surface mount type multilayer circuit board of the present invention. In this embodiment, the surface depression 12 is formed from the front side of the multilayer substrate 1, and the insulating layer closing the surface depression 12 is the insulation layer 1c located at the center in the stacking direction. Further, a surface depression 15 is also formed on the mounting surface side of the multilayer substrate 1. That is, the surface depression 12 and the surface depression 15
Are arranged with one layer of the insulating layer 1c interposed therebetween. In this case, air entrained between the layers between the insulating layers 1a and 1b and between the insulating layers 1b and 1c escapes from the surface depression 12 and becomes insulative.
The air entrained between the layers d, 1d and 1e can escape from the surface depression 15. In this case, it is not necessary to form the surface depression 12 on the front side of the multilayer substrate 1 and the surface depression 15 on the mounting side of the multilayer substrate 1 at the same location. That is, when the number of laminated insulating layers of the multilayer substrate 1 is N, the surface depression 12 is constituted by at least the insulating layer on the front side or through holes of (N−1) layers from the front side.

【0045】このような構造では、大型表面実装型多層
回路基板10における表面窪み部12内に封止部材7が
充填される量が減少するため、分割、切断処理を行いや
すくなる。
In such a structure, the amount of the sealing member 7 filled in the surface depression 12 in the large-sized surface-mount type multilayer circuit board 10 is reduced, so that the division and cutting can be easily performed.

【0046】なお、本発明は上記の実施の形態例に限定
されるものではなく、本発明の要旨を逸脱しない範囲内
での種々の変更や改良などは何ら差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

【0047】上述の実施例では、ガラス-セラミック材
料の多層基板を例にした表面実装型多層回路基板で説明
したが、ガラスエポキシ材、変成ポリイミド材などの有
機材料の多層基板であってもよい。
In the above-described embodiment, the surface mount type multilayer circuit board has been described as an example of a multilayer board made of a glass-ceramic material. However, a multilayer board made of an organic material such as a glass epoxy material or a modified polyimide material may be used. .

【0048】また、これらの表面窪み部12、15の内
壁面に導体膜を付着するようにして、例えば、多層基板
1の内部配線層2と、さらには表面配線層4や端子電極
5と電気的に接続するようにしても構わない。
Further, a conductor film is attached to the inner wall surfaces of these surface depressions 12 and 15 so that, for example, the internal wiring layer 2 of the multilayer substrate 1 and the surface wiring layer 4 and the terminal electrodes 5 are electrically connected to each other. The connection may be made automatically.

【0049】[0049]

【発明の効果】本発明の表面実装型多層回路基板によれ
ば、多層基板の表面側に表面窪み部を形成するととも
に、この表面窪み部内に、封止部材を充填している。即
ち、製造工程において、大型表面実装型多層回路基板の
形状が大きくても、グリーンシートの層間に巻き込まれ
る空気を逃がす表面窪み部が点在することになるため、
絶縁層間のデラミネーションを有効に抑え、多層基板内
の内部配線層を安定した形成することができる。
According to the surface mounting type multilayer circuit board of the present invention, a surface depression is formed on the surface side of the multilayer substrate, and the sealing member is filled in the surface depression. That is, in the manufacturing process, even if the shape of the large-sized surface-mount type multilayer circuit board is large, the surface dents that allow the air entrained between the layers of the green sheet to escape are dotted,
Delamination between the insulating layers can be effectively suppressed, and the internal wiring layer in the multilayer substrate can be formed stably.

【0050】また、表面実装型多層回路基板側に、表面
に塗布した封止部材が回り込むことがないため、マザー
ボードへの実装性で飛躍的に向上する。さらに、この表
面窪み部を表面実装型多層回路基板の周縁部に形成する
ことにより、表面実装型多層回路基板の表面の表面配線
層や回路構成部品の実装効率が向上し、表面実装型多層
回路基板の小型、高密度実装が実現できる。
Also, since the sealing member applied to the surface does not wrap around the surface mount type multilayer circuit board, the mountability on the motherboard is dramatically improved. Further, by forming the surface depressions on the periphery of the surface-mounted multilayer circuit board, the mounting efficiency of the surface wiring layer and circuit components on the surface of the surface-mounted multilayer circuit board is improved, and the surface-mounted multilayer circuit is improved. Small and high-density mounting of the substrate can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の表面実装型多層回路基板の断面図であ
る。
FIG. 1 is a sectional view of a surface mount type multilayer circuit board according to the present invention.

【図2】図1の表面実装型多層回路基板が抽出される大
型表面実装型多層回路基板の部分断面図である。
FIG. 2 is a partial cross-sectional view of a large-sized surface-mounted multilayer circuit board from which the surface-mounted multilayer circuit board of FIG. 1 is extracted.

【図3】図2の大型表面実装型多層回路基板の平面図で
ある。
FIG. 3 is a plan view of the large-sized surface-mount type multilayer circuit board of FIG. 2;

【図4】本発明の表面実装型多層回路基板の他の実施例
の断面図である。
FIG. 4 is a sectional view of another embodiment of the surface mount type multilayer circuit board of the present invention.

【図5】(a)〜(c)は、本発明の表面窪み部の形成
位置を示す平面図である。
FIGS. 5A to 5C are plan views showing formation positions of surface depressions of the present invention.

【図6】本発明の他の実施例の表面窪み部を示す部分断
面図である。
FIG. 6 is a partial sectional view showing a surface depression according to another embodiment of the present invention.

【図7】従来の大型表面実装型多層回路基板の断面図で
ある。
FIG. 7 is a cross-sectional view of a conventional large-sized surface-mount type multilayer circuit board.

【符号の説明】[Explanation of symbols]

11 表面実装型多層回路基板 12 表面窪み部 10 大型表面実装型多層回路基板 1 多層基板 1a〜1e 絶縁層 2 内部配線層 4 表面配線層 5 端子電極 6 回路構成部品 7 封止部材 8 分離線 12 表面窪み部 12a〜12d 貫通孔 DESCRIPTION OF SYMBOLS 11 Surface mount type multilayer circuit board 12 Surface recessed part 10 Large surface mount type multilayer circuit board 1 Multilayer substrate 1a-1e Insulation layer 2 Internal wiring layer 4 Surface wiring layer 5 Terminal electrode 6 Circuit component 7 Sealing member 8 Separation line 12 Surface depression 12a-12d Through hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の絶縁層が積層された多層基板の表
面に、表面配線層及び回路構成部品を配置するととも
に、該表面配線層及び回路構成部品を封止部材で被覆し
て成り、且つ前記多層基板の裏面に端子電極を形成した
表面実装型多層回路基板において、 前記多層基板の表面に表面窪み部を形成するとともに、
該表面窪み部内に前記封止部材を充填させたことを特徴
とする表面実装型多層回路基板。
1. A surface wiring layer and a circuit component are arranged on a surface of a multilayer substrate on which a plurality of insulating layers are stacked, and the surface wiring layer and the circuit component are covered with a sealing member. In a surface-mounted multilayer circuit board having terminal electrodes formed on the back surface of the multilayer board, while forming a surface depression on the surface of the multilayer board,
A surface-mounted multilayer circuit board, wherein the surface recess is filled with the sealing member.
【請求項2】 前記表面窪み部と対向する裏面に、前記
絶縁層のいずれか1層を挟んで、裏面窪み部が形成され
ていることを特徴とする請求項1記載の表面実装型多層
回路基板。
2. The surface-mounted multilayer circuit according to claim 1, wherein a back surface depression is formed on the back surface facing the surface depression portion with one of the insulating layers interposed therebetween. substrate.
【請求項3】 前記表面窪み部は、前記多層基板の周縁
部に形成されていることを特徴とする請求項1または2
記載の表面実装型多層回路基板。
3. The multi-layer substrate according to claim 1, wherein the surface depression is formed at a peripheral edge of the multilayer substrate.
The surface-mounted multilayer circuit board as described.
JP2001163547A 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board Pending JP2002359473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001163547A JP2002359473A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001163547A JP2002359473A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Publications (1)

Publication Number Publication Date
JP2002359473A true JP2002359473A (en) 2002-12-13

Family

ID=19006494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001163547A Pending JP2002359473A (en) 2001-05-31 2001-05-31 Surface-mounted multilayer circuit board

Country Status (1)

Country Link
JP (1) JP2002359473A (en)

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