JP2002359319A - Wiring board incorporating electric element and method of manufacturing it - Google Patents

Wiring board incorporating electric element and method of manufacturing it

Info

Publication number
JP2002359319A
JP2002359319A JP2001164635A JP2001164635A JP2002359319A JP 2002359319 A JP2002359319 A JP 2002359319A JP 2001164635 A JP2001164635 A JP 2001164635A JP 2001164635 A JP2001164635 A JP 2001164635A JP 2002359319 A JP2002359319 A JP 2002359319A
Authority
JP
Japan
Prior art keywords
electric element
wiring board
built
conductive particles
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001164635A
Other languages
Japanese (ja)
Other versions
JP4683770B2 (en
Inventor
Akiya Fujisaki
昭哉 藤崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001164635A priority Critical patent/JP4683770B2/en
Publication of JP2002359319A publication Critical patent/JP2002359319A/en
Application granted granted Critical
Publication of JP4683770B2 publication Critical patent/JP4683770B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board incorporating an electric element of a structure that the electrical connection of thermal electrodes on the electric element with wiring circuit layers and via hole conductors in the wiring board can be modified without processing via holes, and to provide a method of manufacturing the wiring board incorporating the electric element. SOLUTION: A wiring board incorporating an electric element is constituted in a structure that the insulating layer 5 of at least one layer of a plurality of insulating layers 1, 3 and 5 contains conductive grains 19 and the electric element 17 is electrically connected with via hole conductors 11 and/or wiring circuit layers 8, 9, 13 and 15 on the side of the wiring board A via condensed parts 21 using the grains 19.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、多層配線
基板および半導体素子収納用パッケージなどに適し、特
に、絶縁基板内部に電気素子が内蔵されている電気素子
内蔵配線基板およびその製法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a multilayer wiring board and a package for accommodating a semiconductor element, and more particularly to a wiring board with a built-in electric element in which an electric element is built in an insulating substrate and a method for manufacturing the same. is there.

【0002】[0002]

【従来技術】近年、電子機器の高性能化および小型化の
要求に伴い、回路部品の高密度、高機能化に対応した配
線基板が要求されている。このような配線基板として
は、少なくとも有機樹脂を含有する絶縁層を複数積層し
て形成された絶縁基板の表面および/または内部に、複
数の配線回路層と、これらの配線回路層を絶縁層の厚み
方向に接続するビアホール導体が形成されたものが知ら
れており、さらに、この配線基板の内部に積層コンデン
サや半導体素子等の電気素子が半田や導電性接着剤等の
接合剤により接続されている。
2. Description of the Related Art In recent years, with the demand for higher performance and smaller size of electronic equipment, there has been a demand for a wiring board which is compatible with higher density and higher functionality of circuit components. As such a wiring board, a plurality of wiring circuit layers and these wiring circuit layers are formed on the surface and / or inside of an insulating substrate formed by laminating at least a plurality of insulating layers containing an organic resin. It is known that a via hole conductor connected in the thickness direction is formed, and further, an electric element such as a multilayer capacitor or a semiconductor element is connected to the inside of the wiring board by a bonding agent such as solder or a conductive adhesive. I have.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
ような電気素子内蔵配線基板では、配線基板に内蔵され
る積層コンデンサや半導体素子等の電気素子が導電性接
着剤により接続され加熱加圧されることから、内蔵され
る電気素子の端子電極の間隔を狭くした場合に、この端
子電極に塗布された導電性接着剤が変形して広がり、近
接する端子電極間に架橋して配線回路層が短絡するとい
う問題があった。
However, in the above-described wiring board with a built-in electric element, electric elements such as a multilayer capacitor and a semiconductor element built in the wiring board are connected by a conductive adhesive and heated and pressed. Therefore, when the distance between the terminal electrodes of the built-in electric element is reduced, the conductive adhesive applied to the terminal electrodes is deformed and spreads, bridging between adjacent terminal electrodes, and the wiring circuit layer is short-circuited. There was a problem of doing.

【0004】また、配線基板の小型高密度化による配線
回路層の細線化とビアホールの小径化および積層コンデ
ンサ等の電気素子の小型化に伴う端子電極の小型化と端
子電極の狭ピッチ化のために、端子電極と、配線基板に
形成されたビアホール導体や配線回路層とは、接続部の
小面積化や接続位置のずれにより接続が困難となり、配
線基板の電気抵抗の増加やインピーダンス整合ができな
くなるという問題があった。
[0004] Further, to reduce the thickness of the wiring circuit layer and the diameter of the via hole by reducing the size and density of the wiring board, and to reduce the terminal electrodes and the pitch of the terminal electrodes due to the reduction in the size of electric elements such as multilayer capacitors. In addition, the connection between the terminal electrode and the via hole conductor or the wiring circuit layer formed on the wiring board becomes difficult due to the reduction in the area of the connection part or the displacement of the connection position, and the electrical resistance of the wiring board can be increased and impedance matching can be performed. There was a problem that it disappeared.

【0005】また、配線基板に形成されるビアホールの
小径化やビアホール数の増加に伴う加工時間の増大や、
ビアホール加工時に発生する加工屑の除去工程の増加の
ために、製造コスト高になるという問題があった。
In addition, the processing time is increased due to the reduction in the diameter of via holes formed in the wiring board and the increase in the number of via holes,
There is a problem in that the manufacturing cost is increased due to an increase in the number of steps for removing processing waste generated during via hole processing.

【0006】従って、本発明は、電気素子の端子電極と
配線基板の配線回路層やビアホール導体と、ビアホール
を加工することなく電気的接続を改善できる電気素子内
蔵配線基板およびその製法を提供することを目的とす
る。
Accordingly, the present invention provides a wiring board with a built-in electric element and a method of manufacturing the same, which can improve the electrical connection between the terminal electrode of the electric element and the wiring circuit layer or the via hole conductor of the wiring board without processing the via hole. With the goal.

【0007】[0007]

【課題を解決するための手段】本発明者は、上記課題に
対して検討を重ねた結果、電気素子内蔵配線基板を形成
するにあたり、配線基板の内部に、電気素子が接続され
る側の絶縁層として、導電性粒子と熱硬化性樹脂からな
る導電性粒子分散絶縁シートを用いて加熱加圧を行い、
電気素子の突起状端子電極をこの導電性粒子分散シート
に埋設し、端子電極の領域に導電性粒子による凝縮部を
形成することにより、配線基板内部の配線回路層やビア
ホール導体と電気的に安定に接続できる電気素子内蔵配
線基板を提供できることを知見し、本発明に至った。
The inventor of the present invention has studied the above-mentioned problems, and as a result, when forming a wiring board with a built-in electric element, the inside of the wiring board has insulation on the side to which the electric element is connected. As a layer, conducting heating and pressing using a conductive particle-dispersed insulating sheet made of conductive particles and a thermosetting resin,
By embedding the protruding terminal electrode of the electric element in this conductive particle dispersion sheet and forming a condensed part by conductive particles in the area of the terminal electrode, it is electrically stable with the wiring circuit layer and via hole conductor inside the wiring board It has been found that a wiring board with a built-in electric element can be provided which can be connected to a device, and the present invention has been accomplished.

【0008】即ち、本発明の電気素子内蔵配線基板は、
少なくとも有機樹脂を含有する絶縁層を積層してなる絶
縁基板と、該絶縁基板の表面および/または内部に形成
された複数層の配線回路層と、少なくとも前記絶縁基板
内部に金属成分を充填してなるビアホール導体とを具備
する配線基板の内部に端子電極を有する電気素子を内蔵
してなる電気素子内蔵配線基板において、前記複数の絶
縁層のうち、少なくとも1層の前記絶縁層が導電性粒子
を含有し、前記電気素子の端子電極が前記導電性粒子に
よる凝縮部を介して前記配線基板側のビアホール導体お
よび/または配線回路層と電気的に接続してなることを
特徴とするものである。
That is, the wiring board with a built-in electric element of the present invention comprises:
An insulating substrate formed by laminating an insulating layer containing at least an organic resin, a plurality of wiring circuit layers formed on the surface and / or inside of the insulating substrate, and at least a metal component filled in the insulating substrate. In a wiring board with a built-in electrical element having a built-in electrical element having a terminal electrode inside a wiring board having a via hole conductor, at least one of the plurality of insulating layers includes conductive particles. Wherein the terminal electrode of the electric element is electrically connected to a via-hole conductor and / or a wiring circuit layer on the wiring board side via a condensing portion of the conductive particles.

【0009】このような構成によれば、配線基板の配線
回路層やビアホール導体と、電気素子の端子電極とを、
半田や導電性接着剤等の接合剤を用いることなしに接続
することから、加熱加圧時に接合剤の変形や広がりが抑
制され、電気素子と、配線基板内部の配線回路層やビア
ホール導体との接続性を高めることができる。
According to such a configuration, the wiring circuit layer or the via-hole conductor of the wiring board and the terminal electrode of the electric element are connected to each other.
Since the connection is made without using a bonding agent such as solder or a conductive adhesive, the deformation and spread of the bonding agent during heating and pressing are suppressed, and the electric element and the wiring circuit layer or the via-hole conductor inside the wiring board are connected. Connectivity can be improved.

【0010】また、端子電極の位置に導電性粒子を含む
凝縮部を確実に形成できることから、配線基板内部の配
線回路層やビアホール導体と、電気素子の端子電極との
位置のずれを無くして接続でき、配線基板の電気抵抗の
増加を抑制し、インピーダンス整合を高めることができ
る。
[0010] Further, since a condensed portion containing conductive particles can be reliably formed at the position of the terminal electrode, connection is made without displacing the position of the terminal electrode of the electric element with the wiring circuit layer or via hole conductor inside the wiring board. As a result, an increase in the electrical resistance of the wiring board can be suppressed, and the impedance matching can be improved.

【0011】上記電気素子内蔵配線基板では、絶縁層中
の導電性粒子の割合が5〜30体積%であることが望ま
しい。絶縁層中の導電性粒子の含有量をこの範囲に設定
することにより、導電性粒子の不足による導通不良やこ
の導電性粒子の過剰量による短絡を防止し、低い電気抵
抗を有する接続部を形成できる。
In the above-described wiring board with a built-in electric element, the proportion of the conductive particles in the insulating layer is preferably 5 to 30% by volume. By setting the content of the conductive particles in the insulating layer in this range, it is possible to prevent a conduction failure due to a shortage of the conductive particles and a short circuit due to an excessive amount of the conductive particles, and form a connection portion having a low electric resistance. it can.

【0012】上記電気素子内蔵配線基板では、導電性粒
子が、Ag、Cu、NiおよびAuから選ばれる1種あ
るいはこれらの合金からなることが望ましい。凝縮部を
構成する導電性粒子として、低抵抗の金属を用いること
により、配線基板内の伝送速度を高めることができる。
In the wiring board with a built-in electric element, the conductive particles are desirably made of one kind selected from Ag, Cu, Ni and Au, or an alloy thereof. By using a low-resistance metal as the conductive particles constituting the condensing portion, the transmission speed in the wiring board can be increased.

【0013】上記電気素子内蔵配線基板では、導電性粒
子が略球状粒子であることが望ましい。このように凝縮
部を構成する導電性粒子の形状を略球状とすることによ
り、導電性粒子同士の接触点において絶縁層に含まれる
熱硬化性樹脂を排除し、電気的接続性を高めることがで
きる。
In the above-mentioned wiring board with a built-in electric element, the conductive particles are preferably substantially spherical particles. By making the shape of the conductive particles constituting the condensing portion substantially spherical as described above, the thermosetting resin contained in the insulating layer at the contact points between the conductive particles can be eliminated, and the electrical connectivity can be improved. it can.

【0014】上記電気素子内蔵配線基板では、導電性粒
子の平均粒径が10μm以下であることが望ましい。こ
のように平均粒径の小さい導電性粒子を用いることによ
り、絶縁層内部における導電性粒子の均一分散性を高
め、凝縮部とそれ以外の部分の電気抵抗差を大きくで
き、凝縮部における電気的接続性を高めることができ
る。
In the wiring board with a built-in electric element, the average particle size of the conductive particles is preferably 10 μm or less. By using the conductive particles having a small average particle size in this manner, the uniform dispersibility of the conductive particles inside the insulating layer can be increased, and the difference in electric resistance between the condensing portion and the other portions can be increased. Connectivity can be improved.

【0015】上記電気素子内蔵配線基板では、電気素子
が該電気素子の少なくとも主面側に突起状の端子電極を
具備することが望ましい。このように端子電極が電気素
子の主面側に凸状に形成されているため、この突起状の
端子電極が絶縁層に形成される導電性粒子を強制的に押
し込むことにより、凝縮部の密度を高め、電気素子に形
成された端子電極と配線回路層やビアホール導体との電
気的接続性を高めることができる。
In the above-mentioned wiring board with a built-in electric element, it is desirable that the electric element has a protruding terminal electrode on at least the main surface side of the electric element. Since the terminal electrodes are formed in a convex shape on the main surface side of the electric element, the protruding terminal electrodes forcibly push the conductive particles formed on the insulating layer, thereby reducing the density of the condensed portion. And the electrical connection between the terminal electrode formed on the electric element and the wiring circuit layer or via-hole conductor can be improved.

【0016】上記電気素子内蔵配線基板では、電気素子
の厚みが絶縁層厚みの50〜95%であることが望まし
い。このように電気素子の主面から端子電極をより高く
することにより導電性粒子の凝縮部の密度をさらに高く
でき、この凝縮部の電気抵抗を低下させ、電気素子と配
線基板との電気的接続性を高めることができるとともに
位置ずれを防止できる。
In the above wiring board with a built-in electric element, the thickness of the electric element is preferably 50 to 95% of the thickness of the insulating layer. By making the terminal electrode higher from the main surface of the electric element in this way, the density of the condensed portion of the conductive particles can be further increased, the electric resistance of the condensed portion is reduced, and the electric connection between the electric element and the wiring board is reduced. Performance can be improved and misalignment can be prevented.

【0017】上記電気素子内蔵配線基板では、突起状の
端子電極の高さが、絶縁層厚みの20〜65%であるこ
とが望ましい。配線基板の内部に内蔵される電気素子が
絶縁層の厚みに比較して薄くすることにより、絶縁層の
変形を抑制し、配線基板内部での電気素子の位置ずれを
防止できる。
In the wiring board with a built-in electric element, the height of the protruding terminal electrode is preferably 20 to 65% of the thickness of the insulating layer. By making the electric element built inside the wiring board thinner than the thickness of the insulating layer, the deformation of the insulating layer can be suppressed, and the displacement of the electric element inside the wiring board can be prevented.

【0018】上記電気素子内蔵配線基板では、電気素子
において、最近接する端子電極間距離が400μm以下
であることが望ましい。電気素子の接続部として、導電
性粒子による凝縮部を形成することにより、半田や導電
性接着剤等の接合剤を用いる場合のような、接合剤の変
形や広がりが抑制できることから、配線基板の配線回路
層や電気素子の端子電極の間隔を狭くできる。
In the above-described wiring board with a built-in electric element, it is desirable that the distance between the terminal electrodes closest to the electric element is 400 μm or less. By forming a condensed portion made of conductive particles as the connection portion of the electric element, the deformation and spread of the bonding agent, such as when using a bonding agent such as solder or a conductive adhesive, can be suppressed. The distance between the wiring circuit layer and the terminal electrode of the electric element can be reduced.

【0019】上記電気素子内蔵配線基板では、電気素子
が内部電極層と誘電体層とを交互に積層して形成された
積層コンデンサであることが望ましい。
In the wiring board with a built-in electric element, the electric element is preferably a multilayer capacitor formed by alternately laminating internal electrode layers and dielectric layers.

【0020】配線基板に内蔵される電気素子が積層コン
デンサであれば、より小型化された電気素子を用いて配
線基板の静電容量およびインダクタンスを効果的に制御
でき、電気素子内蔵配線基板としてその有用性を高める
ことができる。
If the electric element incorporated in the wiring board is a multilayer capacitor, the capacitance and inductance of the wiring board can be effectively controlled by using a more miniaturized electric element. Usability can be enhanced.

【0021】本発明の電気素子内蔵配線基板の製法は、
(a)電気素子の少なくとも一方主面に突起状の端子電
極を形成する工程と、(b)未硬化または半硬化の熱硬
化性樹脂および無機フィラーを含有する絶縁シートを形
成する工程と、(c)未硬化または半硬化の熱硬化性樹
脂および導電性粒子を含有する導電性粒子分散絶縁シー
トを形成する工程と、(d)前記無機フィラーを含有す
る絶縁シートの所定箇所にビアホール導体を形成する工
程と、(e)可とう性フィルムの表面に金属箔からなる
配線回路パターンが形成された転写シートを形成する工
程と、(f)(d)工程によって得られた絶縁シートの
表面に転写シートを熱圧着して、配線回路パターンが形
成された配線回路シートを形成する工程と、(g)
(c)工程のよって得られた導電性粒子分散絶縁シート
の表面に転写シートを熱圧着して、配線回路パターンが
形成された導電部形成配線回路シートを形成する工程
と、(h)(f)工程によって得られた前記複数の配線
回路シートの層間に、(g)工程によって得られた前記
導電部形成配線回路シートを少なくとも1層積層すると
ともに、前記配線回路シートと前記導電部形成配線回路
シートとの層間の所定位置に電気素子を載置した仮積層
体を作製する工程と、(i)前記仮積層体を加熱加圧し
て、前記絶縁シートおよび導電性粒子分散絶縁シート中
に含まれる前記熱硬化性樹脂を硬化するとともに、前記
電気素子に形成された突起状の端子電極の延長方向に導
電性粒子を含む凝縮部を形成する工程と、を具備する製
法である。
The manufacturing method of the wiring board with a built-in electric element of the present invention is as follows.
(A) a step of forming a protruding terminal electrode on at least one main surface of the electric element, and (b) a step of forming an insulating sheet containing an uncured or semi-cured thermosetting resin and an inorganic filler; c) forming a conductive particle-dispersed insulating sheet containing an uncured or semi-cured thermosetting resin and conductive particles, and (d) forming a via-hole conductor at a predetermined position of the insulating sheet containing the inorganic filler. (E) forming a transfer sheet in which a wiring circuit pattern made of a metal foil is formed on the surface of a flexible film; and (f) transferring to the surface of the insulating sheet obtained by the (d) step. (G) a step of thermocompression bonding the sheet to form a wiring circuit sheet on which a wiring circuit pattern is formed;
(C) a step of thermocompression-bonding the transfer sheet to the surface of the conductive particle-dispersed insulating sheet obtained in the step to form a conductive portion forming wiring circuit sheet on which a wiring circuit pattern is formed; (h) (f) A) laminating at least one layer of the conductive part forming wiring circuit sheet obtained in the step (g) between the layers of the plurality of wiring circuit sheets obtained in the step; A step of preparing a temporary laminate in which an electric element is placed at a predetermined position between layers between the sheet and the sheet; and (i) heating and pressurizing the temporary laminate to be included in the insulating sheet and the conductive particle-dispersed insulating sheet. Curing the thermosetting resin and forming a condensed portion containing conductive particles in the extending direction of the protruding terminal electrode formed on the electric element.

【0022】この製法によれば、予め形成した配線回路
パターンを未硬化の絶縁シートに転写することにより、
配線回路パターンをその表面に埋設して形成し、一括硬
化により容易に配線基板を形成できる。
According to this manufacturing method, the previously formed wiring circuit pattern is transferred to the uncured insulating sheet,
The wiring circuit pattern is formed by being buried on the surface thereof, and the wiring substrate can be easily formed by batch curing.

【0023】また、この電気素子の端子電極と、配線基
板に形成された配線回路パターンやビアホール導体とを
一括硬化時に接合し、電気素子を配線基板の内部に一括
して内蔵できる。
Further, the terminal electrodes of the electric element and the wiring circuit patterns and via-hole conductors formed on the wiring board are joined together at the time of curing, so that the electric element can be built in the wiring board at a time.

【0024】さらに、電気素子が当接する絶縁層とし
て、導電性粒子と熱硬化性樹脂とを混合して形成した導
電性粒子分散絶縁シートを用いることにより、半田や導
電性接着剤等の接合剤を付与することなしに、電気素子
を配線基板の配線回路層やビアホール導体に容易に接続
できる。
Furthermore, by using a conductive particle-dispersed insulating sheet formed by mixing conductive particles and a thermosetting resin as the insulating layer with which the electric element contacts, a bonding agent such as solder or a conductive adhesive is used. The electric element can be easily connected to the wiring circuit layer of the wiring board and the via-hole conductor without providing the wiring board.

【0025】そして、本発明の製法によれば、電気素子
や配線回路層と接続されるビアホール導体を加工する必
要がないことから製造コストを低減できる。
According to the manufacturing method of the present invention, it is not necessary to process a via-hole conductor connected to an electric element or a wiring circuit layer, so that the manufacturing cost can be reduced.

【0026】上記電気素子内蔵配線基板の製法では、
(c)工程において、絶縁層中の導電性粒子の割合が5
〜30体積%であることが望ましく、この工程では、絶
縁層中の導電性粒子の含有量をこの範囲に設定すること
により、加圧加熱工程において電気素子の端子電極と配
線回路層やビアホール導体との間に形成される導電性粒
子の凝縮部を容易に形成できるとともに、導電性の高い
凝縮部を形成できる。
In the method of manufacturing a wiring board with a built-in electric element,
In the step (c), the ratio of the conductive particles in the insulating layer is 5
In this step, the content of the conductive particles in the insulating layer is set in this range, so that the terminal electrodes of the electric element and the wiring circuit layer or the via hole conductor are formed in the pressurizing and heating step. The condensed portion of the conductive particles formed between them can be easily formed, and a highly conductive condensed portion can be formed.

【0027】上記電気素子内蔵配線基板の製法では、
(c)工程において、導電性粒子が、Ag、Cu、Ni
およびAuから選ばれる1種あるいはこれらの合金から
なることが望ましい。
In the above-described method of manufacturing a wiring board with a built-in electric element,
In the step (c), the conductive particles are made of Ag, Cu, Ni.
It is desirable to be made of one or an alloy selected from Au and Au.

【0028】この工程では、上記のように高導電率を有
する導電性粒子により構成されることから、高い導電性
を有する凝縮部を容易に形成できる。
In this step, a condensed part having high conductivity can be easily formed because the conductive part is made of the conductive particles having high conductivity as described above.

【0029】上記電気素子内蔵配線基板の製法では、
(c)工程において、導電性粒子が略球状粒子であるこ
とが望ましい。この工程では、絶縁シート中に含まれる
導電性粒子を略球状とすることにより、加圧加熱時に導
電性粒子同士の接触点における絶縁層に含まれる熱硬化
性樹脂を容易に排除でき、凝縮部の電気的接続性を高め
ることができる。
In the method of manufacturing the wiring board with a built-in electric element,
In the step (c), the conductive particles are preferably substantially spherical particles. In this step, the conductive particles contained in the insulating sheet are made substantially spherical, so that the thermosetting resin contained in the insulating layer at the contact point between the conductive particles at the time of pressurizing and heating can be easily removed, and the condensing section Can be improved in electrical connectivity.

【0030】上記電気素子内蔵配線基板の製法では、
(c)工程において、導電性粒子の平均粒径が10μm
以下であることが望ましい。この工程では、絶縁層厚み
に比較して粒子径の小さい導電性粒子を用いることによ
り、加熱加圧により、導電性粒子から構成される凝縮部
を容易に形成でき、この凝縮部とそれ以外の部分の電気
抵抗差を大きくできる。
In the above-described method of manufacturing a wiring board with a built-in electric element,
In the step (c), the average particle size of the conductive particles is 10 μm.
It is desirable that: In this step, by using conductive particles having a smaller particle diameter than the thickness of the insulating layer, a condensed portion composed of the conductive particles can be easily formed by heating and pressurizing. The difference in electrical resistance between the parts can be increased.

【0031】上記電気素子内蔵配線基板の製法では、電
気素子が該電気素子の少なくとも主面側に突起状の端子
電極を具備することが望ましい。
In the method of manufacturing a wiring board with a built-in electric element, the electric element preferably has a protruding terminal electrode on at least the main surface side of the electric element.

【0032】この工程では、端子電極が凸状であること
から、加熱加圧時に、導電性粒子を強制的に押し込むこ
とにより、容易に凝縮部の密度を高め、電気素子の端子
電極と配線回路層やビアホール導体との電気的接続性を
高めることができる。
In this step, since the terminal electrodes are convex, the density of the condensed portion can be easily increased by forcibly pushing in the conductive particles during heating and pressurization, and the terminal electrodes of the electric element and the wiring circuit Electrical connectivity with the layer and via-hole conductor can be improved.

【0033】上記電気素子内蔵配線基板の製法では、電
気素子の厚みが絶縁層厚みの50〜95%であることが
望ましい。この工程では、電気素子の主面から端子電極
をより高く形成することにより、加圧加熱時に、さらに
導電性粒子を強制的に押し込むことにより、導電性粒子
の凝縮部の密度をさらに高くでき、この凝縮部の電気抵
抗を低下させ、電気素子と配線基板との電気的接続性を
高めることができる。
In the method of manufacturing a wiring board with a built-in electric element, the thickness of the electric element is desirably 50 to 95% of the thickness of the insulating layer. In this step, by forming the terminal electrode higher from the main surface of the electric element, during pressurizing and heating, the conductive particles are forcibly pushed in, so that the density of the condensed portion of the conductive particles can be further increased, The electric resistance of the condensing part can be reduced, and the electrical connection between the electric element and the wiring board can be improved.

【0034】上記電気素子内蔵配線基板の製法では、突
起状端子電極の厚みが、絶縁層厚みの20〜65%であ
ることが望ましい。この工程では、配線基板の内部に内
蔵される電気素子の厚みが絶縁層の厚みに比較して薄
く、端子電極の突起がこの範囲の高さを有することによ
り絶縁層の変形を抑制でき、容易に、電気素子を内蔵で
きる。
In the above-mentioned method of manufacturing a wiring board with a built-in electric element, the thickness of the protruding terminal electrode is preferably 20 to 65% of the thickness of the insulating layer. In this step, the thickness of the electric element incorporated inside the wiring board is smaller than the thickness of the insulating layer, and the protrusion of the terminal electrode has a height in this range, so that the deformation of the insulating layer can be suppressed, and In addition, an electric element can be incorporated.

【0035】上記電気素子内蔵配線基板の製法では、電
気素子が複数の端子電極を有し、該端子電極の最近接す
る端子電極間距離が400μm以下であることが望まし
い。この工程では、半田や導電性接着剤等の接合剤を用
いることなしに、電気素子と接続できることから、接合
剤の変形や広がりを抑制でき、接合剤による端子電極間
の短絡を防止できることから、電気素子の端子電極間隔
を狭くできる。
In the method of manufacturing a wiring board with a built-in electric element, the electric element preferably has a plurality of terminal electrodes, and the distance between the terminal electrodes closest to the terminal electrodes is preferably 400 μm or less. In this step, since it can be connected to the electric element without using a bonding agent such as solder or conductive adhesive, deformation and spreading of the bonding agent can be suppressed, and a short circuit between the terminal electrodes due to the bonding agent can be prevented. The distance between the terminal electrodes of the electric element can be reduced.

【0036】上記電気素子内蔵配線基板の製法では、電
気素子が内部電極層と誘電体層とを交互に積層して形成
された積層コンデンサであることが望ましい。この工程
では、電気素子が積層コンデンサであれば、小型化しや
すく、一括硬化においても配線基板内に容易に内蔵で
き、配線基板の静電容量およびインダクタンスを効果的
に制御できる。
In the above-described method for manufacturing a wiring board with a built-in electric element, it is preferable that the electric element is a multilayer capacitor formed by alternately stacking internal electrode layers and dielectric layers. In this step, if the electric element is a multilayer capacitor, it can be easily reduced in size, can be easily incorporated into the wiring board even when it is cured at once, and the capacitance and inductance of the wiring board can be effectively controlled.

【0037】[0037]

【発明の実施の形態】(構造)本発明の電気素子内蔵配
線基板の一形態について、図1の概略断面図をもとに詳
細に説明する。本発明の配線基板Aは、少なくとも有機
樹脂を含有する絶縁層1、3、5を積層した絶縁基板7
を備えているが、絶縁層1、3の間に位置する絶縁層5
には導電性粒子19が含まれている。また、絶縁基板7
の両表面に配線回路層8、9が形成され、さらに、これ
らの絶縁層1、3には、厚み方向にビアホール導体11
が形成されており、このビアホール導体11は、絶縁基
板7の、表面の配線回路層8、9と内部の配線回路層1
3、15とを電気的に接続している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure) One embodiment of the wiring board with a built-in electric element of the present invention will be described in detail with reference to the schematic sectional view of FIG. The wiring board A according to the present invention includes an insulating substrate 7 on which insulating layers 1, 3, and 5 containing at least an organic resin are laminated.
But the insulating layer 5 located between the insulating layers 1 and 3
Contains conductive particles 19. Also, the insulating substrate 7
The wiring circuit layers 8 and 9 are formed on both surfaces of the insulating layer 1 and the insulating layers 1 and 3.
Are formed. The via-hole conductors 11 are connected to the wiring circuit layers 8 and 9 on the surface of the insulating substrate 7 and the wiring circuit layer 1 inside the insulating substrate 7.
3, 15 are electrically connected.

【0038】また、配線回路層13、15には絶縁層5
側に突起25が形成されており、この突起25による絶
縁層5中の導電性粒子19の押し込みにより、導電性粒
子19により構成された凝縮ビア23が形成され、配線
基板A内部の配線回路層13、15間および配線回路層
8、9間をビアホール導体を形成することなしに接続さ
れている。
The insulating layers 5 are provided on the wiring circuit layers 13 and 15.
A projection 25 is formed on the side of the wiring board A. When the conductive particles 19 in the insulating layer 5 are pushed by the projection 25, a condensation via 23 made of the conductive particles 19 is formed. 13 and 15 and between the wiring circuit layers 8 and 9 are connected without forming a via-hole conductor.

【0039】また、この凝縮ビア23に当接する突起2
5の高さは、凝縮ビア23変形を抑え且つ導電性を高め
るために、絶縁層5の厚みの50〜95%、特に、50
〜70%が望ましい。
Further, the projections 2 contacting the condensation via 23
The height of the insulating layer 5 is 50 to 95% of the thickness of the insulating layer 5, particularly 50 to 95%, in order to suppress the deformation of the condensation via 23 and increase the conductivity.
~ 70% is desirable.

【0040】また、絶縁層1と導電性粒子19を含む絶
縁層5の間には、電気素子17が埋設され、この電気素
子17は絶縁層5の内部に形成された導電性粒子19に
よりなる凝縮部21を介して絶縁層5の上面側の配線回
路層15に接続されている。
An electric element 17 is embedded between the insulating layer 1 and the insulating layer 5 containing the conductive particles 19, and the electric element 17 is made of the conductive particles 19 formed inside the insulating layer 5. It is connected to the wiring circuit layer 15 on the upper surface side of the insulating layer 5 via the condenser 21.

【0041】このようにして導電性粒子19から構成さ
れた凝縮部21により接続された電気素子17を備える
電気素子内蔵配線基板が構成されている。
In this manner, a wiring board with a built-in electric element including the electric elements 17 connected by the condensing portion 21 composed of the conductive particles 19 is formed.

【0042】そして、絶縁層5内の凝縮部21を形成し
ている導電性粒子19は、導電性粒子19の不足による
導通不良や、一方、導電性粒子19の過剰量による短絡
を防止し、低い電気抵抗を有する接続部を形成するとい
う理由から体積分率で5〜30体積%の割合で含有する
ことが望ましい。特に、電気抵抗を下げ、インピーダン
ス整合を安定化させるという理由から、絶縁層5中の導
電性粒子19の量は10〜25体積%であることがより
望ましい。
The conductive particles 19 forming the condensed portion 21 in the insulating layer 5 prevent conduction failure due to shortage of the conductive particles 19 and short-circuit due to excessive amount of the conductive particles 19, It is desirable that the content be 5 to 30% by volume in volume fraction because a connection portion having low electric resistance is formed. In particular, the amount of the conductive particles 19 in the insulating layer 5 is more preferably 10 to 25% by volume because the electric resistance is reduced and the impedance matching is stabilized.

【0043】また、凝縮部21を形成する導電性粒子1
9が、Ag、Cu、NiおよびAuから選ばれる1種あ
るいはこれらの合金からなることが望ましい。このよう
に低抵抗の金属を用いることによって導電性粒子19に
より形成された凝縮部21の電気抵抗を低く抑えること
ができる。特に、導電率が高く、廉価という理由からC
uが好適に用いられる。さらに、耐マイグレーション性
を高めるという理由からAg−Cu合金を用いることが
できる。
The conductive particles 1 forming the condensing portion 21
Desirably, 9 is made of one selected from Ag, Cu, Ni and Au, or an alloy thereof. By using such a low-resistance metal, the electrical resistance of the condensing portion 21 formed by the conductive particles 19 can be suppressed low. In particular, C is preferred because of its high conductivity and low cost.
u is preferably used. Further, an Ag—Cu alloy can be used for the purpose of improving migration resistance.

【0044】また、凝縮部21を形成している導電性粒
子19の形状は、導電性粒子19同士の接触点において
絶縁層5に含まれる熱硬化性樹脂を排除し易く、凝縮部
21の電気的接続性を高められるといという理由から球
状あるいは略球状粒子であることが望ましい。尚、この
ように球状あるいは略球状粒子からなる導電性粒子19
は均一な粒径であることが望ましいが、凝縮部21の充
填密度を高めるという理由から粒度分布を有しているこ
とがより望ましい。
Further, the shape of the conductive particles 19 forming the condensing portion 21 makes it easy to remove the thermosetting resin contained in the insulating layer 5 at the contact points between the conductive particles 19, so that the electric conductivity of the condensing portion 21 can be reduced. Spherical or substantially spherical particles are desirable because they can enhance the physical connectivity. The conductive particles 19 formed of spherical or substantially spherical particles as described above.
Has a uniform particle size, but more preferably has a particle size distribution because the packing density of the condensing section 21 is increased.

【0045】そして、導電性粒子19の平均粒径は絶縁
層厚みよりも小さく、10μm以下であることが、絶縁
層5の任意の場所における凝縮部21の大きさを均一に
するという理由から望ましく、特に、電気抵抗を均一に
するという理由から導電性粒子19の平均粒径は1〜5
μmであることが望ましい。
The average particle size of the conductive particles 19 is preferably smaller than the thickness of the insulating layer and equal to or less than 10 μm, because the size of the condensing portion 21 at an arbitrary position of the insulating layer 5 is made uniform. In particular, the average particle size of the conductive particles 19 is 1 to 5 because the electric resistance is made uniform.
μm is desirable.

【0046】電気素子17は、例えば、図2に示すよう
に、複数の内部電極層30a、30bと複数の誘電体層
31a、31bとを交互に積層してなる電気素子本体3
2と、この電気素子本体32の4角端部にそれぞれ設け
られた4個の端子電極27a、27b、29a、29b
とから構成されており、内部電極層30aは端子電極2
7a、27bと、一方、内部電極層30aとは交互に積
層されている内部電極層30bは、端子電極29a、2
9bと接続されている。
The electric element 17 is, for example, as shown in FIG. 2, an electric element main body 3 formed by alternately laminating a plurality of internal electrode layers 30a, 30b and a plurality of dielectric layers 31a, 31b.
2 and four terminal electrodes 27a, 27b, 29a, 29b provided at the four corners of the electric element body 32, respectively.
And the internal electrode layer 30a is provided with the terminal electrode 2
7a and 27b, and the internal electrode layer 30b alternately laminated with the internal electrode layer 30a form terminal electrodes 29a and 2a.
9b.

【0047】尚、上記のように、端子電極27a、27
b、29a、29bが電気素子本体32の端面から主面
にかけて形成されている構造であれば、端子電極27
a、27b、29a、29bの数および間隔は任意に変
更することができる。
As described above, the terminal electrodes 27a, 27
b, 29a and 29b are formed from the end face to the main face of the electric element main body 32, the terminal electrode 27
The numbers and intervals of a, 27b, 29a, 29b can be arbitrarily changed.

【0048】そして、この例では、内蔵される電気素子
17は1個であるが、本発明の配線基板Aでは、複数の
電気素子17を内蔵することもできる。
In this example, one electric element 17 is incorporated, but a plurality of electric elements 17 can be incorporated in the wiring board A of the present invention.

【0049】そして、この電気素子17の端部に形成さ
れた端子電極27a、27b、29a、29bは、絶縁
層5の内部の導電性粒子19により形成される凝縮部2
1を端子電極27a、27b、29a、29bの直下に
形成するという理由から、電気素子17の主面方向に突
起状に形成されていることが望ましく、さらに、この突
起状に形成された端子電極27a、27b、29a、2
9bの頂部33は導電性粒子19を絶縁層5の厚み方向
に均一に押し込むことができるという理由から、電気素
子17の主面に平行に平坦化されていることが望まし
い。
The terminal electrodes 27 a, 27 b, 29 a, and 29 b formed at the end of the electric element 17 are connected to the condensing section 2 formed by the conductive particles 19 inside the insulating layer 5.
1 is formed immediately below the terminal electrodes 27a, 27b, 29a, and 29b, it is preferable that the electrode 1 be formed in a projecting shape in the direction of the main surface of the electric element 17, and furthermore, the terminal electrode formed in this projecting shape 27a, 27b, 29a, 2
It is desirable that the top 33 of 9 b is flattened in parallel with the main surface of the electric element 17 because the conductive particles 19 can be uniformly pushed in the thickness direction of the insulating layer 5.

【0050】また、電気素子17の厚みは絶縁層厚みの
50〜95%であることが、配線基板Aの内部に内蔵さ
れる電気素子17が絶縁層の厚みに比較して薄くするこ
とにより、絶縁層5ならびに絶縁層1、3の変形を抑制
し、配線基板A内部での電気素子17の位置ずれを防止
できるという理由から望ましい。さらに、絶縁層5の厚
みに対するこの電気素子17の厚みは60〜80%が望
ましい。
The thickness of the electric element 17 is 50 to 95% of the thickness of the insulating layer. This is because the electric element 17 built in the wiring board A is made thinner than the insulating layer. This is desirable because the deformation of the insulating layer 5 and the insulating layers 1 and 3 can be suppressed, and the displacement of the electric element 17 inside the wiring board A can be prevented. Further, the thickness of the electric element 17 with respect to the thickness of the insulating layer 5 is desirably 60 to 80%.

【0051】また、端子電極27a、27b、29a、
29bの突起の高さは、絶縁層厚みの20〜65%であ
ることが、導電性粒子19の強制的な押し込みを強く
し、凝縮部21の密度をさらに高くでき、この凝縮部2
1の電気抵抗を低下させ、電気素子17と配線基板Aと
の電気的接続性を高めることができるという理由から望
ましい。そして、端子電極27a、27b、29a、2
9bの高さは、特には、30〜50%が望ましい。
The terminal electrodes 27a, 27b, 29a,
When the height of the protrusions 29b is 20 to 65% of the thickness of the insulating layer, the forced indentation of the conductive particles 19 can be strengthened, and the density of the condensing portion 21 can be further increased.
1 is preferable because the electrical resistance of the electrical element 17 can be reduced and the electrical connectivity between the electrical element 17 and the wiring board A can be increased. Then, the terminal electrodes 27a, 27b, 29a, 2
The height of 9b is particularly preferably 30 to 50%.

【0052】また、電気素子17に形成される端子電極
27a、27b、29a、29bに関し、最も近接する
端子電極間距離(近接する端子電極の周縁部同士の間
隔)が400μm以下であることが望ましい。このよう
に導電性粒子19から形成される凝縮部21により配線
基板Aに内蔵される電気素子17が接続されるような接
合の場合に、電気素子17と、配線基板Aの配線回路層
13、15やビアホール導体11間に、あらためてボリ
ュームのある半田や導電性接着剤等の接合剤を付与する
必要がないことから好適に用いることができ、特に、端
子電極間距離は50〜350μmであることがこの端子
電極間の絶縁性を確保できるという理由から望ましい。
Further, with respect to the terminal electrodes 27a, 27b, 29a and 29b formed on the electric element 17, it is desirable that the distance between the closest terminal electrodes (the distance between the peripheral edges of the adjacent terminal electrodes) is 400 μm or less. . In the case where the electric element 17 incorporated in the wiring board A is connected by the condensing portion 21 formed of the conductive particles 19 as described above, the electric element 17 and the wiring circuit layer 13 of the wiring board A 15 and via-hole conductors 11 and can be suitably used because it is not necessary to apply a bonding agent such as a solder having a large volume or a conductive adhesive again. In particular, the distance between terminal electrodes is 50 to 350 μm. Is desirable because insulation between the terminal electrodes can be ensured.

【0053】また、この電気素子内蔵配線基板Bに内蔵
される電気素子17は、小型化および高容量化を同時に
満たす電気素子17を形成することができるという理由
から、チップ部品が好適に用いられ、特に、図2に示し
たような積層コンデンサからなることが望ましいが、こ
の他、チップ抵抗やチップインダクタも好適に用いるこ
とができる。尚、積層コンデンサは、BaTiO3を主
成分とするセラミック誘電体層とNi、Cu等の卑金属
あるいはAg、Pd等の貴金属からなる内部電極とが交
互に積層され形成されている。
Further, as the electric element 17 incorporated in the electric element built-in wiring board B, a chip component is preferably used because the electric element 17 which satisfies both miniaturization and high capacity can be formed at the same time. In particular, it is desirable to use a multilayer capacitor as shown in FIG. 2, but in addition, a chip resistor and a chip inductor can also be suitably used. The multilayer capacitor is formed by alternately laminating a ceramic dielectric layer mainly composed of BaTiO 3 and internal electrodes made of a base metal such as Ni or Cu or a noble metal such as Ag or Pd.

【0054】また、積層コンデンサを複数個並列回路に
て内蔵することもでき、その場合には、静電容量の向上
とともに、インダクタンスの低減を図ることができる。
複数個内蔵する場合には、静電容量の異なる積層コンデ
ンサを内蔵することもでき、さらには、積層コンデンサ
以外のチップ部品を同時に内蔵することもできる。
A plurality of multilayer capacitors can be built in a parallel circuit. In this case, the capacitance can be improved and the inductance can be reduced.
When a plurality of capacitors are incorporated, multilayer capacitors having different capacitances can be incorporated, and further, chip components other than the multilayer capacitors can be incorporated at the same time.

【0055】(材料)本発明の配線基板Aにおける絶縁
基板7の材質としては、上記のような電気素子内蔵構造
が形成可能であれば、いわゆる焼結体からなるセラミッ
ク系絶縁材料、または絶縁成分として、少なくとも有機
樹脂を含有する有機系絶縁材料のいずれであってもよい
が、予め形成された複数の電極を具備する電気素子17
を基板内部に埋設した構造を形成する上では、焼成工程
を必要としない有機樹脂を含有するもの、特に無機フィ
ラーと有機樹脂からなる絶縁材料が望ましい。
(Material) As the material of the insulating substrate 7 in the wiring board A of the present invention, a ceramic insulating material made of a so-called sintered body, or an insulating component, as long as the above-described electric element built-in structure can be formed. Any one of an organic insulating material containing at least an organic resin may be used, but an electric element 17 having a plurality of electrodes formed in advance may be used.
In order to form a structure in which is embedded in the substrate, a material containing an organic resin that does not require a firing step, particularly an insulating material composed of an inorganic filler and an organic resin, is desirable.

【0056】また、配線基板Aにおける絶縁基板7のう
ち絶縁層1、3は熱硬化性樹脂と無機フィラーとの複合
体によって構成されている。無機フィラーは、例えば、
SiO2、Al23、AlN、SiCの群から選ばれる
少なくとも1種を好適に用いることができる。
The insulating layers 1 and 3 of the insulating substrate 7 in the wiring board A are made of a composite of a thermosetting resin and an inorganic filler. The inorganic filler, for example,
At least one selected from the group consisting of SiO 2 , Al 2 O 3 , AlN, and SiC can be suitably used.

【0057】無機フィラーとして、SiO2を用いた場
合は絶縁層1、3の比誘電率を小さくすることができ
る。また、無機フィラーとして、Al23を用いた場合
には配線基板Aの熱伝導率を高めることができる。特
に、電子機器の小型化、高性能化を目的として、高速伝
送を行うためには、低誘電率のSiO2を用いることが
望ましい。
When SiO 2 is used as the inorganic filler, the relative permittivity of the insulating layers 1 and 3 can be reduced. Further, when Al 2 O 3 is used as the inorganic filler, the thermal conductivity of the wiring board A can be increased. In particular, in order to perform high-speed transmission for the purpose of miniaturization and high performance of electronic devices, it is desirable to use SiO 2 having a low dielectric constant.

【0058】そして、上記の絶縁層1、3に含まれる熱
硬化性樹脂としては、ポリフェニレンエーテル(APP
E)系樹脂、エポキシ系樹脂、ポリイミド樹脂、フッ素
樹脂、フェノール樹脂およびシアネート系樹脂の群から
選ばれる少なくとも1種が好ましい。この中でAPPE
樹脂は比誘電率が低く、誘電損失が低く、吸水率が低
く、さらに、ガラス転移点が高いために、高耐熱性であ
ることから、特に好ましい。さらに、混合物はフィラー
とのぬれ性を改善するために、分散剤やカップリング剤
を含んでもよい。
The thermosetting resin contained in the insulating layers 1 and 3 is polyphenylene ether (APP).
E) At least one selected from the group consisting of a resin, an epoxy resin, a polyimide resin, a fluorine resin, a phenol resin and a cyanate resin is preferable. APPE
The resin is particularly preferable because it has a low relative dielectric constant, a low dielectric loss, a low water absorption, and a high glass transition point, and thus has high heat resistance. Further, the mixture may contain a dispersant or a coupling agent to improve the wettability with the filler.

【0059】尚、熱硬化性樹脂と無機フィラーとの複合
材料においては、有機樹脂:無機フィラーとは、体積比
率で50:50〜95:5の比率で複合化されることが
望ましい。また、無機フィラーの表面は有機樹脂との塗
れを良くするために、カップリング処理されていても良
い。
In the composite material of the thermosetting resin and the inorganic filler, it is desirable that the organic resin and the inorganic filler are combined in a volume ratio of 50:50 to 95: 5. Further, the surface of the inorganic filler may be subjected to a coupling treatment in order to improve the wettability with the organic resin.

【0060】さらに、熱硬化性樹脂と無機フィラーとの
複合材によって絶縁層1、3を形成すれば、絶縁シート
の熱的安定性とともに機械的強度を高めることができ
る。また、通常のガラス−エポキシ基板等に比較して、
フィラーが繊維状ではないことから、フィラーと有機樹
脂との界面が孤立している形態をとることができ、マイ
グレーションが進展しにくくなり絶縁信頼性を高めるこ
とができる。
Further, if the insulating layers 1 and 3 are formed of a composite material of a thermosetting resin and an inorganic filler, the mechanical strength as well as the thermal stability of the insulating sheet can be increased. Also, compared to a normal glass-epoxy substrate, etc.
Since the filler is not fibrous, the interface between the filler and the organic resin can be isolated, so that migration does not easily progress and insulation reliability can be improved.

【0061】一方、導電性粒子19と熱硬化性樹脂との
複合体から構成されている絶縁層5では、導電性粒子1
9は、Ag、Cu、NiおよびAuから選ばれる1種あ
るいはこれらの合金からなることが望ましいが、絶縁層
5を構成する導電性粒子19の割合は有機樹脂に対して
5〜30体積%、特に10〜25体積%であることが望
ましい。導電性粒子19の割合を上記の範囲に限定した
のは、導電性粒子19の含有率が5%よりも低いと、電
気素子17と配線間の導電性粒子19が十分に凝縮され
ず、導通するためのパスが確保できなくなるためであ
る。一方導電性粒子19の含有率が30体積%を超える
と、凝縮部21以外の配線間においても導電性粒子19
のパスが発生し、もしくは信頼性に耐えうる絶縁性が確
保できずに上下配線間において短絡してしまうからであ
る。
On the other hand, in the insulating layer 5 composed of a composite of the conductive particles 19 and the thermosetting resin, the conductive particles 1
9 is preferably made of one selected from Ag, Cu, Ni and Au or an alloy thereof, but the proportion of the conductive particles 19 constituting the insulating layer 5 is 5 to 30% by volume with respect to the organic resin, It is particularly desirable that the content be 10 to 25% by volume. The ratio of the conductive particles 19 is limited to the above range. When the content of the conductive particles 19 is lower than 5%, the conductive particles 19 between the electric element 17 and the wiring are not sufficiently condensed and the conductive This is because it becomes impossible to secure a path for performing the operation. On the other hand, if the content of the conductive particles 19 exceeds 30% by volume, the conductive particles 19
This is because a short circuit occurs between the upper and lower wirings due to the occurrence of the above-mentioned path, or the insulative property that can withstand the reliability cannot be secured.

【0062】尚、絶縁層5の用いる有機樹脂は、硬化温
度を同じにし、また、硬化時の収縮挙動を一致させると
いう理由から、絶縁層1、3に用いる熱硬化性樹脂と同
じ樹脂を用いることが望ましい。
As the organic resin used for the insulating layer 5, the same resin as the thermosetting resin used for the insulating layers 1 and 3 is used because the curing temperature is the same and the shrinkage behavior during curing is matched. It is desirable.

【0063】また、本発明の配線基板Aの配線回路層
8、9、13、15を形成する金属箔として、高い導電
率を有し、且つ微細加工が容易でしかも比較的安価な銅
が好適に用いられる。
As the metal foil for forming the wiring circuit layers 8, 9, 13, and 15 of the wiring board A of the present invention, copper having high conductivity, easy to finely process, and relatively inexpensive is preferable. Used for

【0064】また、絶縁層1、3に形成したビアホール
導体11に形成する導体ペーストとしては、金属成分と
して、銅、銀、アルミニウムおよび金の群から選ばれる
少なくとも1種又は2種以上、特に銅粉末、銀粉末を被
覆した銅粉末、銅−銀合金粉末などの銅含有粉末、ある
いはこの粉末に、Sn粉末や、Sn−Ag−Cu−Bi
などの錫合金粉末を添加したものが使用され、特に、銅
含有粉末に対して、錫含有粉末を添加することによっ
て、製造工程における加熱硬化時に、錫含有粉末が溶融
することから、ビアホール導体11と、配線回路層8、
9、13、15とを容易に接続することができるととも
に、Cu3SnあるいはCu6Sn5からなる耐熱性に優
れた金属間化合物を生成させ、強固に接続することがで
きる。
The conductive paste formed on the via-hole conductors 11 formed on the insulating layers 1 and 3 includes at least one or more selected from the group consisting of copper, silver, aluminum and gold, particularly copper. Powder, a copper powder coated with a silver powder, a copper-containing powder such as a copper-silver alloy powder, or a Sn powder or Sn-Ag-Cu-Bi
The tin-containing powder is added to the via-hole conductor 11 because the tin-containing powder is melted at the time of heat curing in the manufacturing process by adding the tin-containing powder to the copper-containing powder. And the wiring circuit layer 8,
9, 13 and 15 can be easily connected, and an intermetallic compound composed of Cu 3 Sn or Cu 6 Sn 5 having excellent heat resistance can be generated and can be firmly connected.

【0065】(製法)次に、電気素子内蔵配線基板を作
製する方法について図3の工程図をもとに説明する。
(Manufacturing Method) Next, a method of manufacturing a wiring board with a built-in electric element will be described with reference to the process chart of FIG.

【0066】絶縁層1、3となる絶縁シート41、43
は、イミド樹脂、ポリフェニレンエーテル系樹脂、エポ
キシ系樹脂などの熱硬化性樹脂と、SiO2、Al23
などの不定形の無機フィラーとの混合材料から作製され
る(a)。
Insulating sheets 41 and 43 serving as insulating layers 1 and 3
Is a thermosetting resin such as an imide resin, a polyphenylene ether-based resin, or an epoxy-based resin, and SiO 2 , Al 2 O 3
It is made from a mixed material with an amorphous inorganic filler such as (a).

【0067】一方、絶縁層5となる導電性粒子分散絶縁
シート45は、絶縁シート41、43に用いるものと同
様のポリフェニレンエーテル系樹脂、エポキシ系樹脂な
どの熱硬化性樹脂と、Ag、Cu、NiおよびAuなど
の導電性粒子19のうち少なくとも1種の導電性粒子1
9とを混合して形成する。(a)。
On the other hand, the conductive particle-dispersed insulating sheet 45 serving as the insulating layer 5 is made of a thermosetting resin such as a polyphenylene ether resin or an epoxy resin similar to those used for the insulating sheets 41 and 43, Ag, Cu, At least one kind of conductive particles 1 among conductive particles 19 such as Ni and Au;
9 to form a mixture. (A).

【0068】次に、絶縁層1、3となる絶縁シート4
1、43に炭酸ガスレーザやパンチングなどを用いてビ
アホール47を形成する(b)。
Next, the insulating sheet 4 which becomes the insulating layers 1 and 3
Via holes 47 are formed in 1 and 43 by using a carbon dioxide laser or punching (b).

【0069】次に、絶縁シート41、43に形成された
ビアホール47に、Cu粉末を含有する導電性ペースト
を充填して、ビアホール導体49を形成する(c)。
Next, the via holes 47 formed in the insulating sheets 41 and 43 are filled with a conductive paste containing Cu powder to form via-hole conductors 49 (c).

【0070】その後、この絶縁シート41、43および
導電性粒子分散絶縁シート45の表面に、電気素子17
を配置させ、その上面側に配線回路パターン51を形成
して配線回路シート55ならびに導電性粒子を含む導電
部形成配線回路シート57を形成する(d)。
Thereafter, the electric elements 17 are placed on the surfaces of the insulating sheets 41 and 43 and the conductive particle-dispersed insulating sheet 45.
And a wiring circuit pattern 51 is formed on the upper surface thereof to form a wiring circuit sheet 55 and a conductive portion forming wiring circuit sheet 57 containing conductive particles (d).

【0071】これらの配線回路パターン51は、例え
ば、銅箔、Al箔などの金属箔を絶縁シート41、43
の表面に転写した後、レジスト塗布、露光、現像、エッ
チング、レジスト除去の工程によって、所定の配線回路
パターン51を形成する方法、または、予め、可とう性
フィルムの表面に前記絶縁シート41、43の表面に転
写する方法がある。このうち、後者の方法は、絶縁シー
ト41、43がエッチング液などにさらされることがな
く、絶縁シートが劣化することがない点で後者の方が好
適である。
These wiring circuit patterns 51 are made of a metal foil such as a copper foil or an Al foil, for example.
After the transfer to the surface, a method of forming a predetermined wiring circuit pattern 51 by the steps of resist application, exposure, development, etching, and resist removal, or in advance, the insulating sheets 41, 43 on the surface of a flexible film There is a method of transferring to the surface. Among them, the latter method is preferable because the insulating sheets 41 and 43 are not exposed to an etchant or the like and the insulating sheets are not deteriorated.

【0072】次に、上記複数の配線回路シート55と導
電部形成配線回路シート57ならびに電気素子17を用
いて、図3(e)に示すような方法により電気素子17
が内蔵された積層体59を作製する。
Next, using the plurality of wiring circuit sheets 55, the conductive part forming wiring circuit sheet 57 and the electric element 17, the electric element 17 is formed by a method as shown in FIG.
Is manufactured.

【0073】まず、最下層に配線回路シート55を置
き、次に、この配線回路シート55の上面側に導電部形
成配線回路シート57を積層する。そして、この導電部
形成配線回路シート57の上面側に電気素子17を載置
する。この場合、電気素子17の一方主面端部に形成さ
れた端子電極27a、27b、29a、29bが導電部
形成配線回路シート57側に向き、且つ配線回路シート
55の上面に形成された配線回路パターン51における
所定の接続部の直上に当接するように置かれる。
First, the wiring circuit sheet 55 is placed on the lowermost layer, and then the conductive part forming wiring circuit sheet 57 is laminated on the upper surface side of the wiring circuit sheet 55. Then, the electric element 17 is placed on the upper surface side of the conductive portion forming wiring circuit sheet 57. In this case, the terminal electrodes 27 a, 27 b, 29 a, 29 b formed at the end of one main surface of the electric element 17 face the conductive part forming wiring circuit sheet 57 side, and the wiring circuit formed on the upper surface of the wiring circuit sheet 55. It is placed so as to contact directly above a predetermined connection portion in the pattern 51.

【0074】次に、この電気素子17の上面側に、再
び、配線回路シート55を積層し、仮積層体を形成す
る。この場合、Bステージ状態の絶縁シート41、43
および導電性粒子分散シート45を70〜200℃に加
熱しながら電気素子17が絶縁シート表面に埋設できる
程度の圧力を印加する。この電気素子17を埋設するた
めの圧力としては、1kg/cm2以上、特に2〜20
kg/cm2の範囲が望ましい。
Next, the wiring circuit sheet 55 is again laminated on the upper surface side of the electric element 17 to form a temporary laminate. In this case, the insulating sheets 41 and 43 in the B-stage state
While heating the conductive particle-dispersed sheet 45 to 70 to 200 ° C., a pressure is applied so that the electric element 17 can be embedded in the surface of the insulating sheet. The pressure for embedding the electric element 17 is 1 kg / cm 2 or more, especially 2 to 20 kg / cm 2.
The range of kg / cm 2 is desirable.

【0075】このように、仮積層体を前記絶縁シート4
1、43ならびに導電性粒子分散絶縁シート45中の熱
硬化性樹脂が硬化する温度よりも、低い温度で予め予備
的に加熱加圧を行い、電気素子17の端子電極27a、
27b、29a、29bの直下に導電性粒子分散絶縁シ
ート45の内部の導電性粒子19からなる凝縮部21を
形成し、この次に、熱硬化性樹脂が硬化する温度におい
て本硬化を行うことにより、内蔵した電気素子17と絶
縁層1、3に形成された配線回路層8、9、13、15
との間の凝縮部21の密度を高めるとともに、絶縁層
1、3表面との接着を強固にし、硬化過程における配線
基板Aの変形を抑えることができ、このようにして電気
素子内蔵配線基板を作製することができる。
As described above, the provisional laminate is placed on the insulating sheet 4
Preliminary heating and pressurization are performed at a temperature lower than the temperature at which the thermosetting resin in the conductive particle-dispersed insulating sheet 45 is cured.
By forming a condensing portion 21 made of the conductive particles 19 inside the conductive particle-dispersed insulating sheet 45 immediately below 27b, 29a, and 29b, and then performing main curing at a temperature at which the thermosetting resin is cured. , Built-in electric element 17 and wiring circuit layers 8, 9, 13, 15 formed on insulating layers 1, 3
In addition to increasing the density of the condensing portion 21 between the substrate and the insulating layer 1, the adhesion to the surfaces of the insulating layers 1 and 3 is strengthened, and the deformation of the wiring board A during the curing process can be suppressed. Can be made.

【0076】(作用)以上のように構成された電気素子
内蔵配線基板では、複数の絶縁層1、3の間に積層され
た絶縁層5が導電性粒子19を含有し、電気素子17
が、導電性粒子19により構成された凝縮部21を介し
て、配線基板A側のビアホール導体11および/または
配線回路層8、9、13、15と電気的に接続されるこ
とにより、配線基板Aの配線回路層8、9、13、15
やビアホール導体11と、電気素子17の端子電極27
a、27b、29a、29bとを、半田や導電性接着剤
等の接合剤を用いることなしに接続できることから、加
熱加圧時に接合剤の変形や広がりが抑制され、電気素子
17と、配線基板A内部の配線回路層8、9、13、1
5やビアホール導体11との接続性を高めることができ
る。
(Operation) In the wiring board with a built-in electric element configured as described above, the insulating layer 5 laminated between the plurality of insulating layers 1 and 3 contains the conductive particles 19 and the electric element 17
Is electrically connected to the via-hole conductor 11 on the wiring board A side and / or the wiring circuit layers 8, 9, 13, and 15 via the condensing portion 21 formed of the conductive particles 19, thereby forming the wiring board. A wiring circuit layers 8, 9, 13, 15
And via-hole conductor 11 and terminal electrode 27 of electric element 17
a, 27b, 29a, and 29b can be connected without using a bonding agent such as solder or a conductive adhesive, so that deformation and spreading of the bonding agent during heating and pressing can be suppressed, and the electric element 17 and the wiring board can be connected. A, wiring circuit layers 8, 9, 13, 1
5 and the via-hole conductor 11 can be improved in connectivity.

【0077】また、端子電極27a、27b、29a、
29bの位置に確実に導電性粒子19を含む凝縮部21
を形成できることから、配線基板A内部の配線回路層
8、9、13、15やビアホール導体11と、電気素子
17の端子電極27a、27b、29a、29bとの位
置のずれを無くして接続でき、配線基板Aの電気抵抗の
増加を抑制し、インピーダンス整合を高めることができ
る。
The terminal electrodes 27a, 27b, 29a,
Condensing section 21 containing conductive particles 19 surely at position 29b
Can be formed, and the wiring circuit layers 8, 9, 13, 15 and the via-hole conductor 11 inside the wiring board A and the terminal electrodes 27a, 27b, 29a, 29b of the electric element 17 can be connected without displacement. An increase in the electric resistance of the wiring board A can be suppressed, and the impedance matching can be improved.

【0078】さらには、ビアホール加工の工程を削減で
きることから、製造コストを低減できる。
Further, since the number of via hole processing steps can be reduced, the manufacturing cost can be reduced.

【0079】[0079]

【実施例】先ず、内蔵する電気素子として、例えば、セ
ラミックコンデンサを次のように作製した。BaTiO
3系の複数のセラミック誘電体シートの表面に、Niの
金属ペーストを用いて内部電極パターンをスクリーン印
刷した。その後、それらのシートを温度55℃、圧力1
500Pa下で積層密着させ、グリーンの状態でカッタ
ーを用いて切断した後、還元雰囲気1250℃の温度に
おいて焼成して積層コンデンサを作製した。なお、コン
デンサの端面から内部電極が露出していることを確認し
た。
EXAMPLE First, as a built-in electric element, for example, a ceramic capacitor was manufactured as follows. BaTiO
An internal electrode pattern was screen-printed on the surface of a plurality of ceramic dielectric sheets of the 3 series using a Ni metal paste. Thereafter, the sheets were heated at a temperature of 55 ° C. and a pressure of 1
The laminate was brought into close contact with each other at 500 Pa, cut in a green state using a cutter, and then fired at a temperature of 1250 ° C. in a reducing atmosphere to produce a multilayer capacitor. In addition, it was confirmed that the internal electrode was exposed from the end face of the capacitor.

【0080】また、一部のコンデンサ素体の内部電極が
露出した端面に、Cu/Niのペーストを外部電極形成
部に塗布して温度850℃で焼付け、コンデンサの端面
に、表1に示す条件の突起状の端子電極を形成した。な
お、この積層コンデンサは、その寸法が1.6mm×
1.6mm×0.2mm、静電容量が10nF、自己イ
ンダクタンスが80pHのものとした。即ち、内蔵する
積層コンデンサの本体厚みは0.2mmおよび端子電極
間隔は50μm、150μmとした。
Further, a Cu / Ni paste was applied to the end faces of the capacitor elements where the internal electrodes were exposed, and baked at a temperature of 850 ° C. to the end faces of the capacitors. Are formed. The size of this multilayer capacitor is 1.6 mm ×
The size was 1.6 mm × 0.2 mm, the capacitance was 10 nF, and the self inductance was 80 pH. That is, the thickness of the built-in multilayer capacitor was 0.2 mm, and the terminal electrode spacing was 50 μm and 150 μm.

【0081】次に、上記の積層コンデンサを内蔵した配
線基板を以下のようにして作製した。
Next, a wiring board incorporating the above-mentioned multilayer capacitor was manufactured as follows.

【0082】先ず、A−PPE樹脂に対し、不定形のS
iO2粉末を所定量の割合となるように、ワニス状態の
樹脂とを混合し、ドクターブレード法により、厚さ12
0μmの複数の絶縁シートを作製した。
First, an amorphous S-PPE resin was
The iO 2 powder was mixed with a resin in a varnish state so as to have a predetermined ratio, and the thickness was adjusted to 12 mm by a doctor blade method.
A plurality of 0 μm insulating sheets were produced.

【0083】次に、A−PPE樹脂とCu粉末からなる
導電性粒子を混合して、無機フィラーを含む絶縁シート
と同じ成形方法により、厚み500μmの導電性粒子を
含む絶縁シートを作製した。絶縁層中の導電性粒子の割
合は5〜35体積%とした。また、ここで用いた導電性
粒子の平均粒径は5〜10μmのものを用いた。
Next, an A-PPE resin and conductive particles made of Cu powder were mixed, and an insulating sheet containing conductive particles having a thickness of 500 μm was produced by the same molding method as that for the insulating sheet containing an inorganic filler. The ratio of the conductive particles in the insulating layer was 5 to 35% by volume. The average particle size of the conductive particles used here was 5 to 10 μm.

【0084】次に、これらの絶縁シートに、炭酸ガスレ
ーザにより、ビアホール(直径0.1mm)を形成し、
そのビアホールに、Cu粉末を含有する導電性ペースト
を充填してビアホール導体を形成した。
Next, via holes (0.1 mm in diameter) were formed in these insulating sheets by a carbon dioxide gas laser.
The via hole was filled with a conductive paste containing Cu powder to form a via hole conductor.

【0085】次に、ポリエチレンテレフタレート(PE
T)樹脂からなる転写シートの表面に接着剤を塗布し、
厚さ12μm、表面粗さ0.8μmの銅箔を一面に接着
した。そして、ドライフィルムレジストを貼り、露光、
現像を行った後、これを塩化第二鉄溶液を用いたスプレ
ー式エッチング装置を用いて、非パターン部をエッチン
グ除去して、銅箔からなる配線回路パターンを形成した
転写シートを作製した。
Next, polyethylene terephthalate (PE)
T) applying an adhesive to the surface of the transfer sheet made of resin,
A copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was bonded to one surface. Then, apply a dry film resist, expose,
After the development, the non-pattern portion was removed by etching using a spray-type etching apparatus using a ferric chloride solution to prepare a transfer sheet on which a wiring circuit pattern made of copper foil was formed.

【0086】その後、この転写シートの配線回路パター
ン側を130℃、20kg/cm2の条件で圧着して絶
縁シートの表面に配線回路パターンが形成された配線回
路シートを作製した。
Thereafter, the wiring circuit pattern side of this transfer sheet was pressure-bonded at 130 ° C. and 20 kg / cm 2 to produce a wiring circuit sheet having a wiring circuit pattern formed on the surface of an insulating sheet.

【0087】次に、上記複数の配線回路シートおよび電
気素子を用いて、電気素子が1個内蔵された積層体を作
製した。
Next, by using the plurality of wiring circuit sheets and the electric elements, a laminated body containing one electric element was manufactured.

【0088】まず、最下層に無機フィラーを含む配線回
路シートを置き、次に、この無機フィラーを含む配線回
路シートの上面側に導電性粒子を含む導電部形成配線回
路シートを積層した。
First, a wiring circuit sheet containing an inorganic filler was placed on the lowermost layer, and then a conductive part forming wiring circuit sheet containing conductive particles was laminated on the upper surface side of the wiring circuit sheet containing the inorganic filler.

【0089】次に、この導電性粒子を含む導電部形成配
線回路シートの上面側に電気素子17を載置した。この
場合、電気素子の一方主面端部に形成された端子電極が
導電性粒子を含む導電部形成配線回路シート側に向き、
且つ配線回路シートの上面に形成された配線回路パター
ンにおける所定の接続部の直上に当接するように置い
た。
Next, the electric element 17 was mounted on the upper surface side of the conductive part forming wiring circuit sheet containing the conductive particles. In this case, the terminal electrodes formed at the ends of the one main surface of the electric element face the conductive portion forming wiring circuit sheet containing the conductive particles,
In addition, the printed circuit board is placed so as to be in contact with immediately above a predetermined connection portion in the printed circuit pattern formed on the upper surface of the printed circuit sheet.

【0090】次に、導電性粒子を含む導電部形成配線回
路シートの上面側に置かれたこの電気素子の上面側に、
再び、無機フィラーを含む配線回路シートを積層し、仮
積層体を形成した。
Next, on the upper surface side of this electric element placed on the upper surface side of the conductive portion forming wiring circuit sheet containing the conductive particles,
Again, the wiring circuit sheets containing the inorganic filler were laminated to form a temporary laminate.

【0091】そして、この仮積層体を温度130℃、圧
力20kg/cm2の条件で加熱加圧を行い、電気素子
17を導電性粒子を含む導電部形成配線回路シートの表
面に埋設し、次に、温度200℃、圧力20kg/cm
2の条件で本硬化を行い電気素子内蔵配線基板を作製し
た。このとき導電性粒子19による凝縮部21が形成さ
れた絶縁層5の厚みは、硬化後に400μmに変化して
いた。
Then, the temporary laminate is heated and pressurized at a temperature of 130 ° C. and a pressure of 20 kg / cm 2 to embed the electric element 17 on the surface of the conductive portion forming wiring circuit sheet containing the conductive particles. At a temperature of 200 ° C and a pressure of 20 kg / cm
The main curing was performed under the conditions of 2 to prepare a wiring board with a built-in electric element. At this time, the thickness of the insulating layer 5 in which the condensed portion 21 formed by the conductive particles 19 was changed to 400 μm after curing.

【0092】比較例として、絶縁基板を構成する絶縁層
の全層を熱硬化性樹脂と無機フィラーとを混合して作製
した絶縁シートを用い、この絶縁シートのビアホール導
体および配線回路層を形成し、電気素子を導電性接着剤
を用いて接続した試料を作製した。そして、作製した電
気素子内蔵配線基板に対して、以下の検討を行った。
As a comparative example, an insulating sheet prepared by mixing a thermosetting resin and an inorganic filler for all of the insulating layers constituting the insulating substrate was used, and via-hole conductors and wiring circuit layers of the insulating sheet were formed. Then, a sample in which the electric elements were connected using a conductive adhesive was prepared. The following study was performed on the manufactured wiring board with built-in electric elements.

【0093】インピーダンスアナライザを用いて、周波
数1.0MHz〜1.8GHzにおいて、インピーダン
スの周波数特性を測定し、同時に、1MHzでのコンデ
ンサの静電容量を測定し、そして、f0=1/(2π
(L/C)1/2)(式中、f0:共振周波数(Hz)、
C:静電容量(F)、L:インダクタンス(H))に基
づいて、共振周波数からインダクタンスを計算で求めた
(L(室温))。また、作製した電気素子内蔵配線基板
を−45〜125℃の間の温度サイクルテストを100
回行い、試験後の配線基板のインダクタンスおよび絶縁
抵抗の変化率を評価した。絶縁抵抗は絶縁抵抗計を用い
て、印加電圧10V、印加時間1分後の値を測定した。
これらの結果を表1に記載した。試料数は各評価項目に
おいて、n=10とした。
Using an impedance analyzer, the frequency characteristic of the impedance is measured at a frequency of 1.0 MHz to 1.8 GHz, the capacitance of the capacitor at 1 MHz is measured at the same time, and f 0 = 1 / (2π
(L / C) 1/2 , where f 0 is the resonance frequency (Hz),
Based on C: capacitance (F) and L: inductance (H), the inductance was calculated from the resonance frequency (L (room temperature)). A temperature cycle test between −45 ° C. and 125 ° C.
The test was repeated to evaluate the rate of change in inductance and insulation resistance of the wiring board after the test. The insulation resistance was measured using an insulation resistance meter at an applied voltage of 10 V and a value of 1 minute after the application time.
Table 1 shows the results. The number of samples was n = 10 in each evaluation item.

【0094】[0094]

【表1】 [Table 1]

【0095】表1の結果から明らかなように、絶縁層中
に導電性粒子から構成される凝縮部を形成した試料N
o.3〜18では、静電容量が10nF以上、共振周波
数が77MHz以上、およびこれらに値から求めたイン
ダクタンスが140pH以下の値を示し、さらに、TC
T試験においても、一部の試料にTCT試験後に膨れが
見られたものの、インダクタンスの変化率がいずれも1
0%以下であった。
As is clear from the results shown in Table 1, the sample N in which a condensed portion composed of conductive particles was formed in the insulating layer was obtained.
o. 3 to 18, the capacitance is 10 nF or more, the resonance frequency is 77 MHz or more, and the inductance obtained from these values is 140 pH or less.
In the T test, swelling was observed in some of the samples after the TCT test.
0% or less.

【0096】また、導電性粒子の含有量を10〜25体
積%とした、試料No.3、5〜18では、TCT試験
後のインダクタンスの変化率が10%以下となり良好な
特性を示した。
[0096] Sample No. 1 was prepared in which the content of the conductive particles was 10 to 25% by volume. In Nos. 3, 5 to 18, the change rate of the inductance after the TCT test was 10% or less, indicating good characteristics.

【0097】特に、導電性粒子の含有量を20〜30体
積%、電気素子の厚みと絶縁層の厚みの比を60〜80
%とした試料No.7〜9、11、12、および17で
は、静電容量が10nF以上、インダクタンスが110
pH以下、TCT試験でのインダクタンスの変化率が6
%以下、また、TCT試験での絶縁抵抗の変化率が5%
以下と小さくなり、配線基板内に内蔵された電気素子と
配線回路層との接続が良好であることが判った。
In particular, the content of the conductive particles is 20 to 30% by volume, and the ratio of the thickness of the electric element to the thickness of the insulating layer is 60 to 80%.
% Sample No. In 7 to 9, 11, 12, and 17, the capacitance is 10 nF or more and the inductance is 110
Below pH, the rate of change of inductance in the TCT test is 6
% And the rate of change in insulation resistance in the TCT test is 5%
It was found that the connection between the electric element built in the wiring board and the wiring circuit layer was good.

【0098】一方、電気素子を導電性接着剤を用いて接
合した試料のうち、電気素子の間隔を150μmとした
試料No.2では、静電容量が得られたが、TCT試験
後の絶縁抵抗の増加が大きかった。そして、端子電極の
間隔を50μmとしたものは、試料作製後にショートが
発生した。
On the other hand, among the samples in which the electric elements were joined by using a conductive adhesive, the sample No. in which the interval between the electric elements was 150 μm. In No. 2, the capacitance was obtained, but the increase in insulation resistance after the TCT test was large. When the interval between the terminal electrodes was 50 μm, a short circuit occurred after the sample was produced.

【0099】[0099]

【発明の効果】以上詳述したように、本発明の電気素子
内蔵配線基板では、電気素子が、導電性粒子により形成
された凝縮部を介して、配線基板側のビアホール導体お
よび/または配線回路層と電気的に接続されることによ
り、半田や導電性接着剤等の接合剤を用いることなしに
接続できることから、加熱加圧時に接合剤の変形や広が
りが抑制され、電気素子と、配線基板内部の配線回路層
やビアホール導体との接続性を高めることができる。
As described above in detail, in the wiring board with a built-in electric element according to the present invention, the electric element is connected to the via-hole conductor and / or the wiring circuit on the wiring board via the condensing portion formed by the conductive particles. By being electrically connected to the layers, the connection can be performed without using a bonding agent such as solder or a conductive adhesive. The connectivity with the internal wiring circuit layer and via-hole conductor can be improved.

【0100】また、電気素子を接続する絶縁層には、ビ
アホール加工が不要であることから、製造コストを低減
することができる。
Further, the insulating layer for connecting the electric elements does not require via hole processing, so that the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電気素子内蔵配線基板の概略断面図で
ある。
FIG. 1 is a schematic sectional view of a wiring board with a built-in electric element of the present invention.

【図2】内蔵される電気素子の斜視図である。FIG. 2 is a perspective view of a built-in electric element.

【図3】図1の本発明の電気素子内蔵配線基板の製法の
一例を説明するための工程図である。
FIG. 3 is a process chart for explaining an example of a method for manufacturing the wiring board with a built-in electric element of the present invention in FIG. 1;

【符号の説明】[Explanation of symbols]

A・・・・・・・・・・・・・・・・配線基板 1、3、5・・・・・・・・・・・・絶縁層 7・・・・・・・・・・・・・・・・絶縁基板 8、9、13、15・・・・・・・・配線回路層 11、49・・・・・・・・・・・・ビアホール導体 17・・・・・・・・・・・・・・・電気素子 19・・・・・・・・・・・・・・・導電性粒子 21・・・・・・・・・・・・・・・凝縮部 23・・・・・・・・・・・・・・・凝縮ビア 27a、27b、29a、29b・・端子電極 41、43・・・・・・・・・・・・絶縁シート 45・・・・・・・・・・・・・・・導電性粒子分散絶
縁シート 47・・・・・・・・・・・・・・・ビアホール 49・・・・・・・・・・・・・・・ビアホール導体 51・・・・・・・・・・・・・・・配線回路パターン 55・・・・・・・・・・・・・・・配線回路シート 57・・・・・・・・・・・・・・・導電部形成配線回
路シート 59・・・・・・・・・・・・・・・積層体
A ········ Wiring board 1, 3, 5 ··· Insulating layer 7 ..... Insulating substrate 8, 9, 13, 15 ..... Wiring circuit layer 11, 49 ..... Via-hole conductor 17 ... ·············································································································································· 23 ..... Condensed vias 27a, 27b, 29a, 29b .. Terminal electrodes 41, 43 .. Insulating sheet 45 ..・ ・ ・ ・ ・ ・ ・ ・ ・ Conductive particle dispersed insulating sheet 47 ・ ・ ・ ・ ・ ・ ・ Via hole 49 ・ ・ ・ ・ ・ ・ ・ Via hole conductor 51 ... Circuit pattern 55 Wiring circuit sheet 57 Conductive part forming wiring circuit sheet 59・ ・ ・ ・ ・ ・ ・ ・ ・ Laminate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H05K 3/46 T 1/11 N // H05K 1/11 3/32 B 3/32 H01L 23/12 B N Fターム(参考) 5E317 AA24 BB02 BB03 BB12 BB22 CC25 CD27 GG03 5E319 AA01 AA03 BB11 CC61 CD26 GG15 5E346 AA04 AA12 AA15 AA22 AA32 AA35 AA43 AA51 BB11 BB16 BB20 CC08 CC16 CC32 CC37 CC38 CC39 DD02 DD12 DD32 EE06 EE07 EE13 EE15 EE18 FF01 FF18 FF50 GG15 GG19 GG22 GG28 HH07 HH11 HH31──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 T 1/11 N // H05K 1/11 3/32 B 3/32 H01L 23/12 BNF term (reference) 5E317 AA24 BB02 BB03 BB12 BB22 CC25 CD27 GG03 5E319 AA01 AA03 BB11 CC61 CD26 GG15 5E346 AA04 AA12 AA15 AA22 AA32 AA35 AA43 AA51 BB11 BB16 CC32 CC08 EE15 EE18 FF01 FF18 FF50 GG15 GG19 GG22 GG28 HH07 HH11 HH31

Claims (20)

【特許請求の範囲】[Claims] 【請求項1】少なくとも有機樹脂を含有する絶縁層を積
層してなる絶縁基板と、該絶縁基板の表面および/また
は内部に形成された複数層の配線回路層と、少なくとも
前記絶縁基板内部に金属成分を充填してなるビアホール
導体とを具備する配線基板の内部に端子電極を有する電
気素子を内蔵してなる電気素子内蔵配線基板において、
前記複数の絶縁層のうち、少なくとも1層の前記絶縁層
が導電性粒子を含有し、前記電気素子の端子電極が前記
導電性粒子による凝縮部を介して前記配線基板側のビア
ホール導体および/または配線回路層と電気的に接続し
てなることを特徴とする電気素子内蔵配線基板。
An insulating substrate formed by laminating an insulating layer containing at least an organic resin, a plurality of wiring circuit layers formed on the surface and / or inside of the insulating substrate, and at least metal inside the insulating substrate. In a wiring board with a built-in electric element having a built-in electric element having a terminal electrode inside a wiring board having a via-hole conductor filled with a component,
Among the plurality of insulating layers, at least one of the insulating layers contains conductive particles, and a terminal electrode of the electric element has a via-hole conductor on the wiring board side and / or via a condensing portion of the conductive particles. An electric element built-in wiring board, which is electrically connected to a wiring circuit layer.
【請求項2】絶縁層中の導電性粒子の割合が5〜30体
積%であることを特徴とする請求項1記載の電気素子内
蔵配線基板。
2. The wiring board with a built-in electric element according to claim 1, wherein the proportion of the conductive particles in the insulating layer is 5 to 30% by volume.
【請求項3】導電性粒子が、Ag、Cu、NiおよびA
uから選ばれる1種あるいはこれらの合金からなること
を特徴とする請求項1または請求項2に記載の電気素子
内蔵配線基板。
3. The conductive particles are made of Ag, Cu, Ni and A.
3. The wiring board with a built-in electric element according to claim 1, wherein the wiring board is made of one selected from u or an alloy thereof. 4.
【請求項4】導電性粒子が略球状粒子であることを特徴
とする請求項1乃至請求項3のうちいずれか記載の電気
素子内蔵配線基板。
4. The wiring board with a built-in electric element according to claim 1, wherein the conductive particles are substantially spherical particles.
【請求項5】導電性粒子の平均粒径が10μm以下であ
ることを特徴とする請求項1乃至請求項4のうちいずれ
か記載の電気素子内蔵配線基板。
5. The wiring board with a built-in electric element according to claim 1, wherein the average particle size of the conductive particles is 10 μm or less.
【請求項6】電気素子が該電気素子の少なくとも主面側
に突起状の端子電極を具備することを特徴とする請求項
1乃至請求項5のうちいずれか記載の電気素子内蔵配線
基板。
6. The wiring board with a built-in electric element according to claim 1, wherein the electric element has a protruding terminal electrode on at least the main surface side of the electric element.
【請求項7】電気素子の厚みが絶縁層厚みの50〜95
%であることを特徴とする請求項6記載の電気素子内蔵
配線基板。
7. The thickness of the electric element is 50 to 95 times the thickness of the insulating layer.
%. The wiring board with a built-in electric element according to claim 6.
【請求項8】突起状の端子電極の高さが、絶縁層厚みの
20〜65%であることを特徴とする請求項6または7
に記載の電気素子内蔵配線基板。
8. The height of the protruding terminal electrode is 20 to 65% of the thickness of the insulating layer.
3. The wiring board with a built-in electric element according to claim 1.
【請求項9】電気素子において、最近接する端子電極間
距離が400μm以下であることを特徴とする請求項6
乃至請求項8のうちいずれか記載の電気素子内蔵配線基
板。
9. The electric element according to claim 6, wherein the distance between the nearest terminal electrodes is 400 μm or less.
9. The wiring board with a built-in electric element according to claim 8.
【請求項10】電気素子が内部電極層と誘電体層とを交
互に積層して形成された積層コンデンサであることを特
徴とする請求項6乃至請求項9のうちいずれか記載の電
気素子内蔵配線基板。
10. A built-in electric element according to claim 6, wherein the electric element is a multilayer capacitor formed by alternately laminating internal electrode layers and dielectric layers. Wiring board.
【請求項11】(a)電気素子の少なくとも一方主面に
突起状の端子電極を形成する工程と、(b)未硬化また
は半硬化の熱硬化性樹脂および無機フィラーを含有する
絶縁シートを形成する工程と、(c)未硬化または半硬
化の熱硬化性樹脂および導電性粒子を含有する導電性粒
子分散絶縁シートを形成する工程と、(d)(b)工程
において得られた絶縁シートの所定箇所にビアホール導
体を形成する工程と、(e)表面に金属箔からなる配線
回路パターンが形成された転写シートを形成する工程
と、(f)(d)工程によって得られた絶縁シートの表
面に、(e)工程で形成した転写シートから、配線回路
パターンを転写してなる配線回路シートを形成する工程
と、(g)(c)工程によって得られた導電性粒子分散
絶縁シートの表面に、(e)で形成した他の転写シート
から、配線回路パターンを転写してなる導電部形成配線
回路シートを形成する工程と、(h)(f)工程によっ
て得られた前記複数の配線回路シートの層間に、(g)
工程によって得られた前記導電部形成配線回路シートを
少なくとも1層積層するとともに、前記配線回路シート
と前記導電部形成配線回路シートとの層間の所定位置に
電気素子を載置した仮積層体を作製する工程と、(i)
前記仮積層体を加熱加圧して、前記絶縁シートおよび導
電性粒子分散絶縁シート中に含まれる前記熱硬化性樹脂
を硬化するとともに、前記電気素子に形成された端子電
極の延長方向に導電性粒子を含む凝縮部を形成する工程
と、を具備することを特徴とする電気素子内蔵配線基板
の製法。
11. A step of (a) forming a protruding terminal electrode on at least one main surface of an electric element, and (b) forming an insulating sheet containing an uncured or semi-cured thermosetting resin and an inorganic filler. (C) forming a conductive particle-dispersed insulating sheet containing an uncured or semi-cured thermosetting resin and conductive particles; and (d) forming the insulating sheet obtained in the step (b). A step of forming a via-hole conductor at a predetermined location, (e) a step of forming a transfer sheet having a wiring circuit pattern made of a metal foil formed on the surface thereof, and (f) a surface of the insulating sheet obtained by the step (d). (E) forming a wiring circuit sheet by transferring a wiring circuit pattern from the transfer sheet formed in the step (e); and (g) forming a conductive particle-dispersed insulating sheet on the surface of the conductive particle-dispersed insulating sheet obtained in the step (c). (E) forming a conductive portion forming wiring circuit sheet by transferring a wiring circuit pattern from another transfer sheet formed in (e); and (h) forming a plurality of wiring circuit sheets obtained by the steps (f) and (f). (G)
Producing a temporary laminate in which at least one layer of the conductive part forming wiring circuit sheet obtained in the step is laminated, and an electric element is placed at a predetermined position between the wiring circuit sheet and the conductive part forming wiring circuit sheet. (I)
The temporary laminate is heated and pressed to cure the thermosetting resin contained in the insulating sheet and the conductive particle-dispersed insulating sheet, and the conductive particles extend in a direction in which a terminal electrode formed on the electric element extends. Forming a condensing section containing: a method for producing a wiring board with a built-in electric element.
【請求項12】(c)工程において、絶縁層中の導電性
粒子の割合が5〜30体積%であることを特徴とする請
求項11記載の電気素子内蔵配線基板の製法。
12. The method according to claim 11, wherein in the step (c), the proportion of the conductive particles in the insulating layer is 5 to 30% by volume.
【請求項13】(c)工程において、導電性粒子が、A
g、Cu、NiおよびAuから選ばれる1種あるいはこ
れらの合金からなることを特徴とする請求項11または
請求項12に記載の電気素子内蔵配線基板の製法。
13. The method according to claim 13, wherein in the step (c), the conductive particles
13. The method for manufacturing a wiring board with a built-in electric element according to claim 11, wherein the wiring board is made of one kind selected from g, Cu, Ni, and Au or an alloy thereof.
【請求項14】(c)工程において、導電性粒子が略球
状粒子であることを特徴とする請求項11乃至請求項1
3のうちいずれか記載の電気素子内蔵配線基板の製法。
14. The method according to claim 11, wherein in the step (c), the conductive particles are substantially spherical particles.
3. The method for producing a wiring board with a built-in electric element according to any one of the above items 3.
【請求項15】(c)工程において、導電性粒子の平均
粒径が10μm以下であることを特徴とする請求項11
乃至請求項14のうちいずれか記載の電気素子内蔵配線
基板の製法。
15. The method according to claim 11, wherein in the step (c), the conductive particles have an average particle diameter of 10 μm or less.
A method for producing the wiring board with a built-in electric element according to any one of claims 14 to 14.
【請求項16】電気素子が該電気素子の少なくとも主面
側に突起状の端子電極を具備することを特徴とする請求
項11乃至請求項15のうちいずれか記載の電気素子内
蔵配線基板の製法。
16. The method for producing a wiring board with a built-in electric element according to claim 11, wherein the electric element has a protruding terminal electrode on at least the main surface side of the electric element. .
【請求項17】電気素子の厚みが絶縁層厚みの50〜9
5%であることを特徴とする請求項11乃至請求項16
のうちいずれか記載の電気素子内蔵配線基板の製法。
17. The thickness of the electric element is 50 to 9 times the thickness of the insulating layer.
17. The method according to claim 11, wherein the value is 5%.
The method for producing a wiring board with a built-in electric element according to any one of the above.
【請求項18】電気素子における突起状の端子電極の高
さが、絶縁層厚みの20〜65%であることを特徴とす
る請求項16記載の電気素子内蔵配線基板の製法。
18. The method according to claim 16, wherein the height of the protruding terminal electrodes of the electric element is 20 to 65% of the thickness of the insulating layer.
【請求項19】電気素子が複数の端子電極を有し、該端
子電極の最近接する端子電極間距離が400μm以下で
あることを特徴とする請求項11乃至請求項18のうち
いずれか記載の電気素子内蔵配線基板の製法。
19. The electric device according to claim 11, wherein the electric element has a plurality of terminal electrodes, and a distance between the terminal electrodes closest to the terminal electrodes is 400 μm or less. Manufacturing method of wiring board with built-in element.
【請求項20】電気素子が内部電極層と誘電体層とを交
互に積層して形成された積層コンデンサであることを特
徴とする請求項11乃至請求項19のうちいずれか記載
の電気素子内蔵配線基板の製法。
20. A built-in electric element according to claim 11, wherein the electric element is a multilayer capacitor formed by alternately stacking internal electrode layers and dielectric layers. Manufacturing method of wiring board.
JP2001164635A 2001-05-31 2001-05-31 Wiring board with built-in electric element and manufacturing method thereof Expired - Fee Related JP4683770B2 (en)

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253225A (en) * 2005-03-08 2006-09-21 Denso Corp Circuit substrate, method of manufacturing the same, and electronic circuit apparatus
JP2007266129A (en) * 2006-03-27 2007-10-11 Fujitsu Ltd Semiconductor device, and method of manufacturing semiconductor device
JP2010097601A (en) * 2008-09-18 2010-04-30 Semiconductor Energy Lab Co Ltd Semiconductor device
KR100980296B1 (en) 2008-06-30 2010-09-06 주식회사 하이닉스반도체 Circuit substrate having circuit wire, method of manufacturing the circuit substrate, and semiconductor package having the circuit wire
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US8008754B2 (en) 2008-12-10 2011-08-30 Hynix Semiconductor Inc. Semiconductor package having an antenna with reduced area and method for fabricating the same
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177864A (en) * 1990-11-13 1992-06-25 Nec Corp Manufacture of multilayer interconnection substrate
JPH0794868A (en) * 1993-09-24 1995-04-07 Shinko Electric Ind Co Ltd Multilayered wiring board and its manufacture
JPH1126631A (en) * 1997-07-02 1999-01-29 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH11219980A (en) * 1998-02-02 1999-08-10 Hitachi Chem Co Ltd Electronic part device
JPH11340631A (en) * 1998-05-26 1999-12-10 Yamaichi Electronics Co Ltd Ivh multilayer wiring substrate and manufacture thereof
JP2000243873A (en) * 1999-02-22 2000-09-08 Ngk Spark Plug Co Ltd Wiring board, core substrate with built-in capacitor, main body of core substrate, capacitor and their manufacture
JP2001007472A (en) * 1999-06-17 2001-01-12 Sony Corp Electronic circuit device and its manufacture
JP2001044641A (en) * 1999-07-30 2001-02-16 Kyocera Corp Wiring board incorporating semiconductor element and its manufacture
JP2001085804A (en) * 1999-09-17 2001-03-30 Sony Corp Printed wiring board and manufacturing method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177864A (en) * 1990-11-13 1992-06-25 Nec Corp Manufacture of multilayer interconnection substrate
JPH0794868A (en) * 1993-09-24 1995-04-07 Shinko Electric Ind Co Ltd Multilayered wiring board and its manufacture
JPH1126631A (en) * 1997-07-02 1999-01-29 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JPH11219980A (en) * 1998-02-02 1999-08-10 Hitachi Chem Co Ltd Electronic part device
JPH11340631A (en) * 1998-05-26 1999-12-10 Yamaichi Electronics Co Ltd Ivh multilayer wiring substrate and manufacture thereof
JP2000243873A (en) * 1999-02-22 2000-09-08 Ngk Spark Plug Co Ltd Wiring board, core substrate with built-in capacitor, main body of core substrate, capacitor and their manufacture
JP2001007472A (en) * 1999-06-17 2001-01-12 Sony Corp Electronic circuit device and its manufacture
JP2001044641A (en) * 1999-07-30 2001-02-16 Kyocera Corp Wiring board incorporating semiconductor element and its manufacture
JP2001085804A (en) * 1999-09-17 2001-03-30 Sony Corp Printed wiring board and manufacturing method thereof

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253225A (en) * 2005-03-08 2006-09-21 Denso Corp Circuit substrate, method of manufacturing the same, and electronic circuit apparatus
JP2007266129A (en) * 2006-03-27 2007-10-11 Fujitsu Ltd Semiconductor device, and method of manufacturing semiconductor device
US8168471B2 (en) 2006-03-27 2012-05-01 Fujitsu Limited Semiconductor device and manufacturing method of a semiconductor device
US8802998B2 (en) 2007-09-10 2014-08-12 Murata Manufacturing Co., Ltd. Ceramic multilayer substrate and method for producing the same
KR100980296B1 (en) 2008-06-30 2010-09-06 주식회사 하이닉스반도체 Circuit substrate having circuit wire, method of manufacturing the circuit substrate, and semiconductor package having the circuit wire
US11127732B2 (en) 2008-09-18 2021-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9177978B2 (en) 2008-09-18 2015-11-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10020296B2 (en) 2008-09-18 2018-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2010097601A (en) * 2008-09-18 2010-04-30 Semiconductor Energy Lab Co Ltd Semiconductor device
KR101053544B1 (en) 2008-12-10 2011-08-03 주식회사 하이닉스반도체 Semiconductor package and manufacturing method thereof
US8008754B2 (en) 2008-12-10 2011-08-30 Hynix Semiconductor Inc. Semiconductor package having an antenna with reduced area and method for fabricating the same
US8383463B2 (en) 2008-12-10 2013-02-26 Hynix Semiconductor Inc. Semiconductor package having an antenna with reduced area and method for fabricating the same
WO2010129002A1 (en) * 2009-05-04 2010-11-11 R&D Circuits Inc. Method and apparatus for improving power and loss for interconect configurations
JP2011044583A (en) * 2009-08-21 2011-03-03 Dainippon Printing Co Ltd Wiring board with built-in component
JP2011082203A (en) * 2009-10-02 2011-04-21 Nec Corp Insulating layer with conductive region, electronic component, and method of manufacturing the insulating layer and the electronic component
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US8952507B2 (en) 2012-08-10 2015-02-10 Ibiden Co., Ltd. Wiring board and method for manufacturing wiring board
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