JP2002359246A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2002359246A5 JP2002359246A5 JP2002089262A JP2002089262A JP2002359246A5 JP 2002359246 A5 JP2002359246 A5 JP 2002359246A5 JP 2002089262 A JP2002089262 A JP 2002089262A JP 2002089262 A JP2002089262 A JP 2002089262A JP 2002359246 A5 JP2002359246 A5 JP 2002359246A5
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- width
- wiring
- manufacturing
- resist mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (15)
前記第2の導電層は前記第1の導電層及び前記第3の導電層より低抵抗であり、
前記第1の導電層、前記第2の導電層、前記第3の導電層のうち少なくとも前記第2の導電層の端部における断面形状は、テーパー形状であることを特徴とする配線。 A first conductive layer having a first width, the second conductive layer first have a second width narrower than the width as a main component Al, narrow third than the second width A laminated structure with a third conductive layer having a width;
The second conductive layer has a lower resistance than the first conductive layer and the third conductive layer;
The wiring characterized in that a cross-sectional shape of at least an end portion of the second conductive layer among the first conductive layer , the second conductive layer , and the third conductive layer is a tapered shape.
前記第3の導電層上に所定の形状のレジストマスクを形成し、前記第1の導電層、前記第2の導電層および前記第3の導電層をエッチングした後、
前記レジストマスクを除去せずに、前記第2の導電層と前記第3の導電層とをエッチングして、第1の幅を有する第1の導電層と、前記第1の幅より狭い第2の幅を有する第2の導電層と、前記第2の幅より狭い第3の幅を有する第3の導電層との積層からなる導電層を形成する配線の作製方法であって、
前記第1の幅を有する第1の導電層、前記第2の幅を有する第2の導電層、前記第3の幅を有する第3の導電層のうち少なくとも前記第2の導電層の端部における断面形状がテーパー形状になるようにエッチングされることを特徴とする配線の作製方法。On the insulating surface, a first conductive layer, a second conductive layer containing Al as a main component, and a third conductive layer are stacked and formed.
A resist mask having a predetermined shape is formed on the third conductive layer, and after etching the first conductive layer, the second conductive layer, and the third conductive layer,
The second conductive layer and the third conductive layer are etched without removing the resist mask, and a first conductive layer having a first width and a second narrower than the first width . a second conductive layer, the third method for manufacturing a wiring for forming the conductive layer ing a lamination of a conductive layer having a narrower third width than the second width having a width,
The first conductive layer having a first width, the second conductive layer having a second width, the third conductive at least the end portion of the second conductive layer of the layer having a third width the method for manufacturing a wiring cross-sectional shape and wherein Rukoto is etched so as to taper in.
前記第3の導電層上に所定の形状のレジストマスクを形成し、前記第2の導電層および前記第3の導電層をエッチングし、
前記レジストマスクを除去せずに、前記第1の導電層をエッチングした後、
前記レジストマスクを除去せずに、前記第2の導電層と前記第3の導電層とをエッチングして、第1の幅を有する第1の導電層と、前記第1の幅より狭い第2の幅を有する第2の導電層と、前記第2の幅より狭い第3の幅を有する第3の導電層との積層からなる導電層を形成する配線の作製方法であって、
前記第1の幅を有する第1の導電層、前記第2の幅を有する第2の導電層、前記第3の幅を有する第3の導電層のうち少なくとも前記第2の導電層の端部における断面形状がテーパー形状になるようにエッチングされることを特徴とする配線の作製方法。On the insulating surface, a first conductive layer, a second conductive layer containing Al as a main component, and a third conductive layer are stacked and formed.
Forming a resist mask having a predetermined shape on the third conductive layer, etching the second conductive layer and the third conductive layer;
After etching the first conductive layer without removing the resist mask ,
The second conductive layer and the third conductive layer are etched without removing the resist mask, and a first conductive layer having a first width and a second narrower than the first width . a second conductive layer, the third method for manufacturing a wiring for forming the conductive layer ing a lamination of a conductive layer having a narrower third width than the second width having a width,
The first conductive layer having a first width, the second conductive layer having a second width, the third conductive at least the end portion of the second conductive layer of the layer having a third width the method for manufacturing a wiring cross-sectional shape and wherein Rukoto is etched so as to taper in.
前記第3の導電層上に所定の形状のレジストマスクを形成し、前記第1の導電層、前記第2の導電層および前記第3の導電層をエッチングした後、
前記レジストマスクを除去せずに、前記第2の導電層と前記第3の導電層とをエッチングして、第1の幅を有する第1の導電層と、前記第1の幅より狭い第2の幅を有する第2の導電層と、前記第2の幅より狭い第3の幅を有する第3の導電層との積層からなる導電層を形成し、
プラズマ処理を行うことによって、前記第2の幅を有する第2の導電層の、前記第1の幅を有する第1の導電層および前記第3の幅を有する第3の導電層と接しない部分を酸化する配線の作製方法であって、
前記第1の幅を有する第1の導電層、前記第2の幅を有する第2の導電層、前記第3の幅を有する第3の導電層のうち少なくとも前記第2の導電層の端部における断面形状がテーパー形状になるようにエッチングされることを特徴とする配線の作製方法。On the insulating surface, a first conductive layer, a second conductive layer containing Al as a main component, and a third conductive layer are stacked and formed.
A resist mask having a predetermined shape is formed on the third conductive layer, and after etching the first conductive layer, the second conductive layer, and the third conductive layer,
The second conductive layer and the third conductive layer are etched without removing the resist mask, and a first conductive layer having a first width and a second narrower than the first width . a second conductive layer having a width of, forming a conductive layer ing a lamination of a third conductive layer having the narrower than the second width third width,
By performing flop plasma processing, the second conductive layer having the second width, not in contact with the third conductive layer having the first conductive layer and the third width having a first width A method of manufacturing a wiring that oxidizes a portion ,
The first conductive layer having a first width, the second conductive layer having a second width, the third conductive at least the end portion of the second conductive layer of the layer having a third width the method for manufacturing a wiring cross-sectional shape and wherein Rukoto is etched so as to taper in.
前記第3の導電層上に所定の形状のレジストマスクを形成し、前記第2の導電層および前記第3の導電層をエッチングし、
前記レジストマスクを除去せずに、前記第1の導電層をエッチングした後、
前記レジストマスクを除去せずに、前記第2の導電層と前記第3の導電層とをエッチングして、第1の幅を有する第1の導電層と、前記第1の幅より狭い第2の幅を有する第2の導電層と、前記第2の幅より狭い第3の幅を有する第3の導電層との積層からなる導電層を形成し、
プラズマ処理を行うことによって、前記第2の幅を有する第2の導電層の、前記第1の幅を有する第1の導電層および前記第3の幅を有する第3の導電層と接しない部分を酸化する配線の作製方法であって、
前記第1の幅を有する第1の導電層、前記第2の幅を有する第2の導電層、前記第3の幅を有する第3の導電層のうち少なくとも前記第2の導電層の端部における断面形状がテーパー形状になるようにエッチングされることを特徴とする配線の作製方法。On the insulating surface, a first conductive layer, a second conductive layer containing Al as a main component, and a third conductive layer are stacked and formed.
Forming a resist mask having a predetermined shape on the third conductive layer, etching the second conductive layer and the third conductive layer;
After etching the first conductive layer without removing the resist mask ,
The second conductive layer and the third conductive layer are etched without removing the resist mask, and a first conductive layer having a first width and a second narrower than the first width . a second conductive layer having a width of, forming a conductive layer ing a lamination of a third conductive layer having the narrower than the second width third width,
By performing flop plasma processing, the second conductive layer having the second width, not in contact with the third conductive layer having the first conductive layer and the third width having a first width A method of manufacturing a wiring that oxidizes a portion ,
The first conductive layer having a first width, the second conductive layer having a second width, the third conductive at least the end portion of the second conductive layer of the layer having a third width the method for manufacturing a wiring cross-sectional shape and wherein Rukoto is etched so as to taper in.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002089262A JP4338934B2 (en) | 2001-03-27 | 2002-03-27 | Wiring fabrication method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001091192 | 2001-03-27 | ||
JP2001-91192 | 2001-03-27 | ||
JP2002089262A JP4338934B2 (en) | 2001-03-27 | 2002-03-27 | Wiring fabrication method |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008277827A Division JP5376709B2 (en) | 2001-03-27 | 2008-10-29 | Semiconductor device and manufacturing method thereof |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2002359246A JP2002359246A (en) | 2002-12-13 |
JP2002359246A5 true JP2002359246A5 (en) | 2005-09-08 |
JP4338934B2 JP4338934B2 (en) | 2009-10-07 |
Family
ID=26612251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002089262A Expired - Lifetime JP4338934B2 (en) | 2001-03-27 | 2002-03-27 | Wiring fabrication method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4338934B2 (en) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG116443A1 (en) * | 2001-03-27 | 2005-11-28 | Semiconductor Energy Lab | Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same. |
US7405033B2 (en) | 2003-01-17 | 2008-07-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing resist pattern and method for manufacturing semiconductor device |
US7183146B2 (en) | 2003-01-17 | 2007-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
EP1592053B1 (en) * | 2003-02-05 | 2011-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Wiring fabricating method |
EP1592049A1 (en) | 2003-02-05 | 2005-11-02 | Sel Semiconductor Energy Laboratory Co., Ltd. | Process for manufacturing display |
JPWO2004070823A1 (en) | 2003-02-05 | 2006-06-01 | 株式会社半導体エネルギー研究所 | Method for manufacturing display device |
WO2004070821A1 (en) | 2003-02-06 | 2004-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Display manufacturing method |
WO2004070822A1 (en) | 2003-02-06 | 2004-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Methods for manufacturing semiconductor device and display |
KR20110031384A (en) | 2003-02-06 | 2011-03-25 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor producing apparatus |
US7061570B2 (en) | 2003-03-26 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
WO2004086487A1 (en) | 2003-03-26 | 2004-10-07 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device and method for manufacturing same |
JPWO2004096449A1 (en) | 2003-04-25 | 2006-07-13 | 株式会社半導体エネルギー研究所 | Droplet discharge apparatus using charged beam and method for producing pattern using the apparatus |
US7192859B2 (en) | 2003-05-16 | 2007-03-20 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device and display device |
US7202155B2 (en) | 2003-08-15 | 2007-04-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing wiring and method for manufacturing semiconductor device |
CN100568457C (en) | 2003-10-02 | 2009-12-09 | 株式会社半导体能源研究所 | The manufacture method of semiconductor device |
KR101088103B1 (en) | 2003-10-28 | 2011-11-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device, and television receiver |
US8101467B2 (en) | 2003-10-28 | 2012-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for manufacturing the same, and liquid crystal television receiver |
US7446054B2 (en) | 2003-10-28 | 2008-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
KR101030056B1 (en) | 2003-11-14 | 2011-04-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for manufacturing liquid crystal display device |
WO2005048222A1 (en) | 2003-11-14 | 2005-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting display device, method for manufacturing the same, and tv set |
US20050170643A1 (en) | 2004-01-29 | 2005-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Forming method of contact hole, and manufacturing method of semiconductor device, liquid crystal display device and EL display device |
US7416977B2 (en) | 2004-04-28 | 2008-08-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device, liquid crystal television, and EL television |
US7494923B2 (en) | 2004-06-14 | 2009-02-24 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of wiring substrate and semiconductor device |
WO2006030937A1 (en) | 2004-09-15 | 2006-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US7888702B2 (en) | 2005-04-15 | 2011-02-15 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method of the display device |
JP4817946B2 (en) * | 2005-04-15 | 2011-11-16 | 株式会社半導体エネルギー研究所 | Method for manufacturing display device |
KR100817746B1 (en) | 2006-12-07 | 2008-03-31 | 한국전자통신연구원 | The fabrication process the thin film transistor having multilayer gate metal on plastic substrate and active matrix display device including the thin film transistor |
JP2011064751A (en) * | 2009-09-15 | 2011-03-31 | Seiko Epson Corp | Conductive film laminated member, electrooptical device, and electronic apparatus |
JP6585354B2 (en) * | 2014-03-07 | 2019-10-02 | 株式会社半導体エネルギー研究所 | Semiconductor device |
KR102470044B1 (en) | 2016-05-13 | 2022-11-24 | 삼성디스플레이 주식회사 | Flexible display device and fabrication method of the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0945688A (en) * | 1995-07-28 | 1997-02-14 | Sony Corp | Interconnection structure and its formation method |
JPH1116913A (en) * | 1997-06-27 | 1999-01-22 | Sony Corp | Semiconductor device and its manufacture |
JP3883706B2 (en) * | 1998-07-31 | 2007-02-21 | シャープ株式会社 | Etching method and method of manufacturing thin film transistor matrix substrate |
JP4159713B2 (en) * | 1998-11-25 | 2008-10-01 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP2001053283A (en) * | 1999-08-12 | 2001-02-23 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
-
2002
- 2002-03-27 JP JP2002089262A patent/JP4338934B2/en not_active Expired - Lifetime
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2002359246A5 (en) | ||
JPH11126976A (en) | Laminated structure body of printed circuit board | |
TW200723474A (en) | High thermal conducting circuit substrate and manufacturing process thereof | |
CN110071124B (en) | Display panel and manufacturing method thereof | |
WO2007084982A8 (en) | Dual-damascene process to fabricate thick wire structure | |
EP2282382A3 (en) | Surface emitting laser, method for manufacturing surface emitting laser, and image forming apparatus | |
WO2006101638A3 (en) | Printed circuit patterned embedded capacitance layer | |
JP5386962B2 (en) | Etching method and method of manufacturing semiconductor device using etching method | |
JP4871777B2 (en) | Etching solution and transistor manufacturing method | |
JP4909912B2 (en) | Pattern formation method | |
JP2007049071A (en) | Chip resistor and manufacturing method thereof | |
KR930020590A (en) | Etching method of metal thin film mainly composed of aluminum and manufacturing method of thin film transistor | |
JP2016127224A5 (en) | ||
JP5616822B2 (en) | Manufacturing method of semiconductor device | |
JP2008135598A (en) | Manufacturing method for thin-film transistor panel | |
JP2006041502A5 (en) | ||
JP6297604B2 (en) | Light emitting device | |
US20050014363A1 (en) | Method of forming metal line layer in semiconductor device | |
TWI458114B (en) | Method of manufacturing solar cell | |
TW200504979A (en) | Method of forming multilayer interconnection structure, and manufacturing method for multilayer wiring boards | |
JP2008288467A (en) | Thin film resistor and its manufacturing method | |
TW201128707A (en) | Active device array substrate and fabricating method thereof | |
JP2007005583A5 (en) | ||
JP2003068501A (en) | Resistor | |
TWI271869B (en) | Method for fabricating a thin film transistor |