JP2002359246A - Wiring and manufacturing method therefor, and circuit board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring capable of dealing with the increase in the area of a pixel part by using a material having a low resistance and to provide a circuit board. SOLUTION: The wiring comprises a laminated structure of a first conductive layer, having a first width and made of an alloy containing one type or a plurality of types of elements, selected from the group consisting of W and Mo or containing the elements as the main component or a compound as a first layer, a second conductive layer having a second width narrower than the first width, having a low resistance and made of an alloy containing Al as the main component or a compound as a second layer, and a third conductive layer having a third width narrower than the second width and containing Ti as the main component or a compound as a third layer. With the thus constitution, the wiring can fully deal with the increase in the area of the pixel part. A sectional shape of the end of at least the second conductive layer is set as a tapered shape. By forming it into such a shape, coverage can be made proper.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a wiring formed by using a thin film technique and a method of manufacturing the wiring. Further, the present invention relates to a wiring substrate and a method for manufacturing the wiring substrate. Note that in this specification, a wiring substrate refers to an insulating substrate such as glass having wiring formed using a thin film technique or various substrates.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs (Integrated Circuits) and electro-optical devices, and their development is particularly urgent as switching elements for image display devices.

Conventionally, a liquid crystal display has been known as an image display. Active-matrix liquid crystal display devices have come to be used more often because high-definition images can be obtained as compared with passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and a counter electrode corresponding to the pixel electrode, optical modulation of a liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is perceived by the observer as a display pattern.

The applications of such an active matrix type liquid crystal display device are expanding, and the demand for higher definition, higher aperture ratio, and higher reliability is increasing as the screen size is increased. At the same time, demands for higher productivity and lower cost have been increasing.

[0005]

In the case where a TFT is manufactured using Al (aluminum) as the wiring of the above-mentioned TFT, protrusions such as hillocks and whiskers are formed by heat treatment, and an insulating film and an active region of Al atoms, particularly Diffusion into the channel formation region may cause a malfunction of the TFT or a decrease in electrical characteristics of the TFT.

Therefore, a metal material (typically, a metal element having a high melting point) that can withstand heat treatment, such as W
(Tungsten) or Mo (molybdenum) may be used. However, the resistivity of these elements is A
Very high compared to 1. (Table 1)

[0007]

[Table 1]

Therefore, when the screen size is increased,
Wiring delay becomes a problem. Therefore, a method of reducing the resistance by making the wiring thicker is considered. However, when the width of the wiring is widened, there is a problem that the degree of freedom in design and the aperture ratio in the pixel portion are reduced. In addition, when the thickness of the wiring is increased, a short circuit easily occurs at a place where the wiring crosses three-dimensionally, and coverage at a step portion of the wiring deteriorates.

Therefore, the present invention solves the above problems,
It is an object to provide a wiring and a method for manufacturing the wiring which can cope with a large screen, and a wiring substrate and a method for manufacturing the wiring substrate.

[0010]

According to the present invention, a wiring structure is provided.
One or more selected from W or Mo, or a conductive film mainly containing one or more selected from W or Mo is used as the first layer, and Al is used as a main component as the second layer. A low resistance conductive film is used, and Ti is used as the third layer.
With a stacked structure using a conductive film mainly containing, the resistance of the wiring is reduced. In the present invention, the formation of projections such as hillocks and whiskers by heat treatment can be prevented by sandwiching a low-resistance conductive film containing Al as a main component between other conductive films. Further, since the first layer and the third layer are conductive films having a high melting point, the first layer and the third layer function as a barrier metal, so that it is possible to prevent Al atoms from diffusing into the insulating film or the active region. (Table 2) When an insulating film is formed on the wiring of the present invention and a contact with the wiring is formed,
Since the third layer functions as a stopper in the etching of the insulating film, contact formation is facilitated. In addition, when Al contacts a typical ITO film as a transparent conductive film, it causes electrolytic corrosion and increases the contact resistance. However, since the third layer is formed of a conductive film containing Ti as a main component, the contact resistance is increased. The value is good.

[0011]

[Table 2]

Further, in the present invention, at least Al
It is assumed that the end of the second layer formed of a low-resistance conductive film whose main component is a tapered shape. The taper shape improves coverage at the step. Note that, in this specification, the taper angle refers to an angle formed between a horizontal plane and a side surface of the material layer. In this specification, for convenience, a side surface having a taper angle is referred to as a tapered shape, and a portion having a tapered shape is referred to as a tapered portion.

According to the structure of the invention disclosed in this specification, a first conductive layer having a first width is used as a first layer, and a second conductive layer having a second width smaller than the first width is used as a first layer. The second layer has a stacked structure in which a third conductive layer having a third width smaller than the second width is a third layer, and the first conductive layer or the second conductive layer or the second conductive layer has a third width smaller than the second width. The cross-sectional shape at the end of the conductive layer 3 is tapered.

In the above structure, the wiring is a conductive layer (first layer) made of an alloy or a compound containing W as a main component.
And a conductive layer (third layer) composed of an alloy or a compound mainly composed of Al and a conductive layer (third layer) composed of an alloy or a compound mainly composed of Ti. It is characterized by. Alternatively, the wiring is a conductive layer (first layer) made of an alloy or a compound containing Mo as a main component.
Layer), a conductive layer (second layer) made of an alloy or compound mainly composed of Al, and a conductive layer (third layer) made of an alloy or compound mainly composed of Ti. It is characterized by having. For example, as the first layer,
W, WN, Mo, or the like can be used. As the second layer,
Al, Al-Si (2 wt%), Al-Ti (1 wt%)
%), Al-Nd (1 wt%), Al-Sc (0.18
wt%) or the like, and Ti,
TiN or the like can be used. These are sputtering methods,
It can be formed by a plasma CVD method or the like. To form Al—Si or the like in the second layer, S
Limit that element such as i can be dissolved in Al (solid solubility limit)
The higher the solid solubility, the higher the resistivity and the heat resistance. Therefore, the resistivity and heat resistance suitable for wiring, S
The ratio of Si or the like in Al may be appropriately determined by the practitioner depending on the solid solubility limit of the element such as i.

Table 3 shows an example of the resistivity of each conductive layer forming a wiring. Table 3 shows that the conductive layer made of an alloy or a compound containing Al as a main component has much lower resistance than other conductive layers.

[0016]

[Table 3]

The first conductive film, the second conductive film, and the third conductive film having heat resistance and conductivity can be etched at high speed and with high accuracy to further form a tapered end. Any etching method can be used. Among them, it is particularly preferable to apply a dry etching method using high-density plasma. Microwaves and helicon waves (Heli
con Wave Plasma (HWP) and inductively coupled plasma (Induc)
An etching apparatus using tively coupled plasma (ICP) is suitable. For example, ECR (Electron Cyclotr
on Resonance etching system, SWP (Surface Wave)
Plasma) etching equipment, ICP etching equipment, 2
A parallel plate excitation type etching apparatus with a frequency may be used. In particular, an ICP etching apparatus can easily control plasma and can cope with an increase in the area of a processing substrate.

For example, as means for performing plasma processing with high precision, high-frequency power is applied to a multi-spiral coil having a plurality of spiral coil portions connected in parallel via an impedance matching device to form plasma. Is used. Further, a bias voltage is applied by separately applying a high-frequency power to the lower electrode holding the object to be processed.

When an etching apparatus using an ICP to which such a multi-spiral coil is applied is used, the angle of the tapered portion (taper angle) greatly changes depending on the bias power applied to the substrate side, and the bias power is further increased. By changing the pressure, the angle of the tapered portion can be changed from 5 to 85 °.

The gas used for etching the second layer and the third layer is preferably a chlorine-based gas. For example, S
iCl ₄ , HCl, CCl ₄ , BCl ₃ , Cl _{2 and the} like can be used.

The gas used for etching the first layer is preferably a fluorine-based gas. For example, NF ₃ , CF ₄ , C ₂
F ₆ , SF ₆ or the like can be used. Further, it is preferable to introduce a chlorine-based gas at the same time as the fluorine-based gas in the etching of the first layer, since the etching rate is improved.

Further, by forming a wiring having a laminated structure using the above-described conductive layer, the end of the wiring is tapered by using an ICP etching method or the like. By forming the end portion of the wiring in a tapered shape, coverage of a film or the like formed in a later step can be improved.

In the above structure, it is preferable that an end of the first conductive layer has a tapered shape. The tapered portion (taper portion) is the second portion.
And the width of the region is the width obtained by subtracting the second width from the first width. Further, it is preferable that the second conductive layer has a tapered shape and is larger than a taper angle of a tapered portion in the first conductive layer. Further, it is desirable that the third conductive layer also has a tapered shape, and it is desirable that the third conductive layer has almost the same taper angle as the tapered portion of the second conductive layer.

A structure for realizing the present invention is a conductive layer having a first shape formed by laminating a first conductive layer, a second conductive layer, and a third conductive layer on an insulating surface. Is formed, and the first conductive layer, the second conductive layer, and the third conductive layer are etched to form a first conductive layer having a first width and a second conductive layer having a second width. A conductive layer having a second shape, which is formed by laminating a conductive layer having a second width and a third conductive layer having a third width, and forming a second conductive layer having the second width; The third conductive layer having a width is etched to form a fourth conductive layer.
Forming a third shape conductive layer composed of a stack of a first conductive layer having a width of?, A second conductive layer having a fifth width, and a third conductive layer having a sixth width. A method for manufacturing a wiring, wherein an end of a first conductive layer having the fourth width, a second conductive layer having the fifth width, or an end of the third conductive layer having the sixth width is provided. The cross-sectional shape is characterized by a tapered shape.

In the above structure, the wiring is a conductive layer (first layer) made of an alloy or compound containing W as a main component.
And a conductive layer (third layer) composed of an alloy or a compound mainly composed of Al and a conductive layer (third layer) composed of an alloy or a compound mainly composed of Ti. It is characterized by. Alternatively, the wiring is a conductive layer (first layer) made of an alloy or a compound containing Mo as a main component.
Layer), a conductive layer (second layer) made of an alloy or compound mainly composed of Al, and a conductive layer (third layer) made of an alloy or compound mainly composed of Ti. It is characterized by having.

Further, by forming a wiring having a laminated structure using the above-described conductive layer, an ICP (Inductively Coupled) is provided.
Plasma: Inductively coupled plasma) The end of the wiring is tapered by using an etching method or the like. By forming the end portion of the wiring in a tapered shape, coverage of a film or the like formed in a later step can be improved.

In the above structure, it is preferable that an end of the first conductive layer has a tapered shape. The tapered portion (taper portion) is the second portion.
And the width of the region is the width obtained by subtracting the second width from the first width. Further, it is preferable that the second conductive layer has a tapered shape and is larger than a taper angle of a tapered portion in the first conductive layer. Further, it is desirable that the third conductive layer also has a tapered shape, and it is desirable that the third conductive layer has almost the same taper angle as the tapered portion of the second conductive layer.

Further, another configuration of the present invention includes an insulating substrate,
In the wiring board having a wiring, the wiring has a first conductive layer having a first width as a first layer and a second conductive layer having a second width smaller than the first width as a second layer. A stacked structure in which a third conductive layer having a third width smaller than the second width is used as a third layer, wherein the first conductive layer or the second conductive layer or the third conductive layer has a third width smaller than the second width. The cross-sectional shape at the end of the conductive layer is tapered.

In the above structure, the step of forming the wiring includes forming a conductive film mainly containing W, forming a conductive film mainly containing Al, and forming a conductive film mainly containing Ti. It is characterized by being formed by etching with a mask after lamination. In the above structure, the step of forming the wiring includes forming a conductive film mainly containing Mo, forming a conductive film mainly containing Al, and forming a conductive film mainly containing Ti. It is characterized in that after lamination, it is formed by etching with a mask.

In the above structure, it is preferable that an end of the first conductive layer has a tapered shape. The tapered portion (taper portion) is the second portion.
And the width of the region is the width obtained by subtracting the second width from the first width. Further, it is preferable that the second conductive layer has a tapered shape and is larger than a taper angle of a tapered portion in the first conductive layer. Further, it is desirable that the third conductive layer also has a tapered shape, and it is desirable that the third conductive layer has almost the same taper angle as the tapered portion of the second conductive layer.

Further, a configuration for realizing the present invention is that a first-shaped conductive layer formed by laminating a first conductive layer, a second conductive layer, and a third conductive layer on an insulating surface. Is formed, and the first conductive layer, the second conductive layer, and the third conductive layer are etched to form a first conductive layer having a first width and a second conductive layer having a second width. A conductive layer having a second shape, which is formed by laminating a conductive layer having a second width and a third conductive layer having a third width, and forming a second conductive layer having the second width; The third conductive layer having a width is etched to form a fourth conductive layer.
Forming a third shape conductive layer composed of a stack of a first conductive layer having a width of?, A second conductive layer having a fifth width, and a third conductive layer having a sixth width. A method of manufacturing a wiring board, comprising: forming a first conductive layer having a fourth width, a second conductive layer having a fifth width, or a third conductive layer having a sixth width. The sectional shape at the end is characterized by a tapered shape.

In the above structure, the step of forming the wiring includes forming a conductive film mainly containing W, forming a conductive film mainly containing Al, and forming a conductive film mainly containing Ti. It is characterized by being formed by etching with a mask after lamination. In the above structure, the step of forming the wiring includes forming a conductive film mainly containing Mo, forming a conductive film mainly containing Al, and forming a conductive film mainly containing Ti. It is characterized in that after lamination, it is formed by etching with a mask.

Further, by forming a wiring having a laminated structure using the above-described conductive layer, an ICP (Inductively Coupled) is provided.
Plasma: Inductively coupled plasma) The end of the wiring is tapered by using an etching method or the like. By forming the end portion of the wiring in a tapered shape, coverage of a film or the like formed in a later step can be improved.

In the above structure, it is preferable that an end of the first conductive layer has a tapered shape. The tapered portion (taper portion) is the second portion.
And the width of the region is the width obtained by subtracting the second width from the first width. Further, it is preferable that the second conductive layer has a tapered shape and is larger than a taper angle of a tapered portion in the first conductive layer. Further, it is desirable that the third conductive layer also has a tapered shape, and it is desirable that the third conductive layer has almost the same taper angle as the tapered portion of the second conductive layer.

According to the present invention, the resistance of the wiring can be reduced by a simple method that is compatible with a conventional wiring or wiring board manufacturing process. Therefore, the degree of freedom in design and the aperture ratio in the pixel portion can be improved. Since the wiring includes the conductive layer having a tapered shape, good coverage can be obtained. In addition to satisfying such advantages, in a semiconductor device represented by an active matrix liquid crystal display device, it is possible to sufficiently cope with an increase in the area of a pixel portion and an increase in screen size. It is possible to improve operating characteristics and reliability.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
This will be described with reference to FIG. In the present embodiment, a wiring substrate provided with a gate electrode of a TFT using the present invention will be described.

First, a base insulating film 11 is formed on a substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a silicon substrate, a plastic substrate, a metal substrate, a flexible substrate, or the like can be used. Examples of the glass substrate include a substrate made of glass such as barium borosilicate glass or aluminoborosilicate glass. Further, the flexible substrate is a film-shaped substrate made of PET, PES, PEN, acrylic, or the like. If a semiconductor device is manufactured using the flexible substrate, weight reduction is expected. An aluminum film (A) is formed on the front surface or the front and back surfaces of the flexible substrate.
It is desirable to form a barrier layer such as 1ON, AlN, AlO, etc., a carbon film (DLC (diamond-like carbon), etc.), SiN or the like into a single layer or a multilayer, since durability and the like are improved.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example is shown in which a two-layer structure (11a, 11b) is used as the base film 11, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Note that the base insulating film need not be formed.

Next, the semiconductor layer 12 is formed on the base insulating film. The semiconductor layer 12 is formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) and then performing a known crystallization treatment (a laser crystallization method, a thermal crystallization method, or the like). , Or a thermal crystallization method using a catalyst such as nickel) is used to pattern the crystalline semiconductor film into a desired shape using a first photomask. The thickness of the semiconductor layer 12 is 25
It is formed with a thickness of about 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

Next, an insulating film 13 covering the semiconductor layer 12 is formed. The insulating film 13 is formed using a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and have a single-layer or stacked-layer structure of an insulating film containing silicon. The insulating film 13 becomes a gate insulating film.

Next, a film thickness of 20 to 100
A first conductive film 14 having a thickness of 100 nm, a second conductive film 15 having a thickness of 100 to 800 nm, and a third conductive film 16 having a thickness of 20 to 100 nm are stacked. Here, a sputtering method, a plasma CVD method, or the like is used, and as the first conductive layer in contact with the insulating film, a conductive film containing W or Mo as a main component (W, WMo, Mo) in order to prevent diffusion to a channel formation region. Etc.) may be used. Further, as the second conductive layer, a low-resistance conductive film (Al, Al—Ti, Al—S) containing Al as a main component is used.
c, Al-Si, etc.). In addition, as the third conductive layer, Ti (Ti, TiN
Etc.) may be used.

Next, a resist mask 17a is formed using a second photomask, and a first etching step is performed using an ICP etching apparatus or the like. In the first etching step, the first to third conductive films 14 to 16 are etched, and as shown in FIG. 1B, a conductive layer having a tapered portion (a tapered portion) at an end portion. 18a to 20a are obtained.

Next, using the resist mask 17a formed in the second photolithography process as it is
Second etching is performed using an etching apparatus or the like. By this second etching step, the second conductive layer 19a
Then, the third conductive layer 18a is selectively etched to form a second conductive layer 19b and a third conductive layer 18b as shown in FIG. At the time of this second etching, the resist mask, the first conductive layer, and the insulating film are also slightly etched, and the resist mask 17
b, a first conductive layer 20b and an insulating film 21b are formed.
The first conductive layer 20b has a first width (W1), the second conductive layer 19b has a second width (W2), and the third conductive layer 18b has It has a third width (W3). Note that the first width is larger than the second width, and the second width is larger than the third width.

In this case, two etchings (a first etching step and a second etching step) are performed to suppress the film thickness of the insulating film 13 from being reduced, but as shown in FIG. As long as an electrode structure (a laminate of the third conductive layer 18b, the second conductive layer 19b, and the first conductive layer 20b) can be formed, the number of times is not particularly limited to two, and a plurality of times may be used. It may be performed in one etching step.

As described above, in the present invention, since the gate wiring is formed of a conductive layer having a low resistance, it can be sufficiently driven even if the area of the pixel portion is increased. Of course, the present invention can be used not only for gate wiring but also for various wirings, and a wiring substrate having these wirings formed on a substrate can be manufactured. Then, it is possible to improve the operating characteristics and reliability of the semiconductor device in which such wiring is formed.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0047]

Embodiments of the present invention will be described below, but it is needless to say that the present invention is not limited to these embodiments.

Embodiment 1 An example of the structure of a wiring board provided with a gate electrode using the present invention will be described below.

First, a base insulating film 11 is formed on a substrate 10. As the substrate 10, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a flexible substrate on which an insulating film is formed may be used. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used. In this embodiment, a 1737 glass substrate manufactured by Corning Incorporated was used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. Here, an example is shown in which a two-layer structure (11a, 11b) is used as the base film 11, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. Note that the base insulating film need not be formed. In this embodiment, a 50 nm-thick silicon oxynitride film 11a (composition ratio: Si = 32%, O = 27%, N = 24%, H = 17)
%). Next, a 100 nm-thick silicon oxynitride film 11b (composition ratio: Si = 32%, O = 59%, N = 7)
%, H = 2%).

Next, the semiconductor layer 12 is formed on the base insulating film. The semiconductor layer 12 is formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) and then performing a known crystallization treatment (a laser crystallization method, a thermal crystallization method, or the like). , Or a thermal crystallization method using a catalyst such as nickel) is used to pattern the crystalline semiconductor film into a desired shape using a first photomask. The thickness of the semiconductor layer 12 is 25
It is formed with a thickness of about 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. After dehydrogenation (500 ° C., 1 hour) of this amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed, and laser annealing treatment for improving crystallization is further performed. A crystalline silicon film was formed. The crystalline silicon film is patterned by photolithography to form a semiconductor layer 1.
2 was formed.

Next, an insulating film 13 covering the semiconductor layer 12 is formed. The insulating film 13 is formed using a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and have a single-layer or stacked-layer structure of an insulating film containing silicon. The insulating film 13 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2) with a thickness of 110 nm by a plasma CVD method.
%).

Next, a film thickness of 20 to 100
A first conductive film 14 having a thickness of 100 nm, a second conductive film 15 having a thickness of 100 to 800 nm, and a third conductive film 16 having a thickness of 20 to 100 nm are stacked. As the first conductive layer which is in contact with the insulating film by a sputtering method or the like, a conductive film containing W or Mo as a main component (W, WMo, Mo, or the like) may be used to prevent diffusion to a channel formation region. Further, as the second conductive layer, a low-resistance conductive film containing Al as a main component (such as Al, Al-Ti, Al-Sc, or Al-Si) may be used. Further, as the third conductive layer, a conductive film (Ti, TiN) mainly composed of Ti having a low contact resistance is used.
Etc.) may be used. In this embodiment, a first conductive film 14 made of a W film having a thickness of 30 nm is formed by a sputtering method.
Second conductive film 1 made of a 500 nm thick Al-Ti film
5 and a third conductive film 16 made of a 50 nm-thick Ti film
Were laminated. The ratio of Ti in the second conductive film 15 is 1
%, And was formed using Al-Ti as the target.

Subsequently, a first etching process is performed. In the first etching process, the first etching condition and the second etching condition are used.
The etching conditions are as follows. In the present embodiment, as the first etching condition, ICP (Inductively Coupled Plasma:
An inductively coupled plasma) etching method, using BCl ₂ , Cl ₂ and O ₂ as etching gases, with a gas flow ratio of 65: 10: 5 (sccm) and 1.2P
RF of 450 W (13.56 MH)
z) Power was applied to generate plasma, and etching was performed for 147 seconds. Here, I manufactured by Matsushita Electric Industrial Co., Ltd.
Dry etching system using CP (Model E645)
− □ ICP) was used. 3 on the substrate side (sample stage)
Apply RF (13.56 MHz) power of 00 W and apply a substantially negative self-bias voltage. The etching rate for the resist under the first etching condition is 235.5 nm /
min, and the etching rate for Al-Ti is 2
It is 33.4 nm / min, and the etching rate for W is 133.8 nm / min. The etching rate of Ti is almost the same as that of Al-Ti. FIG.
As shown in FIG.
By etching the Ti film and the Ti film, a second conductive layer 29 and a third conductive layer 28 each having a tapered end are obtained. Also, depending on the first etching condition, Al
-The taper angle of the Ti film and the Ti film is about 45 °. The etching rate for W is resist, T
i, sufficiently lower than Al—Ti, the first conductive layer 3
In the case of 0, mainly only the surface is etched, and a region which does not overlap with the second conductive layer 29 and the third conductive layer 28 is thin.

After that, the mask 17a made of resist is not removed and the second etching condition is changed. CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 25:25: 10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for 30 seconds. 20W RF (13.5) on the substrate side (sample stage)
6MHz) Power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ , Cl ₂ and O ₂ are mixed, only the W film is etched. The etching rate for W under the second etching condition is 124.6 n.
m / min. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

As described above, the etching of the first conductive layer 30 under the second etching condition is performed by etching the second conductive layer 29 and the third conductive layer 28 (and the resist 27) formed under the first etching condition. Is used as a mask. Therefore, the width of the first conductive layer 20a formed under the second etching condition may be controlled by the first etching condition. Through such steps, the width of the region serving as the impurity region can be easily controlled.

In the first etching process, by making the shape of the resist mask appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. Thus, by the first etching process, the first conductive layer 20a, the second conductive layer 19a, and the third conductive layer 18a are formed.
Is formed. Here, the width of the first conductive layer in the channel length direction corresponds to W1 described in the above embodiment. Reference numeral 21a denotes a gate insulating film, and a region which is not covered with the first shape conductive layer is etched by about 20 to 50 nm to form a thinned region. Note that the first etching treatment here corresponds to the first etching step (FIG. 1B) described in the embodiment. FIG. 2A is a SEM photograph of the first shape conductive layer formed as described above.
Shown in

Next, a second etching process is performed without removing the resist mask. Here, BCl ₃ and Cl ₂ are used as etching gases, the respective gas flow rates are set to 20:60 (sccm), and 600 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. Then, plasma was generated to perform etching. 100 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the Al—Ti film and T
The i film is selectively etched. By this second etching, the taper angles of the Al—Ti film and the Ti film become 80
°. By this second etching process, a second conductive layer 19b and a third conductive layer 18b are formed. On the other hand, the first conductive layer 20a is hardly etched compared to the second conductive layer and the third conductive layer, and the first conductive layer 2a is not etched.
0b is formed. Note that the second etching process here is the second etching process (FIG. 1) described in the embodiment mode.
(C)). Thus, the width of the first conductive layer in the channel length direction is W1, the width of the second conductive layer is W2,
A conductive layer having a second shape in which the width of the third conductive layer was W3 was formed. FIG. 2 shows an SEM photograph of the second shape conductive layer.
It is shown in (B).

Table 4 shows that the ratio of the etching rate of the film formed under the Al-Ti film to the Al-Ti film is 2 to 10 in consideration of the in-plane variation of the etching rate of the Al-Ti film. The result of calculation of the thickness (unit: nm) of the lower layer film to be etched, if any, is shown. At this time, the thickness of the Al—Ti film was set to 500 nm, and ± 5
Calculated as having% variation.

[0060]

[Table 4]

As shown in Table 4, as the variation in the etching rate with respect to the Al—Ti film increases, the film thickness to be etched increases, and as the selectivity to the underlying film increases, the film thickness to be etched decreases. Become. By utilizing this characteristic, it is possible to form a wiring having a desired shape.

As described above, according to the present invention, since the gate wiring is formed of a conductive layer having a low resistance, even if the area of the pixel portion is increased, it can be sufficiently driven without a problem such as wiring delay. . Then, it is possible to improve the operating characteristics and reliability of the semiconductor device in which such wiring is formed.

[Embodiment 2] In this embodiment, the case where the first etching condition in the first etching process in Embodiment 1 is changed will be described below with reference to FIGS. . Here, since the condition in the first etching condition is changed, the gate wiring is not used in the first embodiment.
Although only two layers, the second conductive layer and the third conductive layer, are formed in the first embodiment, the present invention can be applied to the case where the first conductive layer in the first embodiment is formed as a lower layer in three layers.

First, a 200 nm-thick oxynitride film 33 is formed on a 1737 glass substrate 10 by a sputtering method. Next, on the insulating film 33 by a sputtering method,
First conductive film 3 made of an Al—Ti film having a thickness of 500 nm
And a second conductive film 3 made of a Ti film having a thickness of 100 nm
5 were laminated (FIG. 3A).

Subsequently, a resist is formed on the second conductive film, and an etching process is performed. This etching process
This corresponds to the first etching condition in the first embodiment. In this embodiment, an ICP (Inductivel
y Coupled Plasma: Inductively coupled plasma) using an etching method and applying a pressure of 1.2 Pa
l ₂ and Cl ₂ were used. Etching was performed by changing the respective gas flow ratios and the electric power applied to the coil-type electrode and the substrate side (sample stage) as shown in Table 5 (FIG. 3B). With this etching process, the resist, the second conductive film 35 and the first conductive film 34 are etched, and the second conductive film 37 and the first conductive layer 3 are etched.
8 are formed. Further, the insulating film is also etched to form an insulating film having a shape shown by 40.

[0066]

[Table 5]

FIGS. 4 to 6 show the shapes of the conductive layers obtained under the conditions shown in Table 5 as observed at 15,000 times by SEM. 4A shows a conductive layer formed under Condition 1, FIG. 4B shows a conductive layer formed under Condition 2, and FIG. 4C shows a conductive layer formed under Condition 3. . 5A shows a conductive layer formed under the condition 4, FIG. 5B shows a conductive layer formed under the condition 5, and FIG. 5C shows a conductive layer formed under the condition 6. It is. 6A shows a conductive layer formed under the condition 7, FIG. 6B shows a conductive layer formed under the condition 8, and FIG. 6C shows a conductive layer formed under the condition 9. It is. FIG. 4 shows that the taper angle increases as the power applied to the coil-type electrode increases. FIG.
It can be seen from the graph that the taper angle increases as the power applied to the substrate increases. FIG. 6 shows that the taper angle increases as the gas flow rate of BCl ₂ increases. Thus, it can be seen that the angle of the obtained tapered portion changes depending on the conditions. Also, Table 6 shows Table 5
Shows the etching rate obtained under the conditions shown by.
Table 7 shows the selectivity for each film. A
Anisotropic etching can be performed under the condition that the selectivity between l-Ti and W is large, and a conductive layer having a desired shape can be formed.

[0068]

[Table 6]

[0069]

[Table 7]

As described above, by changing the conditions, a conductive layer having a desired shape can be obtained. In addition, even when the area of the pixel portion is increased, the pixel portion can be sufficiently driven without a problem such as a wiring delay. Then, it is possible to improve the operating characteristics and reliability of the semiconductor device in which such wiring is formed.

[Embodiment 3] In this embodiment, the case where plasma processing is performed on the wiring formed in Embodiment 1 will be described with reference to FIG.
This will be described with reference to FIG. Note that, in this specification, the plasma treatment refers to a treatment in which a sample is exposed to an atmosphere in which a gas is turned into plasma.

First, according to the first embodiment, FIG.
Get the state of. Note that FIGS. 17A and 1C show the same state, and the same reference numerals are used for corresponding parts.

Then, plasma treatment is performed on the formed wiring using oxygen or a gas containing oxygen as a main component, or H ₂ O. (FIG. 17B) The plasma treatment is performed for 30 seconds to 20 minutes (preferably 3 to 15 minutes) using a plasma generator (plasma CVD device, dry etching device, sputtering device, or the like). Further, when the gas flow rate is 50 to
It is desirable to perform processing at 300 sccm, a substrate temperature of room temperature to 200 degrees, and an RF of 100 to 2000 W. By performing the plasma treatment, the second conductive layer 19b formed of a conductive layer formed of Al or an alloy or compound containing Al as a main component among the conductive layers having a three-layer structure is easily oxidized. In the conductive layer 19b, a portion 22 not in contact with another conductive layer is oxidized. Therefore, the formation of protrusions such as hillocks and whiskers can be further reduced.

Of course, in order to remove the resist 17b, oxygen or a gas containing oxygen as a main component or H ₂
If the ashing with O is performed, the exposed portion of the second conductive layer is oxidized. However, it is easier to form a sufficient oxide film by performing the plasma treatment after removing the resist 17b.

As described above, in the present invention, since the gate wiring is formed of a conductive layer having a low resistance, even if the area of the pixel portion is increased, it can be sufficiently driven without causing a problem such as wiring delay. it can. Then, it is possible to improve the operating characteristics and reliability of the semiconductor device in which such wiring is formed.

[Embodiment 4] An example of manufacturing a wiring board by applying the present invention to a wiring structure different from those of Embodiments 1 to 3 will be described below with reference to FIG.

First, the substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a flexible substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used. In this embodiment, a 1737 glass substrate manufactured by Corning Incorporated is used.

Next, a film having a thickness of 20 to 100 n is formed on the substrate 10.
m of the first conductive film 44 and 100-800 nm of the second conductive film 44.
Conductive film 45 and third conductive film 4 having a thickness of 20 to 100 nm
6 are laminated. Here, a sputtering method is used, and as the first conductive layer in contact with the insulating film, a conductive film containing W or Mo as its main component in order to prevent diffusion of impurities from the substrate 10 may be used. Further, as the second conductive layer, A
A low-resistance conductive film containing l or Cu as a main component may be used. In addition, as the third conductive layer, a conductive film containing Ti as a main component and having low contact resistance may be used. In this embodiment, a first conductive film 44 made of a Mo film having a thickness of 30 nm and an Al—Ti film having a thickness of 500 nm are formed by sputtering.
A second conductive film 45 made of a film and a third conductive film 46 made of a 50-nm-thick Ti film are stacked.

Then, an etching process is performed. The etching is performed under the first etching condition and the second etching condition. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as a first etching condition, and B is used as an etching gas.
Using Cl ₂ , Cl _2, and O ₂ , the respective gas flow ratios are 65: 10: 5 (sccm), and 450 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. To generate plasma to perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 300W RF (13.56MHz) on substrate side (sample stage)
Power is applied and a substantially negative self-bias voltage is applied. The Al—Ti film and the Ti film are etched under the first etching conditions to make the end of the first conductive layer tapered. Further, according to the first etching condition, the taper angles of the Al—Ti film and the Ti film are about 45 degrees.
°, but Mo is not etched.

Thereafter, the second etching condition was changed without removing the mask 47 made of resist, and CF ₄ , Cl _2, and O ₂ were used as etching gases, and the respective gas flow ratios were 25:25: At 10 sccm, 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma to perform etching. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. C
Under the second etching condition in which F ₄ , Cl ₂ and O ₂ are mixed, only the Mo film is etched. In order to perform etching without leaving a residue on the gate insulating film, 10 to 2
It is preferable to increase the etching time at a rate of about 0%.

In the above-mentioned etching process, the end of the first conductive layer and the end of the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side by making the shape of the resist mask appropriate. Becomes The angle of the tapered portion may be 15 to 45 degrees. Thus, the first conductive layer 50 and the second conductive layer 4 are etched by the etching process.
9 and a third conductive layer 48 are formed.

Next, an insulating film 51 covering the conductive layer is formed. The insulating film 51 is formed by a plasma CVD method or a sputtering method to have a thickness of 40 to 150 nm and have a single-layer or stacked-layer structure of an insulating film containing silicon. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2) with a thickness of 110 nm by a plasma CVD method.
%).

Next, a semiconductor layer 52 is formed on the insulating film 51. The semiconductor layer 52 is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), and then performing a known crystallization treatment (laser crystallization method, thermal crystallization, or the like). , Or a thermal crystallization method using a catalyst such as nickel) is used to pattern the crystalline semiconductor film into a desired shape using a photomask. The thickness of this semiconductor layer 52 is 25-30.
It is formed with a thickness of 0 nm (preferably 30 to 150 nm). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy. In this embodiment, a crystalline silicon film is formed by performing a laser annealing process after forming an amorphous silicon film of 55 nm by a plasma CVD method. Then, the semiconductor layer 52 is formed by patterning the crystalline silicon film using a photolithography method.

As described above, according to the present invention, since the gate wiring is formed of the conductive layer having a low resistance, the inverted staggered T
Even when the FT is used, even if the area of the pixel portion is increased, the pixel portion can be sufficiently driven without a problem such as a wiring delay. Then, it is possible to improve the operating characteristics and reliability of the semiconductor device in which such wiring is formed.

Embodiment 5 In this embodiment, a method for manufacturing an active matrix substrate will be described as an example of a wiring substrate utilizing the present invention with reference to FIGS. Note that in this specification, a substrate in which a driver circuit including a CMOS circuit, a pixel portion including a pixel TFT, and a storage capacitor are formed over the same substrate is referred to as an active matrix substrate for convenience.

First, in this embodiment, Corning # 70
A substrate 400 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 400, a quartz substrate, a silicon substrate, a metal substrate, or a flexible substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 401 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 400. Although a two-layer structure is used as the base film 401 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 401, a plasma CVD method is used, and SiH ₄ , N
The silicon oxynitride film 401a formed using H ₃ and N ₂ O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 10 nm).
0 nm). In this embodiment, a 50-nm-thick silicon oxynitride film 401a (composition ratio: Si = 32%, O = 27%,
N = 24%, H = 17%). Next, as a second layer of the base film 401, S
A silicon oxynitride film 401b formed using iH ₄ and N ₂ O as a reaction gas is formed to a thickness of 50 to 200 nm (preferably 100 to 200 nm).
(About 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 401b (composition ratio Si =
32%, O = 59%, N = 7%, H = 2%).

Next, the semiconductor layers 402 to 40 are formed on the underlying film.
6 is formed. The semiconductor layers 402 to 406 are formed to have a thickness of 25 to 300 nm (preferably 30 to 200 nm) by a known means (sputtering, LPCVD, plasma CVD, or the like).
nm), and a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization) Method). Then, the obtained crystalline semiconductor film is patterned into a desired shape to form a semiconductor layer 40.
2 to 406 are formed. Examples of the semiconductor film include an amorphous semiconductor film, a microcrystalline semiconductor film, and a crystalline semiconductor film. A compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a plasma CVD method. Then, a solution containing nickel is held on the amorphous silicon film, and the amorphous silicon film is dehydrogenated (at 500 ° C., 1 ° C.).
After that, thermal crystallization (550 ° C., 4 hours) is performed to form a crystalline silicon film. Then, the semiconductor layer 40 is patterned by a patterning process using a photolithography method.
2 to 406 are formed.

When a crystalline semiconductor film is formed by a laser crystallization method, a continuous wave or pulsed solid-state laser, a gas laser, a metal laser, or the like can be used as a laser. As the solid-state laser, a continuous oscillation or pulse oscillation YAG laser, YVO
₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti:
There are sapphire lasers and the like, as the gas laser, a continuous oscillation or pulse oscillation excimer laser, an Ar laser, a Kr laser, a CO ₂ laser, and the like, and as the metal laser, a helium cadmium laser, a copper vapor laser,
A gold vapor laser. In the case of using these lasers, a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and irradiated to a semiconductor film is preferably used. The crystallization conditions are appropriately selected by the practitioner. When a pulse oscillation excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 1200 mJ / cm ² , typically 100 to 700 mJ.
/ cm ² (preferably 200 to 300 mJ / cm ² ). When a pulse oscillation YAG laser is used, the pulse oscillation frequency is set to 1 to 300 Hz using the second harmonic,
The laser energy density is 300 to 1800 mJ / cm ² , typically 300 to 1000 mJ / cm ² (preferably 350 to
５００500 mJ / cm ² ). And width 100-10
A laser beam condensed linearly at 00 μm, for example 400 μm, may be irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beams at this time may be set to 50 to 98%. Also, the energy density in the case of using a continuous wave laser of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed by moving the stage relatively to the laser beam at a speed of about 0.5 to 2000 cm / s.

However, in this embodiment, since the amorphous silicon film was crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film.
Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and heat treatment (such as RTA or thermal annealing using a furnace annealing furnace) is performed to form the amorphous silicon film in the amorphous silicon film. The metal element is diffused, and the amorphous silicon film is removed by etching after the heat treatment. By doing so, the content of the metal element in the crystalline silicon film can be reduced or removed.

Of course, a TFT can be manufactured using a crystalline semiconductor film obtained only by the laser crystallization method. However, if a thermal crystallization method using a metal element and a laser crystallization method are combined, the crystalline semiconductor film can be formed. This is desirable because the electrical properties of the TFT are improved because the crystallinity of the TFT is improved.
For example, when a TFT is manufactured using a crystalline semiconductor film formed only by a laser crystallization method, the mobility is 300 cm ² / V.
When a TFT is manufactured using a crystalline semiconductor film formed by a thermal crystallization method and a laser crystallization method using a metal element, the mobility is remarkably improved to about 500 to 600 cm ² / Vs.

After the formation of the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold value of the TFT.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300 to
400 ° C., high frequency (13.56 MHz) power density 0.
It can be formed by discharging at 5 to 0.8 W / cm ² .
The silicon oxide film thus manufactured is thereafter
Good electrical characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, a film thickness of 20 is formed on the gate insulating film 407.
A first conductive film 408a having a thickness of 100 to 100 nm;
A second conductive film 408b of 800 nm and a thickness of 20 to 10
A third conductive film 408c having a thickness of 0 nm is stacked. In this embodiment, the first conductive film 4 made of a 30 nm-thick WN film is used.
08a and a second 370-nm-thick Al—Sc film.
And a third conductive film 408c formed of a 30-nm-thick TiN film.

In this embodiment, the first conductive film 408
Although a is WN, it is not particularly limited, and the first conductive film may be formed of a conductive layer made of an element selected from W or Mo, or an alloy or a compound containing the above element as a main component. Although the second conductive film 408b is formed of Al-Sc, the present invention is not particularly limited thereto. The second conductive film 408b may be formed of a conductive layer made of Al or an alloy or compound containing Al as a main component. Although the third conductive film 408c is made of TiN, the third conductive film 408c is not particularly limited, and may be formed of a conductive layer made of Ti or an alloy or a compound containing Ti as a main component.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In the first etching process, the first etching condition and the second etching condition are used.
The etching conditions are as follows. (FIG. 8B) In this embodiment, ICP (Inductively Coupled) is used as the first etching condition.
pled Plasma: an inductively coupled plasma) etching method, using BCl ₂ , Cl _2, and O _{2 as} an etching gas as an etching gas, and using a gas flow ratio of 65: 1.
At 0: 5 (sccm), an RF (13.56 MHz) power of 450 W is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching. 300W RF (13.56MHz) power is also applied to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. The Al—Sc film and the TiN film are etched under the first etching condition to make the end portions of the second and third conductive layers tapered. Further, the taper angle of the Al—Sc film and the TiN film becomes about 45 ° under the first etching condition, but the WN film is hardly etched.

Thereafter, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ , Cl _2, and O ₂ were used as etching gases, and the respective gas flow ratios were 25:25:30 (sccm).
500W RF (13.56M) on coil type electrode at pressure of Pa
Hz) Apply power and generate plasma to perform etching. 20W RF (13.56M) on the substrate side (sample stage)
Hz) Apply power and apply a substantially negative self-bias voltage. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
Due to the effect of the bias voltage applied to the substrate side, the end portions of the first to third conductive layers are tapered. The angle of the tapered portion is 15 to 45 °. Thus, the first shape conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layer 417) each including the first conductive layer, the second conductive layer, and the third conductive layer are formed by the first etching process. Conductive layer 417b
To 422b and the third conductive layers 417c to 422c). Reference numeral 416 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 417 to 422 is etched to a thickness of about 20 to 50 nm to form a thinned region.

Next, a second etching process is performed without removing the resist mask. (FIG. 8C) Here, BCl ₃ and Cl ₂ are used as the etching gas, and the respective gas flow ratios are set to 20:60 (sccm).
At a pressure of 2 Pa, a 600 W RF (13.56
MHz), power was supplied to generate plasma, and etching was performed. 100W RF (1) on the substrate side (sample stage)
3.56MHz) Power is applied and a substantially negative self-bias voltage is applied. In the second etching process, Al—Sc
The film and the TiN film are selectively etched. At this time, the second conductive layer 428b is formed by the second etching process.
To 433b and the third conductive layers 428c to 433c. On the other hand, the first conductive layers 417a to 422a are hardly etched, and the second shape conductive layers 428 to 422a are not etched.
433 are formed.

As described above, by the first etching step and the second etching step, the gate electrodes 428 to 431 utilizing the structure of the present invention and the one electrode 432 of the storage capacitor are used.
And source wiring 433 are formed.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer at a low concentration. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ^{13 to} 5
X 10 < ¹⁴ > / cm < ² > and an acceleration voltage of 40 to 80 keV. In this embodiment, the dose is set to 1.5 × 10 ¹³ / cm
² and the acceleration voltage is 60 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, conductive layers 428 to 433 serve as a mask for the impurity element imparting n-type, and impurity regions 423 to 427 are formed in a self-aligned manner. 1 × 10 ¹⁸ to 1 × 10 ²⁰ / c in impurity regions 423 to 427
An impurity element imparting n-type is added in a concentration range of m ³ .

After removing the resist mask, masks 434a to 434c are newly formed, and the second doping process is performed at an acceleration voltage higher than that of the first doping process. The condition of the ion doping method is that the dose is 1 × 10 ¹³ to 1 × 10 ¹⁵ / cm ² and the acceleration voltage is 60 to 120 keV. Doping process is second
The conductive layers 428b to 432b are used as a mask for the impurity element, and the semiconductor layer below the tapered portion of the first conductive layer is doped so that the impurity element is added.
Subsequently, a third doping process is performed by lowering the acceleration voltage from the second doping process to obtain the state in FIG.
The condition of the ion doping method is that the dose is 1 × 10 ¹⁵ to 1 × 1.
0 ¹⁷ / cm ² and an acceleration voltage of 50 to 100 keV. By the second doping process and the third doping process, the low-concentration impurity region 43 overlapping the first conductive layer
1 × 10 ^{18 to} 5 × 10 ¹⁹ / cm for 6, 442 and 448
An impurity element imparting n-type is added in a concentration range of ³ ,
The high-concentration impurity regions 435, 441, 444, and 447 are doped with an impurity element imparting n-type in a concentration range of 1 × 10 ^{19 to} 5 × 10 ²¹ / cm ³ .

Of course, by setting an appropriate acceleration voltage,
The second doping process and the third doping process are 1
It is also possible to form a low concentration impurity region and a high concentration impurity region by a single doping process.

Next, after removing the mask made of resist, masks 450a to 450a made of resist are newly added.
After forming c, a fourth doping process is performed. By this fourth doping process, the impurity regions 453, 454, and 44 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer serving as an active layer of a p-channel TFT.
59 and 460 are formed. Second conductive layers 428a-428
Using 2a as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. In this embodiment, the impurity regions 453, 454,
459 and 460 are formed by an ion doping method using diborane (B ₂ H ₆ ). (FIG. 9B) In the fourth doping process, the semiconductor layers forming the n-channel TFT are covered with masks 450a to 450c made of resist. Doping processing of the first to third, but the impurity regions 438 and 439 are doped with phosphorus in different concentrations, respectively, the concentration of 1 × 10 ¹⁹ impurity element imparting p-type well in that any region 5 × 10 ²¹ at
By doping to oms / cm ³
There is no problem because it functions as the source and drain regions of the p-channel TFT.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

Next, a mask 450a made of resist is used.
To 450c are removed to form a first interlayer insulating film 461. As the first interlayer insulating film 461, plasma C
Using a VD method or a sputtering method, a thickness of 100 to 200
The insulating film containing silicon is formed as nm. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 461 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 9C, a laser beam is irradiated to recover the crystallinity of the semiconductor layers and activate the impurity elements added to the respective semiconductor layers. The laser used is preferably a continuous wave or pulsed solid laser, gas laser or metal laser.
Particularly, it is preferable to perform a laser annealing method using a YAG laser. If a continuous wave laser is used, the energy density of the laser beam is 0.01 to 100 MW / cm ^2.
(Preferably 0.01 to 10 MW / cm ² ), and the substrate is relatively moved to the laser beam by 0.5 to 20 MW / cm ^2.
Move at a speed of 00 cm / s. If a pulsed laser is used, it is desirable that the frequency be 300 Hz and the laser energy density be 50 to 900 mJ / cm ² (typically 50 to 500 mJ / cm ² ). At this time, the laser beams may be overlapped by 50 to 98%. In the case where protrusions such as hillocks and whiskers are not formed even when heat treatment is performed because a region in contact with the first interlayer insulating film in the second conductive layer is sufficiently oxidized, a furnace annealing furnace may be used. , And a rapid thermal annealing method (RTA method).

Further, heat treatment may be performed before forming the first interlayer insulating film. However, when the used wiring is weak to heat, activation is performed after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment. Preferably, a treatment is performed.

Then, a heat treatment (at 300 to 450 ° C. for 1 hour)
熱処理 12 hours), hydrogenation can be performed. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the first interlayer insulating film 461. The semiconductor layer can be hydrogenated regardless of the presence of the first interlayer insulating film. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
Or 300-45 in an atmosphere containing 3-100% hydrogen.
Heat treatment at 0 ° C. for 1 to 12 hours may be performed.

Next, a second interlayer insulating film 462a made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm.
m, an acrylic resin film having a viscosity of 10 to 100
0 cp, preferably 40 to 200 cp, and those having irregularities on the surface are used. When the organic resin film is not used, a second interlayer insulating film 462b having a shape as shown in FIG. 21 is formed.

In this embodiment, in order to prevent specular reflection, a second interlayer insulating film having a surface with irregularities is formed to form irregularities on the surface of the pixel electrode. In addition, a projection may be formed in a region below the pixel electrode in order to obtain light scattering by providing unevenness on the surface of the pixel electrode. In that case, the projection can be formed using the same photomask as that for forming the TFT, and thus can be formed without increasing the number of steps. Note that the protrusions may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, irregularities are formed on the surface of the pixel electrode along irregularities formed on the surface of the insulating film covering the convex portions.

Further, a film whose surface is flattened may be used as second interlayer insulating film 462a. In that case, after forming the pixel electrode, the surface is made uneven by adding a process such as a known sand blasting method or an etching method to prevent specular reflection and increase whiteness by scattering reflected light. Is preferred.

In the drive circuit 506, the wirings 463 to 467 electrically connected to the respective impurity regions, respectively.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a three- or more-layer structure. Also, as the material of the wiring,
Not limited to Al and Ti. For example, Al or C on a TaN film
u may be formed, and a wiring may be formed by patterning the laminated film on which the Ti film is formed. (FIG. 10)

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. The source electrode (433a to 433a to
433c), an electrical connection is formed with the pixel TFT. Further, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 4
In 70, an electrical connection is formed with the drain region 442 of the pixel TFT, and an electrical connection is formed with the semiconductor layer 458 functioning as one electrode forming a storage capacitor. In addition, as the pixel electrode 470, a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof, is preferably used.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
And driving circuit 506 having n-channel TFT 503
And a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the driving circuit 506
Reference numeral 1 denotes a low-concentration impurity region 4 which overlaps with a channel formation region 437 and a first conductive layer 428a which forms part of a gate electrode.
36 (GOLD region), and a high-concentration impurity region 452 functioning as a source region or a drain region.
A p-channel TFT 502 connected to the n-channel TFT 501 with an electrode 466 to form a CMOS circuit includes a channel formation region 440, a high-concentration impurity region 454 functioning as a source region or a drain region, and an impurity element imparting n-type conductivity. And an impurity region 453 into which an impurity element imparting p-type is introduced. The n-channel TFT 503 includes a channel formation region 443, a low-concentration impurity region 442 (GOLD region) overlapping with the first conductive layer 430a which forms part of a gate electrode, and a high-concentration impurity functioning as a source or drain region. Area 4
56.

The pixel TFT 504 in the pixel portion has a channel formation region 446, a low concentration impurity region 445 (LDD region) formed outside the gate electrode, and a high concentration impurity region 458 functioning as a source or drain region. I have. The semiconductor layer functioning as one electrode of the storage capacitor 505 includes an impurity element imparting n-type and p
An impurity element for imparting a mold is added. Storage capacity 5
05 is an electrode (432a) using the insulating film 416 as a dielectric.
To 432c) and a semiconductor layer.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

FIG. 11 is a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. Note that the same reference numerals are used for portions corresponding to FIGS.
A chain line AA ′ in FIG. 10 corresponds to a cross-sectional view cut along a chain line AA ′ in FIG. Also, a chain line B in FIG.
-B 'corresponds to a cross-sectional view taken along a chain line BB' in FIG.

The wiring manufactured in this manner has a reduced resistance, and the wiring board having the wiring can be sufficiently adapted without a problem such as wiring delay even if the pixel area is enlarged. It has become something.

This embodiment can be freely combined with any one of Embodiments 1 to 4.

[Embodiment 6] In this embodiment, a process of manufacturing a reflective liquid crystal display device from the active matrix substrate manufactured in Embodiment 5 will be described below. Figure 12 for explanation
Is used. Although this embodiment does not describe the present invention, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment 5 is used.

First, according to the fifth embodiment, after obtaining the active matrix substrate in the state shown in FIG. 10, an alignment film 567 is formed on the active matrix substrate shown in FIG. Note that in this embodiment, before forming the alignment film 567, a columnar spacer 572 for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. Next, the coloring layers 570 and 571 and the planarizing film 573 are formed over the counter substrate 569. The red coloring layer 570 and the blue coloring layer 571 are overlapped to form a light-shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in the fifth embodiment is used. Therefore, FIG. 1 shows a top view of the pixel portion of the fifth embodiment.
1, at least the gate wiring 469 and the pixel electrode 470
, The gap between the gate wiring 469 and the connection electrode 468, and the gap between the connection electrode 468 and the pixel electrode 470 need to be shielded from light. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gaps between the pixels with the light-shielding portion formed of the colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 576 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 573, an alignment film 574 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are sealed with a sealing material 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 575 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 575. Thus, the reflection type liquid crystal display device shown in FIG. 12 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.
Since the liquid crystal display panel does not lower the aperture ratio and does not cause a problem such as wiring delay in the pixel portion, the liquid crystal display panel can sufficiently cope with an increase in area.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 7] In this embodiment, a process of manufacturing an active matrix liquid crystal display device different from that of Embodiment 6 from the active matrix substrate manufactured in Embodiment 5 will be described below. FIG. 13 is used for the description. Although this embodiment does not describe the present invention, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment 5 is used.

First, according to the fifth embodiment, after obtaining the active matrix substrate in the state shown in FIG. 8, an alignment film 1067 is formed on the active matrix substrate shown in FIG. 8, and a rubbing process is performed. Note that in this embodiment, before forming the alignment film 1067, a columnar spacer for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 1068 is prepared. The opposite substrate is provided with a color filter in which a coloring layer 1074 and a light-shielding layer 1075 are arranged corresponding to each pixel. Further, a light-blocking layer 1077 was provided also in a portion of the driver circuit. A flattening film 1076 covering the color filter and the light-shielding layer 1077 was provided. Next, a counter electrode 1069 made of a transparent conductive film was formed in the pixel portion over the planarization film 1076, an alignment film 1070 was formed over the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with the sealing material 107.
Attach with 1 A filler is mixed in the sealant 1071, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. After that, a liquid crystal material 1073 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Liquid crystal material 107
For 3, a known liquid crystal material may be used. Thus, the active matrix type liquid crystal display device shown in FIG. 11 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. further,
A polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.
Since the liquid crystal display panel does not lower the aperture ratio and does not cause a problem such as wiring delay in the pixel portion, the liquid crystal display panel can sufficiently cope with an increase in area.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 8] In this embodiment, as an example of a wiring board utilizing the present invention, a light emitting device is manufactured by using the method for manufacturing a TFT for manufacturing an active matrix substrate shown in Embodiment 5. An example will be described. Although this embodiment does not describe the present invention, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment 5 is used. In this specification, a light-emitting device refers to a display panel in which a light-emitting element formed over a substrate is sealed between the substrate and a cover member, and an IC mounted on the display panel.
Is a generic term for display modules that implement. Note that the light-emitting element has a layer (light-emitting layer) containing an organic compound capable of obtaining luminescence (Electro Luminescence) generated by applying an electric field, an anode layer, and a cathode layer. In addition, luminescence in an organic compound includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning to a ground state from a triplet excited state.
Emission of one or both of these is included.

In this specification, all layers formed between an anode and a cathode in a light emitting element are defined as organic light emitting layers. The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light-emitting element has a structure in which an anode layer, a light-emitting layer, and a cathode layer are sequentially stacked. In addition to this structure, an anode layer, a hole injection layer, a light-emitting layer, a cathode layer, and an anode layer , A hole injection layer, a light emitting layer, an electron transport layer, a cathode layer, and the like.

FIG. 14 is a sectional view of the light emitting device of this embodiment. In FIG. 14, the switching TFT 603 provided on the substrate 700 is the n-channel TFT 50 of FIG.
3 is formed. Therefore, for the description of the structure, the description of the n-channel TFT 503 may be referred to.

Although the present embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The driving circuit provided on the substrate 700 is shown in FIG.
0 CMOS circuit. Therefore, the description of the structure is made of the n-channel TFT 501 and the p-channel TFT
Reference may be made to the description of 502. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The wirings 701 and 703 function as a source wiring of a CMOS circuit, and the wiring 702 functions as a drain wiring.
The wiring 704 is connected to the source wiring 708 and the switching T
The wiring 705 functions as a wiring for electrically connecting the source region of the FT to the source region.
It functions as a wiring for electrically connecting the drain region of the FT.

Note that the current control TFT 604 corresponds to p
It is formed using a channel type TFT 502. Therefore,
For the description of the structure, the description of the p-channel TFT 502 can be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

A wiring 706 is a source wiring of the current control TFT (corresponding to a current supply line), and 707 is an electrode which is electrically connected to the pixel electrode 711 by being superposed on the pixel electrode 711 of the current control TFT. is there.

Note that reference numeral 711 denotes a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As a transparent conductive film,
A compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used. The pixel electrode 711 is formed by a flat interlayer insulating film 7 before forming the wiring.
10 is formed. In this embodiment, it is very important to flatten the step due to the TFT using the flattening film 710 made of resin. Since a light-emitting layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming it so that the light emitting layer can be formed as flat as possible.

After forming the wirings 701 to 707, a bank 712 is formed as shown in FIG. Bank 712 is 10
The insulating film or the organic resin film containing silicon having a thickness of 0 to 400 nm may be formed by patterning.

Since the bank 712 is an insulating film,
Attention must be paid to electrostatic breakdown of the element during film formation.
In this embodiment, carbon particles or metal particles are added to the insulating film that is a material of the bank 712 to lower the resistivity and suppress generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of the carbon particles and the metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

The light emitting layer 713 is formed on the pixel electrode 711. Although only one pixel is shown in FIG. 14, in this embodiment, light emitting layers corresponding to each of R (red), G (green), and B (blue) are separately formed. In this embodiment, the low molecular weight organic light emitting material is formed by a vapor deposition method.
Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a light emitting layer is formed on the copper phthalocyanine film.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of the organic light emitting material that can be used as the light emitting layer, and it is not necessary to limit the present invention to this. A light-emitting layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer has been described, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. Note that in this specification, an organic light-emitting material having no sublimability and having a molecular number of 20 or less or a chain of molecules having a length of 10 μm or less is defined as a medium-molecular-weight organic light-emitting material. As an example of using a high molecular weight organic light emitting material, a hole injection layer having a thickness of 20 nm is used.
A polythiophene (PEDOT) film may be provided by a spin coating method, and a paraphenylene vinylene (PPV) film having a thickness of about 100 nm may be provided thereon as a light emitting layer. When a π-conjugated polymer of PPV is used, the emission wavelength can be selected from red to blue. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic light emitting materials and inorganic materials.

Next, a cathode 714 made of a conductive film is provided on the light emitting layer 713. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

The light emitting element 715 is completed when the cathode 714 is formed. The light emitting element 71 here
Reference numeral 5 denotes a diode formed by the pixel electrode (anode) 711, the light emitting layer 713, and the cathode 714.

It is effective to provide the passivation film 716 so as to completely cover the light emitting element 715. As the passivation film 716, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used in a single layer or in a stacked layer.

At this time, a film having good coverage is preferably used as a passivation film, and a carbon film, particularly, a D film is preferably used.
It is effective to use an LC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed above the light-emitting layer 713 having low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the light-emitting layer 713
Can be suppressed. Therefore, the problem that the light emitting layer 713 is oxidized during the subsequent sealing step can be prevented.

Furthermore, a sealing material 717 is provided on the passivation film 716, and a cover material 718 is attached. As the sealing material 717, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 718 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

Thus, a light emitting device having a structure as shown in FIG. 14 is completed. Note that it is effective to continuously process the steps from the formation of the bank 712 to the formation of the passivation film 716 without exposing to the atmosphere using a multi-chamber (or in-line) film forming apparatus. . Further, by further developing, it is also possible to continuously perform processing up to the step of bonding the cover material 718 without releasing to the atmosphere.

Thus, the n-channel type T
FTs 601 and 602, a switching TFT (n-channel TFT) 603, and a current control TFT (n-channel TFT) 604 are formed.

Further, as described with reference to FIG.
By providing an impurity region overlapping the gate electrode with an insulating film interposed therebetween, n is resistant to deterioration caused by the hot carrier effect.
A channel type TFT can be formed. for that reason,
A highly reliable light-emitting device can be realized.

In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other components such as a signal dividing circuit, a D / A converter, an operational amplifier, and a γ correction circuit are also provided. Can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, the light emitting device of this embodiment after performing a sealing (or enclosing) step for protecting the light emitting element will be described with reference to FIG. Note that the reference numerals used in FIG.

FIG. 15A is a top view showing a state in which the light emitting element has been sealed, and FIG. 15B is a cross-sectional view of FIG. 15A taken along the line CC ′. 80 shown by dotted line
Reference numeral 1 denotes a source side driving circuit, 806 denotes a pixel portion, and 807 denotes a gate side driving circuit. Reference numeral 901 denotes a cover material;
Denotes a first sealant, 903 denotes a second sealant, and a sealant 907 is provided inside the first sealant 902.

Reference numeral 904 denotes a wiring for transmitting signals input to the source-side drive circuit 801 and the gate-side drive circuit 807, and a video signal or a clock signal from an FPC (flexible print circuit) 905 serving as an external input terminal. Receive. Although only the FPC is shown here, this FPC has a printed wiring board (P
WB) may be attached. The light emitting device in this specification includes not only the light emitting device body but also an FPC
Alternatively, this also includes a state where the PWB is attached.

Next, the cross-sectional structure will be described with reference to FIG. A pixel portion 806 and a gate driver circuit 807 are formed above the substrate 700.
Is formed by a plurality of pixels including a current control TFT 604 and a pixel electrode 710 electrically connected to its drain. The gate side drive circuit 807 is an n-channel type TF
It is formed using a CMOS circuit (see FIG. 14) in which T601 and p-channel TFT 602 are combined.

The pixel electrode 711 functions as an anode of a light emitting element. Further, banks 712 are provided at both ends of the pixel electrode 711.
Are formed, and a light-emitting layer 713 and a cathode 714 of a light-emitting element are formed over the pixel electrode 711.

The cathode 714 also functions as a common wiring for all pixels, and is electrically connected to the FPC 905 via the connection wiring 904. Further, the elements included in the pixel portion 806 and the gate side driver circuit 807 are all covered with the cathode 714 and the passivation film 716.

The cover member 901 is attached by the first seal member 902. Note that a spacer made of a resin film may be provided to secure an interval between the cover member 901 and the light emitting element. The inside of the first sealant 902 is filled with a sealant 907. Note that an epoxy resin is preferably used for the first sealant 902 and the sealant 907. Further, it is desirable that the first sealant 902 be a material that does not transmit moisture and oxygen as much as possible. Further, a substance having a moisture absorbing effect or a substance having an antioxidant effect may be contained in the sealing material 907.

[0167] The sealing material 907 provided so as to cover the light-emitting element also functions as an adhesive for bonding the cover material 901. In this embodiment, FRP (Fibergla) is used as the material of the plastic substrate forming the cover member 901.
ss-Reinforced Plastics), PVF (polyvinyl fluoride), mylar, polyester or acrylic can be used.

[0168] The sealing material 907 is used to cover the cover 90.
After bonding, the second sealing material 903 is provided so as to cover the side surface (exposed surface) of the sealing material 907. Second sealing material 90
For 3, the same material as the first sealant 902 can be used.

With the above structure, the light emitting element is sealed with the sealing material 90.
By encapsulating the light-emitting element in the light-emitting element 7, the light-emitting element can be completely shut off from the outside, and a substance such as moisture or oxygen, which promotes deterioration of the light-emitting layer due to oxidation, can be prevented from entering from the outside. Therefore, a highly reliable light emitting device can be obtained. In addition, the light-emitting device can sufficiently cope with an increase in area because the aperture ratio does not decrease in the pixel portion and no problem such as wiring delay occurs.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 9] In this embodiment, a light emitting device having a pixel structure different from that of Embodiment 8 will be described. FIG. 16 is used for the description. Although the present invention is not described in this embodiment, a TFT having a wiring formed by applying the present invention is used.
Therefore, it can be said that the present invention is applied.

In FIG. 16, a TF having the same structure as the p-channel TFT 502 of FIG.
T as switching TFT 4402 in FIG.
The TFT having the same structure as the pixel TFT 504 is used. Of course, the gate electrode of the current controlling TFT 4501 is electrically connected to the drain wiring of the switching TFT 4402. Further, the drain wiring of the current controlling TFT is electrically connected to the pixel electrode 4504.

In this embodiment, the pixel electrode 4 made of a conductive film is used.
504 functions as a cathode of the light emitting element. In particular,
Although an alloy film of aluminum and lithium is used, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

On the pixel electrode 4504, a light emitting layer 4505 is provided.
Is formed. Although only one pixel is shown in FIG. 16, a light emitting layer corresponding to G (green) is formed by a vapor deposition method and a coating method (preferably a spin coating method) in this embodiment. Specifically, 20n is used as the electron injection layer.
It has a laminated structure in which a m-thick lithium fluoride (LiF) film is provided, and a 70-nm-thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

Next, an anode 4506 made of a transparent conductive film is provided on the light emitting layer 4505. In the case of this embodiment,
As the transparent conductive film, a conductive film including a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used.

When the anode 4506 is formed, the light emitting element 4507 is completed. Note that the light-emitting element 4507 here includes a pixel electrode (cathode) 4504 and a light-emitting layer 450.
5 and a diode formed by the anode 4506.

It is effective to provide the passivation film 4508 so as to completely cover the light emitting element 4507. As the passivation film 4508, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a stacked layer.

Further, a sealing material 4509 is provided on the passivation film 4508, and a cover material 4510 is attached. As the sealing material 4509, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 4510 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

The resistance of the wiring of the light emitting device manufactured in this manner can be reduced.
Since problems such as wiring delay do not occur without lowering the aperture ratio, it is possible to sufficiently cope with an increase in area.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 10] In this embodiment, an example in which a liquid crystal display device is manufactured by using the present invention will be described, taking an example in which the TFT structure is different from that of the active matrix substrate manufactured in Embodiment 5. Although there is no description of the present invention in this embodiment, it can be said that the present invention is applied since the TFT is manufactured using a TFT having a wiring formed by applying the present invention.

The active matrix substrate shown in FIG. 18A has an n-channel TFT 503 and a p-channel TF
A driving circuit 506 having T502 and a pixel TFT 504;
And a pixel portion 507 having a storage capacitor 505 are formed.

In these TFTs, after a gate wiring 512 to 517 is formed on a substrate 510, an insulating film 511 is formed on the gate wiring, and a channel forming region, a source region, a drain region, and a semiconductor layer on the insulating film are formed. It is formed by providing an LDD region and the like. The semiconductor layers are the same as those of the first to fifth embodiments.
It is formed using the present invention in the same manner as described above.

The gate wirings 512 to 517 are formed to have a thickness of 200 to 400 nm, preferably 250 nm. It is formed so as to have a tapered shape. The angle of the tapered portion is 5 to 30 degrees, preferably 15 to 25 degrees. The tapered portion is formed by a dry etching method, and its angle is controlled by an etching gas and a bias voltage applied to the substrate side.

[0185] The impurity regions are formed by the first to third doping steps. First, a first doping step is performed to form an LDD (Lightly
Doped drain) region is formed. The doping may be performed by an ion doping method or an ion implantation method. Phosphorus (P) is added as an impurity element (donor) for imparting n-type, and a first impurity region is formed using a mask. Then, a mask is newly formed to cover the LDD region of the n-channel TFT, and the second doping step is performed by forming a source region and a drain region of the n-channel TFT.

By the third doping process, the source region and the drain region of the p-channel type TFT are formed. As a doping method, an impurity element (acceptor) for imparting a p-type may be added by ion doping or ion implantation. At this time, since a mask is formed on the semiconductor layer forming the n-channel TFT, an impurity element imparting p-type conductivity is not added. In this embodiment, the LDD region is not formed in the p-channel TFT, but may be formed.

In this manner, the n-channel TFT 50
3 has an LDD region 53 outside the channel formation region 529.
0, a source region or a drain region 531 is formed. The p-channel TFT 502 has the same configuration, and includes a channel formation region 527, a source region or a drain region 5,
Consists of 28. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

In the pixel portion 507, an n-channel type TF
A pixel TFT 504 formed of T has a multi-gate structure for the purpose of reducing off-state current. An LDD region 533 and a source or drain region 534 are provided outside a channel formation region 532.

The interlayer insulating film is made of an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.
And a second interlayer insulating film 5 made of an organic insulating material such as polyimide, acrylic, polyimide amide, or BCB (benzocyclobutene).
41. As described above, by forming the second interlayer insulating film with the organic insulating material, the surface can be satisfactorily planarized. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, it is hygroscopic and is not suitable as a protective film.
Is preferably formed in combination with the interlayer insulating film 540.

Thereafter, a resist mask having a predetermined pattern is formed, and a contact hole reaching a source region or a drain region formed in each semiconductor layer is formed. The formation of the contact hole is performed by a dry etching method. In this case, CF ₄ , O ₂ , He is used as an etching gas.
First, the second interlayer insulating film 541 made of an organic resin material is etched using a mixed gas of, and then, the first interlayer insulating film 540 is etched using CF ₄ and O ₂ as etching gases.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, and a resist mask pattern is formed.
Wirings 543 to 549 are formed by etching. Thus, an active matrix substrate can be formed.

A process for manufacturing an active matrix type liquid crystal display device using the active matrix substrate shown in FIG. FIG. 18B illustrates a state where the active matrix substrate and the counter substrate 554 are attached to each other with a sealant 558. First, the columnar spacer 55 is formed on the active matrix substrate in the state shown in FIG.
1, 552 are formed. Spacer 551 provided in pixel portion
Is provided so as to overlap the contact portion on the pixel electrode. The spacer has a height of 3 to 10 μm, although it depends on the liquid crystal material used. In the contact portion, a concave portion corresponding to the contact hole is formed. By forming a spacer in accordance with this portion, it is possible to prevent the alignment of the liquid crystal from being disordered. After that, an alignment film 553 is formed and a rubbing process is performed. The transparent conductive film 555 and the alignment film 55
6 is formed. After that, the active matrix substrate and the opposite substrate are bonded to each other, and the liquid crystal 557 is injected.

The active matrix type liquid crystal display device manufactured as described above can be used as a display device of various electronic devices. Since the liquid crystal display panel does not lower the aperture ratio and does not cause a problem such as wiring delay in the pixel portion, the liquid crystal display panel can sufficiently cope with an increase in area.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 11] In this embodiment, Embodiment 10 will be described.
An example in which a light-emitting device is manufactured using the active matrix substrate shown in FIG. Although this embodiment does not describe the present invention, it can be said that the present invention is applied because the active matrix substrate manufactured in Embodiment 10 is used.

In FIG. 19, a TF having the same structure as the n-channel TFT 503 of FIG.
Use T. Of course, the gate electrode of the current controlling TFT 4501 is electrically connected to the drain wiring of the switching TFT 4402. In addition, the current control TFT 45
01 is electrically connected to the pixel electrode 4504.

In this embodiment, the pixel electrode 4 made of a conductive film is used.
504 functions as a cathode of the light emitting element. In particular,
Although an alloy film of aluminum and lithium is used, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

A light emitting layer 4505 is provided on the pixel electrode 4504.
Is formed. Although only one pixel is shown in FIG. 19, in this embodiment, a light emitting layer corresponding to G (green) is formed by a vapor deposition method and a coating method (preferably a spin coating method). Specifically, 20n is used as the electron injection layer.
It has a laminated structure in which a m-thick lithium fluoride (LiF) film is provided, and a 70-nm-thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

Next, an anode 4506 made of a transparent conductive film is provided on the light emitting layer 4505. In the case of this embodiment,
As the transparent conductive film, a conductive film including a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used.

The light emitting element 4507 is completed when the anode 4506 is formed. Note that the light-emitting element 4507 here includes a pixel electrode (cathode) 4504 and a light-emitting layer 450.
5 and a diode formed by the anode 4506.

It is effective to provide the passivation film 4508 so as to completely cover the light emitting element 4507. As the passivation film 4508, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating film is used as a single layer or a stacked layer.

Further, a sealing material 4509 is provided on the passivation film 4508, and a cover material 4510 is attached. As the sealing material 4509, an ultraviolet curable resin may be used, and it is effective to provide a substance having a moisture absorbing effect or a substance having an antioxidant effect inside. In this embodiment, a cover material 4510 having a carbon film (preferably a diamond-like carbon film) formed on both surfaces of a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) is used.

The light emitting device manufactured in this manner can sufficiently cope with an increase in the area because the aperture ratio does not decrease in the pixel portion and no problem such as wiring delay occurs. It has become.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 12] By applying the present invention, a wiring board formed by carrying out the present invention can be applied to various electro-optical devices (active matrix type liquid crystal display device, active matrix type EC display device, active matrix type Light-emitting device). That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

As such electronic equipment, there are a personal computer, a display, and the like. Examples of those are shown in FIG.

FIG. 20A shows a personal computer, which includes a main body 3001, an image input section 3002, and a display section 30.
03, a keyboard 3004 and the like. Display unit 3 of the present invention
003 can be applied. By applying the present invention,
It is possible to cope with an increase in the area of the display portion 3003.

FIG. 20B shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 3401, a display portion 3402, and a speaker portion 340.
3, a recording medium 3404, an operation switch 3405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games and the Internet. The present invention can be applied to the display portion 3402. If the present invention is applied, the display unit 340
2 can correspond to an increase in area.

FIG. 20C shows a display, which includes a main body 4101, a support 4102, a display portion 4103, and the like.
The present invention can be applied to the display portion 4103. The display of the present invention has a configuration that can sufficiently cope with a particularly large screen. It is particularly advantageous for a display having a diagonal of 10 inches or more (especially 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 11.

[0211]

According to the present invention, the following significance can be obtained. (A) It is a simple method that is compatible with a conventional wiring or wiring board manufacturing process. (B) Low resistance of the wiring can be realized. Therefore, the degree of freedom in design and the aperture ratio in the pixel portion can be improved. (C) Good coverage can be achieved. (D) After satisfying the above advantages, in a semiconductor device represented by an active matrix type liquid crystal display device,
It is possible to sufficiently cope with an increase in the area of the pixel portion and an increase in the screen size, and to improve the operation characteristics and reliability of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of the concept of the present invention.

FIG. 2 is a diagram showing an example of the shape of a wiring manufactured by applying the present invention.

FIG. 3 is a diagram showing a schematic view of a shape of a wiring manufactured by applying the present invention.

FIG. 4 is a diagram showing an example of the shape of a wiring manufactured by applying the present invention.

FIG. 5 is a diagram showing an example of the shape of a wiring manufactured by applying the present invention.

FIG. 6 is a diagram showing an example of the shape of a wiring manufactured by applying the present invention.

FIG. 7 is a diagram showing an example of the concept of the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 11 is a top view illustrating a configuration of a pixel TFT.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 14 is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.

FIG. 15A is a top view of a light-emitting device. FIG. 2B is a cross-sectional structural view of a driving circuit and a pixel portion of a light-emitting device.

FIG. 16 is a cross-sectional structure diagram of a driving circuit and a pixel portion of a light-emitting device.

FIG. 17 is a diagram showing an example of the concept of the present invention.

FIG. 18 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 19 is a cross-sectional structure diagram of a pixel portion of a light-emitting device.

FIG. 20 illustrates an example of a semiconductor device.

FIG. 21 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 22 illustrates an example of a shape of a conductive layer formed under first etching conditions.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/786 H01L 29/78 617K 617L 617J (72) Inventor Yoshihiro Kusuyama 398 Hase, Atsugi City, Kanagawa Prefecture, Inc. Semiconductor Energy Laboratory

Claims (29)

[Claims] The first conductive layer having a first width is a first layer, the second conductive layer having a second width smaller than the first width is a second layer, and the second conductive layer is a second layer. A stacked structure including a third conductive layer having a third width smaller than the width as a third layer, and a cross section at an end of the first conductive layer, the second conductive layer, or the third conductive layer. The wiring is characterized by a tapered shape. 2. The first conductive layer according to claim 1, wherein the first conductive layer contains one or more elements selected from W or Mo, or one or more elements selected from W or Mo as a main component. A conductive layer made of an alloy or a compound described above. 3. The wiring according to claim 1, wherein the second conductive layer is a conductive layer made of an alloy or a compound containing Al as a main component. 4. The wiring according to claim 1, wherein the third conductive layer is a conductive layer made of an alloy or a compound containing Ti as a main component. 5. The semiconductor device according to claim 1, wherein the second conductive layer is covered with the first conductive layer, the third conductive layer, and an insulating film. A wiring in which a contacting region is oxidized. 6. The wiring according to claim 1, wherein the wiring is a wiring of a liquid crystal display device or a light emitting device. 7. A conductive layer having a first shape formed of a stack of a first conductive layer, a second conductive layer, and a third conductive layer is formed on an insulating surface; Etching the second conductive layer and the third conductive layer to form a first conductive layer having a first width, a second conductive layer having a second width, and a third width; Forming a conductive layer of a second shape formed of a laminate with a third conductive layer having a second conductive layer having a second width; and a third conductive layer having a third width. By etching, a third shape including a stack of a first conductive layer having a fourth width, a second conductive layer having a fifth width, and a third conductive layer having a sixth width A method for manufacturing a wiring for forming a conductive layer of
A first conductive layer having the fourth width, a second conductive layer having the fifth width, or a third conductive layer having the sixth width.
Wherein the cross-sectional shape at the end of the conductive layer is tapered. 8. A conductive layer having a first shape formed by laminating a first conductive layer, a second conductive layer, and a third conductive layer on an insulating surface, wherein the second conductive layer And etching the third conductive layer to form a first conductive layer, a second conductive layer having a first width, and a third conductive layer having a second width. A first conductive layer having a third width, a second conductive layer having the first width, and a first conductive layer having a third width. Forming a third shape conductive layer formed of a laminate with a third conductive layer having a width of 2; a second conductive layer having the first width; and a third conductive layer having the second width. Etching the layer, a first conductive layer having a fourth width, a second conductive layer having a fifth width,
A method for manufacturing a wiring for forming a fourth-shaped conductive layer formed by laminating a third conductive layer having a sixth width, wherein the first conductive layer having the fourth width or the fifth conductive layer is formed. A cross-sectional shape at an end of the second conductive layer having a width of or the third conductive layer having a width of ６ is a tapered shape. 9. A first conductive layer having a first shape formed by stacking a first conductive layer, a second conductive layer, and a third conductive layer on an insulating surface; Etching the second conductive layer and the third conductive layer to form a first conductive layer having a first width, a second conductive layer having a second width, and a third width; Forming a conductive layer of a second shape formed of a laminate with a third conductive layer having a second conductive layer having a second width; and a third conductive layer having a third width. By etching, a third shape including a stack of a first conductive layer having a fourth width, a second conductive layer having a fifth width, and a third conductive layer having a sixth width Forming a conductive layer of the third shape, and performing a plasma treatment on the conductive layer of the third shape, wherein the first conductive layer having the fourth width or the fifth width Third with the second conductive layer or the sixth width with
Wherein the cross-sectional shape at the end of the conductive layer is tapered. 10. A first conductive layer and a second conductive layer on an insulating surface.
A conductive layer having a first shape formed by laminating a third conductive layer and a third conductive layer; etching the second conductive layer and the third conductive layer to form the first conductive layer; Forming a second shape conductive layer composed of a stack of a second conductive layer having a first width and a third conductive layer having a second width; and etching the first conductive layer. And a third shape formed by laminating a first conductive layer having a third width, a second conductive layer having the first width, and a third conductive layer having the second width. A second conductive layer having the first width and a third conductive layer having the second width are etched to form a first conductive layer having a fourth width; A second conductive layer having a fifth width,
A method for manufacturing a wiring in which a fourth-shaped conductive layer formed of a laminate with a third conductive layer having a sixth width is formed, and plasma processing is performed on the fourth-shaped conductive layer, A first conductive layer having a width of 4 or a second conductive layer having a width of 5
A cross-sectional shape at an end of the conductive layer or the third conductive layer having the sixth width is a tapered shape. 11. The method according to claim 7, wherein the first conductive layer is one or more elements selected from W or Mo, or one or more elements selected from W or Mo. A method for manufacturing a wiring, which is a conductive layer including an alloy or a compound containing a plurality of elements as main components. 12. The method for manufacturing a wiring according to claim 7, wherein the second conductive layer is a conductive layer made of an alloy or a compound containing Al as a main component. 13. The method for manufacturing a wiring according to claim 7, wherein the third conductive layer is a conductive layer made of an alloy or a compound containing Ti as a main component. 14. The method according to claim 9, wherein
The method for manufacturing a wiring, wherein the plasma treatment is performed using oxygen, a gas containing oxygen as a main component, or H ₂ O. 15. A wiring board having an insulating substrate and a wiring, wherein the wiring has a first conductive layer having a first width as a first layer, and a second width smaller than the first width. A second conductive layer having a second layer, and a third conductive layer having a third width smaller than the second width.
And a third conductive layer having a width of 3 mm as a third layer, and a cross-sectional shape at an end of the first conductive layer, the second conductive layer, or the third conductive layer is a tapered shape. A wiring board, characterized in that: 16. The first conductive layer according to claim 15, wherein the first conductive layer contains one or more elements selected from W or Mo, or one or more elements selected from W or Mo as a main component. A wiring substrate, which is an alloy material or a compound material. 17. The wiring substrate according to claim 15, wherein the second conductive layer is made of an alloy material or a compound material containing Al as a main component. 18. The wiring board according to claim 15, wherein the third conductive layer is made of an alloy material or a compound material containing Ti as a main component. 19. The semiconductor device according to claim 15, wherein the second conductive layer is covered with the first conductive layer, the third conductive layer, and an insulating film. A wiring substrate, wherein a contacting region is oxidized. 20. The wiring substrate according to claim 15, wherein a liquid crystal display device or a light emitting device is manufactured using the wiring substrate. 21. A first conductive layer and a second conductive layer on an insulating surface.
A conductive layer having a first shape formed by laminating a third conductive layer, and etching the first conductive layer, the second conductive layer, and the third conductive layer, A conductive layer having a second shape, which is formed by stacking a first conductive layer having a first width, a second conductive layer having a second width, and a third conductive layer having a third width, Forming, etching the second conductive layer having the second width and the third conductive layer having the third width to form a first conductive layer having a fourth width; A method of manufacturing a wiring board for forming a conductive layer having a third shape, which is formed by laminating a second conductive layer having a width of 6 mm and a third conductive layer having a width of 6 mm; The cross-sectional shape at the end of the first conductive layer having a width, the second conductive layer having the fifth width, or the third conductive layer having the sixth width is as follows. The method for manufacturing a wiring substrate, which is a tapered shape. 22. A first conductive layer and a second conductive layer on an insulating surface.
A conductive layer having a first shape formed by laminating a third conductive layer and a second conductive layer; etching the second conductive layer and the third conductive layer to form the first conductive layer; Forming a second shape conductive layer composed of a laminate of a second conductive layer having a first width and a third conductive layer having a second width; and etching the first conductive layer. And a third shape comprising a stack of a first conductive layer having a third width, a second conductive layer having the first width, and a third conductive layer having the second width. A second conductive layer having the first width and a third conductive layer having the second width are etched to form a first conductive layer having a fourth width; A second conductive layer having a fifth width,
A method for manufacturing a wiring board for forming a fourth-shaped conductive layer comprising a laminate with a third conductive layer having a sixth width, wherein the first conductive layer having the fourth width; A method for manufacturing a wiring substrate, wherein a cross-sectional shape of an end of a second conductive layer having a fifth width or a third conductive layer having a sixth width is tapered. 23. forming a first conductive layer on the insulating surface;
Forming a second conductive layer on the first conductive film;
Forming a third conductive layer on the conductive film of
Etching the conductive layer to form a conductive layer having a tapered portion, and performing plasma processing on the conductive layer having the tapered portion. 24. A semiconductor device comprising: a first conductive layer on an insulating surface;
A conductive layer having a first shape formed of a stack of a third conductive layer and a third conductive layer, and etching the first conductive layer, the second conductive layer, and the third conductive layer, A conductive layer having a second shape, which is formed by stacking a first conductive layer having a first width, a second conductive layer having a second width, and a third conductive layer having a third width, Forming, etching the second conductive layer having the second width and the third conductive layer having the third width to form a first conductive layer having a fourth width; Forming a third-shape conductive layer comprising a laminate of a second conductive layer having a width of 6 mm and a third conductive layer having a sixth width, and subjecting the third-shape conductive layer to plasma treatment A method of manufacturing a wiring board, wherein the first conductive layer having the fourth width, the second conductive layer having the fifth width, or the sixth width is formed. The method for manufacturing a wiring substrate, wherein a cross-sectional shape of the end portion of the third conductive layer has a tapered shape. 25. A first conductive layer and a second conductive layer on an insulating surface.
A conductive layer having a first shape formed by laminating a third conductive layer and a second conductive layer; etching the second conductive layer and the third conductive layer to form the first conductive layer; Forming a second shape conductive layer composed of a laminate of a second conductive layer having a first width and a third conductive layer having a second width; and etching the first conductive layer. And a third shape formed by laminating a first conductive layer having a third width, a second conductive layer having the first width, and a third conductive layer having the second width. A second conductive layer having the first width and a third conductive layer having the second width are etched to form a first conductive layer having a fourth width; A second conductive layer having a fifth width,
A method of manufacturing a wiring substrate, comprising: forming a fourth shape conductive layer formed by laminating a third conductive layer having a sixth width; and performing a plasma treatment on the fourth shape conductive layer, The cross-sectional shape at the end of the first conductive layer having the fourth width, the second conductive layer having the fifth width, or the third conductive layer having the sixth width is tapered. A method for manufacturing a wiring substrate. 26. The method according to claim 21, wherein the first conductive layer is one or more elements selected from W or Mo, or one or a plurality of elements selected from W or Mo. A method for manufacturing a wiring board, which is an alloy material or a compound material containing a plurality of elements as main components. 27. The method for manufacturing a wiring board according to claim 21, wherein the second conductive layer is an alloy material or a compound material containing Al as a main component. 28. The method for manufacturing a wiring substrate according to claim 21, wherein the third conductive layer is an alloy material or a compound material containing Ti as a main component. 29. The method for manufacturing a wiring substrate according to claim 23, wherein the plasma treatment is performed using oxygen, a gas containing oxygen as a main component, or H ₂ O. .