JP2002329788A - Variable capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable capacitor which has a stable dielectric constant of a dielectric layer corresponding to the voltage applied from the outside. SOLUTION: This capacitor is formed by connecting each other a plurality of capacitance generating regions a, b comprising dielectric layers 31, 32 which have a variable dielectric constant corresponding to the outside applied voltage and are sandwiched between upper electrode layers 41, 42 and lower electrode layers 21, 22. In a manufacturing method of this capacitor, the lower electrode layers 21, 22 and a lower terminal electrode layer 23 consisting of Ti and Au are formed on a holding substrate consisting of sapphire. Then, as the dielectric layers 31, 32, (BaSr)TiO3 of 1 μm thickness is formed by sputtering. And then, the upper electrode layers 41, 42 and an upper terminal electrode layer 43 consisting of Au are formed, and finally a protection film is formed so as to expose the upper and lower terminal electrode layers 43, 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitor having a dielectric layer whose dielectric constant changes according to a voltage applied between a lower electrode layer and an upper electrode layer.

[0002]

2. Description of the Related Art Conventionally, in the case of a strontium titanate (SrTiO ₃ ) thin film as a paraelectric or a strontium barium titanate (Ba, Sr) TiO ₃ thin film as a ferroelectric, a predetermined voltage is applied to the dielectric thin film. By doing
It is known that a nonlinear change in dielectric constant is observed (A.
Walkenhorst et al., Appl.Phys. Lett. 60 (1992) 1744 and Ce
m Bascri et.al., J. Appl. Phys 82 (1997) 2497).

A thin film capacitor using a ferroelectric oxide thin film having a perovskite structure such as strontium titanate or strontium barium titanate as a dielectric layer has been proposed (Japanese Patent Application Laid-Open No. 11-266667).

In these variable capacitance type thin film capacitors, as shown in the sectional view of FIG.
The lower electrode layer 52, the dielectric layer 53, and the upper electrode layer 54 are sequentially formed. Specifically, after a conductive layer to be the lower electrode layer 52 is formed on the support substrate 51 over substantially the entire surface of the substrate 51, pattern processing is performed to form the lower electrode layer 52 having a predetermined shape. Next, a dielectric film 53 is formed on the lower electrode layer 52. The dielectric film 53 is formed by placing a mask at a predetermined position by a thin film technique, or by forming a dielectric layer by a spin coating method, and then patterning into a predetermined shape. In addition, heat curing is performed as needed. The upper electrode layer 54 is formed on the dielectric film 53 by the upper electrode layer 5.
After forming the conductor layer to be No. 4, pattern processing was performed. Here, in the dielectric layer 53, a facing region actually sandwiched between the lower electrode layer 52 and the upper electrode layer 54 is a capacitance generating region.

Then, the dielectric layer 53 in the capacitance generating region
In addition, the dielectric constant of the dielectric layer 53 changes due to an external control voltage supplied between the lower electrode layer 52 and the upper electrode layer 54.

Accordingly, assuming that the area facing the two electrode layers 52 and 54 and the thickness of the dielectric layer 53 are constant, the capacitance value obtained between the two electrode layers 52 and 54 can be reduced by setting the external control voltage to a predetermined voltage. Can be changed.

In the thin-film capacitor shown in FIG. 5, in order to prevent a short circuit between the lower electrode layer 52 and the upper electrode layer 53, the air bridge 55 extends from the upper electrode layer 53 onto the support substrate 51. It has a structure. That is, when extending from the upper electrode layer 54 onto the support substrate 51, a space is formed around the dielectric layer 53.

This space can be formed by, for example, forming an organic resist member formed by a heat treatment or the like, forming an upper electrode layer 54, and then performing a heat treatment.

[0009]

In such a variable capacitor, the capacitance is changed by the control voltage applied between the lower electrode layer 52 and the upper electrode layer 54.
It is important that this voltage be uniformly applied to the dielectric layer 53.

For example, this external control voltage is 10 to
Although it is 0 V, it is difficult to apply the voltage uniformly to the capacitance generating region, and it is difficult to stabilize the dielectric constant of the dielectric layer 53 to a predetermined value. For example, the opposing area of the capacitance generation region is set in consideration of the maximum capacitance. However, the area of the capacitance generation region in which one capacitance generation region seeks to obtain this capacitance value increases. As a result, the upper electrode layer 54 or A voltage drop of the control voltage in the lower electrode layer 52 occurs. For example, the lower electrode layer 52 and the upper electrode layer 54 have portions 52a and 54 extending from the capacitance generation region.
a has a high potential in a portion close to a, and in a central portion of the capacitance generation region and portions away from the extended portions 52a and 54a,
The potential becomes relatively low. That is, there is a problem that a potential distribution occurs in the same capacitance generation region and a sufficient control of the dielectric constant, that is, a sufficiently wide variable range cannot be obtained. The problem was that the capacity could not be obtained.

In order to structurally prevent a short circuit between the upper electrode layer 54 and the lower electrode layer 52, an air bridge 55 is provided. Due to the existence of this hollow body structure, great restrictions and reliability are imposed upon mounting on a motherboard. It was lacking in sex. In addition, the method of manufacturing the upper electrode layer 54 also uses an organic resist for forming the air bridge 55, so that a manufacturing method different from the thin film technique must be used, and the manufacturing process becomes very complicated.

The present invention has been made in view of the above-described problems, and has as its object to reduce the external control voltage applied to
An object of the present invention is to provide a variable capacitor having a structure that can be uniformly applied to a dielectric layer.

Another object of the present invention is to provide a variable capacitor having a structure suitable for surface mounting, in which the manufacturing process is simplified, the upper electrode layer and the lower electrode layer are hardly structurally short-circuited.

[0014]

According to the present invention, a plurality of capacitance generating regions are formed by sandwiching a dielectric layer whose permittivity changes by applying a voltage between a lower electrode layer and an upper electrode layer. Variable capacitors whose generation regions are connected to each other.

Preferably, the upper electrode layer of one of the adjacent capacitance generating regions is connected to have the same potential as the lower electrode layer of the other capacitance generating region.

Further, the variable capacitor is characterized in that the number of the plurality of capacitance generating regions is an even number.

Further, the variable capacitor has a planar shape of one of the upper electrode layer and the lower electrode layer similar to the planar shape of the capacitance generating region.

According to the present invention, the capacitance generating region sandwiched between the upper electrode layer and the lower electrode layer is divided into a plurality of regions, and the plurality of divided capacitance generating regions are connected to each other.

That is, assuming that the thickness of the dielectric layer is constant and the entire area of the capacitance generating region required to generate a predetermined capacitance is constant, the capacitance generating region is divided into a plurality of regions and these are joined. .

Accordingly, the area of a single divided capacity generating region is reduced. Thereby, the area of the opposing portion of the single upper electrode layer and the lower electrode layer is also reduced. That is, even when a predetermined external control voltage is applied between the plurality of upper electrodes and the lower electrode, the area of each electrode layer is reduced, and the voltage drop caused by the conductor resistance in the plane portion of the electrode is effectively reduced. Can be suppressed.

The plurality of divided capacitance generating regions are electrically connected in parallel to each other, that is, the lower electrodes of the adjacent capacitance generating regions have the same potential (the upper electrodes have the same potential). Can be electrically connected in series with each other, that is, the lower electrodes of the adjacent capacitance generating regions can have different potentials (the upper electrodes have different potentials).

The planar shape of either the upper electrode layer or the lower electrode layer, for example, the lower electrode layer has a similar relationship to the planar shape of the capacitance generating region. The area of the capacitance generating region is determined by the facing area between the upper electrode layer and the lower electrode layer. That is, for example, since the planar shape of the lower electrode is similar to the planar shape of the capacitance generating region, it means that there is a portion where the upper electrode is not formed in the planar shape of the lower electrode layer, and the shape of the lower electrode layer is The shape is larger than the electrode layer. Therefore, even if a displacement occurs in the formation of the two electrode layers, the displacement in the region where the lower electrode layer and the dielectric layer are formed absorbs the displacement, and the capacitance characteristics fluctuate. There is no. This structure
The same applies to the upper electrode layer side as well as the lower electrode layer side.

In each case, the lower electrode layer is formed on the supporting substrate, the dielectric layer is formed on the lower electrode layer or the supporting substrate, and the upper electrode layer is formed on the supporting substrate or the dielectric layer. Since it can be formed by deposition and does not use an air bridge structure as in the prior art, the manufacturing process can be formed using a substantially thin film technique. Furthermore, since the structure does not have a hollow structure in the structure, the structural reliability is improved. For example, the mounting surface is simply and reliably mounted on the motherboard using the upper surface of the support substrate as a mounting surface. be able to.

Further, since the current of the external control voltage is dispersed and passes through a plurality of capacitance generating regions, the parasitic inductance can be reduced. As a result, fo = 1/2
(LC) The self-resonant frequency defined by ^1/2 can be increased, and the frequency region operating as a capacitor can be shifted to a higher frequency side.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable capacitor according to the present invention will be described with reference to the drawings.

FIG. 1 shows a cross section of a variable capacitor according to the present invention, and FIG. 2 is a plan view of a main part.

In the drawing, reference numeral 1 denotes a support substrate,
Reference numeral 22 denotes a lower electrode layer (in FIG. 1, the whole is denoted by reference numeral 2), 23 denotes a lower terminal electrode layer, and 31, 32
1 is a dielectric layer (in FIG. 1, generally denoted by reference numeral 3), 41 and 42 are upper electrode layers (in FIG. 1, generally denoted by reference numeral 4), 5 is a protective layer, and 6. 7 is an external terminal. Note that the capacitance generation region is a portion where the dielectric layer 31 is sandwiched between the lower electrode layer 21 and the upper electrode layer 41, and the dielectric layer 32 is sandwiched between the lower electrode layer 22 and the upper electrode layer 42. This is the facing part. In the figure, there are two capacitance generation areas a and b.

The support substrate 1 may be any substrate as long as it has an insulating property. In particular, Al ₂ O _{3 ,}
Sapphire, glass, MgO, LaAlO ₃ are preferred.

The lower electrode layer 21, 2
2 and a lower terminal electrode layer 23 that connects these lower electrodes 21 and 22 in common. As a whole,
The lower electrode layers 21 and 22 and the lower terminal electrode layer 23 have a comb shape. As the conductor material of the lower electrode layers 21, 22 and the lower terminal electrode layer 23, Au or Cu is suitable, but Al, Ag, or the like can also be applied, and the thickness is 0.1 to 5 μm. For example, if it is smaller than 0.1 μm, the resistance of the electrode itself increases, and at the same time,
The continuity of the electrodes is lost, resulting in poor reliability. On the other hand, when the thickness is 5 μm or more, the step coverage failure (intersection (ridge line portion) with the dielectric layers 31 and 32 described later) causes the dielectric layer 3 to fail.
1 and 32 are exposed), and the upper electrode layer 4 and the lower electrode 2 are short-circuited.

The dielectric layers 31 and 32 are formed by a thin film technique such as sputtering. The thin film technology includes a vacuum deposition and a spin coating method using a sol-gel solution in addition to sputtering.

The material of the dielectric layer 3 has a high dielectric constant.
It is preferable to have
And a dielectric material whose dielectric constant can be changed, for example, BaT
iO _Three, SrTiO_Three, (Ba Sr) TiO_ThreeEtc.
Can be

The dielectric layers 31 and 32 are formed, for example, so as to cover the surfaces of the lower electrode layers 21 and 22. For example, as shown in the figure, the dielectric layers 31 and 32 may be formed exclusively in the respective capacitance generating regions a and b, or as shown in FIG. The dielectric layer 3 may be formed so as to be common to the plurality of capacitance generating areas a and b.

The upper electrode layers 41 and 42 and the upper terminal electrode layer 43 are formed using Au or Cu as a conductor material. In addition, Al, Ag, etc. can also be used. Its thickness is 0.1 to 5 μm. Like the lower electrode layer 2, the lower limit of the thickness is set in consideration of the resistance of the electrode itself. In addition, the upper limit is set so as to prevent the occurrence of peeling due to concentration of adhesion stress with a member existing below at the time of forming the upper electrode layer 3.

In addition, the protective film 5 includes a lower terminal electrode layer 23,
The upper terminal electrode 43 is formed so as to expose a part thereof. As the protective film, SiO ₂ , SiN, BCB (benzocyclobutene), polyimide or the like is preferable. This protective film 5 protects not only mechanical shock from the outside but also
It plays a role in preventing deterioration due to humidity, contamination of chemicals, oxidation and the like.

The external terminals 6 and 7 can be exemplified by solder balls and metal bumps. Specifically, for example, a solder ball is formed on a portion where the lower terminal electrode layer 23 and the upper terminal electrode layer 24 are exposed, or a first bonding of a metal wire is performed, and a predetermined length is cut. A bump such as gold may be formed.

In order to form solder balls as the external terminals 6 and 7, a thin film of Ni or Cr for preventing solder erosion is formed on exposed portions of the lower terminal electrode layer 23 and the upper terminal electrode layer 43. No problem. If it is assumed that soldering is performed only at the time of mounting, a thin film of Ni or Cr for preventing the above-mentioned solder erosion may be used as the external terminal.

In FIG. 2, the variable capacitor according to the present invention comprises two capacitance generating areas a and b.
That is, the capacitance generation region a is composed of a portion in which the lower electrode 21, the dielectric layer 31, and the upper electrode layer 41 are sequentially laminated, and the capacitance generation region b is the lower electrode 22, the dielectric layer 32, and the upper electrode layer 42. And are sequentially laminated. Further, the capacitance generation region a and the capacitance generation region b are connected in parallel with each other. That is, the lower terminal electrode layer 23 extending from the lower electrode layers 21 and 22 is shared with each other. Further, the upper terminal electrode layer 43 extending from the upper electrode layers 41 and 42 is commonly used. Therefore, from the terminal electrodes of the external terminals 6 and 7, a combined capacitance in which the capacitances of the two capacitance generating regions a and b are arranged in parallel can be obtained.

In the present invention, by applying a predetermined potential to the dielectric material of the dielectric layers 31 and 32 by applying an external control voltage,
The dielectric constants of the dielectric layers 31 and 32 can be variably controlled. That is, the dielectric constants of the dielectric layers 31 and 32 in the capacitance generating regions a and b are changed by the external control voltages supplied to the external terminals 6 and 7 described above. At this time, a uniform potential with a small potential distribution of the external control voltage is applied to the two capacitance generating regions a and b. Here, it is important that the area of the capacitance generating region is important to obtain a predetermined capacitance. And in the variable capacitor of the present invention, the capacity generation region is divided into two,
The area of a single capacitance generation region is reduced. That is,
When an external control voltage is applied, the distribution of the potentials applied to the capacitance generating areas a and b in the areas becomes smaller. On the other hand, as in the related art, in the upper electrode layer 54, a relatively high potential is applied to a portion directly connected to the extension 54a of the upper electrode layer 54, but the upper electrode layer 54 is separated from the extension 54a. Due to the conductor resistance 54, a voltage drop occurs near the central portion, and the applied potential decreases. On the other hand, in the present invention, the capacity generation region where the predetermined capacity is obtained is
Divided, divided single capacity generation areas a, b
Is の of the area of the capacitance generating region. Thus, a voltage drop generated in the upper electrode layers 41 and 42 can be reduced, and an external control voltage having a stable and uniform potential can be applied to the dielectric layers 31 and 32. That is, in the variable capacitor, the application of an external voltage can be uniformly applied to the dielectric layers 31 and 32, so that the extremely stable and stable
A capacitance value as designed can be easily obtained, and variable control can be performed as designed.

[0038]

EXAMPLE A variable capacitor shown in FIG. 2 was manufactured. On the sapphire as the support substrate 1, an underlying Ti layer and an upper Au layer were formed as lower electrode layers 21 and 22 by sputtering. The underlying Ti layer enhances the adhesion between the support substrate 1 and the upper Au layer, and has a thickness of Ti = 0.05 μm and Au = 1.
μm. The lower electrode layers 21 and 22 and the lower terminal electrode layer 23 shown in FIG. 2 were formed by photolithography using this base electrode layer. Specifically, a resist was applied in a predetermined shape, and was patterned by wet etching.

Subsequently, as the dielectric layers 31 and 32, (Ba
Sr) TiO ₃ is deposited to a thickness of 1 μm by sputtering, and the dielectric layer 3 is formed by photolithography and wet etching techniques.
Patterns 1 and 32 were processed.

Subsequently, Au = 1 μm was formed as the upper electrode layers 41 and 42 and the lower terminal electrode layer 43 by sputtering, and the same patterning as the lower electrode layers 21 and 22 and the lower terminal electrode layer 23 was performed.

In the photolithography of this embodiment, there is a maximum displacement of 2 μm.
The shapes 1 and 22 were made large with a margin of 5 μm in both the x direction and the Y direction of the capacitance generating regions a and b.

Finally, a part of the lower terminal electrode layer 23 and a part of the upper terminal electrode layer 43 are shown. A protective film 5 such as BCB was formed so as to be exposed. Specifically, BCB was applied by a spin coating method, and was etched and patterned by exposure processing.

The opposing areas of the two electrode layers 21 (22) and 41 (42) of the produced capacity generating regions a and b were 0.02 mm in the X direction and 0.01 mm in the Y direction. As a result of evaluating the electrical characteristics of the variable capacitor, the capacitance was 2 pF and the resonance frequency was 5 GHz. From this, when the parasitic inductance is obtained from the equation of fo = ^1/2 (LC) ^1/2 , it is 0.5 nH, which is smaller than that of the conventional variable capacitor having the same area of the capacitance generation area and a single capacitance generation area. And the parasitic inductance became about 1/2.

In order to control the dielectric constant of the dielectric layer 3 or 53 in the variable capacitor of the present invention and the conventional variable capacitor, the external terminals 6 and 7 (extending portion 52a of the lower electrode layer, extending portion of the upper electrode layer). An external control voltage of 10 V was applied during 54a).

As a result, in the conventional variable capacitor, the dielectric constant of the dielectric layer 53 is 1 compared to the state where no voltage is applied.
It decreased by 6%. However, in the variable capacitor of the present invention,
The dielectric constant of the dielectric layer 3 is 2 compared to the state where no voltage is applied.
It could be reduced by 6%. This is because the external control voltage is uniformly applied to the entire dielectric layer 3 and the variation distribution of the dielectric constant is small.

FIG. 4 shows a variable capacitor in which the polarities of two capacitance generating areas a and b are set to opposite potentials.

In this structure, the lower electrode layer 21 of the first capacitance generation region a is connected to the upper electrode layer 4 of the second capacitance generation region b.
2 is connected. Specifically, the extension 24 extending from the lower electrode layer 21 and the extension 45 extending from the upper electrode layer 42 are integrally connected. Similarly, the lower electrode layer 22 in the second capacitance generation region a is connected to the upper electrode layer 41 in the second capacitance generation region b. In particular,
The extension 25 extending from the lower electrode layer 22 and the extension 44 extending from the upper electrode layer 41 are integrally connected.

The method of manufacturing the capacitor includes the following steps: a lower electrode layer 21, an extension 24 extending from the lower electrode layer 21,
The lower electrode layer 22 and the extending portion 25 extending from the lower electrode layer 22 are formed in a staggered manner (in FIG. 3, since the two capacitance generating regions are oblique directions). Next, the dielectric layers 31, 3
Form 2 Next, the upper electrode layer 41, the extension 44 extending from the upper electrode layer 41, the upper electrode layer 42, and the extension 45 extending from the upper electrode layer 42 are formed in a staggered manner.

In such a structure, the lower extension 24,
Upper extension portions 45 and 44 are formed so as to overlap a part of the upper portion 25. That is, the lower extension 24 and the upper extension 4
5 are integrated into one terminal electrode layer, and the lower extension 25 and the upper extension 44 are integrated into the other terminal electrode layer. Although not shown, if the external terminals 6 and 7 are formed in the overlapping connection portion, the thermal shock of mounting on the motherboard can be reduced, and the connection between each terminal electrode layer and the support substrate 1 can be reduced. Adhesion can be improved.

In the structure shown in FIG. 4, when an external control voltage is applied between one terminal electrode layer and the other terminal electrode layer, the current flowing through the dielectric layers 31 and 32, ie, the capacitance generating regions a and b, respectively. Although a path is formed, this current flows uniformly in the capacitance generating regions a and b.

One current path corresponds to a capacitance generation area.
Since a and b are in the same direction (for example, from the right side to the left side of the paper), the magnetic fluxes generated in the current path in the region between the regions cancel each other, and the effective magnetic flux decreases. Therefore, the inductance L (L = Φ / I) defined by the magnetic flux amount Φ generated by the unit current I can be reduced as the magnetic flux decreases.

In such a structure, the dielectric layer 3
3, may be formed continuously over a plurality of capacitance generating regions as shown in FIG.

In FIG. 4, the capacitance generating areas a and b are composed of two areas. On the support substrate 1, the capacity generating areas are formed with even number areas such as two areas, four areas and six areas. Then, it may be set by setting the magnetic fluxes of the adjacent capacitance generating regions to cancel each other.

In the present invention, the terminal electrode layers (extending portions) 23, 24, 25 of the lower electrode layers 21, 22 and the terminal electrode layers (extending portions) of the upper electrode layers 41, 42 are formed on the support substrate 1. 43, 44 and 45 are formed. Since the external terminals 6 and 7 are formed on the terminal electrode layer, it is easy to mount the upper surface of the support substrate 1 on the motherboard. Moreover, unlike a conventional capacitor, since there is no hollow portion in a structure such as an air bridge structure, a very stable and highly reliable mounting can be achieved.

[0055]

According to the variable capacitor of the present invention, a capacitance generating region in which a predetermined capacitance is formed is divided into a plurality of portions, and these divided capacitance generating regions are joined to each other.
That is, when a predetermined potential is applied between the upper electrode layer and the lower electrode layer sandwiching the dielectric layer to control the dielectric constant of the dielectric layer,
Since the potential distribution of the externally applied voltage can be reduced in each divided capacity generation region, the variable capacitor has a wide variable range as controlled and a stable capacitance can be obtained.

Since the current can flow in each of the plurality of capacitance generating regions, the parasitic inductance can be reduced.

Further, since the current flows in the adjacent capacitance generating regions in the same direction, the magnetic flux generated by this current can be canceled each other, and the change in capacitance can be further reduced.

Further, the shape of the one electrode layer is changed to the shape of the capacitance generating region (the shape of the area of the one electrode layer facing the other electrode layer)
Therefore, even when displacement occurs during formation of one or the other electrode layer, a change in the area of the capacitance generation region can be reduced, and stable characteristics can be obtained.

Further, since there is no hollow structure between each electrode layer and the terminal electrode layer, the upper surface of the support substrate can be mounted on the mother boat easily and reliably.

[Brief description of the drawings]

FIG. 1 is a sectional view of a variable capacitor according to the present invention.

FIG. 2 is a plan view of a main part of a variable capacitor according to the present invention.

FIG. 3 is a plan view of a main part of another variable capacitor according to the present invention.

FIG. 4 is a plan view of a main part of another variable capacitor according to the present invention.

FIG. 5 is a sectional view of a conventional variable capacitor.

FIG. 6 is a plan view of a conventional variable capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Support substrate 21, 22, 2 ... Lower electrode layer 31, 32, 3 ... Dielectric layer 41, 42, 4 ... Upper electrode layer 5 ... Protective film 6, 7, ...・ External terminal

Claims (4)

[Claims] 1. A method according to claim 1, wherein a plurality of capacitance generating regions are formed by sandwiching a dielectric layer whose permittivity changes by applying a voltage between a lower electrode layer and an upper electrode layer, and the respective capacitance generating regions are connected to each other. Characteristic variable capacitor. 2. The device according to claim 1, wherein the upper electrode layer of one of the adjacent capacitance generating regions is connected to have the same potential as the lower electrode layer of the other capacitance generating region. Variable capacitors. 3. The variable capacitor according to claim 2, wherein the number of the plurality of capacitance generating regions is an even number. 4. The variable capacitor according to claim 1, wherein the planar shape of one of the upper electrode layer and the lower electrode layer is similar to the planar shape of the capacitance generating region.