JP4044878B2 - Multilayer thin film capacitors - Google Patents

Description

【００３９】
表１の結果からも、電極層の材料をＰｔおよびＡｕとし、電極層の膜厚を微妙に変化させることにより、ＥＳＲを0.07Ω〜0.32Ωの広い範囲でコントロールできることが判明した。
【００４０】
【発明の効果】
以上、説明したように請求項１および請求項２の積層型薄膜コンデンサによれば、支持基板上に電極層と誘電体層とを交互に積層して２つの電極層の間に誘電体層を介在して成る容量発生領域を複数備え、前記電極層のうち最上に位置する電極層が他の電極層より体積抵抗率が小さいことを特徴とする。また、特に、前記最上に位置する電極層の100℃における体積抵抗率が3.0×10^−８Ω・ｍ以下であり、かつ前記他の電極層の100℃における体積抵抗率が10.0×10^−８Ω・ｍ以上20.0×10^−８Ω・ｍ以下であることとする。これにより、ＥＳＲを適当な値にコントロールし、容易に所望の特性を得ることのできる優れた積層薄膜コンデンサを提供することができる。
【００４１】
また、請求項３の積層型薄膜コンデンサによれば、最上層に位置する電極層を構成する材料が、Ａｕ，Ｃｕ，Ａｇから選択された元素から成るので、純度の高い材料を容易に得ることができる。また、最上層以外の電極層を構成する材料をＰｔとすることにより、誘電体層の形成時における酸化のおそれがなく安定した電気特性を得ることができる。
【００４２】
また、特に同一極性の電極層どうしを接続して外部端子とし、この外部端子が高さ0.1ｍｍ以下のはんだバンプであるとすると、はんだバンプに起因するインダクタンスを低くすることができる。
【００４３】
また、特に各誘電体層の厚みが最上層以外の電極層のうちの最大厚みの３倍以上あると、誘電体層の電極層端部への被覆性が良好となり、絶縁劣化などのおそれがなくなり、製品信頼性を確保することができる。
【図面の簡単な説明】
【図１】（ａ）は、本発明に係る積層型薄膜コンデンサの一例を説明する平面図であり、（ｂ）は（ａ）のＡ−Ａ線断面図である。
【図２】（ａ）〜（ｅ）は、それぞれ図１の積層型薄膜コンデンサの形状を説明する平面図であり、（ａ），（ｃ）は電極層のパターンを、（ｂ）は誘電体層のパターンを、（ｄ）は端子電極のパターンを、（ｅ）は保護層のパターンをそれぞれ示す。
【符号の説明】
２，２ａ，２ｂ・・・一方極性の電極層
４，４ａ，４ｂ・・・他方極性の電極層
３，３ａ，３ｂ，３ｃ・・・誘電体層[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer thin film capacitor that is disposed in an electric circuit that operates at high speed and is used for bypassing high frequency noise and preventing fluctuations in power supply voltage, and more particularly to a multilayer thin film capacitor having an equivalent series resistance (ESR) characteristic. It is.
[0002]
[Prior art]
In recent years, as the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to be kept low in order to reduce power consumption. In order to achieve high speed, high density, and low voltage of such IC circuits, passive components such as capacitors should be provided with high functions such as low impedance, low inductance, miniaturization, and thinning. Is required.
[0003]
A thin film capacitor is suitable for manufacturing a capacitor having such a high function. A dielectric layer having a thickness of 1 μm or less has already been disclosed (see, for example, Patent Document 1). Some multilayer thin film capacitors in which a plurality of electrode layers and a plurality of thin film dielectric layers are laminated for the purpose of obtaining a small size and a large capacity are also disclosed (see, for example, Patent Documents 2 and 3).
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 60-94716
[Patent Document 2]
JP-A-7-169648 [0006]
[Patent Document 3]
Japanese Patent Laid-Open No. 11-214245
[Problems to be solved by the invention]
Capacitors used for bypassing high-frequency noise and preventing fluctuations in power supply voltage must have large capacitance and small inductance as characteristics, but equivalent series resistance (ESR) characteristics are also important characteristics. . In general, the lower the ESR, the better. However, depending on the mounting position of the capacitor in the circuit and the function required for the capacitor, if the ESR is too low, the ESR may not work effectively but may have an adverse effect. It is important to control.
[0008]
Accordingly, an object of the present invention is to provide a multilayer thin film capacitor which can easily obtain desired characteristics by controlling ESR to an appropriate value.
[0009]
[Means for Solving the Problems]
The multilayer thin film capacitor of the present invention is as follows: 1) An electrode layer and a dielectric layer thinned to a thickness of 1 μm or less are alternately laminated in a multilayer on a support substrate , and a dielectric layer is interposed between two electrode layers. In the multilayer thin film capacitor having a plurality of capacitance generation regions, only the uppermost electrode layer among the electrode layers has a smaller volume resistivity than the other electrode layers.
[0010]
2) In 1), the volume resistivity at 100 ° C. of the uppermost electrode layer is 3.0 × 10 ⁻⁸ Ω · m or less, and the volume resistivity at 100 ° C. of the other electrode layer is 10.0. ^{X10 −8} Ω · m or more and 20.0 × 10 ⁻⁸ Ω · m or less.
[0011]
3) In 1) to 2), the material constituting the uppermost electrode layer is composed of one or more elements selected from Au, Cu, and Ag.
[0012]
4) In 1) to 3), the material constituting the electrode layer other than the uppermost electrode layer is Pt.
[0013]
5) In 1) to 4), electrode layers having the same polarity may be connected to form an external terminal, and the external terminal may be a solder bump having a height of 0.1 mm or less.
[0014]
Furthermore, in 6) 1) to 5), the thickness of each dielectric layer is at least three times the maximum thickness of the electrode layers other than the uppermost layer. In the method for manufacturing a multilayer thin film capacitor of the present invention, an electrode layer and a dielectric layer thinned to a thickness of 1 μm or less are alternately laminated on a support substrate, and a dielectric layer is provided between the two electrode layers. In a multilayer thin film capacitor having a plurality of capacitance generation regions with intervening layers, only the uppermost electrode layer among the electrode layers is made of a material having a smaller volume resistivity than the other electrode layers, and the film thickness is adjusted. Thus, the desired ESR characteristic is controlled.
[0015]
According to the above 1) and 2), desired ESR characteristics can be obtained by controlling the film thickness of each electrode layer. Although the ESR characteristic of a multilayer thin film capacitor varies depending on the number of layers, the variation width due to the number of layers can be suppressed small by increasing the volume resistivity of the electrode layer other than the uppermost layer corresponding to the multilayer part. By reducing the volume resistivity of only the uppermost electrode layer, the influence on the ESR characteristic of the uppermost electrode layer is increased. Therefore, the ESR characteristic can be easily controlled only by controlling the film thickness of this layer. .
[0016]
In addition, a material having a high purity can be easily obtained by making the material constituting the electrode layer located in the uppermost layer of an element selected from Au, Cu, and Ag. Further, by using Pt as the material constituting the electrode layer other than the uppermost layer, there is no fear of oxidation during formation of the dielectric layer, and stable electrical characteristics can be obtained.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the multilayer thin film capacitor of the present invention will be described in detail with reference to the drawings.
[0018]
FIG. 1 shows a multilayer thin film capacitor in which three capacitance regions are laminated, FIG. 1 (a) is a plan view thereof, and FIG. 1 (b) is a cross-sectional view taken along line AA of FIG. 1 (a). . As shown in FIG. 1, the multilayer thin film capacitor of the present invention has electrode layers and dielectric layers alternately stacked on a support substrate 1 in a multilayer manner, and a dielectric layer is interposed between two electrode layers. A plurality of capacitance generation regions are provided, and the electrode layer located at the uppermost of the electrode layers has a smaller volume resistivity than the other electrode layers. In particular, the volume resistivity at 100 ° C. of the uppermost electrode layer is 3.0 × 10 ⁻⁸ Ω · m or less, and the volume resistivity at 100 ° C. of the other electrode layer is 10.0 × 10 ⁻⁸ Ω · m. m or more and 20.0 × 10 ⁻⁸ Ω · m or less. Specifically, on the support substrate 1, the first one-polar electrode layer 2a, the first dielectric layer 3a, the first other-polar electrode layer 4a, the second dielectric layer 3b, the second This is a multilayer thin film capacitor having a structure in which one polar electrode layer 2b, a third dielectric layer 3c, and a second other polar electrode layer 4b are laminated in order, and one polar electrode layer 2 (generally 2) ) And the other polar electrode layer 4 (generally referred to as 4), three dielectric layers 3 (generally referred to as 3) are sandwiched, and three capacitance regions are laminated.
[0019]
Further, the end portion of the one-polar electrode layer 2 extends to the right side of the drawing from the dielectric layer 3, and the external terminal 5 is provided on the extended end portion via the terminal electrode layer 8. Further, the end portion of the other polarity electrode layer 4 extends to the left side of the figure from the dielectric layer 3, and the external terminal 6 is provided on the extended end portion via the terminal electrode layer 8.
[0020]
Further, the protective layer 7 has an opening that exposes the external terminals 5 and 6, and is formed so as to cover the electrode layers 2 and 4, the dielectric layer 3, and the terminal electrode layer 8.
[0021]
Moreover, in FIG. 1, the electrode layer located in the uppermost layer is the second other polarity electrode layer 4b, and the electrode layer has a volume resistivity of 3.0 × 10 ⁻⁸ Ω · m or less at 100 ° C. It is comprised by. The electrode layers other than the uppermost layer are the first and second one-polar electrode layers 2a and 2b and the first other-polar electrode layer 4a. These electrode layers have a volume resistivity of 10.0 × 10 at 100 ° C. It is made of a material that is ⁻⁸ Ω · m to 20.0 × 10 ⁻⁸ Ω · m. When the electrode layer has such a material structure, it is easy to control the ESR characteristics of the capacitor.
[0022]
The ESR characteristic is affected by the parallel effect of the electrode layers depending on the number of stacked layers, the thickness effect of the electrode layers, and the volume resistivity specific to the material. The number of layers is determined in order to efficiently obtain a desired capacity. Further, if the thickness of the electrode layer is too large compared to the thickness of the dielectric layer, it causes deterioration of insulation, and if it is too thin, a film cannot be formed, so the range to be controlled is limited. Therefore, it is effective to change the material of the electrode layer in order to control ESR.
[0023]
However, changing the material of the electrode layer to control the desired ESR is not preferable from the viewpoint of product stability and economy.
[0024]
Therefore, a material having a relatively high volume resistivity is used for the electrode layers other than the uppermost layer, and a certain amount of ESR is secured by utilizing the parallel effect of the electrode layers depending on the number of stacked layers. In addition, the uppermost electrode layer having a high degree of freedom in film thickness design can be controlled to a desired ESR by using a material having a low volume resistivity.
[0025]
The volume resistivity at 100 ° C. of the electrode layer other than the top layer is set to 10.0 × 10 ⁻⁸ Ω · m or more and 20.0 × 10 ⁻⁸ Ω · m or less due to the contribution of stacking of electrode layers when it is larger than this range. This is because the ESR increases and the desired ESR cannot be obtained even if the volume resistivity of the uppermost electrode layer is reduced. On the other hand, if it is smaller than this range, the ESR due to the stacking contribution of the electrode layer becomes small, and the desired ESR cannot be obtained even if the volume resistivity of the uppermost electrode layer is increased. The volume resistivity at 100 ° C was adopted because the operating environment of passive components mounted on IC circuits as in the technical field of the present invention is considered to be a high temperature range of about 100 ° C. This is because of the design. Although there are several such materials, Pt is most desirable because it can provide stable electric characteristics without fear of oxidation during the formation of the dielectric.
[0026]
The reason why the volume resistivity at 100 ° C. of the uppermost electrode layer is set to 3.0 × 10 ⁻⁸ Ω · m or less is that it is difficult to control the volume resistivity to a desired ESR. As such a material, Au, Cu, and Ag that can easily obtain a high-purity material are desirable.
[0027]
The external terminals 5 and 6 are not particularly limited in shape. When a low inductance is required, the illustrated bump shape is desirable, and the height is desirably 0.1 mm or less. Moreover, although the example with a total of four external terminals 5 and 6 has been shown, the number is not limited to the number, and it is better to increase the number in order to obtain a lower inductance.
[0028]
As a field requiring control of ESR characteristics as in the present invention, it may be used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. In such fields, low inductance characteristics are required. In order to make the invention more effective, it is desirable to have an inductance of 20 pH or less.
[0029]
In the structure of the multilayer thin film capacitor of the present invention, the example of the four electrode layers 2, 4, and 3 dielectric layers 3 is shown, but the number of layers is not limited. Further, the protective film 7 is preferably an inorganic film having a low moisture permeability coefficient such as silicon oxide (SiO _x ) or silicon nitride (SiN _x ) in order to ensure the reliability of the capacitor, and benzocyclobutene (BCB resin). Or an organic film such as polyimide resin. Moreover, in order to ensure reliability more, you may combine multiple. As described above, various modifications can be made without departing from the scope of the present invention.
[0030]
【Example】
Examples in which the present invention is further embodied will be described below.
[0031]
1 and 2 were fabricated, the electrode layers 2 and 4 were formed using a DC sputtering apparatus, and the dielectric layer 3 was formed using an RF sputtering apparatus.
[0032]
First, an adhesion layer made of titanium oxide was formed on a sapphire substrate having a thickness of about 0.25 mm, and a Pt electrode layer having a thickness of about 60 nm was formed thereon. The first one-polar electrode layer 2a was processed into a pattern using a photolithography technique.
[0033]
A dielectric layer made of Ba _0.5 Sr _0.5 TiO ₃ having a thickness of about 250 nm was formed on the processed electrode layer 2a. Similar to the electrode layer, the dielectric layer 3a was processed into a pattern using a photolithography technique.
[0034]
Further, the first other polarity electrode layer 4a, the second dielectric layer 3b, the second one polarity electrode layer 2b, and the third dielectric layer 3c were successively formed and patterned. As the second other polarity electrode layer 4b, which is the uppermost electrode layer, a 300 nm Au electrode layer was formed. As with the other electrode layers, the second other polarity electrode layer 4b was processed into a pattern using a photolithographic technique to form a thin film capacitor having three dielectric layers and four electrode layers.
[0035]
Next, the terminal electrode layer 8 was formed with a Ni layer having a thickness of about 1.0 μm and an Au layer having a thickness of about 0.1 μm, and processed into a pattern using a photolithography technique. Thereafter, a photosensitive BCB was applied, exposed and developed, and a protective film 7 having an opening was formed so that a part of the terminal electrode layer 8 was exposed in order to form the external terminals 5 and 6. Further, using a screen printing technique, a commercially available solder paste was transferred to the opening of the protective film and reflowed to form solder bumps as the external terminals 5 and 6 to obtain the multilayer thin film capacitor of the present invention. . This was used as a sample of the present invention.
[0036]
Using the same method, thin film capacitors having different Pt electrode layer thickness, Au thickness as the uppermost electrode layer, and the number of dielectric layers were obtained.
[0037]
For each sample example, the frequency characteristics of impedance were evaluated using a measuring device manufactured by Hewlett Packard (HP4291A), and ESR was measured. The results are summarized in Table 1.
[0038]
[Table 1]

[0039]
From the results in Table 1, it was also found that the ESR can be controlled in a wide range of 0.07Ω to 0.32Ω by changing the film thickness of the electrode layer to Pt and Au as the material of the electrode layer.
[0040]
【The invention's effect】
As described above, according to the multilayer thin film capacitor of claims 1 and 2, the electrode layer and the dielectric layer are alternately laminated on the support substrate, and the dielectric layer is provided between the two electrode layers. A plurality of intervening capacitance generating regions are provided, and the electrode layer located at the top of the electrode layers has a volume resistivity smaller than that of the other electrode layers. In particular, the volume resistivity at 100 ° C. of the uppermost electrode layer is 3.0 × 10 ⁻⁸ Ω · m or less, and the volume resistivity at 100 ° C. of the other electrode layer is 10.0 × 10 ^−8. Ω · m to 20.0 × 10 ⁻⁸ Ω · m. As a result, it is possible to provide an excellent multilayer thin film capacitor in which ESR is controlled to an appropriate value and desired characteristics can be easily obtained.
[0041]
According to the multilayer thin film capacitor of claim 3, since the material constituting the uppermost electrode layer is composed of an element selected from Au, Cu, and Ag, it is possible to easily obtain a high-purity material. Can do. Further, by using Pt as the material constituting the electrode layer other than the uppermost layer, there is no fear of oxidation during formation of the dielectric layer, and stable electrical characteristics can be obtained.
[0042]
In particular, when the electrode layers having the same polarity are connected to form an external terminal, and the external terminal is a solder bump having a height of 0.1 mm or less, the inductance caused by the solder bump can be reduced.
[0043]
In particular, when the thickness of each dielectric layer is more than three times the maximum thickness of the electrode layers other than the uppermost layer, the coverage of the dielectric layer to the end of the electrode layer is improved, and there is a risk of insulation deterioration. The product reliability can be ensured.
[Brief description of the drawings]
FIG. 1A is a plan view for explaining an example of a multilayer thin film capacitor according to the present invention, and FIG. 1B is a sectional view taken along line AA in FIG.
2 (a) to (e) are plan views for explaining the shape of the multilayer thin film capacitor of FIG. 1, respectively, (a) and (c) are electrode layer patterns, and (b) is dielectric. The body layer pattern, (d) the terminal electrode pattern, and (e) the protective layer pattern, respectively.
[Explanation of symbols]
2, 2a, 2b ... one polarity electrode layer 4, 4a, 4b ... the other polarity electrode layer 3, 3a, 3b, 3c ... dielectric layer

Claims (4)

A laminated type comprising a plurality of capacitance generating regions in which electrode layers and dielectric layers whose thickness is reduced to 1 μm or less are alternately laminated on a support substrate , and a dielectric layer is interposed between two electrode layers. A multilayer thin film capacitor, wherein only the uppermost electrode layer of the electrode layers has a volume resistivity smaller than that of the other electrode layers. The volume resistivity at 100 ° C. of the uppermost electrode layer is 3.0 × 10 ⁻⁸ Ω · m or less, and the volume resistivity at 100 ° C. of the other electrode layer is 10.0 × 10 ^−8. The multilayer thin film capacitor according to claim 1, wherein the thickness is Ω · m or more and 20.0 × 10 ⁻⁸ Ω · m or less. The material constituting the uppermost electrode layer is composed of one or more elements selected from Au, Cu, and Ag, and the material constituting the electrode layer other than the uppermost electrode layer is Pt. The multilayer thin film capacitor according to claim 1, wherein the multilayer thin film capacitor is characterized. A laminated type comprising a plurality of capacitance generating regions in which electrode layers and dielectric layers whose thickness is reduced to 1 μm or less are alternately laminated on a support substrate, and a dielectric layer is interposed between two electrode layers. In the thin film capacitor, only the uppermost electrode layer among the electrode layers is controlled to a desired ESR characteristic by adjusting the film thickness by using a material having a smaller volume resistivity than the other electrode layers. A method for manufacturing a laminated thin film capacitor.

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