JP2002231577A - Thin film electronic component and substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film electronic component and a substrate which can improve the joining strength of an external terminal to a base substrate. SOLUTION: This component is equipped with the base substrate 1, a lower electrode 5 which is formed partially on the base electrode 1, an insulator layer 3 which is formed on the lower substrate 5, an upper electrode 7 which is formed on the insulator layer 3, a connection electrode 13 which is positioned on the bottom surface of a through hole 23 in the insulator layer 3 and formed on the base substrate 1, the connection electrode which is electrically connected to the lower electrode 5, and the external terminal 11a which is provided to the connection electrode 13 in the through hole 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film electronic component and a substrate, for example, a thin-film electronic component and a substrate suitably used for high-frequency applications suitably used for a thin-film capacitor, a thin-film inductor, a thin-film LC filter, a thin-film resistor, a thin-film RC filter and the like. Things.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in electronic devices to be smaller, thinner, and compatible with high frequencies.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is 200 MHz to 1 GHz, and the clock frequency of the bus between chips is also 75 MHz to 133 MHz even at the personal computer level. The speedup is remarkable.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

[0005] As the operating frequency increases, the resistance or inductance of the element causes an instantaneous decrease in the power supply voltage on the logic circuit side or new voltage noise.
As a result, an error occurs in the logic circuit. Particularly in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements, and the allowable fluctuation width of the power supply voltage has been reduced. If the number of elements and the operating frequency further increase in the future, the resistance and inductance components of the mounting part cannot be neglected, and this will be a factor of a logic circuit error.

[0006] In addition to the above-described electrical characteristics of the passive element itself, such as improvement in mounting accuracy due to an increase in the number of elements and improvement in reflow resistance due to component mounting, characteristics relating to mounting (mounting accuracy, mounting reliability). Sex) is also being required at a high level.

[0007] US Pat. No. 4,439,813 describes a technique for reducing the inductance of a connection portion of a capacitor.
In order to obtain an electric signal from the lower electrode made of TiW, Ta, Al, and Cu at the shortest distance, a through hole is provided in the insulating layer, the upper electrode, and the protective layer, and Cr / Cu / A is formed on the inner wall of the through hole.
A thin film capacitor in which a BLM layer made of u is formed, and then a solder bump is formed on the BLM layer is disclosed.

FIG. 5 shows a capacitor disclosed in this publication, in which a lower electrode 33, an insulator layer 35, an upper electrode 37, and a protective layer 39 are sequentially laminated on a support substrate 31. An external terminal 41 is connected to the side electrode 33 via a through hole formed in the protective layer 39.
An external terminal 43 is connected to 7 via a through hole formed in the protective layer 39, and the external terminal 43 is formed on the insulator layer 35.

[0009]

However, in the above-described thin film capacitor, the insulating layer 3 is formed on the lower electrode 33 by a sputtering method, a vapor deposition method, a sol-gel method or the like.
5, the lower electrode 33 undergoes a high-temperature process, so that the adhesion strength between the support substrate 31 and the lower electrode 33 is deteriorated, and the solder fixed to the support substrate 31 via the lower electrode 33 is formed. When the external terminals 41 and 43 made of bumps are bonded on the electrodes of the mother substrate, the external terminals 41 and 43 are easily peeled off from the support substrate 31, the bonding strength of the thin film capacitor to the mother substrate is low, and the thin film capacitor is thinned by some impact. There was a problem that the capacitor dropped off.

That is, the support substrate 31 is provided via the lower electrode 33.
External terminals 41 and 43 made of solder bumps
When an excessive load is applied to the solder bumps, the solder bumps do not break when the external terminal strength is maximized, but, for example, breaks occur at the interface between the support substrate 31 and the lower electrode 33, and the solder bumps originally However, there has been a problem that the strength of the device cannot be maximized and the mounting reliability is reduced.

It is also conceivable to form an adhesion layer between the support substrate 31 and the lower electrode 33. However, the adhesion layer diffuses or moves due to the high-temperature process, and the function as the adhesion layer is sufficiently reduced. The support substrate 31 and the lower electrode 33
However, there is a problem that the adhesion strength is deteriorated.

An object of the present invention is to provide a thin-film electronic component and a substrate capable of improving the bonding strength of an external terminal to a support substrate.

[0013]

According to the present invention, there is provided a thin film electronic component comprising: a support substrate; a lower electrode formed on a part of the support substrate; and an insulator layer formed on the lower electrode. An upper electrode formed on the insulator layer, and a connection electrode formed on a support substrate located on a bottom surface of a through hole formed in the insulator layer and electrically connected to the lower electrode; And an external terminal provided on the connection electrode in the through hole.

In other words, a support substrate, a lower electrode formed on the support substrate, an insulator layer formed on the lower electrode, an upper electrode formed on the insulator layer, A connection electrode formed on the bottom surface of the through hole formed in the insulator layer and electrically connected to the lower electrode, and an external terminal provided on the connection electrode in the through hole,
The connection electrode is provided on the support substrate via a portion where the lower electrode is not formed. In other words, the inside of the through hole formed in the insulator layer is
An insulator layer non-formation area where an insulator layer is not formed is provided, and a connection electrode in the insulator layer non-formation area is provided on the support substrate via a portion where the lower electrode is not formed. Things.

By adopting such a configuration, an insulator layer is formed by a sputtering method, a vapor deposition method, a sol-gel method or the like, and even if the lower electrode is formed through a high-temperature process, it is provided on the supporting substrate. Since the connection electrode is formed after the formation of the insulator layer, the bonding strength between the connection electrode provided on the support substrate and the support substrate directly or via the adhesion layer is improved, and the lower electrode is electrically connected via the connection electrode. The bonding strength of the external terminals connected to the support substrate can be improved, and the mounting reliability can be improved.

In the thin-film electronic component of the present invention, it is preferable that the connection electrode and the lower electrode overlap each other at the inner peripheral portion of the bottom surface of the through hole. By employing such a configuration, the connection electrode and the lower electrode can be reliably electrically connected.

Further, in the thin-film electronic component of the present invention, the overlapping area of the connection electrode and the lower electrode is 1 to 1 of the sectional area of the through hole.
Desirably, it is 0%. By employing such a configuration, the bonding strength of the external terminal to the support substrate can be improved, and electrical connection between the connection electrode and the lower electrode can be ensured.

The substrate of the present invention comprises the above-mentioned thin-film electronic component provided on the surface of a base via external terminals. In such a substrate, since the bonding strength between the external terminal and the support substrate is high, the bonding strength between the thin-film electronic component bonded to the base via the external terminal and the base can be improved.

[0019]

FIG. 1 shows a thin-film electronic component comprising a thin-film capacitor. As shown in FIG.
(Dielectric thin film), a plurality of thin film elements A having a lower electrode 5 and an upper electrode 7 are provided. Lower electrode 5,
The upper electrode 7 is made of Au, and the insulator layer 3 is sandwiched between a part of the lower electrode 5 and a part of the upper electrode 7 to form a thin film element A (capacitance element).

The whole of the thin film element A and the non-insulator layer forming area B where the insulator layer 3 is not formed are covered with a protective layer 9, and the thin film element A is formed on the protective layer 9. An external terminal 11a made of a solder bump electrically connected to the lower electrode 5 and an external terminal 11b made of a solder bump electrically connected to the upper electrode 7 are provided to protrude.

The lower electrode 5 is electrically connected to the upper surface of the insulator layer 3 and the connection electrode 13 formed in the non-insulator layer forming region B. The upper surface of the connection electrode 13 is connected to the solder barrier layer 15. The solder adhesion layer 17 is formed on the upper surface of the solder barrier layer 15.
The external terminals 11a are formed on the solder adhesion layer 17. Thus, the external terminal 11 a is electrically connected to the lower electrode 5 via the connection electrode 13.

The non-insulator layer forming region B where the external terminal 11a is formed corresponds to the inside of the through hole 23 formed in the insulator layer 3, and the connection electrode 13 is a part of the upper surface of the insulator layer 3. And the bottom of the through hole 23, and these are formed continuously.

The connection electrode 13 is formed at the same time as the upper electrode 7, but is insulated from the upper electrode 7 by forming a portion around the external terminal 11a where no metal layer is formed. I have.

The upper electrode 7 formed in the upper surface of the insulator layer 3 and the non-insulator layer forming region B is electrically connected to the metal layer 19 formed simultaneously with the lower electrode 5. A solder barrier layer 15 is formed on the upper surface of the body layer non-forming region B and the upper electrode 7 in the vicinity thereof, and a solder adhesion layer 17 is formed on the upper surface of the solder barrier layer 15. The external terminals 11 b are formed on the solder adhesion layer 17. Is formed. Thus, the external terminal 11b is electrically connected to the metal layer 19 via the upper electrode 7.

The non-insulator layer forming region B where the external terminal 11b is formed corresponds to the inside of the through hole 23 formed in the insulator layer 3, and a part of the upper electrode 7 is formed on the bottom surface of the through hole 23. Is formed.

The metal layer 19 is formed at the same time as the lower electrode 5, but by forming an annular portion around the external terminal 11b where no metal layer is formed, the lower electrode 5 is formed.
Is insulated from

In the present invention, the connection electrode 13 formed on the bottom surface of the through hole 23 is provided on the support substrate 1 via the portion 21 where the lower electrode 5 is not formed. As shown in FIG. 2, the non-insulator layer forming region B is formed by forming a through hole 23 having a circular cross section in the insulating layer 3, and the lower portion of the through hole 25 having a smaller diameter than the through hole 23. By forming the connection electrode 13 in the side electrode 5 and forming the connection electrode 13 in the through hole 25 of the lower electrode 5, the connection electrode 13 is in contact with the support substrate 1. Further, the connection electrode 13 and the lower electrode 5 overlap in the inner peripheral portion of the non-insulator layer forming region B, that is, in the inner peripheral portion of the bottom surface of the through hole 23. The superimposing unit is indicated by a symbol x in FIGS.

Connection electrode 1 in region B where insulator layer is not formed
The overlapping area of the lower electrode 3 and the lower electrode 5 is set to 1 to 10% of the area (cross-sectional area of the through-hole 23) of the region B where the insulator layer is not formed.

The upper electrode 7 in the non-insulator layer forming area B is provided on the support substrate 1 via the portion 27 where the metal layer 19 is not formed. Similarly, in this case, the insulator layer non-forming region B is formed by forming a through hole 23 having a circular cross section in the insulating layer 3 as shown in FIG. Is formed in the metal layer 19, and the upper electrode 7 is formed in the through hole 28 of the metal layer 19 so that the upper electrode 7 is in contact with the support substrate 1. Further, the upper electrode 7 and the metal layer 19 overlap in the inner peripheral portion of the non-insulator layer forming region B.

The insulating layer 3 is formed in a region B where no insulator layer is formed.
The lower electrode (including the metal layer 19) 5 is formed on the entire surface except for the through holes 25 and 28 and the portion etched annularly, and the upper electrode (including the metal layer 13) 7
Is formed on the entire surface except for the portion etched annularly.

Upper electrode 7 in insulator layer non-formation region B
And the metal layer 19 have an overlapping area of 1 to 10% of the area of the non-insulator layer forming region B.

The overlap area between the connection electrode 13 and the lower electrode 5;
The reason why the overlapping area of the upper electrode 7 and the metal layer 19 is set to 1 to 10% of the cross-sectional area of the through hole 23 is larger than 10%.
The contact area of the connection electrode 13 and the upper electrode 7 with the support substrate 1 is reduced, and the influence of the lower electrode 5 and the metal layer 19 whose adhesion strength with the support substrate 1 is reduced through a high-temperature process is increased. This is because the adhesion strength of the terminals 11a and 11b to the support substrate 1 is likely to deteriorate. On the other hand, if it is less than 1%, the overlapping area of the connection electrode 13, the metal layer 19 and the lower electrode 5, the upper electrode 7 becomes small, and a partial electrical connection defect occurs between the two electrodes. This is because there is a risk of deteriorating the electrical characteristics of the component.

The insulator layer 3 constituting the dielectric thin film of the thin film element A may be a dielectric made of a perovskite-type oxide crystal having a high relative dielectric constant in a high frequency region, for example, a Pb (Mg, Nb) O ₃ -based material. , Pb (Mg, Nb) O ₃ -P
bTiO ₃ system, Pb (Zr, Ti) O ₃ system, Pb (Mg,
_{Nb) O 3 -Pb (Zr,} Ti) O 3 system, (Pb, La)
ZrTiO ₃ system, BaTiO ₃ system, (Sr, Ba) TiO
_The compound may be a tri-system or a compound in which other additives are added or substituted, and are not particularly limited.

The thickness of the insulator layer 3 is preferably 0.3 to 1.0 μm in order to ensure high capacity and insulation. This is not good when the thickness is less than 0.3 μm,
This is because the insulating property may decrease, and when the thickness is greater than 1.0 μm, the capacitance tends to decrease. The thickness of the insulator layer 3 is preferably 0.4 to 0.8 μm.

The thicknesses of the lower electrode 5, the upper electrode 7, the connection electrode 13, and the metal layer 19 made of Au are set to 0.3 to 0.
5 μm is desirable. If the thickness of the lower electrode 5, the upper electrode 7, the connection electrode 13, and the metal layer 19 is smaller than 0.3 μm, there is a possibility that a portion not covered by the film may be generated. If the thickness is larger than that, the resistance of the conductor layer hardly changes in consideration of the skin effect of the conductor in the high frequency region.

Here, the supporting substrate 1 is made of alumina,
Sapphire, aluminum nitride, MgO single crystal, SrTiO ₃
The material is selected from single crystal, surface silicon oxide, glass, quartz, and the like, and is not particularly limited.

The solder barrier layer 15 is made of Ti, Cr, Ni,
2 selected from Cu, Pd, Pt, and these metals
Any material may be used as long as it is made of any one or more alloys and can be formed by sputtering, vapor deposition, plating, or the like. The thickness of the solder barrier layer 15 may be 0.3 μm or more in order to exhibit a function as a solder barrier.

The solder adhesion layer 17 is preferably made of a material having good solder wettability.
There are Cr, Au and the like, and Au is particularly desirable. Further, in order to improve the adhesion between the solder barrier layer 15 and the connection electrode 13 and the upper electrode 7 made of Au, a known adhesion material such as Ti or Cr may be interposed between them.

The protective layer 9 is for protecting the surface of the thin film capacitor, for example, Si ₃ N ₄ , SiO ₂ ,
It is composed of a polyimide resin and BCB (benzocyclobutene).

External terminals 11a, 11 made of solder bumps
b is preferably composed of at least two metals of Pb, Sn, Ag, In, Cu, Bi, Sb, and Zn. Depending on the use of the thin-film electronic component, materials having different melting points and eutectic temperatures may be used. Just choose. External terminal 1
1a and 11b are formed by using a known technique such as screen printing and a ball mounter. In FIG. 1, the size of the external terminals 11 a and 11 b is described as not changing much with respect to the thickness of the insulator layer 3, but the external terminals 11 a and 11 b actually correspond to the thickness of the insulator layer 3. Very large.

In the thin film capacitor of the present invention, the supporting substrate 1
An Au film is formed on the upper surface by a DC sputtering method, a through hole 25 is formed at a position where the external terminal 11a is formed by using photolithography technology, and an annular through hole is formed around the position where the external terminal 11b is formed. And a through hole 2 having a smaller diameter than the through hole 23 inside the through hole 23 of the insulator layer 3.
8 is formed.

On the supporting substrate 1, for example, by a sol-gel method
Synthesized Pb (Mg_1/3Nb_2/3) O _Three-PbTiO_Three−P
bZrO_ThreeApply the coating solution using a spin coating method,
After drying, heat treatment and firing are performed to form the insulator layer 3
I do. Then, using photolithography technology, the insulator
A through hole 23 is formed in the insulator layer 3 at a position to be the layer non-formation region B.
The lower electrode 5 or the metal layer 19 is formed on the inner peripheral portion of the bottom surface.
Is exposed, and the through holes 25 and 28 are located in the center.
I do.

Next, an Au film is formed on the upper surface of the insulator layer 3 and the non-insulator layer forming region B, and the upper electrode 7 and the connection electrode 13 are formed by photolithography. The solder barrier layer 1 is formed on the surface of the electrode 13.
5. The solder adhesion layer 17 is formed.

Thereafter, a photosensitive BCB is applied, exposed,
Development is performed to form a protective layer 9 having a through hole so that the solder adhesion layer 17 is exposed.

Thereafter, a eutectic solder paste made of, for example, Pb or Sn is transferred onto the processed solder adhesive layer 17 by screen printing, and reflow is performed, so that the external terminals 11a and 11b made of solder bumps are transferred. Is formed, the thin film capacitor of the present invention is obtained.

In the thin film capacitor configured as described above, the connection electrode 13 and the upper electrode 7 formed after the formation of the insulator layer 3 are directly or an adhesion layer that forms a part of the connection electrode 13 and the upper electrode 7. The connection electrode 13 and the upper electrode 7 do not go through a high-temperature process when the insulating layer 3 is formed, so that the adhesion between the connection electrode 13 and the upper electrode 7 and the support substrate 1 does not go through. Does not deteriorate. for that reason,
The external terminals 11 made of solder bumps provided on the support substrate 1 via the solder adhesion layer 17, the solder barrier layer 15, and the connection electrode 13 or the upper electrode 7 can exhibit the maximum strength, and the mounting reliability is improved. improves.

The material of the lower electrode 5 and the upper electrode 7 according to the present invention is a material made of Au which has low resistance, high oxidation resistance at high temperature and small reaction with the dielectric material. In order to improve the adhesion to the substrate 1, an adhesion layer typified by Ti or Cr may be interposed between the electrodes 5, 7 and the support substrate 1. In this case, the adhesion layer forms a part of the electrodes 5 and 7.

In the above example, the external terminal 11b is provided on the support substrate 1 via the upper electrode 7 in the through hole 28 formed in the metal layer 19, but the external terminal 11b is not necessarily formed on the support substrate 1. It is not necessary to overlap the metal layer 19 and the upper electrode 7.

Here, an example in which the present invention is applied to the thin film capacitor shown in FIG. 1 has been described. However, the present invention is not limited to the above example. For example, a thin film inductor, a thin film LC filter, a thin film resistor, etc. , Thin film RC filter or thin film capacitor, thin film inductor, thin film L
The present invention may be applied to a thin film composite component in which a C filter, a thin film resistor, and a thin film RC filter are combined.

In the above example, a single-plate type in which one insulating layer is sandwiched between electrodes has been described, but a thin-film capacitor in which a plurality of insulating layers and electrode layers are alternately stacked may be used.

Further, in the thin-film electronic component of the present invention, an example in which the external terminals 11a and 11b made of solder bumps are provided has been described. Can be changed.

For example, when no solder bumps are formed, as shown in FIG. 3, the solder adhesion layer 17 exposed in the through hole of the protective layer 9 becomes an external terminal. Note that FIG. 3 is the same as FIG. 1 except that no external terminals made of solder bumps are provided, and thus the same reference numerals are given.

In this case, the surface electrode of the mother board and the solder contact layer 17 are connected by a conductive member at the stage of mounting on the mother board. The conductive member may be in a bump shape, a foil shape, a plate shape, a wire, a paste shape, or the like, and is not particularly limited. A plurality of shapes may be combined.
The materials are Pb, Sn, Au, Cu, Pt, Pd,
There are Ag, Al, Ni, Bi, In, Sb, Zn, etc., as long as they are conductive, and a plurality of materials may be combined. It may be a conductive resin.

When the solder adhesion layer 17 is not formed, or when a metal layer is formed on the upper surface of the solder adhesion layer 17, the layer exposed in the through hole of the protective layer 9 becomes an external terminal.

[0055]

EXAMPLE An electrode, a solder barrier layer and a solder adhesion layer were formed by a DC sputtering method, and a dielectric thin film (insulator layer) was formed by a sol-gel method.

First, Ti is placed on a support substrate made of alumina.
Was formed, and a 0.3 μm Au layer was formed on the upper surface of the adhesion layer to form a lower electrode composed of the adhesion layer and the Au layer.

Using a photolithography technique, in addition to the lower electrode pattern to be a thin film capacitor, a portion (metal layer) without the lower electrode is formed annularly around the external terminal provided on the upper electrode, and The lower electrode and the metal layer are exposed at the inner peripheral portion of the bottom surface of the through hole (the region where the insulator layer is not formed) of the dielectric thin film to be formed next, and the lower portion is formed so that the through hole is formed at the center. The side electrodes were patterned.

On the processed lower electrode, Pb (Mg _1/3 Nb _2/3 ) O ₃ -PbTiO ₃ -Pb synthesized by the sol-gel method was used.
A ZrO ₃ coating solution is applied by spin coating, dried, and then heat-treated at 380 ° C. and baked at 815 ° C. to form 0.7 μm-thick Pb (Mg _1/3 Nb _2/3 ) O _3. −P
to form a dielectric thin film made bTiO ₃ -PbZrO _3. Thereafter, through holes were formed in the dielectric thin film by using a photolithography technique, and the lower electrode layer and the metal layer were exposed at the inner peripheral portion of the bottom surface.

Next, a 30 nm-thick Ti adhesion layer is formed on the top surface of the dielectric thin film and the bottom of the through hole, and a 0.3 μm-thick Au film is formed on this adhesion layer. The Au film and the adhesion layer were processed using a lithography technique to form an upper electrode and a connection electrode.

Thereafter, a solder barrier layer made of Ni having a thickness of 2.0 μm is formed, and thereafter, a solder adhesion layer Au having a thickness of 0.1 μm is formed, and processed into a shape having a diameter of 120 μm by photolithography. did.

Thereafter, a photosensitive BCB is applied, exposed,
Development was performed to form a protective layer having a through hole with a diameter of about 100 μm and a depth of 4 μm so that the solder adhesion layer made of Au was exposed.

Finally, a high-temperature solder paste containing 95% by weight of Pb and 5% by weight of Sn was transferred onto the processed solder adhesion layer by screen printing, and reflow was performed. Terminals were formed to obtain a thin film capacitor as shown in FIG.

The effective electrode area of the obtained thin film capacitor was 1.4 mm ² , and the capacitance at a frequency of 1 kHz was about 40 nF.

Further, in order to examine the effect of the contact area between the connection electrode and the support substrate, the area of the insulating layer non-formation region (through hole) was changed in the same manner as above except that the pattern of the lower electrode was changed. The cross-sectional area of the connecting electrode and the lower electrode was changed to obtain a thin film capacitor having a different overlapping area.

A destruction mode was observed when an excessive load was applied to the external terminals made of solder bumps of the obtained thin film capacitor and the external terminals were intentionally peeled off.
It was shown to.

In FIG. 4, the thin film destruction is one of the destruction modes, and means, for example, that destruction has occurred at the interface between the support substrate and the connection electrode. Similarly, solder breakdown means that the solder bump itself is broken. The destruction mode when the strength of the solder bump is maximized is solder destruction, which can be said to be an ideal destruction mode. According to the result, it is understood that when the overlapping area is large, the breakdown mode of the thin film is increasing, and when the overlapping area is 10% or less, the solder breakdown occurs in 90% or more of the external terminals.

As a comparative example, the lower electrode is entirely formed on the bottom surface of the through hole of the insulator layer without forming the through hole in the lower electrode in the through hole formed in the insulator layer as in the related art. When a connection electrode is formed on the upper surface of the lower electrode, the thin film is broken due to the tendency shown in FIG. 4, and the lower electrode undergoes a high-temperature process. When the external terminals made of the solder bumps fixed to the support substrate via the lower electrode are bonded to the electrodes of the mother substrate, the external terminals are easily peeled off from the support substrate, It is understood that the bonding strength of the thin film capacitor to the motherboard (base) is low.

[0068]

According to the present invention, since the connection electrode formed after the formation of the insulator layer is provided directly on the support substrate, the connection electrode and the support substrate are not interposed via the lower electrode that has undergone the high-temperature process. The adhesion strength does not deteriorate. Therefore, for example, the adhesion strength of an external terminal formed of a solder bump provided on a support substrate via a solder adhesion layer, a solder barrier layer and a connection electrode or an upper electrode is good, and the strength of the external terminal is maximized. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a thin-film electronic component of the present invention.

FIG. 2 is an explanatory diagram showing a superposed state of a connection electrode and a lower electrode and a superposed state of an upper electrode and a metal layer.

FIG. 3 is a cross-sectional view showing the thin-film electronic component of the present invention when a solder adhesion layer becomes an external terminal.

FIG. 4 is a graph showing a ratio of a destruction mode according to a ratio of an overlapping area of a connection electrode and a lower electrode to a cross-sectional area of a through hole.

FIG. 5 is a schematic sectional view showing a conventional thin film electronic component.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Support substrate 3 ... Insulator layer 5 ... Lower electrode 7 ... Upper electrode 11a, 11b ... External terminal 13 ... Connection electrode 21, 27 ... Lower electrode Unformed portion 23 ... through-hole

Claims (4)

[Claims] 1. A support substrate, a lower electrode formed on a part of the support substrate, an insulator layer formed on the lower electrode, and an upper electrode formed on the insulator layer And a connection electrode formed on the support substrate located on the bottom surface of the through hole formed in the insulator layer, and electrically connected to the lower electrode,
An external terminal provided on a connection electrode in the through hole. 2. The thin-film electronic component according to claim 1, wherein the connection electrode and the lower electrode overlap at an inner peripheral portion of the bottom surface of the through hole. 3. The overlapping area of the connecting electrode and the lower electrode is 1 to 10% of the cross-sectional area of the through hole.
The thin film electronic component according to the above. 4. A substrate comprising the thin-film electronic component according to claim 1 provided on a surface of a base via external terminals thereof.