JP2002319857A - Level conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level conversion circuit that can suppress fluctuations in a duty factor caused by dispersion in circuit components. SOLUTION: A differential amplifier amplifies pulse signals at an ECL(Emitter Coupled Logic) level at input terminals 12, 13 as pulse signals at a CMOS level, which are outputted from an output terminal 11. A low threshold level buffer circuit 184 receives a voltage at a node 91 at a threshold level lower than a threshold value of an inverter circuit 10. A delay circuit 183 delays an output of the low threshold level buffer circuit 184 by a sufficiently long delay time and an inverter circuit 181 outputs the delayed output to an NAND circuit 181. A high threshold value inverter circuit 185 receives the voltage at the node 91 at a threshold level higher than the threshold value of the inverter circuit 10 and lower than a level after transition. The NAND circuit 181 NANDs outputs from the low threshold level buffer circuit 184, the delay circuit 183 and the high threshold value inverter circuit 185 and provides an output to a gate of an N-channel MOS transistor 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level conversion circuit,
In particular, the present invention relates to an ECL-CMOS level conversion circuit that converts a signal at an ECL level to a signal at a CMOS level and that can handle a high-frequency signal.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, as one means for enabling a high-speed operation, an internal circuit operation can be performed at a higher speed than an operation at an external level, for example, at an ECL level. For example, a method of converting to a CMOS level may be adopted. In this case, a level conversion circuit such as an ECL-CMOS conversion circuit is used as a circuit for converting the internal level to the external level.

FIG. 5 shows an example of an ECL-CMOS conversion circuit (prior art 1) as a conventional level conversion circuit of this kind.
Is shown. This ECL-CMOS conversion circuit amplifies an ECL level signal input to a differential amplifier into a CMOS level signal and outputs the signal as a CMOS level signal from an output circuit. The differential amplifier performs differential operation 2
N channel MOS transistors 3 and 4, an N channel MOS transistor 5 having a drain commonly connected to the sources of N channel MOS transistors 3 and 4, and load resistors 1 and 2 of N channel MOS transistors 3 and 4. Is done.

An output circuit for extracting the output of the differential amplifier includes a P-channel MOS transistor 6 having a gate connected to the drain of an N-channel MOS transistor 4;
A load resistor 7 connected to the drain of a P-channel transistor 6, a P-channel MOS 8 having a gate connected to the drain of the N-channel MOS transistor 3, and a P-channel MOS having a drain connected to the drain of the P-channel MOS transistor 8 An N-channel MOS transistor 9 connected to the drain of the transistor 6 and an inverter circuit 10 for inverting and outputting the level of the drain of the P-channel MOS transistor 8 are provided.

The differential signal at the ECL level applied to the input terminals 12 and 13 is supplied to an N-channel MOS transistor
4 and a differential amplifier circuit composed of resistors 1 and 2. The inverted output for the input terminal 12 is the P channel M
When the signal is input to the OS transistor 8 and the input terminal 12 is at a higher level than the level of the input terminal 13, the P channel M
When the OS transistor 8 is turned on and at the low level, the P-channel MOS transistor 8 is turned off. On the other hand, the non-inverted output to the input terminal 12 is connected to the gate of the P-channel MOS transistor 6, and when the input of the input terminal 12 is higher than the level of the input terminal 13, the P-channel
OS transistor 6, N-channel MOS transistor 9
Are turned off, and when low, the P-channel MOS transistor 6 and the N-channel MOS transistor 9 are turned on.

As described above, the input terminal 12 is connected to the input terminal 1
3 is higher than the level of P channel M
The OS transistor 8 is turned on, the N-channel MOS transistor 9 is turned off, and the inverter circuit 10 outputs the low-level C
Outputs the MOS level. On the other hand, when the input terminal 12 is at a low level compared to the level of the input terminal 13, the P-channel MOS transistor 8 is turned off, the N-channel MOS transistor 9 is turned on, and the inverter circuit 10 outputs a high CMOS level. As a result, the input terminal 1
The ECL level signal input to 2, 13 can be converted into a CMOS level signal and output from an output terminal.

However, the circuit of the prior art 1 has a CMO
The time until the output signal of the S level rises is short because it is determined by the off time of the P-channel MOS transistor 8 operating in the saturation region. However, the time until the fall is low, the P-channel MOS transistor 6 operating in the linear conduction region. Is turned off, the N-channel MOS transistor 9 is turned off, and the time is determined by the time required for the potential of the node 91 to reach the threshold level of the inverter circuit 10, so the time becomes longer. Therefore, there is a problem that the fall time is slower than the rise time of the CMOS level output signal, and the influence on the duty fluctuation of the CMOS level output signal is increased.

In particular, since the fall time of the CMOS level output signal is determined by the operation time of the N-channel MOS transistor 9, it is easily affected by fluctuations in the threshold value of the N-channel MOS transistor 9. FIG. 6 is a time chart showing this state. The potential of node 61 to which the gate of N-channel MOS transistor 9 is connected is set to
Even if the voltage drops to the threshold value of 0, the potential of the node 91 is delayed by the time t until the potential of the node 91 reaches the threshold value of the inverter circuit 10 due to the threshold value of the N-channel MOS transistor 9, and therefore, the falling output of the inverter circuit 10 is also delayed by the time t. It indicates that you want to.

[0009] The conventional ECL-
FIG. 7 shows a CMOS conversion circuit (prior art 2). In this circuit, a P-channel MOS transistor 17 is connected in parallel with the P-channel MOS transistor 8 in the circuit of the prior art 1 shown in FIG. 5, and the drain of the P-channel MOS transistor 8 is used as an input. A gain adjustment circuit 20 for outputting to the gate is provided.

In the gain adjustment circuit 20, a P-channel MO
The drain (node 91) of the drain of the S transistor 8, the drain of the N-channel MOS transistor 9, and the input terminal of the inverter circuit 10 is connected to the input terminal of the low threshold buffer circuit 184, and the output terminal of the low threshold buffer circuit 184 is connected to the NAND circuit. 186 second input terminal and delay circuit 1
83, the output terminal of the delay circuit 183 is connected to the input terminal of the inverter circuit 182,
The output terminal of the inverter circuit 182 is connected to the NAND circuit 186
, And the output of the NAND circuit 186 is connected to the gate of the P-channel MOS transistor 17. The low threshold buffer circuit 184 operates at a level lower than the threshold of the inverter circuit 10.

When the node 91 maintains the high level, the output of the delay circuit 183 outputs a high level because the output of the low threshold buffer circuit 184 is at the high level, and the inverter circuit 182 outputs the low level to the NAND circuit 186. Is output. Since the low level is input to the NAND circuit 186, the NAND circuit 186 outputs a high level, and the P-channel MOS transistor 17 is off.

When a low-level ECL signal is input to the input terminal 12, the P-channel MOS transistor 8 is turned off and the potential of the node 91 changes from the high level to the low level as in the prior art 1, and the inverter circuit 10 changes the high level. Output. NA at the time of level transition in this case
Since there is no room for the ND circuit 186 to output a low level, the P-channel MOS transistor 17 remains off.

When the potential of the node 91 changes from the high level to the low level, the low threshold buffer 184 of the gain adjustment circuit 18 outputs a low level, and the low level is input to the second input terminal of the NAND circuit 186. , N
The output of the AND circuit 186 remains at the high level, the P-channel MOS transistor 17 maintains the off state, and performs the same operation as the circuit of the related art 1.

Next, a high-level ECL is input to the input terminal 12.
When a signal is input, P-channel MOS transistor 6 turns off and P-channel MOS transistor 8 turns on.
The potential of node 91 is at the level of P-channel MOS transistor 8
Is turned on, and after the P-channel MOS transistor 6 is turned off, the N-channel MOS transistor 9 is gradually turned off and becomes high.

At this time, since the threshold level of the low threshold buffer circuit 184 of the gain adjustment circuit 18 is set lower than the threshold level of the inverter circuit 10, before the inverter circuit 10 outputs the low level from the high level, the low level occurs. The threshold buffer circuit 184 outputs a low level to a high level. When the low threshold buffer circuit 184 outputs a low level to a high level, the NAND circuit 186 outputs a low level for the delay time set by the delay circuit 183.
When the NAND circuit 186 outputs a low level, the P-channel MOS transistor 17 is turned on, and the potential of the node 91 rises to the threshold level of the inverter circuit 10 faster than in the prior art. As a result, the inverter circuit 10 outputs the high level to the low level more quickly, and the time until the CMOS level output signal falls can be made shorter than that of the conventional circuit.

Further, P-channel MOS transistor 17
, The fall time of the CMOS level output signal can be shortened irrespective of the operation of N-channel MOS transistor 9. For the above reasons, the time required for the CMOS level output signal to fall can be shortened, so that it is possible to suppress the duty fluctuation due to the variation in manufacturing the circuit elements.

FIG. 8 is a time chart showing this state. The gain of the P-channel MOS transistor 17 is adjusted by the low threshold buffer circuit 184 of the gain adjustment circuit 20 so that the potential of the node 91 becomes the threshold of the low threshold buffer circuit 184. After that, the duty of the CMOS level output signal is improved by quickly rising to the threshold level of the inverter circuit 10.

[0018]

However, in the prior art 2 described above, the P-channel MOS transistor 17
Is controlled by the delay time of the delay circuit 183, the delay time fluctuates due to manufacturing variations of the delay circuit 183, and the duty fluctuation suppression operation does not occur, or a malfunction in high-frequency operation occurs. There is a problem.

Regarding this problem, the inverter circuit 10
Output a low-level CMOS level output signal with reference to FIGS. 9 and 10.
9 shows a state of a malfunction when the delay time of the delay circuit 183 is short, and FIG. 10 shows a state of a malfunction when the delay time is long.

As shown in FIG. 9, when the delay time of delay circuit 183 is too short, the low-level time of the output of NAND circuit 186 that turns on P-channel MOS transistor 17 becomes short, and the potential of node 91 becomes low. Since the P-channel MOS transistor 17 is turned off before it rises to the threshold voltage of 10, the time until the output signal of the inverter circuit 10 falls does not become short, and the duty is not improved.

Further, as shown in FIG.
The case where the delay time of No. 3 is too long will be described. In this case, P channel MOS transistor 17 is turned on.
The low level time of the output of the AND circuit 186 becomes longer.
Originally, when the next low-level ECL signal is input to the input terminal 12, the potential of the node 91 becomes low and the inverter circuit 10 should output a high level. But,
Even at this time, if the low level time of the output of NAND circuit 186 is long enough to keep the output of NAND circuit 186 low, P channel MOS transistor 17 remains on, and the potential of node 91 changes to the potential of inverter circuit 10. A malfunction occurs in the high-frequency operation without being lower than the threshold voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to provide a level conversion circuit which eliminates fluctuations in duty due to variations in manufacturing circuit elements.

It is a second object of the present invention to provide a level conversion circuit which can operate at high speed.

[0024]

A level conversion circuit according to the present invention includes a first N-channel MOS transistor (3 in FIG. 1) and a second N-channel MOS transistor (3 in FIG. 1) for performing differential amplification by inputting an ECL level pulse signal. 1) 4), a differential amplifier having a third N-channel MOS transistor (5 in FIG. 1) in which the drains are commonly connected to the sources of the first and second two N-channel MOS transistors;
A first P-channel MOS transistor (6 in FIG. 1) having a drain connected to the gate of the N-channel MOS transistor; a second P-channel MOS (8 in FIG. 1) having a gate connected to the drain of the first N-channel MOS transistor; The drain is connected to the drain of the second P-channel MOS transistor, and the gate is connected to the first P-channel MOS transistor.
A fourth N-channel MOS transistor (9 in FIG. 1) connected to the drain of the S transistor;
Third P-channel MO connected in parallel with OS transistor
An S transistor (17 in FIG. 1) and a second P-channel MO
Invert the level of the drain of the S transistor to
An output circuit having an inverter circuit (10 in FIG. 1) for outputting a pulse signal of a level;
A low-threshold buffer circuit (184 in FIG. 1) having as input the drain of the OS transistor, the drain of the fourth N-channel MOS transistor, and the input terminal of the inverter circuit and having a threshold lower than the threshold of the inverter circuit; High threshold inverter circuit having a threshold higher than the threshold of the transition and lower than the level after the transition (1 in FIG. 1)
85), a delay circuit (183 in FIG. 1) for sufficiently delaying the output of the low threshold buffer circuit, a delay inverter circuit (182 in FIG. 1) for inverting and outputting the output of the delay circuit, a low threshold buffer circuit, and a delay. The third P channel M is calculated by taking the logical product of the outputs of the inverter circuit and the high threshold value inverter circuit.
A NAND circuit (181 in FIG. 1) that outputs to the gate of the OS transistor; and a gain adjustment circuit (18 in FIG. 1).

According to the level circuit of the present invention, a high threshold value inverter circuit is provided in a gain amplifying circuit, and the gain adjustment is adjusted not by time but by voltage, thereby improving output level duty deterioration and improving high-speed operation. To achieve.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A level conversion circuit according to the present invention provides an output circuit which amplifies an internal level pulse signal input to a differential amplifier into an external level pulse signal and outputs the amplified signal when an output pulse signal transitions. A gain adjustment circuit provided with a means for accelerating the transition and a means for canceling the acceleration means before the end of the transition is added.

More specifically, an ECL-level pulse signal input to a differential amplifier having a MOS transistor configuration is input to a C
A low-threshold buffer circuit having a threshold level lower than the threshold level of the inverter circuit for inputting the voltage of the input node of the inverter circuit to an output circuit of a MOS transistor configuration which amplifies the pulse signal at the MOS level and outputs the signal from the inverter circuit; A delay circuit that sufficiently delays the output of the threshold buffer circuit, a delay inverter circuit that inverts and outputs the output of the delay circuit, and an inverter circuit that inputs a voltage at an input node of the inverter circuit after a transition higher than the threshold level of the inverter circuit. A gain adjusting circuit configured by a high threshold inverter circuit having a threshold level lower than the level, and a NAND circuit for performing an AND operation of a low threshold buffer circuit, a delay inverter circuit, and a high threshold inverter circuit, and controlling transition of a voltage waveform at an input contact Is added.

FIG. 1 shows an embodiment of the present invention. FIG.
, Three N-channel MOS transistors 3, 4
And 5 and two resistors 1 and 2 amplify the ECL level pulse signal input to input terminals 12 and 13. The output of this differential amplifier is 3
P-channel MOS transistors 6, 8 and 17
, An N-channel MOS transistor 9, a resistor 7, and an inverter circuit 10
It is output from the output terminal 11 as an OS level pulse signal. A feature of the present invention is that a gain adjustment circuit 18 having two inputs at a connection node (node 91) of P-channel MOS transistors 8, 17, an N-channel MOS transistor 9, and an inverter circuit 10 is provided. 17 is to be adjusted.

[0029]

Next, an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention. Similarly to the ECL-CMOS conversion circuits shown in FIGS. 5 and 7, the ECL-CMOS conversion circuit shown in FIG. 2 amplifies an ECL level signal input to the differential amplifier into a CMOS level signal, and To output as a CMOS level signal. The differential amplifier includes two N-channel MOS transistors 3 and 4 performing a differential operation,
N-channel MOS transistor 5 whose drains are commonly connected to the sources of N-channel MOS transistors 3 and 4
And load resistors 1 and 2 of N-channel MOS transistors 3 and 4, respectively.

An output circuit for taking out the output of the differential amplifier includes a P-channel MOS transistor 6 having a drain connected to the gate of the N-channel MOS transistor 4;
A load resistor 7 connected to the drain of a P-channel transistor 6, a P-channel MOS 8 having a gate connected to the drain of the N-channel MOS transistor 3, and a P-channel MOS having a drain connected to the drain of the P-channel MOS transistor 8 An N-channel MOS transistor 9 connected to the drain of the transistor 6 and an inverter circuit 10 for inverting and outputting the level of the drain of the P-channel MOS transistor 8 are provided.

Further, a P-channel MOS transistor 17 is connected in parallel with the P-channel MOS transistor 8, and a gain adjustment circuit 18 is provided which receives the drain of the P-channel MOS transistor 8 as an input and outputs to the gate of the P-channel MOS transistor 17. ing.

First, the gain adjustment circuit 18 serves as a black box to clarify the above connection relationship. The N-channel MOS transistor 3 on one input side of the differential amplifier circuit has a gate connected to the input terminal 12, a drain connected to the first input terminal of the resistor 1, and a gate of the P-channel MOS transistor 8, and a source connected. Connected to the source of N-channel MOS transistor 4 and the drain of N-channel MOS transistor 5. The N-channel MOS transistor 4 on the other input side of the differential amplifier has a gate connected to the input terminal 13, and a drain connected to the first input terminal of the resistor 2 and the gate of the P-channel MOS transistor 6. A second input terminal of the resistor 1 and the resistor 2 is a power terminal 1
5 respectively. The N-channel MOS transistor 5 has a gate connected to the reference voltage input terminal 14 and a source connected to the GND terminal 16.

P channel M on one output side of the differential amplifier circuit
The OS transistor 6 has a drain connected to the first input terminal of the resistor 7 and the gate of the N-channel MOS transistor 9, and a source connected to the power supply terminal 15. The drain of the P-channel MOS transistor 8 on the other output side of the differential amplifier circuit is the drain of the N-channel MOS transistor 9, the drain of the P-channel MOS transistor 17,
Input terminal of inverter circuit 10 and gain adjustment circuit 18
And the source is connected to the power supply terminal 15.

The second terminal of the resistor 7 is connected to the GND terminal 16.
And the source of N-channel MOS transistor 9 is GND
A terminal 16 has a gate of a P-channel MOS transistor 17 connected to an output terminal of a gain adjustment circuit 18 and an inverter circuit 1
0 output terminals are connected to the output terminals 11 respectively.

The gain adjustment circuit 18 includes a low threshold buffer circuit 184, a delay circuit 183, an inverter circuit 182, and an NA.
It comprises an ND circuit 181 and a high threshold inverter circuit 185. That is, the gain adjustment circuit 18 is provided in the gain adjustment circuit 20 shown in FIG.
Is added.

In the gain adjustment circuit 18, a P-channel MO
A node (node 91) of the drain of the S transistor 8, the drain of the N-channel MOS transistor 9, and the input terminal of the inverter circuit 10 is connected to the input terminals of the low threshold buffer circuit 184 and the high threshold inverter circuit 185,
The output terminal of the high threshold inverter circuit 185 is connected to the second input terminal of the NAND circuit 181, and the output terminal of the low threshold buffer circuit 184 is connected to the second input terminal of the NAND circuit 181 and the input terminal of the delay circuit 183, respectively. The output terminal of the delay circuit 183 is connected to the input terminal of the inverter circuit 182, and the output terminal of the inverter circuit 182 is connected to the NA.
Connected to the first input terminal of ND circuit 181, the output of NAND circuit 181 is connected to the gate of P-channel MOS transistor 17.

The low threshold buffer circuit 184 operates at a threshold level lower than the threshold level of the inverter circuit 10, and the high threshold inverter circuit 185 operates at a threshold level higher than the threshold level of the inverter circuit 10 and lower than the level after the level transition. Further, the delay time of the delay circuit 183 is set to be sufficiently long so as not to cause the first problem in the related art as described with reference to FIG.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG.

The ECL level differential signal applied to the input terminals 12 and 13 is
4 and a differential amplifier circuit composed of resistors 1 and 2. The inverted output of the differential amplifier with respect to the input terminal 12 is input to the P-channel MOS transistor 8, and when the input terminal 12 is at a lower level than the input terminal 13, the P-channel MOS transistor 8 is turned off and the potential of the node 91 is at the low level. And the inverter circuit 10 outputs a high level. At this time, the output terminal of the gain adjustment circuit 18 outputs a high level even if the potential of the node 91 changes from a high level to a low level. Therefore, the P channel M
The OS transistor 17 remains off. Next, when a high-level ECL signal is input to the input terminal 12, the P-channel MOS transistor 6 is turned off and the P-channel M
The OS transistor 8 turns on.

After the P-channel MOS transistor 8 is turned on and the P-channel MOS transistor 6 is turned off, the potential of the node 91 becomes higher because the N-channel MOS transistor 9 is gradually turned off. When a voltage set lower than the threshold voltage of the inverter circuit 10 is input to the first input terminal, the gain adjustment circuit 18 outputs a low level from the output terminal and turns on the P-channel MOS transistor 17. When the P-channel MOS transistor 17 is turned on,
The potential of the node 91 quickly becomes the threshold level of the inverter circuit 10, and the inverter circuit 10 outputs a low level, shortens the time until the fall of the CMOS level output signal, and suppresses the duty deterioration. Thereafter, when a voltage at which the potential of the node 91 is set higher than the threshold voltage of the inverter circuit 10 is input to the second input terminal, the gain adjustment circuit 18 turns off the P-channel MOS transistor 17 and returns to the normal operation state. Become.

Next, the operation of this embodiment will be described with reference to a time chart shown in FIG.

The ECL level differential signal applied to the input terminals 12 and 13 is
4 and a differential amplifier circuit composed of resistors 1 and 2. The inverted output for the input terminal 12 is the P channel M
When the signal is input to the OS transistor 8 and the input terminal 12 is at a higher level than the level of the input terminal 13, the P channel M
When the OS transistor 8 is turned on and at the low level, the P-channel MOS transistor 8 is turned off. On the other hand, the non-inverted output to the input terminal 12 is connected to the gate of the P-channel MOS transistor 6, and when the input of the input terminal 12 is higher than the level of the input terminal 13, the P-channel MOS transistor 6 and the N-channel MOS transistor 9 is turned off, and when low, the P-channel MOS transistor 6 and the N-channel MOS transistor 9 are turned on.

As described above, the input terminal 12 is the input terminal 1
3 is higher than the level of P channel M
The OS transistor 8 is turned on, the N-channel MOS transistor 9 is turned off, and the inverter circuit 10 outputs the low-level C
Outputs the MOS level. On the other hand, when input terminal 12 is at a low level compared to the level of input terminal 13, P-channel MOS transistor 8 is turned off, N-channel MOS transistor 9 is turned on, and inverter circuit 10 outputs a high-level CMOS level. As a result, the input terminal 1
The ECL level signal input to 2, 13 can be converted into a CMOS level signal and output from an output terminal.

Now, if the level of the input terminal 12 is the input terminal 1
While the ECL signal of a low level is input compared to the level 3 (part A in FIG. 3), the P-channel MOS transistor 8 is turned off, and the potential of the node 91 is at the low level.
At this time, the low threshold buffer circuit 18 of the gain adjustment circuit 18
4 outputs a low level, and the low level is input to the NAND circuit 181. Therefore, the output of the NAND circuit 181 is at the high level, and the P-channel MOS transistor 17 maintains the off state.

When the ECL signal at the input terminal 12 changes from low level to high level (part B in FIG. 3), the P-channel MOS transistor 6 turns off and the P-channel MOS transistor 8 turns on. After the P-channel MOS transistor 8 is turned on and the P-channel MOS transistor 6 is turned off, the potential of the node 91 is gradually turned off and the N-channel MOS transistor 9 is turned off.

At this time, the low threshold buffer circuit 184 of the gain adjustment circuit 18 outputs a high level to the NAND circuit 181 before the inverter circuit 10 outputs a low level from a high level. This is because the low threshold buffer circuit 184
Is set lower than the threshold level of the inverter circuit 10. When the low threshold buffer circuit 184 outputs a high level, the inverter circuit 1
82 outputs a high level to the NAND circuit 181 with a delay by the delay time of the delay circuit 183. Further, the high-threshold inverter circuit 185 also changes the high level of the NAND circuit 1 since the level of the node 91 has not reached the high threshold at this time.
81.

As a result, the NAND circuit 181 outputs a low level to the P-channel MOS transistor 17 because a logical product is established. Then, P-channel MOS transistor 17 is turned on, the potential of node 91 rises to the threshold level of inverter circuit 10 more quickly, and the time until the CMOS level output signal falls can be shortened. In fact, referring to part B of FIG. 3, it can be seen that the rise in the potential of the node 91 is accelerated in response to the fall of the output of the NAND circuit 181.

Next, when the potential of the node 91 rises to the threshold level of the high threshold inverter circuit 185, the high threshold inverter circuit 185 outputs a low level. Then
NAND circuit 181 outputs a high level to turn off P-channel MOS transistor 17 to return to a normal operation state. Therefore, the rising timing of the output of the NAND circuit 181 has no relation to the delay time of the delay circuit 183, so that the second problem in the related art described with reference to FIG. 10 does not occur. That is, the rise of the output of the NAND circuit 181 is delayed due to the variation of the delay time, and the next ECL signal (low level) is input, and the node 91 should be at the low level.
The channel MOS transistor 17 does not turn off and the node 9
An attempt to maintain 1 at a high level can be eliminated by the low level output from the high threshold inverter circuit 185.

At this time, the threshold level of high-threshold inverter circuit 185 is set to such a level that the potential of node 91 does not become lower than the threshold level of inverter circuit 10 even if P-channel MOS transistor 17 is turned off.
3, the potential of the node 91 once drops in response to the output fall of the NAND circuit 181, but does not reach the threshold level of the inverter circuit 10.

While the node 91 maintains the high level (C in FIG. 3), since the output of the low threshold buffer circuit 184 is at the high level, the delay circuit 183 outputs the high level and the inverter circuit 182 outputs the high level. Outputs low level. Further, the high threshold inverter circuit 185 also outputs a low level. As a result, the NAND circuit 181 outputs a high level, and the P-channel MOS transistor 17 is off.

When the ECL signal of the input terminal 12 transitions from the high level to the low level (part D in FIG. 3), the node 91
Changes from the high level to the low level. When the potential of the node 91 becomes lower than or equal to the threshold level of the high threshold inverter circuit 185, the high threshold inverter circuit 185 outputs a high level to the NAND circuit 181, and the low threshold buffer circuit 184 also outputs a high level to the NAND circuit 181. ing. However, in this time zone, the high level output from the low threshold buffer circuit 184 is input to the delay inverter circuit 182 by the delay circuit 182, and the delay inverter circuit 182 outputs a low level to the NAND circuit 181. Transistor 17 remains off. Further, when the potential of the node 91 drops below the threshold value of the low threshold buffer circuit 184, the low threshold buffer circuit 184 outputs a low level instead of the delay inverter circuit 182, and the output of the NAND circuit 181 remains at the high level. Therefore, P-channel MOS transistor 17 maintains the off state.

As described above, when the potential of the node 91 reaches the threshold level of the low threshold buffer circuit 184, the P-channel MOS transistor 17 is turned on to adjust the gain and shorten the time until the inverter circuit 10 falls. . Next, when the potential of the node 91 reaches the threshold value of the high threshold value inverter circuit 185, the P-channel MOS transistor 17 is turned off to terminate the gain adjustment, and return to the normal operation. That is, the control for turning on the P-channel MOS transistor 17 and adjusting the gain is performed by setting the potential of the node 91 to the gain adjustment circuit 18.
Are controlled by the voltage set at the first input terminal and the voltage set at the second input terminal.

As described above, since the control time of the P-channel MOS transistor 17 is determined by the two threshold levels of the low threshold value of the low threshold value buffer circuit 184 and the high threshold value of the high threshold value inverter circuit 185, it is used in the gain adjustment circuit 18. Regardless of the variation in the delay time of the delay circuit 183,
The malfunction can be prevented by suppressing the duty fluctuation, and the high-speed operation can be performed.

Further, P-channel MOS transistor 17
Is turned on while the node 91 is in the low threshold value buffer circuit 1.
Since it is set by the time from the threshold level of 84 to the threshold level of the high threshold inverter circuit 185, by making the circuit configuration of the low threshold buffer circuit 184, the high threshold inverter circuit 185, and the inverter circuit 10 the same,
The difference voltage of the threshold level of each circuit can be made constant,
It is possible to reduce the influence of device fluctuation.

Although the embodiment described above is a level conversion circuit in which a differential amplifier is constituted by N-channel MOS transistors, the present invention is not limited to this.
As shown in (1), the present invention is also applied to a level conversion circuit in which a differential amplifier is constituted by P-channel MOS transistors. In FIG. 4, the polarities of all the MOS transistors including the output circuit and the positions of the resistors with respect to the power supply are opposite to those in FIG. 2, and the position of the gain adjustment circuit is also different. For convenience, the same reference numbers are used.

[0057]

According to the present invention, in a gain adjustment circuit for accelerating a transition at the time of a level transition of an output pulse waveform of an output circuit with respect to a differential amplifier, the acceleration of the transition is canceled before the transition of the output pulse waveform ends. Since the means is provided and the means is controlled by the voltage in the same manner as the accelerating means, it is possible to obtain an effect of improving the duty deterioration of the output signal due to the variation in manufacturing the circuit element and realizing the high-speed operation. This effect can be enhanced by using the same circuit configuration for the acceleration unit and the cancellation unit.

[Brief description of the drawings]

FIG. 1 is a circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment shown in FIG. 1;

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional technique

FIG. 6 is a time chart showing the operation of the conventional technique 1;

FIG. 7 is a circuit diagram showing prior art 2

FIG. 8 is a time chart showing the operation of the conventional technique 2;

FIG. 9 is a time chart showing a state of a first problem in the related art 2.

FIG. 10 is a time chart showing a state of a second problem in prior art 2;

[Explanation of symbols]

 1, 2, 7 Resistance 3, 4, 5, 9 N-channel MOS transistor 6, 8, 17 P-channel MOS transistor 10, 182 Inverter circuit 11 Output terminal 12, 13 Input terminal 14 Reference voltage input terminal 15 Power supply terminal 16 GND terminal 18, 20 Gain adjustment circuit 181, 186 NAND circuit 183 Delay circuit 184 Low threshold buffer circuit 185 High threshold inverter circuit

Claims (4)

[Claims] An output circuit for amplifying an internal-level pulse signal input to a differential amplifier into an external-level pulse signal and outputting the amplified signal is a means for accelerating the transition when the level of the output pulse signal transitions, and ending the transition. A gain adjustment circuit provided with means for canceling the acceleration means before performing the operation. 2. An MO that amplifies an ECL level pulse signal input to a MOS transistor configuration differential amplifier into a CMOS level pulse signal and outputs the amplified signal from an inverter circuit.
A low threshold buffer circuit having a threshold level lower than a threshold level of the inverter circuit for inputting a voltage of an input node of the inverter circuit to an output circuit having an S transistor configuration; and a delay circuit for sufficiently delaying an output of the low threshold buffer circuit. A delay inverter circuit for inverting and outputting the output of the delay circuit; and a high threshold inverter circuit having a threshold level higher than a threshold level of the inverter circuit for inputting a voltage at an input node of the inverter circuit and lower than a post-transition level. And a NAND circuit that performs a logical product of the low threshold buffer circuit, the delay inverter circuit, and the high threshold inverter circuit, and further includes a gain adjustment circuit that controls transition of a voltage waveform at the contact point. Level conversion circuit. 3. A first N-channel MOS transistor for inputting an ECL level pulse signal and performing differential amplification,
A differential amplifier having an N-channel MOS transistor, a third N-channel MOS transistor having a drain commonly connected to the sources of the two N-channel MOS transistors, and a differential amplifier having a drain connected to the gate of the second N-channel MOS transistor A first P-channel MOS transistor, a second P-channel MOS having a gate connected to a drain of the first N-channel MOS transistor;
A fourth N-channel MOS transistor having a drain connected to the drain of the P-channel MOS transistor and a gate connected to the drain of the first P-channel MOS transistor; a third P-channel MOS transistor connected in parallel with the second P-channel MOS transistor; An output circuit having an inverter circuit for inverting the level of the drain of the second P-channel MOS transistor and outputting a CMOS level pulse signal; a drain of the second and third P-channel MOS transistors; A low-threshold buffer circuit having a drain and a node between the input terminals of the inverter circuit as inputs, and a low-threshold buffer circuit having a threshold lower than the threshold of the inverter circuit; A high threshold inverter circuit having a lower threshold, a delay circuit for sufficiently delaying the output of the low threshold buffer circuit, a delay inverter circuit for inverting and outputting the output of the delay circuit, the low threshold buffer circuit, and the delay inverter And a NAND circuit for performing a logical product of the outputs of the high-threshold inverter circuit and outputting the logical product to the gate of the third P-channel MOS transistor. 4. A first P-channel MOS transistor for inputting an ECL level pulse signal and performing differential amplification,
A differential amplifier having a P-channel MOS transistor, a third P-channel MOS transistor having a drain commonly connected to the sources of the two P-channel MOS transistors, and a differential amplifier having a drain connected to the gate of the second P-channel MOS transistor A first N-channel MOS transistor, a second N-channel MOS having a gate connected to the drain of the first P-channel MOS transistor,
A fourth P-channel MOS transistor having a drain connected to the drain of the N-channel MOS transistor and a gate connected to the drain of the first N-channel MOS transistor, a third N-channel MOS transistor connected in parallel with the second N-channel MOS transistor, An output circuit having an inverter circuit for inverting the level of the drain of the second N-channel MOS transistor and outputting a CMOS-level pulse signal; the drains of the second and third N-channel MOS transistors and the fourth P-channel MOS transistor A low-threshold buffer circuit having a drain and a node between the input terminals of the inverter circuit as inputs, and a low-threshold buffer circuit having a threshold lower than the threshold of the inverter circuit; A high threshold inverter circuit having a lower threshold, a delay circuit for sufficiently delaying the output of the low threshold buffer circuit, a delay inverter circuit for inverting and outputting the output of the delay circuit, the low threshold buffer circuit, and the delay inverter And a NAND circuit for performing a logical product of the outputs of the high-threshold inverter circuit and outputting the result to the gate of the third N-channel MOS transistor.