JP2002318827A - 集積回路製造システム - Google Patents

集積回路製造システム

Info

Publication number
JP2002318827A
JP2002318827A JP2002035971A JP2002035971A JP2002318827A JP 2002318827 A JP2002318827 A JP 2002318827A JP 2002035971 A JP2002035971 A JP 2002035971A JP 2002035971 A JP2002035971 A JP 2002035971A JP 2002318827 A JP2002318827 A JP 2002318827A
Authority
JP
Japan
Prior art keywords
interconnect
interconnects
integrated circuit
capacitance
functional blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002035971A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002318827A5 (enExample
Inventor
C Miller Brian
ブライアン・シー・ミラー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2002318827A publication Critical patent/JP2002318827A/ja
Publication of JP2002318827A5 publication Critical patent/JP2002318827A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2002035971A 2001-02-14 2002-02-13 集積回路製造システム Withdrawn JP2002318827A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US783434 2001-02-14
US09/783,434 US6567966B2 (en) 2001-02-14 2001-02-14 Interweaved integrated circuit interconnects

Publications (2)

Publication Number Publication Date
JP2002318827A true JP2002318827A (ja) 2002-10-31
JP2002318827A5 JP2002318827A5 (enExample) 2005-07-21

Family

ID=25129237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002035971A Withdrawn JP2002318827A (ja) 2001-02-14 2002-02-13 集積回路製造システム

Country Status (3)

Country Link
US (1) US6567966B2 (enExample)
JP (1) JP2002318827A (enExample)
DE (1) DE10205559B4 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007286687A (ja) * 2006-04-12 2007-11-01 Mitsubishi Electric Corp 伝送特性解析装置及びプログラム

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7103863B2 (en) * 2001-06-08 2006-09-05 Magma Design Automation, Inc. Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
US6640331B2 (en) * 2001-11-29 2003-10-28 Sun Microsystems, Inc. Decoupling capacitor assignment technique with respect to leakage power
US6938234B1 (en) * 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7218491B2 (en) * 2002-12-23 2007-05-15 Intel Corporation Electrostatic discharge protection unit including equalization
US7823112B1 (en) 2003-05-30 2010-10-26 Golden Gate Technology, Inc. Method, software and system for ensuring timing between clocked components in a circuit
US7992122B1 (en) * 2005-03-25 2011-08-02 Gg Technology, Inc. Method of placing and routing for power optimization and timing closure
US7577933B1 (en) * 2006-11-17 2009-08-18 Sun Microsystems, Inc. Timing driven pin assignment
US8751999B2 (en) * 2011-07-05 2014-06-10 Fujitsu Limited Component placement tool for printed circuit board
US8935559B2 (en) * 2012-01-27 2015-01-13 Nvidia Corporation System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters
JP6089849B2 (ja) * 2013-03-22 2017-03-08 富士通株式会社 プログラム、情報処理装置および設計検証方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
JP2753263B2 (ja) * 1988-05-13 1998-05-18 株式会社日立製作所 半導体集積回路の自動配線方法
US5123107A (en) * 1989-06-20 1992-06-16 Mensch Jr William D Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto
US5287528A (en) * 1990-07-03 1994-02-15 National Instruments Corporation IEEE 488 interface for message handling method
US5306967A (en) * 1992-05-29 1994-04-26 Integrated Device Technology, Inc. Apparatus for improving signal transmission along parallel lines
US5687088A (en) * 1993-05-19 1997-11-11 Matsushita Electric Industrial Co., Ltd. Net list for use in logic simulation and back annotation method of feedbacking delay information obtained through layout design to logic simulation
US5481695A (en) * 1993-10-26 1996-01-02 Cadence Design Systems, Inc. System and method for estimating crosstalk between signal lines in a circuit
US5535133A (en) * 1995-02-09 1996-07-09 Unisys Corporation Method of fabricating IC chips with table look-up estimated crosstalk voltages being less than noise margin
JP3608832B2 (ja) * 1995-02-28 2005-01-12 富士通株式会社 自動配線方法および自動配線装置
GB9723440D0 (en) * 1997-11-06 1998-01-07 Int Computers Ltd Simulation model for a digital system
US6253359B1 (en) * 1998-01-29 2001-06-26 Texas Instruments Incorporated Method for analyzing circuit delays caused by capacitive coupling in digital circuits
US6175947B1 (en) * 1998-04-20 2001-01-16 International Business Machines Corporation Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization
US6185726B1 (en) 1998-06-03 2001-02-06 Sony Corporation System and method for efficiently designing integrated circuit devices
JP4560846B2 (ja) * 1998-07-23 2010-10-13 日本テキサス・インスツルメンツ株式会社 クロストーク防止回路
US6363516B1 (en) * 1999-11-12 2002-03-26 Texas Instruments Incorporated Method for hierarchical parasitic extraction of a CMOS design

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007286687A (ja) * 2006-04-12 2007-11-01 Mitsubishi Electric Corp 伝送特性解析装置及びプログラム

Also Published As

Publication number Publication date
DE10205559B4 (de) 2007-05-10
US20020112220A1 (en) 2002-08-15
DE10205559A1 (de) 2002-08-29
US6567966B2 (en) 2003-05-20

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