JP2002318572A - Image processor and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor capable of dealing with video signals different in screen size and format, and easily changing the effective term of an image without burdening a deflection circuit with a large load, and to provide an image display device using the processor. SOLUTION: Image signals which are put into a digital format are written into a dual port RAM 10 with a timing set by writing clock signals CKW that are generated in accordance with synchronizing signals. Then, the stored image signals are read with the timing set by reading clock signals CKR having the frequency different from that of the signals CKW being generated in accordance with the synchronizing signals. By conducting the above, a time axis conversion is conducted for the image signals and the scanning interval and the return line interval in an image display are appropriately controlled in accordance with the characteristics of the deflection circuit and the display device. Thus, the image processor can deal with video signals having different formats without burdening the deflection circuit with an excessive work load and the circuit constitution can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus which displays image signals having different screen sizes and which can handle image signals having different effective video periods, and an image display apparatus using the same.

[0002]

2. Description of the Related Art In order to display images having different screen dimensions in the horizontal direction in a television receiver, it is necessary to control a horizontal deflection driving current supplied to a horizontal deflection coil. FIG. 3 shows two screens having different horizontal sizes. FIG. 3A shows a display screen in which the size ratio between the horizontal and vertical directions of the screen is 4: 3, that is, the display screen of a normal television receiver. On the other hand, FIG.
This is a display screen in which the size ratio between the horizontal and vertical directions of the screen is 16: 9, and shows a display screen generally called a wide screen.

In order to display images having different horizontal dimensions as shown in FIG. 3 on the same display, it is necessary to control the moving distance of the electron beam differently in the horizontal direction. In order to realize this, it is necessary to change the amplitude of the driving current supplied to the horizontal deflection coil and change the strength of the magnetic field in the horizontal direction. That is, in order to support display screens having different horizontal dimensions, it is necessary to control the magnitude of the drive current supplied to the horizontal deflection coil in the display device. FIG. 4 exemplifies a video signal corresponding to the display screen shown in FIG. 3 and a driving current of the horizontal deflection coil. FIG.
(A) and (b) show the waveforms of the video signal and the drive current corresponding to the display screen of FIG. 3 (a), and FIG. 4 (c) and (d)
5A shows a waveform of a video signal corresponding to the display screen shown in FIG. 3B and a waveform of a driving current of the horizontal deflection coil.

As shown in FIG. 4, when the type of the video signal is different, the waveforms of the video signal and the deflection driving current for displaying the video signal are different. For example, even when one horizontal cycle of a video signal is the same as 1H, the period actually occupied by the video signal during one horizontal cycle, that is, the effective period of the video signal differs depending on the format of the video signal. Video signal to CRT
In the case of displaying on a display device such as the above, the valid period of the video signal corresponds to the scanning period of the electron beam, and the period from the end of the valid period to the next valid period is a retrace period for returning the scanning line to the scanning start position. Depending on the format of the video signal, the ratio of the scanning period and the retrace period in image display is different,
It is necessary to adjust the deflection circuit according to this ratio.

[0005]

Generally, in an image display device using a CRT, the amplitude of a drive current supplied to a horizontal deflection coil must be increased as the horizontal size of a display screen increases. For this reason, a circuit for handling a large voltage and a large current is required in the horizontal deflection circuit, and the circuit load is increased. To deal with this, the size of the horizontal deflection circuit is increased.

Further, when a display device is used in which the screen size is switched according to the format of the video signal, it is necessary to optimize the deflection circuit according to each screen display size. As described above, in each video signal format, the period occupied by the effective video signal in one horizontal cycle, that is, the ratio of the effective period is different. Needs to be changed.

Further, in order to display various formats of video signals having different numbers of scanning lines and frames, it is necessary to switch to a deflection circuit optimized according to each format. growing. Further, depending on the retrace period in the format, accurate display of an image may be difficult. For example, SM
Although the 1080 / 60p format, which is one of the signal formats standardized by the PTE, that is, the number of scanning lines in one frame is 1080 and the format of 60 frames per second is long, the effective period of the video signal is long. Since the line period is extremely short, in the conventional horizontal deflection circuit, all video signals are not normally displayed during the valid period, and for example, image folding occurs.
It is difficult to display all video signals without dropping them.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a large deflection circuit for a video signal having a short blanking period, which can support video signals having different screen sizes or formats. Without burdening
An object of the present invention is to provide an image processing apparatus capable of easily changing an effective period of an image and accurately displaying an image of the effective period, and an image display apparatus using the same.

[0009]

In order to achieve the above object, an image processing apparatus according to a first aspect of the present invention writes a digitized image signal at a timing set by a first clock signal. And a multi-port storage device for reading the image signal at a timing set by a second clock signal having a frequency different from that of the second clock signal.

In the present invention, preferably, a first clock generation circuit for generating the first clock signal in response to a synchronization signal indicating a cycle of the image signal, and the first clock generation circuit in response to the synchronization signal And a second clock generation circuit for generating two clock generation circuits.

In the present invention, preferably, the first clock generation circuit multiplies the synchronization signal by a first multiplication ratio and outputs the multiplied signal as the first clock signal. A second multiplying circuit for multiplying the synchronization signal at a second multiplying ratio and outputting the multiplied signal as the second clock signal;

In the present invention, preferably, the digitized image signal input serially is converted into parallel image data, and the converted parallel image data is converted at a timing set by the first clock signal. It further has a serial / parallel conversion circuit for outputting to the multiport storage device.

According to a second aspect of the present invention, there is provided an image processing apparatus comprising: an A / D converter for converting an input image signal into a digital signal; and a timing which sets the digitized image signal by a first clock signal. Write with
A multi-port storage device for reading out at a timing set by a second clock signal having a frequency different from the first clock signal.

The image display device according to a first aspect of the present invention writes a digitized image signal at a timing set by a first clock signal, and outputs a second image having a frequency different from that of the first clock signal. A multi-port storage means for reading the image signal at a timing set by the clock signal, and a read period for the image signal as a scan period in synchronization with a synchronization signal indicating the cycle of the image signal, and A deflection circuit for generating a deflection signal with a period until the synchronization signal is input as a retrace period, and an image display means for displaying an image signal read from the storage means on a scanning line controlled by the deflection signal. Having.

In the present invention, the image display means is preferably a picture tube (CRT) in which a drive current according to the deflection signal is supplied to a deflection coil.

Further, an image display device according to a second aspect of the present invention is an A / D converter for converting an input image signal into a digital signal.
A converter for writing the digitized image signal at a timing set by the first clock signal and a second signal having a frequency different from that of the first clock signal;
Multi-port storage means for reading out at a timing set by the clock signal, and a synchronizing signal indicating the cycle of the image signal, wherein a reading period of the image signal is a scanning period, and the next synchronizing signal after the end of the reading A deflection circuit that generates a deflection signal with a period until the input of the deflection signal as a flyback period, and image display means that displays an image signal read from the storage means on a scanning line controlled by the deflection signal.

[0017]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus or an image display apparatus according to the present invention. As illustrated, the image processing apparatus according to the present embodiment includes a multi-port memory, for example, a dual-port RAM (Random Acceses) having an input port and an output port, respectively.
s Memory) 10, clock generation circuits 20, 30, a serial / parallel conversion circuit 40, an A / D converter 50, an input switching circuit 60, a D / A converter 70, a deflection circuit 80, and a picture tube 90.

Hereinafter, the function and operation of each component of the image processing apparatus according to the present embodiment will be described with reference to FIG. The dual port RAM 10 has a clock input terminal C
The data input to the data input port D _in at set timing by the write clock signal CKW inputted to LK1 sequentially written into a predetermined storage area, and, by the read clock signal CKR which is input to the clock input terminal CLK2 The storage data is sequentially read from the storage area at the set timing, and the output port D
Output to _out .

The video data output from the output port D _out is converted into an analog video signal by, for example, a D / A converter. The converted video signal is output to a display device such as a CRT. Alternatively, the read video data may be output to another signal processing circuit, subjected to predetermined signal processing, and then output to a display device or a recording device.

The clock generation circuit 20 generates a synchronization signal SYN
A write clock signal CKW is generated according to C. On the other hand, the clock generation circuit 30 generates a read clock signal CKR according to the synchronization signal SYNC. The clock generation circuits 20 and 30 can be configured by, for example, multiplication circuits that multiply the synchronization signal SYNC by a predetermined multiplication ratio. Specifically, the multiplying circuit can be constituted by, for example, a PLL circuit provided with a frequency dividing circuit in a feedback loop. The frequency division ratio of the frequency dividing circuit is set according to the desired multiplication ratio.

The synchronization signal SYNC is, for example, a synchronization signal generated by a synchronization reproduction circuit (not shown). Incidentally, the synchronization signal is, for example, the frame synchronization signal is either or composite signal containing all of these synchronization signals of the vertical synchronizing signal S _V, the horizontal sync signal S _H. Since the video signal is written to the dual port RAM 10 every horizontal cycle, at least the horizontal synchronizing signal S is included in the synchronizing signal SYNC.
_H is included. The read clock signal CKR has a different frequency from the write clock signal CKW. As a result, the time axis conversion of the video signal can be realized. The time axis conversion of the video signal will be described in more detail later.

The serial / parallel conversion circuit 40 converts the input serial video data SD into parallel data and outputs it to the switching circuit 60. A / D converter 50 converts the digital signal at the timing set by the clock signal CKR write a video signal S _p analog input, and outputs to the switching circuit 60 the converted digital signal. The serial video data input to the serial / parallel conversion circuit 40 is, for example, a serial video signal obtained by multiplexing each of the digitized luminance signal Y and color difference signal C and further adding a synchronization signal. The video signal S _p to be inputted to the A / D converter 50, for example, the luminance signal Y and chrominance signals C
Is a video signal including both of the above. A / D converter 50
Converts these analog signals into digital signals and outputs them to the switching circuit 60. Here,
The input signal to the A / D converter is an example, and another input signal may be used. For example, an A / D converter can input a video signal in which R, G, and B signals are separated from each other, digitize each input signal, and output the digitalized signal to the switching circuit 60.

The switching circuit 60 has a switching control signal S
_{According to C} , one of the input signals is selected and supplied to the dual port RAM 10. That is, the image processing apparatus according to the present embodiment can support both analog input and digital input. When an analog video signal is input, it is converted into a digitized signal by the A / D converter 50 and output to the dual port RAM 10 via the switching circuit 60. On the other hand, when an already digitized video signal is input, for example,
When a serial digital video signal in which a luminance signal and a chrominance signal are multiplexed according to a predetermined format is input, the serial / parallel conversion circuit 40 converts the input data into parallel data, Output to the RAM 10.

The D / A converter 70 converts the video data read from the output port of the dual port RAM 10 into an analog signal and outputs it to the picture tube 90. The deflection circuit 80 generates a deflection signal, for example, a drive current _ID to be supplied to a horizontal deflection coil of a picture tube, according to the synchronization signal SYNC.

The picture tube 90 generates a magnetic field for deflecting the electron beam according to the drive current _ID supplied to the deflection coil, and outputs the magnetic field from the D / A converter 70 on the scanning line generated by the deflection of the electron beam. The displayed video signal is displayed.

Hereinafter, the operation of the image processing (display) apparatus according to the present embodiment will be described with reference to the timing chart shown in FIG. FIG. 2A shows an example of a waveform of an input video signal. As shown, the horizontal cycle of this video signal is 1H, and the time T _p
There is a valid video signal during the period. That is, the valid period of the video signal is T _p .

FIG. 2B shows an example of a horizontal deflection signal generated by a horizontal deflection circuit when the video signal shown in FIG. 2A is displayed on a CRT, for example. As shown in the drawing, the horizontal deflection signal rises at a constant gradient from the initial level during the effective period T _p of the video signal, and the effective period T _p
Is a sawtooth wave that returns to the initial level before the next horizontal cycle starts after the end of the above. The effective period T _p of the video signal is a scanning period of the scanning line, and a period from the end of the effective period T _p to the start of the next horizontal cycle is a retrace period of the scanning line. The format of the video signal, the ratio of the effective period T _p occupies a horizontal period 1H, that is, the effective time ratio is different, the length of the scanning period and the blanking period is different depending on the video signal format.

FIG. 2C shows the timing of the write clock signal CKW generated by the clock generation circuit 20. As shown, the write clock signal CKW has, for example, a period T _CKW . In the image processing apparatus shown in FIG. 1, for example, when digital video data is input, the input video data is transferred to the dual port RAM 1 at the timing of the write clock signal CKW.
Written to 0. When an analog video signal is input, the video signal is digitized by the A / D converter 50 at the timing of the write clock signal CKW, and the converted video data is written into the write clock signal CK.
The data is sequentially written to a predetermined area of the dual port RAM 10 at the timing of W.

FIG. 2D shows the timing of the read clock signal CKR generated by the clock generation circuit 30. As shown, the period of the read clock signal CKR is T _CKR . In the image processing apparatus shown in FIG. 1, video data stored in the dual port RAM 10 is read at the timing of the read clock signal CKR. As a result, the video signal shown in FIG.

As shown in FIG. 2E, the read clock signal C having a different frequency from the write clock signal CKW is used.
By reading the video data from the dual port RAM 10 by the KR, the video signal can be compressed or expanded on the time axis. That is, time axis conversion can be performed on the video signal. In this time axis conversion, since only the output timing of the video data is different and no change is made to the video data itself, after the time axis conversion, for example, on a screen displayed on a display device,
The original video signal is reproduced almost exactly, and loss of information due to conversion of the time axis can be avoided.

FIG. 2 (f) shows an example of the horizontal deflection signal when the video signal after the time axis conversion shown in FIG. 2 (e) is displayed on a CRT. As shown in the figure, since the video signal is compressed on the time axis by the conversion of the time axis, when the video signal is displayed on the CRT, the effective period T of the signal is equivalently displayed.
_P1 has become shorter. That is, T _P1 <T _p . Since the horizontal period 1H is constant, the retrace period of the scanning line is longer than before conversion. That is, as a result of the time axis conversion, a display device such as a CRT
The ratio between the scanning period and the flyback period in FIG. In the example shown in FIG. 2, since the retrace period is long, the scanning line can slowly return to the scanning start position, so that the timing control of the deflection circuit becomes easy and the load on the circuit can be reduced.

Further, the conversion of the time axis, for example, for different types of video signal-lived T _p, by appropriately controlling the frequency of the read clock signal CKR which is generated by the clock generation circuit 30, converts Since the effective period T _p1 of the subsequent video signal can be set to an optimum value according to the performance of the display device, when displaying video signals of different formats, adjusting the characteristics of the deflection circuit according to each signal format And the circuit configuration of the deflection circuit can be simplified.

Although FIG. 1 shows an embodiment of the image processing apparatus according to the present invention, the present invention is not limited to this configuration, and various modifications are conceivable. For example,
In the case of an image processing apparatus that handles only digital video signals, the A / D converter 50 and the switching circuit 60 shown in FIG. 1 can be omitted. The circuit 40 and the switching circuit 60 can be omitted. Further, when the video signal whose timing has been converted on the time axis is not displayed, but is recorded on, for example, a video signal recording medium, the D / A converter 70, the deflection circuit 80, and the picture tube 90 shown in FIG. 1 can be omitted. May be provided with an image recording device.

[0034]

As described above, according to the image processing apparatus of the present invention and the image display apparatus using the same, the conversion of the timing on the time axis with respect to the video signal can be easily realized, and the time axis conversion can be performed. By doing so, it is possible to cope with a plurality of types of video signals having different formats without imposing a large load on the deflection circuit. Further, according to the present invention, the effective period of the video signal can be changed to a desired value by time axis conversion, so that even when a video signal of a different format is displayed on the picture tube, the characteristics of the deflection circuit and the picture tube are changed. There is an advantage that there is no need to individually adjust according to the signal format, and the circuit configuration of the deflection circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart showing the operation of the image processing apparatus of the present invention.

FIG. 3 is a diagram showing display screens having different sizes.

4 is a waveform diagram showing waveforms of a video signal and a horizontal deflection drive current corresponding to the display screen shown in FIG.

[Explanation of symbols]

10: dual port RAM, 20, 30: clock generation circuit, 40: serial / parallel conversion circuit, 50: A
/ D converter, 60 switching circuit, 70 D / A converter, 80 deflection circuit, 90 picture tube.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 3/16 H04N 5/46 5/46 5/907 B 5/907 G09G 5/00 555K 5/92 H04N 5/92 DF term (reference) 5C025 BA02 BA20 BA21 BA27 BA30 DA01 DA10 5C052 AA17 AA20 CC02 CC03 DD01 DD08 5C053 FA27 GA10 JA27 KA04 KA08 KA18 KA25 LA06 5C068 AA01 AA06 BA02 HB03 5C082 AA03 BC20 BC41 BC21 BC BD01 BD09 DA53 DA63 DA76 EA15 EA18 MM02 MM04

Claims (13)

[Claims] 1. A digital image signal is written at a timing set by a first clock signal, and the image signal is written at a timing set by a second clock signal having a frequency different from the first clock signal. An image processing device having a multiport storage device for reading. 2. A first clock generation circuit for generating the first clock signal in accordance with a synchronization signal indicating a cycle of the image signal, and a second clock generation circuit in accordance with the synchronization signal. The image processing device according to claim 1, further comprising a second clock generation circuit. 3. The first clock generation circuit has a first multiplication circuit for multiplying the synchronization signal at a first multiplication ratio and outputting the multiplication signal as the first clock signal. Image processing device. 4. The second clock generating circuit according to claim 2, further comprising a second multiplying circuit for multiplying the synchronizing signal at a second multiplying ratio and outputting the multiplied signal as the second clock signal. Image processing device. 5. The multi-port storage device converts the digitized image signal input serially into parallel image data and outputs the converted parallel image data at a timing set by the first clock signal. The image processing apparatus according to claim 1, further comprising a serial / parallel conversion circuit. 6. An A / D converter for converting an input image signal into a digital signal, writing the digitized image signal at a timing set by a first clock signal, and setting a frequency different from the first clock signal. And a multi-port storage device for reading at a timing set by the second clock signal. 7. A first clock generation circuit for generating the first clock signal according to a synchronization signal indicating a cycle of the image signal, and a second clock generation circuit for generating the second clock signal according to the synchronization signal. The image processing apparatus according to claim 6, further comprising a second clock generation circuit. 8. The first clock generation circuit includes a first multiplication circuit that multiplies the synchronization signal at a first multiplication ratio and outputs the multiplication signal as the first clock signal. Image processing device. 9. The second clock generating circuit according to claim 7, further comprising a second multiplying circuit for multiplying the synchronizing signal at a second multiplying ratio and outputting the multiplied signal as the second clock signal. Image processing device. 10. A digital image signal is written at a timing set by a first clock signal, and the image signal is written at a timing set by a second clock signal having a frequency different from that of the first clock signal. In synchronization with a synchronization signal indicating the cycle of the image signal, a read period of the image signal is set as a scanning period, and a period from the end of the reading to the next input of the synchronization signal is returned. An image display device comprising: a deflection circuit for generating a deflection signal as a line period; and an image display means for displaying an image signal read from the storage means on a scanning line controlled by the deflection signal. 11. A picture tube (CR) in which a driving current according to the deflection signal is supplied to a deflection coil.
The image display device according to claim 10, which is T). 12. An A / D converter for converting an input image signal into a digital signal, writing the digitized image signal at a timing set by a first clock signal, and setting a frequency different from the first clock signal. A multi-port storage means for reading out at a timing set by the second clock signal possessed by the second clock signal; A deflection circuit that generates a deflection signal with a period until the synchronization signal is input as a blanking period; and an image display unit that displays an image signal read from the storage unit on a scanning line controlled by the deflection signal. Image display device having the same. 13. A picture tube (CR) in which a driving current according to the deflection signal is supplied to a deflection coil.
The image display device according to claim 12, which is T).