JP2002314404A - Frequency divider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency divider with a wide operable frequency range for stable 1/(2n+1) frequency division (n is an integer of 1 or over) even at a low speed operation or a high speed operation when a phase difference between the two outputted signals is 90 degrees. SOLUTION: An adder circuit 5 sums the outputs of multiplier circuits 3, 4 receiving two signals with a phase difference of 90 degrees, which are obtained by giving an input signal to a 90-degree phase shift circuit 2, so as to cancel only high frequency components and to extract only low frequency components with emphasis being outputs of the multiplier circuits 3, 4, a 1/2n frequency divider circuit 6 applies 1/2n frequency division to the extracted frequency components, a 90-degree phase shift circuit 7 receiving the 1/2n frequency division signal generates two signals with a phase difference of 90 degrees, and the multiplier circuits 3, 4 respectively multiply the input signal with signals subjected to 1/(2n+1) frequency division by giving two signals obtained from the 90-degree phase shift circuit 7 respectively to the multiplier circuits 3, 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider capable of high-speed operation for extracting two (2n + 1) frequency-divided output signals having a duty factor of 50% and a phase difference of 90 degrees from an input signal. It is.

[0002]

2. Description of the Related Art Most conventional frequency dividers have an even-numbered frequency divider, and there are not many frequency-divided frequency dividers having an odd-numbered frequency divider. It is quite limited at 50%.

A frequency divider shown in FIG. 11 has been employed as a conventional frequency divider capable of extracting a frequency-divided output signal having a duty factor of 50% from an input signal and operating at high speed. In FIG. 11, 1 is a signal input terminal, 3 is 2
Multiplication circuit for multiplying two input signals, 11 is an amplifier, 1
Reference numeral 4 denotes a divide-by-2 circuit for dividing the input signal by 2. Amplifier 1
Reference numeral 1 denotes an amplifier circuit 12 and a low-pass filter 13.

[0004] In FIG.
Is connected to the signal input terminal 1, the output terminal 3c of the multiplication circuit 3 is connected to the input terminal of the amplifier 11,
An output terminal of the amplifier 11 is connected to an input terminal of the divide-by-2 circuit 14.

Further, the output terminal of the divide-by-2 circuit 14 is connected to the signal output terminal 8 and the second input terminal 3b of the multiplication circuit 3.

Then, an input signal having a frequency of 3f is supplied from a signal input terminal 1 to a first input terminal 3a of the multiplication circuit 3. Further, the second input terminal 3b of the multiplication circuit 3
A signal having a frequency f that is obtained by dividing the input signal given to the first input terminal 3a by 3 is input.

In this case, a signal having a frequency 2f twice as high as the frequency f and a signal having a frequency 4f four times as high as the frequency f appear in the spectrum of the signal output from the multiplication circuit 3.

[0008] These two signals are input to the amplifier 11. Here, a frequency characteristic is set so that the signal of the frequency 4f is attenuated in the amplifier 11. At this time, the amplifier 11 incorporates, for example, the configuration of the low-pass filter 13. As a result, at the output of the amplifier 11, the signal level at the frequency 2f is higher than the signal level at the frequency 4f. This signal is input to the divide-by-2 circuit 14.

The signal level of the frequency 2f is divided by 2
Is larger than the signal level of the frequency 4f in the above, and if the input sensitivity is obtained, the signal of the frequency 2f is divided by two, and the input signal of the frequency 3f given to the signal input terminal 1 from the frequency dividing circuit 14 is The signal f divided by three is output.

Here, it is necessary for the amplifier 11 to sufficiently lower the amplitude of the signal of the frequency 4f as compared with the signal of the frequency 2f so that the frequency dividing circuit 14 does not divide the frequency at the frequency 4f.

FIG. 12 shows a circuit in which the signal input terminal 1, the multiplying circuit 3 and the amplifier 11 of FIG. 11 are replaced by circuits actually used.

In the multiplication circuit 3, the signal input terminal 1 is connected to the bases of the transistors 1202 and 1203, and the transistors 1201 and 12
A fixed voltage is input to the base of the circuit 04. Here, an input signal divided by three is input to the signal input terminal 1.

Further, the emitters of the transistor 1203 and the transistor 1204 are connected in common, and the transistor 1
206 is connected to the collector. Transistor 1201
And the emitter of the transistor 1202 are connected in common and connected to the collector of the transistor 1205. Further, the emitters of the transistor 1205 and the transistor 1206 are commonly connected and connected to a constant current source including a transistor and a resistor.

Further, the collectors of the transistor 1201 and the transistor 1203 are connected in common and the output terminal 12
Connected to 1. The collectors of the transistor 1202 and the transistor 1204 are connected in common and connected to the output terminal 122.

Further, the base of the transistor 1205 is connected to the output terminal 51 of the divide-by-2 circuit 14, and the base of the transistor 1206 and the output terminal 52 of the divide-by-2 circuit 14 are connected.
Are connected.

With the above configuration, the multiplication circuit 3
Is the signal supplied to the signal input terminal 1 and the divide-by-2 circuit 14
Is multiplied by the signal given between the output terminals 51 and 52, and the result is output to terminals 121 and 122. A signal having a phase difference of 180 degrees is input from terminals 121 and 122, and a signal having a phase difference of 180 degrees is obtained from terminals 141 and 142.

Next, the amplifier 11 will be described. The output terminal 121 of the multiplication circuit 3 is connected to the base of the transistor 1207. In addition, the transistor 1208
Is connected to the output terminal 122 of the multiplication circuit 3.
The emitters of the transistor 1207 and the transistor 1208 are commonly connected and connected to a constant current source. The collectors of transistors 1207 and 1208 are individually connected to the bases of transistors 1209 and 1210. Then, the emitter of the transistor 1209 is connected to the output terminal 141, and the transistor 1210
Are connected to the output terminal 142. With such a configuration, a phase difference of 180 from terminals 121 and 122 is obtained.
Input signal and output the amplified signal to the output terminal 14.
1, 142 output.

FIG. 5 shows a circuit obtained by replacing the divide-by-2 circuit 14 with an actual circuit. The input terminals 241 and 242 are respectively connected to the output terminals 141 and 142 of the amplifier 11 in FIG. The input terminal 241 is connected to the bases of the transistors 505 and 511,
2 and the bases of transistors 506 and 512 are connected. The emitters of the transistors 505 and 506 and the emitters of the transistors 511 and 512 are respectively connected to constant current sources. The collector of transistor 505 is connected to the emitters of transistors 501 and 504, and the collector of transistor 506 is connected to the emitters of transistors 502 and 503.

Transistors 501 and 502
Is connected to the bases of the transistors 507 and 503, and the collectors of the transistors 503 and 504 are connected to the bases of the transistors 502 and 510. The collectors of the transistors 507 and 508 are connected to the bases of the transistors 504 and 509. The collectors of the transistors 509 and 510 are connected to the bases of the transistors 508 and 501. Then, the signals input from the input terminals 241 and 242 are divided by two, and the signals are extracted from the terminals 51, 52, 53 and 54.

FIGS. 13 to 17 show the results of simulation using the circuits shown in FIGS. 12 and 5. FIG.

FIG. 13 is a characteristic diagram showing the result of frequency division by inputting a 1200 MHz signal. The lower graph shows the signal applied to the signal input terminal 1, and the middle graph shows the signal obtained at terminals 51 and 53. The upper graph is the output of the multiplication circuit (the output obtained from the terminal 121). Here, a signal whose input signal is divided by 3 and whose duty factor is 50% is output.
And the phase difference between the signals obtained at the terminal 53 is 118 degrees.

In FIG. 13, the input frequency divided by 3 is 120
Since the frequency is 0 MHz, the output of the multiplication circuit is 12
400 MHz obtained by dividing the 00 MHz waveform by 3 and the input 1
From 200 MHz, 800 MHz and 1600 MHz are output.

In the circuit shown in FIG. 12, the resistance 1212 and the capacitance parasitically added to the base of the transistor 1209 cause the resistance 1212 and the transistor
And a capacitor parasitically added to the base of the filter, individually forms a low-pass filter. In the low-pass filter of the amplifier 11, frequency characteristics are set so as to lower the output level at 1600 MHz. In this configuration, when an 800 MHz signal is input to the divide-by-2 circuit 14,
A signal of 00 MHz is output.

However, as shown in the middle graph of FIG. 13, the phase difference between the signals obtained at the terminals 51 and 53 is not 90 degrees but 118 degrees, that is, about 120 degrees. This is because the signal input to the divide-by-2 circuit 14 is
This is because, as shown in the upper graph of FIG. 3, the duty factor is not 50% but a signal of about 66.6%.

FIG. 14 is a characteristic diagram showing the result of frequency division by inputting a 700 MHz signal, and FIG.
FIG. 16 is a characteristic diagram showing a result of frequency division by inputting a signal of z, FIG. 16 is a characteristic diagram showing a result of frequency division by inputting a signal of 2600 MHz, and FIG. 17 is a characteristic diagram showing a result of inputting a signal of 2700 MHz. FIG. 9 is a characteristic diagram showing a result of frequency division performed by dividing the frequency.

These figures show 800 MHz and 2600 M
When inputting Hz, a frequency-divided waveform appears at the output, but when 700 MHz and 2700 MHz are input, a waveform obtained by dividing by 3 does not appear at the output, and at low-frequency and high-frequency, It indicates that an operating limit exists.

However, it is known that the operation limit output frequency of the divide-by-2 circuit 4 in FIG. 5 is from 4 MHz to 1000 MHz. Therefore, as long as the divide-by-2 circuit 14 is used, the operation limit frequency of the divide-by-3 circuit is 3 MHz to 3 MHz.
000 MHz, but actually from 800 MHz to 26 MHz
00 MHz. High frequency limit operating frequency is 3000MH
Although it is almost close to 2600 MHz from z, the low-frequency limit operating frequency greatly changes from 12 MHz to 800 MHz to a high frequency side, and the operable frequency range is narrowed.
The high-frequency side operates up to a very high frequency of 2600 MHz, while the low-frequency side has an operating limit frequency of 800 MHz, narrowing the operating frequency range.

The cause is that the amplitude of the signal of frequency 4f out of the signals of frequency 2f and frequency 4f output from the multiplying circuit 3 cannot be sufficiently reduced by the low-pass filter parasitically produced by the amplifier 11. It is considered that it is. Below 800 MHz, the signal amplitude of the frequency 4f cannot be reduced, and the 2 divider 14 operates at the frequency 4f, so that it does not operate normally as a 3 divider.

In a low-pass filter parasitically produced by the amplifier 11, it is generally difficult to arbitrarily set the cutoff frequency, and the variation is large. Therefore, it is difficult to operate stably at a particularly low frequency.

Even when the frequency division operation is performed by three, the terminal 51
And the signal obtained at the terminal 53 is 800 MHz
119 degrees at 1200 MHz, 118 degrees at 2600 MHz
At MHz, it is 67 degrees, which is a large deviation from 90 degrees.

[0031]

As described above, in this conventional circuit, the signals taken out at the terminals 51 and 53 have a duty factor of 50% with respect to the signal inputted to the terminal 1 and have a duty factor of 50%. Be circulated.

However, the phase difference between the signals taken out at the terminals 51 and 53 is not 90 degrees. In addition, very high-speed operation is possible and the operating frequency on the high frequency side is very high,
Operation is not stable during low-speed operation. As a result, the operable frequency on the low frequency side is increased, and the entire operable frequency range is narrowed.

The present invention has been made in view of this problem, and
The phase difference between the signals is 90 degrees, and the (2n + 1) frequency dividing operation (n is 1) is stable both in the low-speed operation and the high-speed operation.
It is an object to provide a frequency divider having a wide operable frequency range.

[0034]

In order to achieve this object, a (2n + 1) frequency divider according to the present invention comprises a first 90-degree phase shift circuit for converting an input signal into a phase difference from each other. Are separately input to the first and second multiplication circuits, and the outputs of the first and second multiplication circuits are added together to output the signals from the first and second multiplication circuits. Only high frequency components are canceled out, and only low frequency components are emphasized and extracted.
The second 90-degree phase shift circuit produces two signals having a phase difference of 90 degrees from the signal obtained by dividing the frequency by n and further dividing by 2n, and dividing the two signals obtained from the second 90-degree phase shift circuit It has a configuration in which the input signal is input to the first and second multiplication circuits and the input signal is multiplied by the (2n + 1) frequency-divided signal. With this configuration, the two (2n +
1) The phase difference between the frequency-divided signals is 90 degrees, and the (2n + 1) frequency-divide operation is performed stably both at the time of low-speed operation and at the time of high-speed operation. Become.

More specifically, the frequency divider according to the first aspect of the present invention includes a first output signal from an input signal and a second output signal delayed by 90 degrees from the first output signal. , A first and second multiplying circuit for respectively outputting a signal obtained by multiplying two input signals, and an output of each of the first and second multiplying circuits. An addition circuit for adding signals, and an output signal of the addition circuit being 2n
A 2n frequency dividing circuit for dividing and outputting (n is an integer of 1 or more), a first output signal from the output signal of the 2n frequency dividing circuit, and a second output signal delayed by 90 degrees from the first output signal And a second 90-degree phase shift circuit for generating an output signal.

Then, the first output signal of the first 90-degree phase shift circuit and the first output signal of the second 90-degree phase shift circuit are input to a first multiplication circuit, and the first 90-degree phase shift circuit is input to the first multiplication circuit. By inputting the second output signal of the phase shift circuit and the second output signal of the second 90 degree phase shift circuit to the second multiplication circuit, the first output of the second 90 degree phase shift circuit is obtained. The signal becomes a signal having a duty factor of 50% obtained by dividing the input signal by (2n + 1), and the second 9
The second output signal of the 0-degree phase shift circuit is configured to be a signal delayed by 90 degrees from the first output signal.

With this configuration, two signals obtained by passing a signal input from the signal input terminal through the first 90-degree phase shift circuit are separately input to the first and second multiplication circuits. Then, the outputs of the first and second multiplication circuits are added to cancel only the high frequency components output from the first and second multiplication circuits, and only the low frequency components are emphasized and extracted. Is divided by 2n, and two signals having a phase difference of 90 degrees are formed by a second 90-degree phase shift circuit from the signals divided by 2n, and the two signals obtained from the second 90-degree phase shift circuit The first
And the second multiplication circuit, and the input signal and (2n +
1) It has a configuration for multiplying the divided signal. With this configuration, the signal input from the signal input terminal is frequency-divided by (2n + 1), and the frequency of the signal having a phase difference of 90 degrees is increased.
Two signals can be extracted. At this time, the phase difference between the two output (2n + 1) frequency-divided signals is 90 degrees, and stable (2)
The (n + 1) frequency division operation is performed, and the frequency division operation with a wide operable frequency range becomes possible.

According to a second aspect of the present invention, in the frequency divider of the first aspect, the first 90-degree phase shift circuit includes a capacitor and a resistor.

According to this configuration, since the first 90-degree phase shift circuit is composed of the capacitor and the resistor, the phase shift from the input signal differs from the input signal by 90 degrees with a relatively simple configuration.
It is possible to realize a 90-degree phase shift circuit that generates two signals.

Further, the frequency divider according to the third aspect of the present invention is the frequency divider according to the first or second aspect, wherein the first output signal and the second output of the first 90-degree phase shift circuit are provided. A phase correction circuit for correcting and outputting the signal so that the phase difference of the signal becomes 90 degrees is provided, and the first 90-degree phase shift circuit and the phase correction circuit are cascaded.

According to this configuration, the phase difference between the first output signal and the second output signal of the first 90-degree phase shift circuit is corrected by the phase correction circuit so as to be closer to 90 degrees. High frequency components output from the first and second multiplication circuits are canceled out, the effect of emphasizing low frequency components is enhanced, and the operating range of (2n + 1) frequency division can be expanded.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the (2n + 1) frequency divider according to the first embodiment of the present invention. In FIG. 1, 1 is a signal input terminal, 2 is a first 90-degree phase shift circuit, 3 is a first multiplication circuit, 4 is a second multiplication circuit, 5 is an addition circuit, 6 is a 2n frequency dividing circuit, Reference numeral 7 denotes a second 90-degree phase shift circuit.

In FIG. 1, a first 90-degree phase shift circuit 2
Is connected to the signal input terminal 1, the first output terminal 2a of the first 90-degree phase shift circuit 2 is connected to the first input terminal 3a of the first multiplication circuit 3, and the first 90 The second output terminal 2b of the phase shift circuit 2 is connected to the first input terminal 4a of the second multiplication circuit 4.

Further, the output terminal 3c of the first multiplication circuit 3
Is connected to the first input terminal 5a of the addition circuit 5, the output terminal 4c of the second multiplication circuit 4 is connected to the second input terminal 5b of the addition circuit 5, and the output terminal 5c of the addition circuit 5 Is connected to the input terminal of the divide-by-2 circuit 6.

Further, the output terminal of the 2n frequency dividing circuit 6 is the second
Of the second 90-degree phase shift circuit 7
The first output terminal 7a of the phase shift circuit 7 is connected to the signal output terminal 8 and the second input terminal 3b of the first multiplication circuit 3, and the second output terminal of the second 90 degree phase shift circuit 7 7b is connected to the signal output terminal 9 and the second input terminal 4b of the second multiplication circuit 4.

Here, for simplicity, when n = 1,
In other words, the 2n frequency dividing circuit 6 becomes a frequency dividing circuit by 2, and the present invention
The case of operating as a frequency divider will be described. Hereinafter, reference numeral 6 is referred to as a divide-by-2 circuit.

A signal having a frequency of 3f is supplied from the signal input terminal 1 to the input terminal of the first 90-degree phase shift circuit 2. From the input signal, the first 90-degree phase shift circuit 2
Two signals having a phase difference of 0 degree are output from the first output terminal 2a and the second output terminal 2b of the 90 degree phase shift circuit 2.

Here, suppose that the signal output from the first output terminal 2a of the first 90-degree phase shift circuit 2 is advanced by 90 degrees from the signal output from the second output terminal 2b. The first input terminal 3a of the multiplication circuit 3 has a frequency 3f that is 90 degrees ahead of the signal output from the second output terminal 2b from the first output terminal 2a of the first 90-degree phase shift circuit 2. Is input. The first input terminal 4a of the second multiplying circuit 4 is delayed by 90 degrees from the signal output from the first output terminal 2a from the second output terminal 2b of the first 90-degree phase shift circuit 2. The signal of the frequency 3f is input.

It is assumed here that the first 90-degree phase shift circuit 7
If the signal output from the first output terminal 7a is advanced by 90 degrees from the signal output from the second output terminal 7b, the second input terminal 3b of the first multiplication circuit 3
From the first output terminal 7a of the 90-degree phase shift circuit 7, a signal having a frequency f which is advanced by 90 degrees from the signal output from the second output terminal 7b and obtained by dividing the input signal by 3 is input. Also,
The second input terminal 4b of the second multiplication circuit 4 has a second 90
From the second output terminal 7b of the phase shift circuit 7, a signal having a frequency f which is delayed by 90 degrees from the signal output from the first output terminal 7a and obtained by dividing the input signal by 3 is input.

In this case, the spectrum of the signal output from the first multiplication circuit 3 has a frequency 2f which is twice the frequency f.
And a signal having a frequency 4f which is four times as high. Similarly, in the spectrum of the signal output from the second multiplying circuit 4, a signal having a frequency 2f twice the frequency f and a signal having a frequency 4f four times the frequency f appear.

However, in the signal output from the first multiplication circuit 3 and the signal output from the second multiplication circuit 4,
The phase difference between the signals of frequency 2f is 0 degree,
Are 180 degrees.

Therefore, by adding the signal output from the first multiplication circuit 3 and the signal output from the second multiplication circuit 4 by the addition circuit 5, the signal component of the frequency 2f is doubled. , Frequency 4f are canceled out.

To make this easier to understand, assuming that the signal input from the signal input terminal 1 is a sine wave, the first 90-degree phase shifter 2 outputs the cos signal from the first output terminal 2a.
(3f) is output, and sin is output from the second output terminal 2b.
(3f) is output, cos (f) is output from the first output terminal 7a of the second 90-degree phase shift circuit 7, and sin (f) is output from the second output terminal 7b. Become.

Then, the signal output from the first multiplying circuit 3 is: cos (3f) × cos (f) = (cos (2f) + c
os (4f)) / 2. The signal output from the second multiplication circuit 4 is sin (3f) × sin (f) = (cos (2f) −c
os (4f)) / 2. Therefore, the signal output from the addition circuit 5 is (cos (2f) + cos (4f)) / 2+ (cos
(2f) -cos (4f)) / 2 = cos (2f).

As described above, the signal output from the addition circuit 5 has only the signal component of the frequency 2f, and the divide-by-2 circuit 6 operates at the frequency 2f. Will be output. The above is irrespective of the frequency, and a normal divide-by-3 operation can be expected in a wide frequency range.

FIG. 2 is a block diagram showing the configuration of the (2n + 1) frequency divider according to the second embodiment of the present invention. In the second embodiment, the phase difference between the signal at the first output terminal 2a and the signal at the second output terminal 2b of the first 90-degree phase shift circuit 2 is different from that of the embodiment shown in FIG. The operation is further stabilized by adding a phase correction circuit 10 for performing correction so as to be as close as possible to 90 degrees. First nine
The 0-degree phase shift circuit 2 and the phase correction circuit 10 are cascaded.

FIG. 3 shows the (2n + 1) frequency divider shown in FIG. 2 in which the signal input terminal 1, the 90-degree phase shift circuit 2, and the phase correction circuit 10 are replaced by circuits actually used. 3, reference numerals 301 and 304 denote capacitors, 30
Reference numerals 2303 denote resistors and reference numerals 305 to 312 denote transistors, which constitute a first 90-degree phase shift circuit 2.
31 to 33, 35 are output terminals of the first 90-degree phase shift circuit 2; Reference numerals 313 to 316 denote transistors, which constitute the phase correction circuit 10. 36 to 39 are output terminals of the phase correction circuit 10.

Here, in FIG.
3, 314, 315, 316 are deleted, and terminals 36, 3
7, 38 and 39 are connected to terminals 33, 34, 35 and 36, respectively.
Then, it corresponds to the frequency divider according to the first and second aspects.

FIG. 4 shows a circuit in which the multiplying circuit 3, the multiplying circuit 4 and the adding circuit 5 are replaced by circuits actually used. In FIG. 4, 401 to 414 are transistors. 41 and 42 are output terminals of the adder circuit 5. These output terminals are input terminals 241 and 242 of the divide-by-2 circuit 14 in FIG.
42 respectively.

FIG. 5 shows that the 2n frequency dividing circuit 6 is divided into two frequency dividing circuits (n =
1) 14 denotes a circuit which is replaced with an actually used circuit.

FIGS. 6 to 10 show the results of simulation using the circuits of FIGS. 3, 4, and 5. FIG.

FIG. 6 is a characteristic diagram showing the result of frequency division by inputting a 1200 MHz signal. The lower graph is a signal applied to the input terminal 1, and the middle graph is a signal supplied to the terminal 51,
53 is the signal output obtained at 53.
1 is a signal output obtained by 1 (addition circuit). Here, the input signal is divided by 3 and a signal having a duty factor of 50% is output, and the phase difference between the signals obtained at the terminals 51 and 53 is 95 degrees. The phase difference of the conventional invention is 118 degrees, which is improved by 23 degrees.

FIG. 7 is a characteristic diagram showing a result of frequency division by inputting a 100 MHz signal, FIG. 8 is a characteristic diagram showing a result of frequency division by inputting a 200 MHz signal, and FIG. 9 is a characteristic diagram of FIG. FIG. 10 is a characteristic diagram showing a result of inputting and dividing the frequency of a 2500 MHz signal, and FIG. 10 is a characteristic diagram showing a result of dividing the frequency by inputting a signal of 2600 MHz.

These figures show 200 MHz and 2500 M
When inputting Hz, a frequency-divided waveform appears in the output. However, when 100 MHz and 2600 MHz are input, the waveform obtained by dividing by 3 does not appear in the output, and the low-frequency and high-frequency frequencies do not appear. It indicates that an operating limit exists.

However, as compared with the conventional example, the highest operating frequency is higher than 2600 MHz to 2500 MHz at higher frequencies.
However, at low frequencies, the operating frequency greatly increases from 800 MHz to 200 MHz.
The operation limit output frequency of the divide-by-2 circuit 6 in FIG. 5 is from 4 MHz to 1000 MHz, whereas the operation limit output frequency of the divide-by-3 circuit according to the embodiment of the present invention is from 6.6 MHz to 833 MHz. It can be seen that the operation limit of the circuit 6 is considerably approached.

In the present invention, the terminal 51 and the terminal 53 are operable at the operable frequencies of 200 MHz and 2500 MHz.
Are 94 degrees and 100 degrees, whereas the conventional example has 67 degrees and 119 degrees at 800 MHz and 2600 MHz.
As a result, the present invention has obtained a result closer to 90 degrees than the conventional example.

[0068]

As described above, according to the frequency divider of the present invention, the phase difference between the two output signals is approximately 90 degrees, and is stable (2n + 1) at both low speed operation and high speed operation. The frequency dividing operation can be performed, and the operable frequency range can be widened.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a ３ frequency divider according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a ３ frequency divider according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram specifically showing each block of the frequency divider of FIG. 1;

FIG. 4 is a circuit diagram specifically showing each block of the frequency divider of FIG. 1;

FIG. 5 is a circuit diagram specifically showing each block of the frequency divider of FIG. 1;

FIG. 6 is a characteristic diagram showing a simulation result using the circuits of FIGS. 3, 4, and 5;

FIG. 7 is a characteristic diagram showing a simulation result using the circuits of FIGS. 3, 4, and 5;

FIG. 8 is a characteristic diagram showing a simulation result using the circuits of FIGS. 3, 4, and 5;

FIG. 9 is a characteristic diagram showing a simulation result using the circuits of FIGS. 3, 4, and 5;

FIG. 10 is a characteristic diagram showing a simulation result using the circuits of FIGS. 3, 4, and 5;

FIG. 11 is a configuration diagram of a conventional frequency divider of 3;

FIG. 12 is a circuit diagram specifically showing each block of the frequency divider of FIG. 11;

FIG. 13 is a characteristic diagram showing a simulation result using the circuits of FIGS. 12 and 5 in the configuration of the conventional frequency divider of 3;

FIG. 14 is a characteristic diagram showing a simulation result using the circuits of FIGS. 12 and 5 in the configuration of the conventional frequency divider of 3;

FIG. 15 is a characteristic diagram showing a simulation result using the circuits of FIGS. 12 and 5 in the configuration of the conventional frequency divider of 3;

FIG. 16 is a characteristic diagram showing a simulation result using the circuits of FIGS. 12 and 5 in the configuration of the conventional frequency divider of 3;

FIG. 17 is a characteristic diagram showing a simulation result using the circuits of FIGS. 12 and 5 in the configuration of the conventional frequency divider of 3;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 signal input terminal 2 90 degree phase shift circuit 3 multiplication circuit 4 multiplication circuit 5 addition circuit 6 2n frequency divider 7 90 degree phase shift circuit 8 signal output terminal 9 signal output terminal 10 phase correction circuit 11 amplifier 12 amplifier circuit 13 low pass Filter 301, 304 Capacitor 302, 303 Resistance 305-316 Transistor 31-33, 35-39 Terminal 401-414 Transistor 41, 42 Terminal 501-512 Transistor 51-54 Terminal 1201-1210 Transistor 1211, 1212 Resistance 121, 122 Terminal

Claims (3)

[Claims] A first output signal from the input signal and a first output signal;
A first 90-degree phase shift circuit for generating a second output signal delayed by 90 degrees from the output signal of the first and second signals, and first and second multiplications for respectively outputting a signal obtained by multiplying the two input signals Circuit, an addition circuit that adds the output signals of the first and second multiplication circuits, and 2n that divides the output signal of the addition circuit by 2n (n is an integer of 1 or more) and outputs the result.
A frequency dividing circuit, and a second 90-degree phase shifter for generating a first output signal from the output signal of the 2n frequency dividing circuit and a second output signal delayed by 90 degrees from the first output signal. And a first output signal of the first 90-degree phase shift circuit and the second output signal.
The first output signal of the 90-degree phase shift circuit is input to the first multiplication circuit, and the second output signal of the first 90-degree phase shift circuit and the second output signal of the second 90-degree phase shift circuit are input to the first multiplication circuit. By inputting the second output signal to the second multiplication circuit, the first output signal of the second 90-degree phase shift circuit changes the input signal to (2
(n + 1) is a signal having a duty factor of 50% which is frequency-divided, and the second output signal of the second 90-degree phase shift circuit is a signal delayed by 90 degrees from the first output signal. A frequency divider characterized by the above-mentioned. 2. The frequency divider according to claim 1, wherein said first 90-degree phase shift circuit comprises a capacitor and a resistor. 3. A phase correction circuit for correcting and outputting a phase difference between a first output signal and a second output signal of the first 90-degree phase shift circuit so that the difference between the first output signal and the second output signal is 90 degrees. 3. The frequency divider according to claim 1, wherein the 90-degree phase shift circuit and the phase correction circuit are connected in cascade.