CN110336537B - Multi-frequency point control circuit - Google Patents
Multi-frequency point control circuit Download PDFInfo
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- CN110336537B CN110336537B CN201910542669.6A CN201910542669A CN110336537B CN 110336537 B CN110336537 B CN 110336537B CN 201910542669 A CN201910542669 A CN 201910542669A CN 110336537 B CN110336537 B CN 110336537B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The present application relates to a multi-frequency point control circuit, which includes: a power divider dividing a circuit to which a reference signal is input into at least a first circuit and a second circuit; the first processing unit processes an input reference signal to generate a first frequency signal; a second processing unit which processes the input reference signal to generate a second frequency signal; a first switch for controlling the output of the first frequency signal; the second switch controls the output of the second frequency signal; the third switch controls the output of the first frequency signal or the second frequency signal; the control unit controls the conduction of the first switch, the second switch and the third switch, selectively outputs the first frequency signal or the second frequency signal, realizes the input of a single reference signal and the selective output of a multi-frequency point signal, and has the advantages of quick frequency output switching, high isolation and low stray of output signals.
Description
Technical Field
The present application relates to the field of circuits, and in particular, to a multi-frequency-point control circuit.
Background
A frequency synthesizing circuit is a circuit for performing frequency synthesis to output a specific frequency.
In a traditional frequency synthesis circuit, two common methods are used, one is to adopt a Direct Digital Synthesis (DDS) method based on Complex Programmable Logic (CPLD) to synthesize the frequency, so as to realize double-frequency output, but the stray signal of the circuit is difficult to process, and the realized power consumption is relatively large; the other method is to adopt phase-locked loop (PLL) frequency synthesis, but the circuit of the method is complex, the time delay of frequency switching is large, a small number of PLL forms are needed, the problem of spurious exists, and the phase detector can deteriorate phase noise.
Disclosure of Invention
In view of the above, it is desirable to provide a multi-frequency point control circuit.
The invention provides a multi-frequency point control circuit, which comprises:
the power divider is used for dividing a circuit of an input reference signal into at least two circuits, and the at least two circuits comprise a first circuit and a second circuit;
at least two processing units, including a first processing unit and a second processing unit;
the first processing unit is connected with the first circuit and used for processing an input reference signal to generate a first frequency signal;
the second processing unit is connected with the second circuit and used for processing the input reference signal to generate a second frequency signal;
the first switch is connected with the first processing unit and used for controlling the output of the first frequency signal;
the second switch is connected with the second processing unit and used for controlling the output of the second frequency signal;
a third switch connected to the first switch and the second switch, for controlling an output of the first frequency signal or the second frequency signal;
and the control unit is connected with the first switch, the second switch and the third switch, and is used for controlling the conduction of the first switch, the second switch and the third switch and selectively outputting the first frequency signal or the second frequency signal.
In one embodiment, the first processing unit is a frequency dividing unit, and is configured to perform frequency dividing processing on the input reference signal to generate the first frequency signal;
the second processing unit is a frequency doubling unit and is configured to perform frequency doubling processing on the input reference signal to generate the second frequency signal.
In one embodiment, the first processing unit and the second processing unit are both frequency dividing units, and are configured to perform frequency dividing processing on the input reference signal to generate the first frequency signal and the second frequency signal, where the first processing unit generates the first frequency signal, and the second processing unit generates the second frequency signal; or
The first processing unit and the second processing unit are frequency doubling units and are used for performing frequency doubling processing on the input reference signal to generate a first frequency signal and a second frequency signal; the first processing unit generates the first frequency signal, and the second processing unit generates the second frequency signal.
In one embodiment, the frequency dividing unit comprises a frequency divider, a first low-pass filter, a first amplifier, and a first high-pass filter;
the frequency divider is connected with the first circuit and used for generating a frequency division signal of the reference signal and a harmonic signal of the frequency division signal;
the first low-pass filter is connected with the frequency divider and used for extracting a first signal which is less than or equal to the first frequency signal in a frequency division signal of the reference signal and a harmonic signal of the frequency division signal;
the first amplifier is connected with the first low-pass filter and used for increasing the level of a reference signal input into the frequency dividing unit;
the first high-pass filter is connected with the first amplifier and the first switch and used for extracting a second signal which is greater than or equal to the first frequency signal in a frequency division signal of the reference signal and a harmonic signal of the frequency division signal.
In one embodiment, the frequency multiplying unit comprises a frequency multiplier, a second low-pass filter, a second amplifier, and a second high-pass filter;
the frequency multiplier is connected with the second circuit and used for generating a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal;
the second low-pass filter is connected with the frequency multiplier and is used for extracting a third signal which is less than or equal to the second frequency signal from a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal;
the second amplifier is connected with the second low-pass filter and used for increasing the level loss of the reference signal input into the frequency doubling unit;
the second high-pass filter is connected with the second amplifier and the second switch and used for extracting a fourth signal which is greater than or equal to the second frequency signal in a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal.
In one embodiment, the multi-frequency point control circuit further includes:
the first load is connected with the first switch and used for consuming the first frequency signal;
and the second load is connected with the second switch and used for consuming the second frequency signal.
In one embodiment, the multi-frequency point control circuit further includes:
a first extracting unit connected to the first switch and the third switch, for extracting the first frequency signal;
and the second extraction unit is connected with the second switch and the third switch and used for extracting the second frequency signal.
In one embodiment, the first extraction unit includes:
a first band pass filter and a third amplifier;
the first band-pass filter is connected with the first switch and used for extracting the first frequency signal;
the third amplifier is connected with the first band-pass filter and is used for increasing the level of the first frequency signal;
the third switch is connected with the third amplifier and controls to output the first frequency signal.
In one embodiment, the second extraction unit includes:
a second band pass filter and a fourth amplifier;
the second band-pass filter is connected with the second switch and used for extracting the second frequency signal;
the fourth amplifier is connected with the second band-pass filter, and the amplifier is used for increasing the level of the second frequency signal;
and the third switch is connected with the fourth amplifier and controls and outputs the second frequency signal.
In one embodiment, the control unit is a TTL level signal control unit.
The multi-frequency point control circuit provided by the invention divides an input reference signal into at least two circuits through the power divider, at least two processing units respectively process the reference signal input by the at least two circuits to generate a first frequency signal and a second frequency signal, a first switch controls the output of the first frequency signal, a second switch controls the output of the second frequency signal, a third switch controls the final output of the first frequency signal or the second frequency signal, and a control unit controls the conduction of the first switch, the second switch and the third switch to selectively output the first frequency signal or the second frequency signal, so that the rapid switching of the frequency output of the whole circuit is realized, and the multi-frequency point signal with high isolation and low spurious is output to meet the actual requirement.
Drawings
FIG. 1 is a schematic diagram of a multi-frequency point control circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-frequency point control circuit according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of a multi-frequency point control circuit in another embodiment of the present invention;
fig. 4 is a schematic diagram of a multi-frequency point control circuit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, a schematic diagram of a multi-frequency point control circuit according to an embodiment of the present invention is shown. The multi-frequency point control circuit 100 includes:
the power divider 110 is configured to divide a circuit of an input reference signal into at least two circuits, where the at least two circuits include the first circuit 101 and the second circuit 102.
At least two processing units including a first processing unit 121 and a second processing unit 122.
In this embodiment, the power divider 110 is a one-to-two power divider, the input reference signal F is amplified to a suitable level by an amplifier (not shown), and the circuit of the input reference signal F is divided into two circuits, i.e., the first circuit 101 and the second circuit 102, by the one-to-two power divider 110.
A first processing unit 121, connected to the first circuit 101, for processing an input reference signal F to generate a first frequency signal a; and a second processing unit 122, connected to the second circuit 102, for processing the input reference signal F to generate a second frequency signal B.
A first switch 131 connected to the first processing unit 121, for controlling the output of the first frequency signal a; a second switch 132 connected to the second processing unit 122 for controlling the output of the second frequency signal B; and a third switch 140 connected to the first switch 131 and the second switch 132, for controlling the output of the first frequency signal a or the second frequency signal B.
And a control unit 150 connected to the first switch 131, the second switch 132, and the third switch 140, for controlling the first switch 131, the second switch 132, and the third switch 140 to be turned on, and selectively outputting the first frequency signal a or the second frequency signal B.
In one embodiment, the control unit 150 is a TTL level signal control unit, and outputs a TTL level signal to control the first switch 131, the second switch 132 and the third switch 140 to be turned on, so as to selectively output the first frequency signal a or the second frequency signal B.
In one embodiment, the TTL level signal control unit inputs a low level, the first switch 131 and the third switch 140 are turned on, the second switch 132 is turned off, and the first frequency signal a is selectively output; the TTL level signal control unit inputs a high level, the second switch 132 and the third switch 140 are turned on, the first switch 131 is turned off, and the second frequency signal B is selectively output.
In this embodiment, the power divider 110 divides the reference signal F into two paths, and outputs the two paths after being processed by the processing unit, where one path of the control unit 150 controls the first switch 131 and the third switch 140 to be turned on, and the second switch 132 is turned off, and selects to output the first frequency signal a; the other path of the control unit 150 controls the second switch 132 and the third switch 140 to be turned on, and the first switch 131 is turned off to selectively output the second frequency signal B. The invention adopts a hardware circuit, realizes the single reference signal input and the selective output of multi-frequency point signals of the circuit, increases the reliability of the circuit, and increases the isolation of the whole circuit by controlling and selecting the output of any frequency signal through two switches. Furthermore, because two frequency signals exist all the time in the whole circuit, the switching time of the switch is the switching time of the signals, the invention controls the switching output of the signals with different frequencies by controlling the on and off of the switch through the TTL level signal control unit, thereby realizing the rapid switching between the signals with different frequencies, achieving the ns level of switching time and greatly improving the switching delay performance.
Fig. 2 is a schematic diagram of a multi-frequency point control circuit according to another embodiment of the present invention. On the basis of fig. 1, the first processing unit of the multi-frequency point control circuit 200 is a frequency dividing unit 221, configured to perform frequency dividing processing on the input reference signal to generate the first frequency signal a; the second processing unit is a frequency doubling unit 222, configured to perform frequency doubling processing on the input reference signal to generate the second frequency signal B.
The present invention takes the input reference signal F as 100MHz, the first frequency signal a as 450MHz and the second frequency signal B as 500MHz as an example to explain the working process of the multi-frequency point control circuit 200 provided by the present invention.
In one embodiment, the frequency dividing unit 221 includes a frequency divider 2211, a first low pass filter 2212, a first amplifier 2213, and a first high pass filter 2214.
In one embodiment, the frequency multiplying unit 222 includes a frequency multiplier 2221, a second low pass filter 2222, a second amplifier 2223, and a second high pass filter 2224.
The input reference signal F (100 MHz) is amplified to a suitable level through an amplifier (not shown), and the circuit of the input reference signal F is divided into two circuits, i.e., a first circuit 201 and a second circuit 202, by the one-to-two power divider 210.
The frequency divider 2211 is connected to the first circuit 201, and the reference signal F (100 MHz) passes through the half frequency divider 2211 to generate a frequency-divided signal F/2 (50 MHz) of the reference signal F (100 MHz) and a harmonic signal (F/2) × N of the frequency-divided signal (i.e. 50mhz,100mhz,150mhz, \8230;); the first low pass filter 2212 is connected to the frequency divider 2211, and extracts a first signal which is less than or equal to the first frequency signal a (450 MHz) from a frequency-divided signal F/2 (50 MHz) of the reference signal F (100 MHz) and a harmonic signal (F/2) × N of the frequency-divided signal; the first amplifier 2213 is connected to the first low-pass filter 2212, and is configured to increase the level of the reference signal input to the frequency dividing unit 221 so as to compensate for a level loss caused by filtering the signal; the first high-pass filter 2214 is connected to the first amplifier 2213, and extracts a second signal, which is greater than or equal to the first frequency signal a (450 MHz), from among a frequency-divided signal F/2 (50 MHz) of the reference signal F (100 MHz) and a harmonic signal (F/2) × N of the frequency-divided signal, the obtained second signal including the first frequency signal a (450 MHz); the first switch 131 is connected to the first high pass filter 2214, and controls the output of the first frequency signal a (450 MHz).
The frequency multiplier 2221 is connected to the second circuit 202, and the reference signal F (100 MHz) passes through the frequency multiplier 2221 to generate a frequency-multiplied signal (100 MHz) of the reference signal F (100 MHz) and a harmonic signal F × M of the frequency-divided signal (i.e., 100mhz,200mhz,300mhz, \8230;); the second low-pass filter 2222 is connected to the frequency multiplier 2221, and extracts a third signal that is less than or equal to the second frequency signal B (500 MHz) from a frequency multiplication signal F (100 MHz) of the reference signal F (100 MHz) and a harmonic signal F × M of the frequency multiplication signal; the second amplifier 2223 is connected to the second low-pass filter 2222, and is configured to increase the level of the reference signal input to the frequency doubling unit 222, so as to compensate for the level loss caused by filtering the signal; the second high-pass filter 2224 is connected to the second amplifier 2223, and extracts a fourth signal that is greater than or equal to the second frequency signal B (500 MHz) from a frequency multiplication signal F (100 MHz) of the reference signal F (100 MHz) and a harmonic signal F × M of the frequency multiplication signal, where the obtained fourth signal includes the second frequency signal B (500 MHz); the second switch 132 is connected to the second high pass filter 2224, and controls the output of the second frequency signal B (500 MHz).
In an embodiment, the frequency dividing unit 221 may include a plurality of filters and amplifiers, the frequency doubling unit 222 may also include a plurality of filters and amplifiers, the filters implement extracting useful signals required in the circuit and filtering out other harmonics and spurious signals, the amplifiers implement level loss compensation of the whole circuit, and the connection relationship is only required to satisfy that each element normally works in the whole circuit, which is not limited herein.
When the control unit 250 inputs a level signal to control the output of the first frequency signal a (450 MHz), the first switch 231 and the third switch 240 are turned on, the second switch 232 is turned off, and the third switch 240 outputs the first frequency signal a (450 MHz);
when the control unit 250 inputs a level signal to control the output of the second frequency signal B (500 MHz), the second switch 232 and the third switch 240 are turned on, the first switch 231 is turned off, and the third switch 240 outputs the second frequency signal B (500 MHz).
In one embodiment, the first processing unit 221 and the second processing unit 222 are both frequency dividing units, and are configured to perform frequency dividing processing on the input reference signal F to generate the first frequency signal a and the second frequency signal B, where the first processing unit 221 generates the first frequency signal a and the second processing unit 222 generates the second frequency signal B. The specific process is as described above and will not be described herein again, when the generated multi-frequency-point signals are all integer multiples of the frequency-divided signal (for example, if the input is 100MHz for the reference signal F, a half frequency divider is used, the generated first frequency signal a is 150MHz, and the generated second frequency signal B is 450 MHz).
In one embodiment, the first processing unit 221 and the second processing unit 222 are both frequency doubling units, and configured to perform frequency doubling processing on the input reference signal F to generate the first frequency signal a and the second frequency signal B; the first processing unit 221 generates the first frequency signal a, and the second processing unit 222 generates the second frequency signal B. The method is applied to the case that the generated multi-frequency point signals are all integer multiples of the frequency doubling signal (for example, the input reference signal F is 100MHz, a frequency multiplier is adopted, the output first frequency signal a is selected to be 200MHz, and the output second frequency signal B is 500 MHz), and the specific process is as described above, and is not described herein again.
In this embodiment, the frequency dividing unit 221 includes a frequency divider 2211, a first low pass filter 2212, a first amplifier 2213 and a first high pass filter 2214, so as to extract the first frequency signal a (450 MHz), and the frequency multiplying unit 222 includes a frequency divider 2221, a second low pass filter 2222, a second amplifier 2223 and a second high pass filter 2224, so as to extract the second frequency signal B (500 MHz). According to the invention, the first/second low-pass filter 2212/2222 is adopted, and the first/second high-pass filter 2214/2224 carries out filtering processing on the first frequency signal A (450 MHz) and the second frequency signal B (500 MHz), so that harmonics of other signals are suppressed, the stray of the first frequency signal A (450 MHz)/the second frequency signal B (500 MHz) is reduced, the control is easy to be below the bottom noise of the whole circuit, and the influence of the generated stray of the first frequency signal A (450 MHz)/the second frequency signal B (500 MHz) on the whole circuit is avoided. In addition, in this embodiment, a 100MHz input reference signal is adopted, and a 450MHz or 500MHz signal is selected to be output, so that a harmonic signal including 500MHz is not generated in the process of generating the 450MHz signal by the frequency divider, and a harmonic signal including 450MHz is not generated in the process of generating the 500MHz signal by the frequency multiplier, thereby further realizing low spurious of the generated multi-frequency point signal (450 MHz/500MHz signal). In addition, the two circuits for generating signals with different frequencies adopt the same filter element and amplifier, so that the amplitude balance degree of the two circuits is reduced while the amplitude difference of the output signals of the two circuits is reduced.
Fig. 3 is a schematic diagram of a multi-frequency point control circuit according to another embodiment of the present invention. The difference from fig. 2 is that the multi-frequency point control circuit 300 further includes:
a first load 303 connected to the first switch 331 for consuming the first frequency signal;
a second load 304 connected to the second switch 332 for consuming the second frequency signal.
When the control unit 350 controls to output the first frequency signal a (450 MHz), the first switch 331 and the third switch 340 are turned on, the second switch 332 and the second load 304 are turned on, the second frequency signal B (500 MHz) flows to the second load 304 through the second switch 332, the first frequency signal a (450 MHz) flows to the third switch 340 through the first switch 331, the control unit 350 controls the third switch 340 to be turned on, and the third switch 340 outputs the first frequency signal a (450 MHz). The second load 304 consumes the second frequency signal B (500 MHz), reducing the leakage of the second frequency signal B (500 MHz) to the third switch 340, and avoiding affecting the output of the first frequency signal a (450 MHz).
When the control unit 350 controls to output the second frequency signal B (500 MHz), the second switch 332 and the third switch 340 are turned on, the first switch 331 and the first load 303 are turned on, the first frequency signal a (450 MHz) flows to the first load 303 through the first switch 331, the second frequency signal B (500 MHz) flows to the third switch 340 through the second switch 332, the control unit 350 controls the third switch 340 to be turned on, and the third switch 340 outputs the second frequency signal B (500 MHz). The first load 303 consumes the first frequency signal a (450 MHz), reducing leakage of the first frequency signal a (450 MHz) to the third switch 340, and avoiding affecting output of the second frequency signal B (500 MHz).
In this embodiment, when the control unit 350 controls to output the first frequency signal a (450 MHz), the control unit controls on and off of the switch combination (the first switch 331, the second switch 332, and the third switch 340) to enable the second frequency B (500 MHz) to flow to the second load 304 for consumption, and when the control unit 350 controls to output the second frequency signal B (500 MHz), the control unit controls on and off of the switch combination (the first switch 331, the second switch 332, and the third switch 340) to enable the first frequency a (450 MHz) to flow to the first load 303 for consumption, thereby reducing leakage between different frequency signals, further increasing isolation of the switches, and finally selecting the output frequency signal more accurately.
Fig. 4 is a schematic diagram of a multi-frequency point control circuit according to another embodiment of the present invention. The difference from fig. 3 is that the multi-frequency point control circuit 400 further includes:
a first extracting unit 461 connected to the first switch 431 and the third switch 440 for extracting the first frequency signal; a second extracting unit 462 connected to the second switch 440 and the third switch 450 for extracting the second frequency signal.
In one embodiment, the first extracting unit 461 comprises: a first bandpass filter 4611, a third amplifier 4612, and a second bandpass filter 4613.
In one embodiment, the second extraction unit 462 includes: a third bandpass filter 4621, a fourth amplifier 4622, and a fourth bandpass filter 4623.
When the control unit 450 controls to output the first frequency signal a (450 MHz), the first switch 431 and the third switch 440 are turned on, the second switch 432 and the second load 404 are turned on, the second frequency signal B (500 MHz) flows to the second load 404 through the second switch 432, the first bandpass filter 4611 is connected to the first switch 430, and the first frequency signal a (450 MHz) flows to the first bandpass filter 4611 through the first switch 431 to extract the first frequency signal a (450 MHz) in the third signal; the third amplifier 4612 is connected to the first band-pass filter 4611 to increase the level of the first frequency signal a (450 MHz) to compensate for the level loss caused by filtering; said third amplifier 4612 is connected to said second band-pass filter 4613 to further extract said first frequency signal a (450 MHz); the third switch 440 is connected to the second band-pass filter 4613, the control unit 450 controls the third switch 440 and the second band-pass filter 4613 to be turned on, and the third switch 440 and the fourth band-pass filter 4623 are turned off, so as to selectively output the first frequency signal a (450 MHz).
When the control unit 450 controls to output the second frequency signal B (500 MHz), the second switch 432 and the third switch 440 are turned on, the first switch 431 and the first load 403 are turned on, the first frequency signal a (450 MHz) flows to the first load 403 through the first switch 431, the third band-pass filter 4621 is connected to the second switch 432, and the second frequency signal B (500 MHz) flows to the third band-pass filter 4621 through the second switch 432, so as to extract the second frequency signal B (500 MHz) in the fourth signal; the fourth amplifier 473 is connected to the third band-pass filter 4621 to increase the level of the second frequency signal B (500 MHz) to compensate for the level loss caused by the signal being filtered; said fourth amplifier 4622 is connected to said fourth band-pass filter 4623 to further extract said second frequency signal B (500 MHz); the third switch 440 is connected to the fourth amplifier 4622, the control unit 450 controls the third switch 440 and the fourth bandpass filter 4623 to be turned on, and the third switch 440 and the second bandpass filter 4613 are turned off, so as to selectively output the second frequency signal B (500 MHz).
In an embodiment, the first extraction unit 461 may include a plurality of band pass filters and amplifiers, the second extraction unit 462 may include a plurality of band pass filters and amplifiers, the filters implement extracting useful signals required in the circuit, filtering out other harmonics and spurious signals, the amplifiers implement level loss compensation of the whole circuit, and the connection relationship is only required to satisfy that each element normally works in the whole circuit, which is not limited herein.
Through the multifrequency point control circuit described in this embodiment, adopt the reference signal of input 100MHz, select the signal of output 450MHz or 500MHz, through the test, the output amplitude of 450MHz signal and 500MHz signal is about 3dBm, and output amplitude balance degree is within 2dB, and the phase noise of reference signal 100MHz is (-138 dBc/Hz @ 10KHz), and the phase noise of two frequency points of actual design output is: the frequency point is 450MHz (-128 dBc/Hz @ 10KHz), the frequency point is 500MHz (-130 dBc/Hz @ 10KHz), and when the output frequency point is 450MHz, the leakage power of the frequency point is 500MHz is smaller than 75dBc; when the frequency point is output at 500MHz, the leakage power of the frequency point at 450MHz is less than 80dBc, and the integral design requirement is met.
In summary, in the frequency point control circuit provided by the present invention, the reference signal is divided into two circuit signals by the power divider, two signals with different frequencies are obtained by different processing units, and the signals with different frequencies are connected to the switch combination. The control unit controls a switch combination, when the control unit inputs a control signal to select to output a first frequency signal, the second switch is conducted with the second load, the second frequency signal is selectively output to the second load to be consumed, the first switch is conducted with a first extraction unit, the first extraction unit further extracts and filters the first frequency signal and outputs the first frequency signal to a third switch, the third switch is conducted with the first extraction unit, the third switch is disconnected with the second extraction unit, and the third switch outputs the first frequency signal; when the control unit inputs a control signal to select to output a second frequency signal, the first switch is conducted with the first load, the first frequency signal is selectively output to the first load to be consumed, the second switch is conducted with the second extraction unit, the second extraction unit further obtains the second frequency signal, extracts, filters and outputs the second frequency signal to the third switch, the third switch is conducted with the second extraction unit, the third switch is disconnected with the first extraction unit, and the third switch outputs the second frequency signal, so that input of a single reference signal, selective output of multi-frequency point signals, switching of frequency output of the whole circuit is rapid, and the multi-frequency point signals selected to be output have the characteristics of high isolation and low spurious.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A multi-frequency point control circuit, the multi-frequency point control circuit comprising:
the power divider is used for dividing a circuit of an input reference signal into at least two circuits, and the at least two circuits comprise a first circuit and a second circuit;
at least two processing units, including a first processing unit and a second processing unit;
the first processing unit is connected with the first circuit and used for processing an input reference signal to generate a first frequency signal;
the second processing unit is connected with the second circuit and used for processing the input reference signal to generate a second frequency signal;
the first switch is connected with the first processing unit and is used for controlling the output of the first frequency signal;
the second switch is connected with the second processing unit and used for controlling the output of the second frequency signal;
a third switch connected to the first switch and the second switch, for controlling an output of the first frequency signal or the second frequency signal;
a control unit connected to the first switch, the second switch, and the third switch, for controlling the on/off of the first switch, the second switch, and the third switch, and selectively outputting the first frequency signal or the second frequency signal;
the multi-frequency point control circuit further comprises:
a first extracting unit connected to the first switch and the third switch, for extracting the first frequency signal;
and the second extraction unit is connected with the second switch and the third switch and used for extracting the second frequency signal.
2. The multi-frequency-point control circuit of claim 1,
the first processing unit is a frequency dividing unit and is used for performing frequency dividing processing on the input reference signal to generate the first frequency signal;
the second processing unit is a frequency doubling unit and is configured to perform frequency doubling processing on the input reference signal to generate the second frequency signal.
3. The multi-frequency point control circuit of claim 1,
the first processing unit and the second processing unit are both frequency dividing units, and are configured to perform frequency dividing processing on the input reference signal to generate the first frequency signal and the second frequency signal, where the first processing unit generates the first frequency signal, and the second processing unit generates the second frequency signal.
4. The multi-frequency point control circuit of claim 1,
the first processing unit and the second processing unit are frequency doubling units and are used for performing frequency doubling processing on the input reference signal to generate a first frequency signal and a second frequency signal; the first processing unit generates the first frequency signal, and the second processing unit generates the second frequency signal.
5. The multi-frequency-point control circuit of claim 2, wherein the frequency-dividing unit comprises a frequency divider, a first low-pass filter, a first amplifier, and a first high-pass filter;
the frequency divider is connected with the first circuit and used for generating a frequency division signal of the reference signal and a harmonic signal of the frequency division signal;
the first low-pass filter is connected with the frequency divider and is used for extracting a first signal which is less than or equal to the first frequency signal in a frequency division signal of the reference signal and a harmonic signal of the frequency division signal;
the first amplifier is connected with the first low-pass filter and used for increasing the level of a reference signal input into the frequency dividing unit;
the first high-pass filter is connected with the first amplifier and the first switch and used for extracting a second signal which is greater than or equal to the first frequency signal in a frequency division signal of the reference signal and a harmonic signal of the frequency division signal.
6. The multi-frequency-point control circuit of claim 2, wherein the frequency multiplying unit comprises a frequency multiplier, a second low-pass filter, a second amplifier, and a second high-pass filter;
the frequency multiplier is connected with the second circuit and used for generating a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal;
the second low-pass filter is connected with the frequency multiplier and is used for extracting a third signal which is less than or equal to the second frequency signal from a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal;
the second amplifier is connected with the second low-pass filter and used for increasing the level of the reference signal input into the frequency doubling unit;
the second high-pass filter is connected with the second amplifier and the second switch and used for extracting a fourth signal which is greater than or equal to the second frequency signal in a frequency multiplication signal of the reference signal and a harmonic signal of the frequency multiplication signal.
7. The multi-frequency point control circuit of claim 1, further comprising:
the first load is connected with the first switch and used for consuming the first frequency signal;
and the second load is connected with the second switch and used for consuming the second frequency signal.
8. The multi-frequency-point control circuit of claim 1, wherein the first extraction unit comprises:
a first band pass filter and a third amplifier;
the first band-pass filter is connected with the first switch and used for extracting the first frequency signal;
the third amplifier is connected with the first band-pass filter, and the amplifier is used for increasing the level of the first frequency signal;
the third switch is connected with the third amplifier and controls to output the first frequency signal.
9. The multi-frequency-point control circuit of claim 1, wherein the second extraction unit comprises:
a second band pass filter and a fourth amplifier;
the second band-pass filter is connected with the second switch and used for extracting the second frequency signal;
the fourth amplifier is connected with the second band-pass filter, and the amplifier is used for increasing the level of the second frequency signal;
and the third switch is connected with the fourth amplifier and controls and outputs the second frequency signal.
10. The multi-frequency-point control circuit of claim 1, wherein the control unit is a TTL level signal control unit.
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| CN1854741A (en) * | 2005-04-29 | 2006-11-01 | 特克特朗尼克公司 | Multi-band amplifier for test and measurement instruments |
| CN101459465A (en) * | 2007-12-11 | 2009-06-17 | 中兴通讯股份有限公司 | Local oscillation device supporting multiple frequency band working mode |
| CN104378110A (en) * | 2013-08-15 | 2015-02-25 | 同方威视技术股份有限公司 | Frequency sweeping signal generating circuit |
| CN104734792A (en) * | 2014-12-24 | 2015-06-24 | 中国计量科学研究院 | Hybrid two-channel millimeter wave attenuation measuring method and system |
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| CN1854741A (en) * | 2005-04-29 | 2006-11-01 | 特克特朗尼克公司 | Multi-band amplifier for test and measurement instruments |
| CN101459465A (en) * | 2007-12-11 | 2009-06-17 | 中兴通讯股份有限公司 | Local oscillation device supporting multiple frequency band working mode |
| CN104378110A (en) * | 2013-08-15 | 2015-02-25 | 同方威视技术股份有限公司 | Frequency sweeping signal generating circuit |
| CN104734792A (en) * | 2014-12-24 | 2015-06-24 | 中国计量科学研究院 | Hybrid two-channel millimeter wave attenuation measuring method and system |
| CN208539895U (en) * | 2018-07-26 | 2019-02-22 | 维沃移动通信有限公司 | A kind of anti-jamming circuit and mobile terminal |
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