EP2033305B1 - Mixer circuit and method to operate this mixer circuit - Google Patents

Mixer circuit and method to operate this mixer circuit Download PDF

Info

Publication number
EP2033305B1
EP2033305B1 EP07789697.5A EP07789697A EP2033305B1 EP 2033305 B1 EP2033305 B1 EP 2033305B1 EP 07789697 A EP07789697 A EP 07789697A EP 2033305 B1 EP2033305 B1 EP 2033305B1
Authority
EP
European Patent Office
Prior art keywords
signal
current
branch
mixer circuit
pseudo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP07789697.5A
Other languages
German (de)
French (fr)
Other versions
EP2033305A2 (en
Inventor
Frederic F. Villain
Olivier Burg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to EP06300726 priority Critical
Application filed by NXP BV filed Critical NXP BV
Priority to PCT/IB2007/052298 priority patent/WO2008001256A2/en
Priority to EP07789697.5A priority patent/EP2033305B1/en
Publication of EP2033305A2 publication Critical patent/EP2033305A2/en
Application granted granted Critical
Publication of EP2033305B1 publication Critical patent/EP2033305B1/en
Application status is Expired - Fee Related legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1441Balanced arrangements with transistors using field-effect transistors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1458Double balanced arrangements, i.e. where both input signals are differential
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1475Subharmonic mixer arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1483Balanced arrangements with transistors comprising components for selecting a particular frequency component of the output
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • G06F7/584Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register

Description

    FIELD OF THE INVENTION
  • The present invention relates to a mixer circuit and a method to operate this mixer circuit.
  • BACKGROUND OF THE INVENTION
  • In direct conversion and zero-IF (Intermediate Frequency) receivers, it is necessary to maintain the spectral purity of the channel used for reception. Because of limited narrow band selectivity, second order intermodulation distortion (IM2) presents an undesired spectral component within the signal band of interest. This occurs when two or more interfering signals, whose difference in frequency is less than the IF bandwidth of the desired signal, mix with one another due to some second order nonlinearity and produce a baseband spectral component. To minimize the effects of second order intermodulation within critical circuit blocks in the signal path, it is known in the art to use differential circuits. In theory, differential circuits have infinite attenuation to second order intermodulation distortion. In reality, this is far from the truth; due, in no small part, to device mismatches, parametric imbalance, imperfect layout, and other device characteristic inequalities that cause imbalances and provides a lower than desired second order input intercept point (IIP2).
  • IM2 and IIP2 are further defined in EP 1 111 772 , for example.
  • EP 1 111 772 discloses several embodiments of a mixer circuit. Most of these embodiments are double-balanced mixer circuits that need a differential RF (Radio Frequency) signal as inputs.
  • In Fig. 8 of EP 1 111 772 a single balanced mixer circuit is disclosed that needs not a differential RF signal as inputs. This single balanced mixer circuit mixes the RF signal with a LO (Local Oscillator) signal to generate an IF (Intermediate Frequency) signal. This single balanced mixer circuit has a mixing branch including:
    • a transconductance stage having an RF input to receive the RF signal to transform into a current signal, and
    • a current switching core to switch the current signal according to the LO signal and an LO signal which forms with the LO signal a differential signal.
  • However, this single-balanced mixer circuit does not properly reject the LO signal or harmonic of the LO signal in the IF signal.
  • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the invention to provide a mixer circuit which does not need a differential RF signal as inputs while properly rejecting LO signal or LO signal harmonic in the outputted IF signal.
  • The invention provides a mixer circuit according to claim 1 that in addition of the mixing branch has:
    • a dummy branch connected in parallel of the mixing branch (4), the dummy branch comprising:
    • a transconductance stage having an input connected to a reference potential which is independent from the RF signal, to transform the reference potential into a current signal, and
    • a current switching core to switch the current signal according to LO and LO signals, and
    • chopping switches to connect in series the transconductance stage of the mixing branch to the current switching core of the mixing branch and, in alternance, to the current switching core of the dummy branch under the control of a chopping signal, the chopping switches being also able to connect in series the transconductance stage of the dummy branch to the current switching core of the dummy branch and, in alternance to the current switching core of the mixing branch under the control of the chopping signal.
  • In the above mixer the use of chopping switches increases the IIP2. Furthermore, the dummy branch prevents the LO signal from passing to the IF signal. Thus, the above mixer circuit achieves a better noise rejection that the embodiment of Fig. 8 of EP 1 111 772 while still achieving equivalent or better IIP2.
  • The embodiments of the above terminal may comprise one or several of the following features:
    • the mixer circuit has a chopping signal generator able to generate the chopping signal which is a pseudo-random bit sequence that systematically has as many logical zeros as logical ones over one period,
    • the pseudo-random bit sequence generator comprises:
    • a pseudo-random bit sequence builder which builds a pseudo-random bit sequence having a period TB and having a number of logical zeros different from the number of logical ones over period TB, and
    • a reversing core able to output, in alternance, the built pseudo-random bit sequence and its opposite so as to output a longer pseudo-random bits sequence having exactly as many logical zeros as logical ones over each period of this longer pseudo-random bit sequence,
    • the current switching core is series connected with the transconductance stage through a filter having a cut-off frequency strictly higher than zero, and
    • the current switching core is connected between a DC current source and a DC current sink and wherein the transconductance stage is directly connected to another DC current source without passing through one of the current switching stages.
  • The above embodiments of the mixer circuit present the following advantages:
    • cross-switching the connection of the transconductance stage of the mixing and dummy branches with the current switching core of the mixing and dummy branches improves the rejection of the LO signal in the generated IF signal,
    • generating a pseudo-random bit sequence which has systematically as many logical zeros as logical ones improves IM2 cancellation,
    • using a reversing core at the output of a pseudo-random bit sequence builder to obtain the pseudo-random bit sequence having as many logical zeros as logical ones does not impose any constraint to the choice of the pseudo-random bit sequence builder,
    • using a filter having a cut-off frequency strictly higher than zero allows for cancellation of IM2 produced by the chopping switches, and
    • having the transconductance stage directly connected to a DC current source without passing through one of the current switching stages, decreases the power consumption of the mixer circuit.
  • The invention also relates to a method of operating the above mixer circuit according to claim 6.
  • BRIEF DESCRIPTION OF THE DRAWINGS
    • Fig. 1 is a schematic diagram of a mixer circuit,
    • Fig. 2 is a schematic diagram of a pseudo-random bit generator used in the mixer circuit of Fig. 1,
    • Fig. 3 is a schematic diagram of a chopping signal generator used in the mixer circuit of Fig. 1,
    • Figs. 4A and 4B are timing charts of clock signal used in the generator of Fig. 3, and
    • Fig. 5 is a flowchart of a method to operate the mixer circuit of Fig. 1.
    PREFERRED EMBODIMENTS
  • Fig.1 shows a mixer circuit 2 which is intended to mix LO signal with an RF signal to obtain the IF signal.
  • To this end, circuit 2 has a mixing branch 4 connected between a DC supply line 6 and a reference potential 8 like ground.
  • Branch 4 has a transconductance stage 10 which is connected to a current switching core 12 through a filter 14.
  • Stage 10 is able to transform the RF signal received on an input 16 into a current signal Is. For example, stage 10 includes a transistor Q1 having a base connected to an input 16, an emitter connected to ground 8 and a collector connected to core 12 though filter 14.
  • Input 16 is connected to a RF input 24 through a capacitor 22.
  • Current switching core 12 is designed to switch current Is according to the LO signal.
  • For example, core 12 includes two transistors Q5 and Q6, emitters of which are connected together. The base of transistors Q5 and Q6 are directly connected to an LO input 26 and a LO input 28, respectively. Inputs 26 and 28 receive LO signal 26 and LO signal, respectively. LO signal is equal to LO signal multiplied by "-1".
  • The collector of transistor Q5 is connected to a voltage load 30. For example, load 30 is built from a resistor R2 connected in parallel with a capacitor C2. Load 30 is connected between line 6 and the collector of transistor Q5.
  • The emitter of transistors Q5 and Q6 are connected through filter 14 to the collector of transistor Q1. The emitters of Q5 and Q6 are also connected to a DC current sink 32. For example, DC current sink 32 is a single resistor R1 connected on one side to the emitters of transistors Q5 and Q6 and on the other side to ground.
  • Filter 14 has a cut-off frequency which is strictly higher than zero so that only frequency component of current Is which are different from zero can pass through filter 14. For example, filter 14 is a capacitor C1. One plate of capacitor C1 is directly connected to the emitters of transistors Q5 and Q6 whereas the opposite plate is connected to the collector of transistor Q1. The opposite plate is also connected to a DC current source 34. For example, source 34 is a transistor having an emitter connected to line 6 and a collector connected to both filter 14 and the collector of transistor Q1. The base of the transistor is connected to a voltage source VC which determines the amount of current generated by source 34.
  • Mixer circuit 2 has also a dummy branch 42 which is connected in parallel of branch 4 between line 6 and ground 8.
  • Branch 42 is identical to branch 40 except that the transconductance stage input receives a constant reference voltage VREF instead of the RF signal. More precisely, branch 42 has a transconductance stage 44 that converts voltage VREF into a current signal Id and a current switching core 46 that switches current Id according to LO and LO signals.
  • Stage 44 and current switching core 46 are identical to stage 10 and current switching core 12, respectively. In Fig. 1, the transistor of stage 44 and the transistors of core 46 have numerical references Q2, and Q7, Q8, respectively.
  • The other elements of branch 42 which are identical to those of branch 4 have the same numerical references.
  • More precisely, input 16 of stage 44 is connected through capacitor 22 to reference potential VREF. For example, potential VREF is equal to ground 8.
  • Mixer circuit 2 also includes changeover means 50 and 52 to increase IIP2 without needing a very accurate calibration of branch 4 components in relation to branch 42 components.
  • Changeover means 50 are able to connect:
    • stage 10 to current switching core 12 and stage 44 to current switching core 46 and, in alternance,
    • stage 10 to current switching core 46 and stage 44 to current switching core 12.
  • For instance, changeover means 50 include four chopping switches QC1, QC2, QC3 and QC4. Switches QC1, QC2, QC3 and QC4 are transistors that switch under the control of a chopping signal ϕ and a reverse chopping signal ϕ. Signal ϕ is equal to signal ϕ multiplied by "-1".
  • Changeover means 50 are interposed between filters 14 and transconductance stages 10 and 44. More precisely, emitters of transistors QC1 and QC2 are directly connected to the collector of transistor Q1 and emitters of QC3 and QC4 are directly connected to the collector of transistor Q2.
  • Collectors of QC1 and QC3 are directly connected to filter 14 and current source 34 of branch 4. Collectors of transistors QC2 and QC4 are directly connected to filter 14 and current source 34 of branch 42.
  • The bases of transistors QC1 and QC4 are connected to an input 54 to receive signal ϕ and bases of transistors QC2 and QC3 are connected to an input 56 to receive signal ϕ.
  • Changeover means 52 are arranged so that whether current Is is switched by core 12 or by core 46, the resulting current is always outputted through an IF terminal 60 and the resulting reversed current is always outputted through an IF terminal 62.
  • Changeover means 52 are also arranged so that whether current Id is switched by core 12 or, in alternance by core 46, the resulting switched current is always outputted through an IF terminal 62.
  • For example, changeover means 52 include four chopping switches QC5, QC6, QC7 and QC8. Here switches QC5 to QC8 are transistors. The collectors of switches QC5 and QC8 are directly connected to the collectors of transistors Q5 and Q6, respectively. The collectors of transistors QC5 and QC8 are also directly connected to collectors of transistors Q7 and Q8, respectively.
  • The emitters of transistors QC5 and QC8 are directly connected to terminals 60 and 62. respectively.
  • The collectors of transistors QC6 and QC7 are directly connected to the collectors of transistors Q6 and Q5, respectively. The collectors of transistors QC6 and QC7 are also directly connected to the collectors of transistors Q8 and Q7, respectively. Emitters of transistors QC6 and QC7 are directly connected to terminals 60 and 62, respectively.
  • The bases of transistors QC5 and QC6 receives signal ϕ whereas the bases of transistors QC7 and QC8 receives signal ϕ.
  • Finally, mixer circuit 2 has also a generator 66 that generates LO and LO signals and a chopping signal generator 68 that generates signals ϕ and ϕ.
  • For simplicity, the connections between the outputs of generators 66 and 68 and every branch inputs have not been shown as illustrated by the dotted lines.
  • Fig. 2 illustrates a pseudo-random bit sequence generator 70 which is used in generator 68. Generator 70 is designed to output a pseudo-random bit sequence which systematically has as many logical zeros as logical ones. This greatly improves the IIP2.
  • For example, generator 70 has a pseudo-random bit sequence builder 72 and a reversing core 74.
  • Builder 72 outputs pseudo-random bit sequence W0 through output terminal 76. The pseudo-random bit sequence has a period TB.
  • For instance, builder 72 is a feedback shift register having n series connected registers R0 to Rn-1. Each register delays by one clock period the logical value present at its entrance. Each register is clocked by a clock signal clk.
  • Registers R0 to Rn-1 output the values W0 to Wn-1, respectively. Each output of registers Ro to Rn-1 is feedback connected to the entrance of register Rn-1 through a respective block Ci and a respective XOR gate Xi. Block Ci either directly connects the output of register Ri to an input of XOR gate Xi or systematically outputs a zero at the input of XOR gate Xi. Preferably, blocks Ci are chosen so as to provide a maximum length pseudo-random sequence according to Galois' theory, for example. In that case, for n registers, during one period, the outputted signal by builder 72 contains 2n-1 -1 even values and 2n-1 odd values. Thus, the number of logical zeros is not equal to the number of logical ones in the output of builder 72.
  • To obviate this problem, the output of builder 72 is connected to reverse core 74. Reverse core 74 outputs the pseudo-random sequence generated by builder 72 and, in alternance, the opposite pseudo-random bit sequence. The opposite pseudo-bit random sequence is obtained by substituting in the pseudo-random sequence each logical zero by a logical one and each logical one by a logical zero.
  • For example, reversing core 74 has a AND gate 78 designed to make a AND operation between each value outputted by registers R0 to Rn-1. The output of gate 78 is connected to an input of an XOR gate 80. The output of gate 80 is connected to an input of a register 82. The output of register 82 is connected to a second input of gate 80.
  • The output of register 82 is also connected to a first input of an XOR gate 84. The second input of XOR gate 84 is directly connected to the output of register R0. The output of gate 84 is connected to an output 86 of generator 70 through a register 88.
  • When the output of register 82 is equal to zero, output 86 outputs a pseudo-random bit sequence which is equal to the pseudo-random bit sequence built by builder 72. When the output of register 82 is equal to one, output 86 outputs a pseudo-random bit sequence which is the opposite of the pseudo-random bit sequence built by builder 72.
  • More precisely, reversing core 74 detects the end of a period of the pseudo-random bits sequence generated by builder 72 when each value Wo to Wn-1 are equal to a logical one. In response, the output of register 82 shifts from zero to one or conversely from one to zero. The value of the output of register 82 remains constant as long as the end of the period of the pseudo-random bit sequence generated by builder 72 has not been reached. Thus, the pseudo-random bit sequence outputted through output 86 has a period of 2TB and is made from one pseudo-random bit sequence followed by the opposite pseudo-random bit sequence. As a consequence, the pseudo-random bit sequence outputted through output 86 has as many logical ones as logical zeros.
  • Fig. 3 shows in more details generator 68.
  • Generator 68 includes pseudo-random bit sequence generator 70 which is clocked by a clock signal clk. The output 86 of generator 70 is connected to a buffer 90, output of which is connected to an input of a register 92. Register 92 is clocked by signal clk which is passed through a buffer 94. The output of register 92 is connected to an input of a multiplexer 96. The clock outputted by buffer 94 is also inputted in a clock divider 98. The output of divider 98 is connected to an input of multiplexer 96.
  • Divider 98 divides by two the frequency of the clock signal clk so as to obtain a square wave having a duty cycle very close to 50% even if the clock signal is not ideal.
  • The output of multiplexer 96 is connected to the input of a buffer 100 which outputs both signals ϕ and ϕ.
  • Generator 68 is able to output a pseudo-random bit sequence having as many logical ones as logical zeros when multiplexer 96 selects the signals outputted through register 92 and, in alternance, to output a square wave having a duty cycle equal or very close to 50% when multiplexer 96 selects the output of divider 98.
  • Square waves and pseudo-random bit sequence are of interest in different situations as explained in EP 1 111 772 .
  • Figs. 4A and 4B show timing charts illustrating how divider 98 works. Fig. 4A shows a clock signal clk which has a duty cycle very far from 50%. In Fig. 4A, the duty cycle is close to 60%.
  • Divider 98 output shifts from a logical one to a logical zero and vice versa only at each rising edge of the clock signal. Thus, as can be seen from Fig. 4B, the duty cycle of the wave outputted by divider 98 becomes very close to 50% even if the clock cycle of the inputted clock signal is far away from this value.
  • Having a duty cycle close to 50% increases the IIP2.
  • The operation of mixer circuit 2 will now be described with reference to Fig. 5. In step 110, RF signal is inputted through input 24 to the transconductance stage. Thus, in step 110, stage 10 generates a current IS corresponding to the RF signal.
  • In parallel, in step 112, the reference potential VREF is inputted in transconductance stage 44 and stage 44 generates a current signal Id corresponding to potential VREF.
  • Subsequently, in step 114, changeover means 50 connect stage 10 to current switching core 12 and stage 44 to current switching core 46.
  • Thus, in a step 116, switching core 12 switches current signal Is according to LO and LO signals.
  • In parallel, in step 118, current signal Id is switched by switching core 46 according to LO and LO signals.
  • Subsequently, in response to chopping signals ϕ, ϕ changes, in step 120, changeover means 50 disconnect stage 10 from current switching core 12 and connect stage 10 to current switching core 46. At the same time, changeover means 50 disconnect stage 44 from current switching core 46 and connect stage 44 to current switching core 12.
  • Thus, current signal IS is then switched by current switching core 46 and current signal Id is switched by current switching core 12.
  • Then the operations are iterated.
  • Switching the current signal in alternance with current switching cores 12 and 46 increases IIP2 as disclosed in EP 1 111 772 .
  • Many other embodiments are possible. For example, chopping switches QC1, QC2, QC3 and QC4 may be placed elsewhere in the mixer circuit. For example, switches QC1, QC2, QC3 and QC4 may be placed at the same place as disclosed in the different embodiments of EP 1 111 772 .

Claims (6)

  1. A mixer circuit to mix a RF, Radio Frequency, signal with a LO, Local Oscillator, signal to generate an IF, Intermediate Frequency, signal, the mixer circuit having
    - a mixing branch (4) comprising a transconductance stage (10) having an RF input (16) to receive the RF signal to transform into a current signal (Is), and a dummy branch (42) connected in parallel of the mixing branch (4) and comprising a transconductance stage (44) having an input connected to a reference potential which is independent from the RF signal, to transform the reference potential into a current signal (Id),
    - chopping switches (QC1 to QC4) able to connect in series the transconductance stage (10) of the mixing branch to a current input of a current switching core (12) of the mixing branch and, in alternance, to a current input of a current switching core (46) of the dummy branch under the control of a chopping signal, and able to connect in series the transconductance stage (44) of the dummy branch to the current input of the current switching core (46) of the dummy branch and, in alternance, to the current input of the current switching core (12) of the mixing branch under the control of the chopping signal
    - said current switching core (12) of the mixing branch being able to switch the current signal received at its current input, according to the LO signal and an LO signal which forms with the LO signal a differential signal,
    - said current switching core (46) of the dummy branch being able to switch the current signal received at its current input according to LO and LO signals.
  2. The mixer circuit according to claim 1, wherein the mixer circuit has a chopping signal generator (68) able to generate the chopping signal which is a pseudorandom bit sequence that systematically has as many logical zeros as logical ones over one period.
  3. The mixer circuit according to claim 2, wherein the pseudo-random bit sequence generator comprises:
    - a pseudo-random bit sequence builder (72) which builds a pseudo-random bit sequence having a period TB and having a number of logical zeros different from the number of logical ones over period TB, and
    - a reversing core (74) able to output, in alternance, the built pseudo-random bit sequence and its opposite so as to output a longer pseudo-random bits sequence having exactly as many logical zeros as logical ones over each period of this longer pseudo-random bit sequence.
  4. The mixer circuit according to any one of the preceding claims, wherein each current input of each current switching core (12, 46) is series connected with the transconductance stages (10, 44) through respective filters (14) having a cut-off frequency strictly higher than zero.
  5. The mixer circuit according to claim 4, wherein each current switching core (12, 46) is connected between a DC current source (30, 6) and a DC current sink (32) and wherein each transconductance stage (10, 44) is directly connected to another DC current source without passing through one of the current switching stages.
  6. A method to operate a mixer circuit conformed to any one of the preceding claims, wherein the chopping switches connect in series the transconductance stage of the mixing branch to the current switching core of the mixing branch and, in alternance, to the current switching core of the dummy branch under the control of a chopping signal.
EP07789697.5A 2006-06-27 2007-06-15 Mixer circuit and method to operate this mixer circuit Expired - Fee Related EP2033305B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06300726 2006-06-27
PCT/IB2007/052298 WO2008001256A2 (en) 2006-06-27 2007-06-15 Mixer circuit and method to operate this mixer circuit
EP07789697.5A EP2033305B1 (en) 2006-06-27 2007-06-15 Mixer circuit and method to operate this mixer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07789697.5A EP2033305B1 (en) 2006-06-27 2007-06-15 Mixer circuit and method to operate this mixer circuit

Publications (2)

Publication Number Publication Date
EP2033305A2 EP2033305A2 (en) 2009-03-11
EP2033305B1 true EP2033305B1 (en) 2015-08-05

Family

ID=38846049

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07789697.5A Expired - Fee Related EP2033305B1 (en) 2006-06-27 2007-06-15 Mixer circuit and method to operate this mixer circuit

Country Status (3)

Country Link
US (1) US8140044B2 (en)
EP (1) EP2033305B1 (en)
WO (1) WO2008001256A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7596139B2 (en) 2000-11-17 2009-09-29 Foundry Networks, Inc. Backplane interface adapter with error control and redundant fabric
US7187687B1 (en) 2002-05-06 2007-03-06 Foundry Networks, Inc. Pipeline method and system for switching packets
US20120155466A1 (en) 2002-05-06 2012-06-21 Ian Edward Davis Method and apparatus for efficiently processing data packets in a computer network
US7649885B1 (en) * 2002-05-06 2010-01-19 Foundry Networks, Inc. Network routing system for enhanced efficiency and monitoring capability
US6901072B1 (en) * 2003-05-15 2005-05-31 Foundry Networks, Inc. System and method for high speed packet transmission implementing dual transmit and receive pipelines
US7817659B2 (en) 2004-03-26 2010-10-19 Foundry Networks, Llc Method and apparatus for aggregating input data streams
US8730961B1 (en) 2004-04-26 2014-05-20 Foundry Networks, Llc System and method for optimizing router lookup
US8448162B2 (en) * 2005-12-28 2013-05-21 Foundry Networks, Llc Hitless software upgrades
US8238255B2 (en) 2006-11-22 2012-08-07 Foundry Networks, Llc Recovering from failures without impact on data traffic in a shared bus architecture
US20090279441A1 (en) 2007-01-11 2009-11-12 Foundry Networks, Inc. Techniques for transmitting failure detection protocol packets
US8509236B2 (en) 2007-09-26 2013-08-13 Foundry Networks, Llc Techniques for selecting paths and/or trunk ports for forwarding traffic flows
US8599850B2 (en) * 2009-09-21 2013-12-03 Brocade Communications Systems, Inc. Provisioning single or multistage networks using ethernet service instances (ESIs)
US8515380B2 (en) * 2011-06-16 2013-08-20 Texas Instruments Incorporated Current mode blixer with noise cancellation
TWI455498B (en) * 2011-07-26 2014-10-01 Mstar Semiconductor Inc Direct conversion receiver and calibration method thereof
US8624660B2 (en) * 2012-04-19 2014-01-07 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for mixer-based harmonic rejection
JP6063296B2 (en) * 2013-02-26 2017-01-18 パナソニック株式会社 Harmonic rejection mixer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630228A (en) * 1995-04-24 1997-05-13 Motorola, Inc. Double balanced mixer circuit with active filter load for a portable comunication receiver
GB2331193B (en) * 1997-11-07 2001-07-11 Plessey Semiconductors Ltd Image reject mixer arrangements
US5945878A (en) * 1998-02-17 1999-08-31 Motorola, Inc. Single-ended to differential converter
EP1111772B1 (en) * 1999-12-21 2007-07-25 Freescale Semiconductor, Inc. Method and apparatus providing improved intermodulation distortion protection
US6871057B2 (en) * 2000-03-08 2005-03-22 Nippon Telegraph And Telephone Corporation Mixer circuit
US7437137B2 (en) * 2003-02-14 2008-10-14 Alan Fiedler Mixer system
WO2005081398A1 (en) * 2004-01-22 2005-09-01 Nokia Corporation Mixer circuit
TWI235558B (en) * 2004-04-07 2005-07-01 Arcadyan Technology Corp RF output power control method for wireless communication device

Also Published As

Publication number Publication date
WO2008001256A2 (en) 2008-01-03
US8140044B2 (en) 2012-03-20
US20100048152A1 (en) 2010-02-25
EP2033305A2 (en) 2009-03-11
WO2008001256A3 (en) 2008-07-10

Similar Documents

Publication Publication Date Title
Crols et al. A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology
US5995819A (en) Frequency converter and radio receiver using same
KR0178685B1 (en) Frequency converter capable of reducing noise components in local oscillation signals
US7106805B2 (en) 3G radio
US7062248B2 (en) Direct conversion receiver having a low pass pole implemented with an active low pass filter
US7657246B2 (en) Techniques for passive subharmonic mixing
US6510185B2 (en) Single chip CMOS transmitter/receiver
KR101066054B1 (en) Systems, methods, and apparatus for frequency conversion
EP1157456B1 (en) Direct conversion receiver employing subharmonic frequency translator architecture and related preprocessor
US6704551B2 (en) Calibration of in-phase and quadrature transmit branches of a transmitter
US6194947B1 (en) VCO-mixer structure
US7457605B2 (en) Low noise image reject mixer and method therefor
EP2173038A1 (en) Harmonic reject receiver architecture and mixer
RU2315423C2 (en) Distortion suppressing calibration
US6810242B2 (en) Subharmonic mixer
US7750749B2 (en) Switching circuit, and a modulator, demodulator or mixer including such a circuit
EP1529338B1 (en) Improved mixers with a plurality of local oscillators and systems based thereon
EP2136468B1 (en) Harmonic suppression mixer and tuner
US6909886B2 (en) Current driven polyphase filters and method of operation
US6807407B2 (en) Dual double balanced mixer
KR101165485B1 (en) Balanced Mixer Using Fits
US7421259B2 (en) RF mixer with high local oscillator linearity using multiple local oscillator phases
EP2179503A2 (en) Passive mixer and high q rf filter using a passive mixer
US6144845A (en) Method and circuit for image rejection
US20040198297A1 (en) Quadrature signal generator with feedback type frequency doubler

Legal Events

Date Code Title Description
AX Request for extension of the european patent to:

Extension state: AL BA HR MK RS

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

17P Request for examination filed

Effective date: 20090113

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

DAX Request for extension of the european patent (to any country) (deleted)
17Q First examination report despatched

Effective date: 20101215

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 7/58 20060101ALI20150122BHEP

Ipc: H03K 3/84 20060101ALI20150122BHEP

Ipc: H03D 7/14 20060101AFI20150122BHEP

INTG Intention to grant announced

Effective date: 20150209

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602007042459

Country of ref document: DE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602007042459

Country of ref document: DE

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 10

26N No opposition filed

Effective date: 20160509

REG Reference to a national code

Ref country code: DE

Ref legal event code: R081

Ref document number: 602007042459

Country of ref document: DE

Owner name: OCT CIRCUIT TECHNOLOGIES INTERNATIONAL LTD., IE

Free format text: FORMER OWNER: NXP B.V., EINDHOVEN, NL

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 11

PGFP Annual fee paid to national office [announced from national office to epo]

Ref country code: FR

Payment date: 20170523

Year of fee payment: 11

Ref country code: GB

Payment date: 20170526

Year of fee payment: 11

Ref country code: DE

Payment date: 20170522

Year of fee payment: 11

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602007042459

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20180615

PG25 Lapsed in a contracting state [announced from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180615

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180630

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190101