JP2002314021A - Structure of lead frame for electronic component - Google Patents

Structure of lead frame for electronic component

Info

Publication number
JP2002314021A
JP2002314021A JP2001114151A JP2001114151A JP2002314021A JP 2002314021 A JP2002314021 A JP 2002314021A JP 2001114151 A JP2001114151 A JP 2001114151A JP 2001114151 A JP2001114151 A JP 2001114151A JP 2002314021 A JP2002314021 A JP 2002314021A
Authority
JP
Japan
Prior art keywords
lead terminal
lead
pairs
electronic component
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001114151A
Other languages
Japanese (ja)
Inventor
Kazumi Morimoto
和巳 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2001114151A priority Critical patent/JP2002314021A/en
Publication of JP2002314021A publication Critical patent/JP2002314021A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame that can manufacture a plurality of lead terminals 3, 4, and 5 to a semiconductor device, and a number of electronic components 2 that project from one side of a package body 8 to the semiconductor device using a simply process. SOLUTION: At a site between left and right side frames 11a and at a region between section bars 11b for mutually interlocking both the side frames, a plurality of pairs 6 of first lead terminals for composing one electronic component and a plurality of pairs 6' of second lead terminals for composing one electronic component are aligned so that the pairs face in the opposite direction; at the same time, each of the lead terminals 3', 4', and 5' in each of the pairs 6' of the second lead terminals is positioned among the lead terminals 3, 4, and 5 in the pairs 6 of the first lead terminals; and semiconductor device mounting sections 3a and 3a' in each of the pairs 6 of the first lead terminals and each of the pairs 6' of the second ones are interlocked to the section bars 11b via a narrow piece 11d.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、トランジスター又
はダイオード等の電子部品のうち、図4に示すように、
半導体素子に対する複数本のリード端子3,4,5を、
前記半導体素子を密封する合成樹脂製パッケージ体8に
おける一つの側面より突出するように構成して成る電子
部品において、その製造に際して使用するリードフレー
ムの構造に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to an electronic component such as a transistor or a diode, as shown in FIG.
A plurality of lead terminals 3, 4, 5 for the semiconductor element,
The present invention relates to a structure of a lead frame used in the manufacture of an electronic component configured to protrude from one side surface of a synthetic resin package 8 for sealing the semiconductor element.

【0002】[0002]

【従来の技術】従来、この種の電子部品の製造に際して
は、図1〜図3に示す方法が広く採用されている。
2. Description of the Related Art Conventionally, the method shown in FIG. 1 to FIG.

【0003】すなわち、図1に示すように、先端に半導
体素子搭載部3aを備えたベース用リード端子3とその
両側に位置する二本のリード端子4,5とから成り一つ
の電子部品2を構成するリード端子対6の複数個を、長
手方向に適宜ピッチPの間隔で形成するようにしたリー
ドフレーム1を、薄い金属板より打ち抜く。このとき、
前記各リード端子3,4,5の相互間を一体的に連結す
るタイバー1aを同時に打ち抜き形成する。
That is, as shown in FIG. 1, one electronic component 2 is composed of a base lead terminal 3 having a semiconductor element mounting portion 3a at the tip and two lead terminals 4 and 5 located on both sides thereof. A lead frame 1 in which a plurality of lead terminal pairs 6 are formed at appropriate intervals in the longitudinal direction at a pitch P is punched out from a thin metal plate. At this time,
The tie bar 1a for integrally connecting the lead terminals 3, 4, and 5 is punched and formed at the same time.

【0004】次いで、このリードフレーム1の各リード
端子対6におけるベース用リード端子3の先端の半導体
素子搭載部3aに半導体素子7を搭載したのち、この半
導体素子7と両リード端子4,5との間をワイヤボンデ
ィング等にて電気的に接続する。
Next, after mounting the semiconductor element 7 on the semiconductor element mounting portion 3a at the tip of the base lead terminal 3 in each lead terminal pair 6 of the lead frame 1, the semiconductor element 7 and the two lead terminals 4 and 5 are mounted. Are electrically connected by wire bonding or the like.

【0005】次いで、図2に示すように、前記各リード
端子対6の先端に、半導体素子6の部分を密封する合成
樹脂製のパッケージ体8を成形したのち、前記各リード
端子対6の相互間におけるタイバー1aを斜線で示すパ
ンチA,Bにて、また、各リード端子対6における両リ
ード端子4,5のリードフレーム1に対する連接部を斜
線で示すパンチCにて各々打ち抜くことにより、図3に
示すように、各リード端子対6における両リード端子
4,5を、リードフレーム1から切り離す。
[0005] Next, as shown in FIG. 2, a package 8 made of a synthetic resin for sealing the semiconductor element 6 is formed at the tip of each of the lead terminal pairs 6. The tie bars 1a between them are punched by punches A and B indicated by oblique lines, and the connecting portions of the lead terminals 4 and 5 of each lead terminal pair 6 to the lead frame 1 are punched by punches C indicated by oblique lines. As shown in FIG. 3, both lead terminals 4 and 5 of each lead terminal pair 6 are separated from the lead frame 1.

【0006】この状態、つまり、各電子部品2がそのベ
ース用リード端子3を介してリードフレーム1に対して
連結された状態で、各電子部品2におけるパッケージ体
7に対する標印の捺印、及び各電子部品2の通電による
性能検査を行ったのち、最後に、各電子部品2における
ベース用リード端子3のリードフレーム1に対する接続
部をパンチにて打ち抜くことにより、電子部品2をリー
ドフレーム1から切り離すようにしている。
In this state, that is, in a state where each electronic component 2 is connected to the lead frame 1 via the base lead terminal 3, a mark is imprinted on the package 7 of each electronic component 2, and After performing a performance test by energizing the electronic component 2, finally, the connecting portion of the base lead terminal 3 to the lead frame 1 in each electronic component 2 is punched out by a punch, so that the electronic component 2 is separated from the lead frame 1. Like that.

【0007】[0007]

【発明が解決しようとする課題】この従来におけるリー
ドフレームによると、各電子部品2に対する標印の捺
印、及び通電による性能検査等を、リードフレーム1か
ら切り離すことなく、リードフレーム1に対してベース
用リード端子3を介して一体的に連結した形態で容易に
行うことができるという利点を有するが、その反面、電
子部品2を、長手方向に適宜ピッチPでの一列に並べた
形態であることにより、長手方向に沿っての単位長さ当
たりに製造することができる電子部品の個数が少ないと
いう問題があった。
According to this conventional lead frame, the marking of each electronic component 2 and the performance inspection by energization are performed on the lead frame 1 without separating the lead frame 1 from the base. Has the advantage that it can be easily performed in the form of being integrally connected via the lead terminals 3 for use, but on the other hand, the electronic components 2 are arranged in a line at an appropriate pitch P in the longitudinal direction. Accordingly, there is a problem that the number of electronic components that can be manufactured per unit length along the longitudinal direction is small.

【0008】本発明は、電子部品に対する標印の捺印及
び通電による性能検査等を、リードフレームに連接した
形態で行うことができる状態のもとで、リードフレーム
における長手方向に沿って単位長さ当たりの個数を多く
できるようにしたリードフレームの構造を提供すること
を技術的課題とするものである。
According to the present invention, a unit length is measured along a longitudinal direction of a lead frame in a state in which a mark can be imprinted on an electronic component and a performance test by energization can be performed in a form connected to the lead frame. An object of the present invention is to provide a lead frame structure that can increase the number of hits.

【0009】[0009]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「長手方向に延びる左右一対の両サイ
ド枠の相互間を、両サイド枠の長手方向に沿って適宜間
隔で配設したセクションバーにて一体的に連結し、前記
両サイド枠の間で、且つ、この各セクションバーの間の
部位に、先端に半導体素子搭載部を備えたベース用リー
ド端子と少なくとも一本のリード端子とから成る第1リ
ード端子対の複数個を、当該各第1リード端子対におけ
る各リード端子を前記両サイド枠の長手方向と平行にし
て、前記両サイド枠の長手方向と直角の方向に適宜ピッ
チ間隔で並べて配設するとともに、同じく、先端に半導
体素子搭載部を備えたベース用リード端子と少なくとも
一本のリード端子とから成る第2リード端子対の複数個
を、当該各第2リード端子対を前記各第1リード端子対
と逆向きにし、且つ、当該各第2リード端子対における
各リード端子を前記各第1リード端子対における各リー
ド端子の間に位置するように並べて配設し、前記各第1
リード端子及び各第2リード端子における各リード端子
の相互間と両サイド枠との間を、前記両サイド枠の長手
方向と直角の方向に延びるダムバーにて一体的に連結
し、更に、前記各第1リード端子対における半導体素子
搭載部及び前記各第2リード端子対における半導体素子
搭載部の各々を、前記各セクションバーに対して、細幅
片を介して一体的に連結する。」という構成にした。
In order to achieve this technical object, the present invention provides a method of disposing a pair of left and right side frames extending in the longitudinal direction at appropriate intervals along the longitudinal direction of the both side frames. At least one base lead terminal having a semiconductor element mounting portion at the tip is provided between the side frames and between the section bars. A plurality of first lead terminal pairs each including a lead terminal, each lead terminal of each first lead terminal pair being parallel to the longitudinal direction of the side frames, and a direction perpendicular to the longitudinal direction of the both side frames. And a plurality of second lead terminal pairs each including a base lead terminal having a semiconductor element mounting portion at the tip and at least one lead terminal. Re And the lead terminals in the respective second lead terminal pairs are arranged side by side so as to be located between the respective lead terminals in the respective first lead terminal pairs. The first
The lead terminals and the respective second lead terminals of the respective second lead terminals are integrally connected to each other and both side frames by a dam bar extending in a direction perpendicular to the longitudinal direction of the both side frames. Each of the semiconductor element mounting portion of the first lead terminal pair and the semiconductor element mounting portion of each of the second lead terminal pairs is integrally connected to each of the section bars via a narrow strip. ].

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態を図面
について説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図5は、本発明の実施の形態によるリード
フレームの平面図であり、また、図6は、その部分的拡
大図である。
FIG. 5 is a plan view of a lead frame according to an embodiment of the present invention, and FIG. 6 is a partially enlarged view thereof.

【0012】この図において、符号11は、薄い金属板
にて長尺帯状にしたリードフレームを示し、このリード
フレーム11は、長手方向に延びる左右一対の両サイド
枠11aの相互間を、両サイド枠の長手方向に沿って適
宜間隔で配設したセクションバー11bにて一体的に連
結したものに構成されている。
In this figure, reference numeral 11 denotes a lead frame formed in a long strip shape by a thin metal plate, and the lead frame 11 is formed by a pair of left and right side frames 11a extending in the longitudinal direction. They are integrally connected by section bars 11b arranged at appropriate intervals along the longitudinal direction of the frame.

【0013】そして、前記リードフレーム11のうち前
記両サイド枠11aの間で、且つ、前記各セクションバ
ー11bの間の部位に、先端に例えばアイランド等の半
導体素子搭載部3aを備えたベース用リード端子3とそ
の両側のリード端子4,5とから成るリード端子対6
(このリード端子対6が一つの電子部品2を構成する)
の複数個(本実施の形態では四個)を、当該各第1リー
ド端子対6における各リード端子3,4,5を前記両サ
イド枠11aの長手方向と平行にして、前記両サイド枠
11aの長手方向と直角の方向に適宜ピッチ間隔で並べ
て配設する。
A base lead having a semiconductor element mounting portion 3a such as an island at its tip at a position between the side frames 11a and between the section bars 11b of the lead frame 11. Lead terminal pair 6 comprising terminal 3 and lead terminals 4 and 5 on both sides thereof
(This lead terminal pair 6 constitutes one electronic component 2)
(The four in the present embodiment) with the respective lead terminals 3, 4, and 5 in the respective first lead terminal pairs 6 being parallel to the longitudinal direction of the both side frames 11a. Are arranged at appropriate pitch intervals in a direction perpendicular to the longitudinal direction.

【0014】更に、前記リードフレーム11のうち前記
両サイド枠11aの間で、且つ、前記各セクションバー
11bの間の部位には、同じく、先端に例えばアイラン
ド等の半導体素子搭載部3a′を備えたベース用リード
端子3′とその両側のリード端子4′,5′とから成る
第2リード端子対6′(このリード端子対6が一つの電
子部品2′を構成する)の複数個(本実施の形態では四
個)を、当該各第2リード端子対6′を前記各第1リー
ド端子対6と逆向きにし、且つ、当該各第2リード端子
対6′における各リード端子3′,4′,5′を前記各
第1リード端子対6における各リード端子3,4,5の
間に位置するように並べて配設する。
Further, a portion of the lead frame 11 between the side frames 11a and between the section bars 11b is similarly provided with a semiconductor element mounting portion 3a 'such as an island at the tip. A second lead terminal pair 6 ′ (the lead terminal pair 6 constitutes one electronic component 2 ′) comprising a base lead terminal 3 ′ and lead terminals 4 ′ and 5 ′ on both sides thereof. In the present embodiment, the four lead terminals 6 ′ are turned in the opposite direction to the first lead terminal pairs 6 and the respective lead terminals 3 ′, 3 ′ in the second lead terminal pairs 6 ′. 4 ', 5' are arranged side by side so as to be located between the respective lead terminals 3, 4, 5 in the respective first lead terminal pairs 6.

【0015】そして、前記各第1リード端子6及び各第
2リード端子6′における各リード端子3,4,5,
3′,4′,5′の相互間と両サイド枠11aとの間
を、前記両サイド枠の長手方向と直角の方向に延びる二
本のダムバー11cにて一体的に連結する。
Each of the lead terminals 3, 4, 5, and 5 in each of the first lead terminals 6 and each of the second lead terminals 6 '.
Between the 3 ', 4', 5 'and the two side frames 11a are integrally connected by two dam bars 11c extending in a direction perpendicular to the longitudinal direction of the two side frames.

【0016】更に、前記各第1リード端子対6における
半導体素子搭載部3aを、前記各セクションバー11b
のうちこの半導体素子搭載部3aに隣接するセクション
バー11bに、一本又は複数本(図面では二本)の細幅
片11dを介して一体的に連結する一方、前記各第2リ
ード端子対6′における半導体素子搭載部3a′を、前
記各セクションバー11bのうちこの半導体素子搭載部
3a′に隣接するセクションバー11bに、一本又は複
数本(図面では二本)の細幅片11d′を介して一体的
に連結する。
Further, the semiconductor element mounting portion 3a of each of the first lead terminal pairs 6 is connected to the section bar 11b.
Of the second lead terminal pairs 6 are connected integrally to the section bar 11b adjacent to the semiconductor element mounting portion 3a via one or a plurality of (two in the drawing) narrow pieces 11d. ′, One or a plurality (two in the drawing) of narrow strips 11 d ′ are connected to the section bar 11 b of each section bar 11 b adjacent to the semiconductor element mounting section 3 a ′. And connected together.

【0017】このように構成したリードフレーム11を
使用して、電子部品2を製造するに際しては、先ず、図
7に示すように、各第1リード端子対6における半導体
素子搭載部3a及び各第2リード端子対6′における半
導体素子搭載部3a′の各々に半導体素子7を搭載した
のち、この半導体素子7と、両リード端子4,5、
4′,5′との間のワイヤボンディング等にて電気的に
接続する。
When manufacturing the electronic component 2 using the lead frame 11 configured as described above, first, as shown in FIG. 7, the semiconductor element mounting portion 3a and the first After the semiconductor element 7 is mounted on each of the semiconductor element mounting portions 3a 'of the two lead terminal pairs 6', the semiconductor element 7 and the two lead terminals 4, 5,.
4 'and 5' are electrically connected by wire bonding or the like.

【0018】次いで、前記各第1リード端子対6におけ
る先端の部分、及び前記各第2リード端子対6′におけ
る先端の部分に、図8に示すように、半導体素子7を密
封する合成樹脂製のパッケージ体8を成形することによ
り、前記各第1リード端子対6による電子部品2と、前
記各第2リード端子対6′による電子部品2とにする。
Next, as shown in FIG. 8, the tip of each of the first lead terminal pairs 6 and the tip of each of the second lead terminal pairs 6 'are made of synthetic resin to seal the semiconductor element 7, as shown in FIG. By forming the package body 8 described above, the electronic component 2 by each of the first lead terminal pairs 6 and the electronic component 2 by each of the second lead terminal pairs 6 'are formed.

【0019】次いで、二本のダムバー11cを、図9に
示すように、斜線で示すパンチA,B,Cにて打ち抜く
ことにより、図10に示すように、前記各第1リード端
子対6による電子部品2における各リード端子3,4,
5及び前記各第2リード端子対6′による電子部品2に
おける各リード端子3′4′5′を、リードフレーム1
1から切り離す。
Next, as shown in FIG. 9, the two dam bars 11c are punched out by punches A, B, and C shown by oblique lines, thereby forming the first lead terminal pairs 6 as shown in FIG. Each lead terminal 3, 4, in the electronic component 2
5 and the respective lead terminals 3 ′ 4 ′ 5 ′ in the electronic component 2 by the respective second lead terminal pairs 6 ′ are connected to the lead frame 1.
Disconnect from 1.

【0020】このとき、前記各電子部品2は、リードフ
レームかから完全に切り離されることなく、細幅片11
dを介してリードフレーム11に一体的に連結されてい
るから、この状態、つまり、リードフレーム11に一体
的に連結れた状態で、当該各電子部品2に対する標印の
捺印及び通電による性能検査等を行うことがきるのであ
る。
At this time, each of the electronic components 2 is not completely separated from the lead frame and the narrow pieces 11
In this state, that is, in a state of being integrally connected to the lead frame 11, a performance test is performed by imprinting a mark on each of the electronic components 2 and energizing the electronic components 2, because the electronic components 2 are integrally connected to the lead frame 11 through the lead frame 11 And so on.

【0021】そして、これらの標印の捺印及び通電によ
る性能検査等が終わると、最後に、前記各細幅片11d
を、パンチで打ち抜くことにより、各電子部品2の全て
をリードフレーム11から切り離すのである。
When the performance of the marking and the performance inspection by energization are completed, finally, each of the narrow strips 11d
Is punched out with a punch, so that all of the electronic components 2 are separated from the lead frame 11.

【0022】[0022]

【発明の作用・効果】このように、本発明におけるリー
ドフレームの構造によると、電子部品をリードフレーム
の幅方向に二列に並べて製造することに加えて、二列の
各電子部品におけるリード端子を、リードフレームの長
手方向に対して互いにオーバーラップすることにより、
リードフレームの単位長さ当たりに製造することができ
る電子部品の個数を大幅に増大できる一方、各電子部品
をリードフレームに一体的に連結した状態で、各電子部
品に対する標印の捺印及び通電による性能検査等を行う
ことができるから、この各電子部品に対する性能検査
を、当該電子部品をリードフレームから切り離した後で
行う場合よりも、工程を著しく簡単にできるという効果
を有する。
As described above, according to the structure of the lead frame of the present invention, in addition to manufacturing the electronic components in two rows in the width direction of the lead frame, the lead terminals in each of the two rows of electronic components are manufactured. By overlapping each other with respect to the longitudinal direction of the lead frame,
While the number of electronic components that can be manufactured per unit length of the lead frame can be greatly increased, while each electronic component is integrally connected to the lead frame, the marking and energization of each electronic component are performed. Since a performance test or the like can be performed, there is an effect that the process can be significantly simplified as compared with a case where the performance test for each electronic component is performed after the electronic component is separated from the lead frame.

【0023】特に、請求項2に記載したように、細幅片
を、一つの半導体素子搭載部について複数個にしたこと
により、各電子部品が、その各リード端子をリードフレ
ームから切り離した後において、リードフレームの横方
向にずれ変位したり、表面から浮き上がるか沈むように
変位することを小さくできるから、各電子部品に対する
性能検査を更に容易にできる利点がある。
In particular, as described in claim 2, the plurality of narrow pieces are provided for one semiconductor element mounting portion, so that each electronic component has its lead terminals separated from the lead frame. Since it is possible to reduce the displacement of the lead frame in the lateral direction and the displacement such that the lead frame rises or sinks from the surface, there is an advantage that the performance inspection of each electronic component can be further facilitated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来におけるリードフレームを示す平面図であ
る。
FIG. 1 is a plan view showing a conventional lead frame.

【図2】前記従来のリードフレームにおいてパッケージ
体を成形した状態を示す平面図である。
FIG. 2 is a plan view showing a state where a package body is molded in the conventional lead frame.

【図3】前記従来のリードフレームにおいてリード端子
を切り離した状態を示す平面図である。
FIG. 3 is a plan view showing a state where lead terminals are separated in the conventional lead frame.

【図4】電子部品の斜視図である。FIG. 4 is a perspective view of an electronic component.

【図5】本発明の実施の形態によるリードフレームを示
す平面図である。
FIG. 5 is a plan view showing a lead frame according to the embodiment of the present invention.

【図6】前記図5の要部拡大図である。FIG. 6 is an enlarged view of a main part of FIG. 5;

【図7】前記本発明のリードフレームにおいて半導体素
子を搭載した状態を示す平面図である。
FIG. 7 is a plan view showing a state where a semiconductor element is mounted on the lead frame of the present invention.

【図8】前記本発明のリードフレームにおいてパッケー
ジ体を成形した状態を示す平面図である。
FIG. 8 is a plan view showing a state in which a package is molded in the lead frame of the present invention.

【図9】前記本発明のリードフレームにおいてダムバー
を打ち抜いている状態を示す平面図である。
FIG. 9 is a plan view showing a state in which a dam bar is punched in the lead frame of the present invention.

【図10】前記本発明のリードフレームにおいてダムバ
ーを打ち抜いたあとの状態を示す平面図である。
FIG. 10 is a plan view showing a state after punching a dam bar in the lead frame of the present invention.

【符号の説明】[Explanation of symbols]

2 電子部品 3,3′ ベース用リード端子 3a,3a′ 半導体素子搭載部 4,5,4′,5′ リード端子 6,6′ リード端子対 7 半導体素子 8 パッケージ体 11 リードフレーム 11a サイド枠 11b セクションバー 11c ダムバー 11d 細幅片 2 Electronic component 3, 3 'Base lead terminal 3a, 3a' Semiconductor element mounting part 4, 5, 4 ', 5' Lead terminal 6, 6 'Lead terminal pair 7 Semiconductor element 8 Package body 11 Lead frame 11a Side frame 11b Section bar 11c Dam bar 11d Narrow strip

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】長手方向に延びる左右一対の両サイド枠の
相互間を、両サイド枠の長手方向に沿って適宜間隔で配
設したセクションバーにて一体的に連結し、前記両サイ
ド枠の間で、且つ、この各セクションバーの間の部位
に、先端に半導体素子搭載部を備えたベース用リード端
子と少なくとも一本のリード端子とから成る第1リード
端子対の複数個を、当該各第1リード端子対における各
リード端子を前記両サイド枠の長手方向と平行にして、
前記両サイド枠の長手方向と直角の方向に適宜ピッチ間
隔で並べて配設するとともに、同じく先端に半導体素子
搭載部を備えたベース用リード端子と少なくとも一本の
リード端子とから成る第2リード端子対の複数個を、当
該各第2リード端子対を前記各第1リード端子対と逆向
きにし、且つ、当該各第2リード端子対における各リー
ド端子を前記各第1リード端子対における各リード端子
の間に位置するように並べて配設し、前記各第1リード
端子及び各第2リード端子における各リード端子の相互
間と両サイド枠との間を、前記両サイド枠の長手方向と
直角の方向に延びるダムバーにて一体的に連結し、更
に、前記各第1リード端子対における半導体素子搭載部
及び前記各第2リード端子対における半導体素子搭載部
の各々を、前記各セクションバーに対して、細幅片を介
して一体的に連結したことを特徴とする電子部品用リー
ドフレームの構造。
A pair of left and right side frames extending in the longitudinal direction are integrally connected to each other by section bars disposed at appropriate intervals along the longitudinal direction of the both side frames. A plurality of first lead terminal pairs each including a base lead terminal having a semiconductor element mounting portion at the tip and at least one lead terminal are provided between the section bars. Each lead terminal in the first lead terminal pair is made parallel to the longitudinal direction of both side frames,
A second lead terminal which is disposed at appropriate pitch intervals in a direction perpendicular to the longitudinal direction of the both side frames, and also includes a base lead terminal having a semiconductor element mounting portion at the tip and at least one lead terminal. A plurality of the pairs are arranged such that each of the second lead terminal pairs is opposite to each of the first lead terminal pairs, and each of the lead terminals of each of the second lead terminal pairs is replaced with each of the leads of each of the first lead terminal pairs. The first lead terminal and the second lead terminal are arranged side by side so as to be located between the terminals, and a space between each of the lead terminals and both side frames is perpendicular to the longitudinal direction of the both side frames. And a semiconductor chip mounting portion in each of the first lead terminal pairs and a semiconductor element mounting portion in each of the second lead terminal pairs are respectively connected to the respective memory cells. Relative Deployment bar structure of an electronic component lead frame, characterized in that integrally connected to via a narrow strip.
【請求項2】前記請求項1の記載において、細幅片を、
一つの半導体素子搭載部について複数個にしたことを特
徴とする電子部品用リードフレームの構造。
2. The method according to claim 1, wherein the narrow strip is
A lead frame structure for an electronic component, wherein a plurality of semiconductor element mounting portions are provided.
JP2001114151A 2001-04-12 2001-04-12 Structure of lead frame for electronic component Pending JP2002314021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001114151A JP2002314021A (en) 2001-04-12 2001-04-12 Structure of lead frame for electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001114151A JP2002314021A (en) 2001-04-12 2001-04-12 Structure of lead frame for electronic component

Publications (1)

Publication Number Publication Date
JP2002314021A true JP2002314021A (en) 2002-10-25

Family

ID=18965269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001114151A Pending JP2002314021A (en) 2001-04-12 2001-04-12 Structure of lead frame for electronic component

Country Status (1)

Country Link
JP (1) JP2002314021A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100763962B1 (en) * 2001-07-03 2007-10-05 삼성테크윈 주식회사 Manufacturing method of one-way lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100763962B1 (en) * 2001-07-03 2007-10-05 삼성테크윈 주식회사 Manufacturing method of one-way lead frame

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